Semiconductor structure and method of manufacturing the same, storage system

Abstract

This disclosure provides a semiconductor structure and its fabrication method, as well as a memory system, relating to the field of semiconductor chip technology. It aims to improve the problem of leakage current between a first electrode structure and other conductive structures through a dielectric layer. The semiconductor structure includes a support structure and a capacitor structure. The support structure includes a first support layer and a support pillar. The first support layer has a first surface and a second surface, with the first surface closer to the support pillar than the second surface. The first surface has a protrusion, and the support pillar extends along a first direction and is connected to the protrusion. The capacitor structure includes a first electrode structure, a dielectric layer, and a second electrode structure. The capacitor structure is disposed around the support pillar, and the first electrode structure is also located on one side of the protrusion along the first direction. This arrangement increases the electron flow path between the first electrode structure and other conductive structures, making it difficult for electrons to flow out, thus improving the leakage current between the first electrode structure and other conductive structures through the dielectric layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, its fabrication method, and a storage system. Background Technology

[0002] With the rapid development of Dynamic Random Access Memory (DRAM), the size of DRAM continues to shrink, which places higher demands on the arrangement of transistors in DRAM.

[0003] As DRAM size continues to shrink, the spacing between adjacent memory cells in DRAM is becoming smaller and smaller. Summary of the Invention

[0004] Embodiments of this disclosure provide a semiconductor structure, a method for fabricating the same, and a memory system.

[0005] The embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, a semiconductor structure is provided. The semiconductor structure includes a support structure and a capacitor structure. The support structure includes a first support layer and a support pillar. The first support layer has a first surface and a second surface arranged along a first direction. The first surface is closer to the support pillar than the second surface. The first surface has a protrusion. The support pillar extends along the first direction and is connected to the protrusion. The first direction is the thickness direction of the first support layer. The capacitor structure includes a first electrode structure, a dielectric layer, and a second electrode structure. The dielectric layer is located between the first electrode structure and the second electrode structure. The capacitor structure is disposed around the support pillar. The first electrode structure is located between the dielectric layer and the support pillar, and the first electrode structure is also located on one side of the protrusion along the first direction.

[0007] In some embodiments, the protrusion is larger in size in the second direction than the support post is in the second direction, and the second direction intersects the first direction.

[0008] In some embodiments, the raised sidewall is flush with the sidewall of the first electrode structure in the first direction.

[0009] In some embodiments, the orthographic projection shape of the protrusion in the first direction is the same as the orthographic projection shape of the first electrode structure in the first direction.

[0010] In some embodiments, in the direction from the support pillar to the first support layer, a portion of the dielectric layer extends beyond the first electrode structure.

[0011] In some embodiments, the thickness of the first electrode structure is the same along the circumference of the support column.

[0012] In some embodiments, the cross-sectional shape of the second electrode structure on the reference plane includes a circle, and the reference plane is the plane on which the second surface is located.

[0013] In some embodiments, the semiconductor structure further includes: a second support layer and a third support layer, both of which are perpendicular to the first direction, and the second support layer is located between the first support layer and the third support layer; the first electrode structure extends through the second support layer and the third support layer along the first direction.

[0014] In some embodiments, the second electrode structure includes an electrode layer and a conductive structure. The electrode layer is located between the conductive structure and the dielectric layer. The conductive structure includes interconnected conductive pillars and an extension layer. The conductive pillars penetrate the first support layer and the second support layer along the first direction and extend to the side of the third support layer near the second support layer. A portion of the extension layer is located between the first support layer and the second support layer, and a portion of the extension layer is located between the second support layer and the third support layer.

[0015] In some embodiments, a portion of the dielectric layer is located between the extension layer and the first support layer, a portion of the dielectric layer is located between the extension layer and the second support layer, a portion of the dielectric layer is located between the extension layer and the third support layer, and a portion of the dielectric layer is located between the conductive pillar and the third support layer; a portion of the second electrode structure is located between the extension layer and the dielectric layer.

[0016] In some embodiments, the semiconductor structure includes a plurality of first electrode structures arranged around the conductive pillar.

[0017] In some embodiments, the semiconductor structure further includes a plurality of transistors, which are stacked with the plurality of first electrode structures along the first direction, and one transistor is connected to one of the first electrode structures.

[0018] On the other hand, a method for fabricating a semiconductor structure is also provided, comprising: forming a support structure, the support structure including a first support layer and support pillars, the first support layer having a first surface and a second surface arranged along a first direction, the first surface being closer to the support pillars than the second surface, the first surface having a protrusion, the support pillars extending along the first direction and connected to the protrusions, the first direction being parallel to the thickness direction of the first support layer; forming a capacitor structure, the capacitor structure including a first electrode structure, a dielectric layer and a second electrode structure, the dielectric layer being located between the first electrode structure and the second electrode structure; the capacitor structure being disposed around the support pillars, the first electrode structure being located between the dielectric layer and the support pillars, and in the extension direction of the support pillars, a portion of the support pillars being located between the first electrode structure and the first support layer.

[0019] In some embodiments, forming the support structure includes: forming a stacked structure, the stacked structure including a plurality of support layers and a plurality of sacrificial layers alternately stacked along the first direction; forming a first structural hole, the first structural hole penetrating the stacked structure along the first direction; forming a first electrode structure, the first electrode structure covering the bottom and part of the hole wall of the first structural hole, and the first electrode structure surrounding a second structural hole; and depositing an insulating material in the second structural hole and on the stacked structure to form a support pillar and a first support layer.

[0020] In some embodiments, forming the first electrode structure includes: forming a first electrode layer that covers the bottom and wall of the first structural hole; removing a portion of the first electrode layer to form the first electrode structure, wherein a portion of the sacrificial layer extends beyond the first electrode structure in the first direction.

[0021] In some embodiments, forming the capacitor structure includes: removing the sacrificial layer and a portion of the support layer to form a filling space; and sequentially depositing a dielectric material, an electrode material, and a conductive material in the filling space to form a dielectric layer, a second electrode layer, and a conductive structure, wherein the second electrode layer and the conductive structure together constitute the second electrode structure.

[0022] In some embodiments, forming a filling space includes: forming a third structural hole, the third structural hole penetrating the first support layer to the sacrificial layer along the first direction; removing a portion of the sacrificial layer through the third structural hole to form a first filling space, the first filling space communicating with the third structural hole; removing a portion of the support layer and the sacrificial layer through the third structural hole to form a second filling space, the second filling space communicating with the third structural hole, the third structural hole, the first filling space, and the second filling space together constituting the filling space.

[0023] In another aspect, a storage system is provided, comprising: a semiconductor structure as described above and a controller, the controller being coupled to the semiconductor structure to control the semiconductor structure to store data. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0025] Figure 1 A block diagram of an electronic device according to some embodiments;

[0026] Figure 2 A block diagram of a memory according to some embodiments;

[0027] Figure 3 This is a schematic diagram of a semiconductor structure according to some embodiments;

[0028] Figure 4 This is a structural schematic diagram of a support structure according to some embodiments;

[0029] Figure 5 This is a schematic diagram of a first electrode structure according to some embodiments;

[0030] Figure 6 for Figure 3 Cross-sectional view of AA;

[0031] Figure 7 for Figure 3 Cross-sectional view of BB;

[0032] Figure 8 for Figure 3 Cross-sectional view of CC;

[0033] Figure 9 This is a schematic diagram of the electron flow path according to some embodiments;

[0034] Figure 10 This is a schematic diagram of the semiconductor structure at the reference surface according to some embodiments;

[0035] Figure 11 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0036] Figure 12 This is a schematic diagram of the structure after the stacked structure is formed according to some embodiments;

[0037] Figure 13 This is a schematic diagram of the structure after forming the first structural hole according to some embodiments;

[0038] Figure 14 This is a schematic diagram of the structure after forming the second structural hole according to some embodiments;

[0039] Figure 15 This is a schematic diagram of the structure after the support structure is formed according to some embodiments;

[0040] Figure 16 This is a schematic diagram of the structure after the first filling space is formed according to some embodiments;

[0041] Figure 17 This is a schematic diagram of the structure after the second filling space is formed according to some embodiments;

[0042] Figure 18 This is a schematic diagram of the structure after forming a conductive structure according to some embodiments.

[0043] Reference numerals: 9000, Electronic device; 910, Storage system; 911, Memory; 912, Controller; 920, Motherboard; X, First direction; Y, Second direction; Z, Third direction; 1000, Semiconductor structure; T, Transistor; C, Capacitor structure; 100, First electrode structure; 110, First part; 120, Second part; 130, First space; 200, Second electrode structure; 210, Electrode layer; 220, Conductive structure; 221, Conductive pillar; 222, Extension layer; 300, Dielectric layer; 40 0. Support structure; 410. First support layer; 411. First surface; 4111. Protrusion; 412. Second surface; 420. Support pillar; 500. Support layer; 510. Second support layer; 520. Third support layer; 600. Stacked structure; 610. Sacrificial layer; 620. First structural hole; 630. Second structural hole; 640. First electrode layer; 650. Second electrode layer; 660. Third structural hole; 670. Substrate; 700. Fill space; 710. First fill space; 720. Second fill space. Detailed Implementation

[0044] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0045] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0046] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0047] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0048] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0049] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0050] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0051] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0052] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0053] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0054] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0055] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, the difference between the two equalities being less than or equal to 5% of either one.

[0056] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0057] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0058] Figure 1 This is a block diagram of an electronic device 9000 provided in some embodiments of the present disclosure. The electronic device 9000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, server, in-vehicle equipment, positioning device, wearable electronic device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0059] like Figure 1 As shown, the electronic device 9000 may include a storage system 910 and a motherboard 920. The storage system 910 can be integrated into various types of storage devices, such as memory cards. These memory cards include any of the following: PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital memory cards (SD cards), and universal flash storage (UFS). In other words, the storage system 910 can be applied to and packaged into different types of electronic products.

[0060] The motherboard 920 may include a processor of the electronic device 9000, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The motherboard 920 may be configured to send data to or receive data from memory.

[0061] In some embodiments, the storage system 910 may have one or more memories 911 and a controller 912. For example, the controller 912 may be configured to operate in a low duty cycle environment, such as with an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment with an SSD or eMMC, which is used as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. Or, in some examples, the controller 912 is coupled to the memory 911 and the motherboard 920 and is configured to control the memory 911 to store data while also communicating with external devices (e.g., a host computer).

[0062] The number of memories 911 in the storage system 910 can be one or more. Figure 1 The diagram uses three memories 911 as an example. The controller 912 manages the data stored in each memory 911 and communicates with the motherboard 920. The controller 912 can be configured to control the operation of each memory 911, such as read, write, and refresh operations. The controller 912 can also be configured to manage various functions related to the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management.

[0063] In some implementations, controller 912 is also configured to determine the maximum memory capacity available to the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Controller 912 may also perform any other suitable functions. Controller 912 can communicate with external devices (e.g., motherboard 920) according to a specific communication protocol. For example, controller 912 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0064] The controller 912 mentioned above may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0065] In this embodiment, the storage system 910 can be integrated into various types of storage devices, and is not limited to the electronic device 9000 in the above embodiment.

[0066] Figure 2 Block diagrams of memory provided for some embodiments of this disclosure. For example... Figure 2As shown, memory 911 includes a memory cell array 913 and peripheral circuitry 914 for controlling the memory cell array 913. Peripheral circuitry 914 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 913. For example, peripheral circuitry 914 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0067] For example, the peripheral circuit 914 can use complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0068] The memory cell array 913 and the peripheral circuitry 914 can be arranged side-by-side in the same plane, for example, on the same wafer; that is, the memory cell array 913 and the peripheral circuitry 914 can be located in the same semiconductor structure. Alternatively, the memory cell array 913 and the peripheral circuitry 914 can be formed on different wafers and bonded together face-to-face. Figure 2 As shown, when the memory cell array 913 and the peripheral circuitry 914 are formed on different wafers and bonded together face-to-face, the memory 911 may include a first semiconductor structure 901 and a second semiconductor structure 902, as well as a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902. The first semiconductor structure 901 may include the memory cell array 913, and the second semiconductor structure 902 may include the peripheral circuitry 914.

[0069] The memory cell array 913 may be an array of memory cells that use vertical transistors as switching and selection devices. In some embodiments, the memory cell array 913 may be a dynamic random access memory (DRAM) cell array. For ease of description, DRAM cell array may be used to describe an example of the memory cell array 913 in this disclosure. However, it should be understood that the memory cell array 913 is not limited to DRAM cell arrays, and may include any other suitable type of memory cell array 913 that can use vertical transistors as switching and selection devices, such as PCM cell arrays, static random-access memory (SRAM) cell arrays, FRAM cell arrays, resistive memory cell arrays, magnetic memory cell arrays, spin transfer torque (STT) memory cell arrays, etc.

[0070] When the memory cell array 913 is a DRAM cell array, the memory cells therein are DRAM cells. A DRAM cell includes a capacitor structure and one or more transistors. The capacitor structure is used to store data as positive or negative charges, and the one or more transistors (also called transfer transistors) are used to control (e.g., switch and select) access to the DRAM cell. In some embodiments, each DRAM cell is a transistor and a capacitor structure (1T1C) cell. According to some embodiments, the DRAM cell can be refreshed by peripheral circuitry 914 to retain data.

[0071] Figure 3 This is a schematic diagram of a semiconductor structure according to some embodiments. For example... Figure 3 As shown, some embodiments of this disclosure provide a semiconductor structure that can serve as the first semiconductor structure 901 in the aforementioned memory 911, or the semiconductor structure can serve as the aforementioned memory 911. The following description, in conjunction with... Figures 3 to 9 The semiconductor structure will be explained and described.

[0072] Please refer to Figure 3 , Figure 4 and Figure 5 The semiconductor structure 1000 includes a support structure 400 and a capacitor structure C. The support structure 400 includes a first support layer 410 and support pillars 420. The first support layer 410 has a first surface 411 and a second surface 412 arranged along a first direction X. The first direction is the thickness direction of the first support layer 410. The first surface 411 is closer to the support pillars 420 than the second surface 412. The first surface 411 has a protrusion 4111, and the support pillars 420 extend along the first direction X and are connected to the protrusions 4111. The first support layer 410 and the support pillars 420 are an integral structure.

[0073] The capacitor structure C includes a first electrode structure 100, a dielectric layer 300, and a second electrode structure 200. The dielectric layer 300 is located between the first electrode structure 100 and the second electrode structure 200.

[0074] For example, the constituent materials of the first electrode structure 100 and the second electrode structure 200 may include conductive materials, including but not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides, or other suitable conductive materials.

[0075] For example, the dielectric layer 300 may comprise a high-k (k greater than 2.8) dielectric material to increase the capacitance value per unit area of ​​the capacitor structure C. In a specific embodiment, the dielectric layer 300 may comprise one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO.

[0076] In this embodiment, reference Figure 3 and Figure 4 The support column 420 extends along a first direction X and has a side surface extending along the first direction X. For example, when the support column 420 is a cylindrical structure, the side surface of the support column 420 is curved; when the support column 420 is a frustum-shaped structure, the side surface of the support column 420 is curved; when the support column 420 is a cubic structure, the side surface of the support column 420 includes a plurality of sequentially connected planes.

[0077] The capacitor structure C is arranged around the support pillar 420, and the first electrode structure 100 is located between the dielectric layer 300 and the support pillar 420. This can be understood as the capacitor structure C being arranged around the side of the support pillar 420. Taking a cylindrical support pillar 420 as an example, the capacitor structure C is located around the periphery of the support pillar 420, and the capacitor structure C is arranged around the support pillar 420 along its circumference. "Circumferential direction" refers to the circumferential direction, that is, the circumferential direction around the axis of the cylinder.

[0078] refer to Figure 3 and Figure 5The first electrode structure 100 in the capacitor structure C may include a first portion 110 and a second portion 120. The second portion 120 is connected to one end of the first portion 110 along the first direction X, and the second portion 120 is located on one side of the support column 420 along the first direction X. It should be noted that the first electrode structure 100 is a single integral structure; here, for ease of explanation, the first electrode structure 100 is divided into the first portion 110 and the second portion 120. The first portion 110 extends along the first direction X and covers the side surface of the support column 420. For example, the first portion 110 may cover the entire side surface of the support column 420. Exemplarily, when the support column 420 is a cylindrical structure, the first portion 110 may be a cylindrical structure. In the cross-sections of the support column 420 and the first portion 110, the cross-sections are perpendicular to the first direction X, and the first portion 110 is arranged around the support column 420.

[0079] The second part 120 can be perpendicular to the first direction X. For example, the first electrode structure 100 can be a cylindrical structure with a bottom surface, the first part 110 can be a cylindrical structure, and the second part 120 can be the bottom surface of the cylindrical structure. Then, the first part 110 and the second part 120 can enclose a first space 130. The first electrode structure 100 is arranged around the support column 420, so the support column 420 is located in the first space 130 and can fill the first space 130, thereby providing support for the first electrode structure 100. The support column 420 filling the first space 130 prevents the first electrode structure 100 from bending laterally towards the first space 130, which helps improve the structural stability of the first electrode structure 100.

[0080] The dielectric layer 300 is typically a composite layer composed of multiple layers, each with varying insulation capabilities. The first layer formed has the weakest insulation. Forming the dielectric layer 300 on the surfaces of two conductive devices may create electron flow paths within the dielectric layer 300. These electron flow paths can be understood as the trajectories of electrons flowing from one conductive device to another. When the electron flow paths of the two conductive structures are on the same plane, or very close to it, the electron flow path between the two conductive devices becomes too small. Electrons from one conductive device may flow through the dielectric layer to the other, causing leakage. When the two conductive devices are adjacent electrode plates, if the adjacent electrode plates and the electron flow paths are very close to the same plane, resulting in an excessively small electron flow path between the two electrode plates, leakage will occur. Leakage between the two electrode plates will affect the storage function of the capacitor structure, even leading to storage failure and reducing the yield of the semiconductor structure 1000.

[0081] In this embodiment, we continue to refer to Figure 3 , Figure 4 and Figure 5 The support column 420 extends along the first direction X and is connected to the protrusion 4111. The first electrode structure 100 is arranged around the support column 420 and is also located on one side of the protrusion 4111 along the first direction X. Figure 3 As shown, the protrusion 4111 covers the top surface of the first electrode structure 100, and in the first direction X, the first electrode structure 100 can abut against the protrusion 4111.

[0082] A dielectric layer 300 covers a portion of the surface of the first electrode structure 100 facing away from the support pillar 420. The dielectric layer 300 is also located on the surface of the first support layer 410, such as the first surface 411 (including the surface with protrusions 4111) and the second surface 412. Furthermore, the dielectric layer 300 is in contact with the first electrode structure 100 and also with the first support layer 410.

[0083] Please refer to Figure 3 and Figure 6 In section AA, the first electrode structure 100 is arranged around the support pillar 420, and the dielectric layer 300 is arranged around the first electrode structure 100, and the dielectric layer 300 is in contact with the first electrode structure 100. At this time, in section AA, the dielectric layers 300 that are in contact with each of the first electrode structures 100 (conductive devices) are separate from each other.

[0084] Please continue to refer to this. Figure 3 and Figure 7 In the BB section, the dielectric layer 300 is disposed around the protrusion 4111 and is in contact with the protrusion 4111. At this time, in the BB section, the dielectric layers 300 that are in contact with each of the first electrode structures 100 are still separate from each other.

[0085] Please continue to refer to this. Figure 3 and Figure 8 In the CC section, the dielectric layer 300 is disposed around the second electrode structure 200. This can be understood as the dielectric layers 300 disposed around each of the first electrode structures 100 being connected together in the CC section. Assuming leakage occurs between two adjacent first electrode structures 100 through the dielectric layer 300, the bold line in the figure represents a portion of the electron flow path between the two adjacent first electrode structures 100.

[0086] It should be noted that the AA section is the section taken along the second direction Y and the third direction Z to the first electrode structure 100, the BB section is the section taken along the second direction Y and the third direction Z to the protrusion 4111, and the CC section is the section taken along the second direction Y and the third direction Z to the first support layer 410 (excluding the part of the protrusion 4111). The positions marked in the figure are only for illustration.

[0087] Assuming that leakage occurs between two adjacent first electrode structures 100 through the dielectric layer 300, since the dielectric layers 300 surrounding each first electrode structure 100 are separated from each other at cross sections AA and BB, referring to the figure, electrons in one of the first electrode structures 100 flow upward in the dielectric layer 300 along the first direction X to the cross section CC, flow a part of the distance in the dielectric layer 300 of the cross section CC, and continue to flow downward in the dielectric layer 300 along the first direction X to the other first electrode structure 100.

[0088] Therefore, it can be concluded that, for reference Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Figure 9 ,in Figure 8 and Figure 9 The bold black line with arrows illustrates the electron flow path. The electron flow path between two adjacent first electrode structures 100 is extended by two distances. One distance is the distance electrons in one first electrode structure 100 travel upwards along the first direction X in the dielectric layer 300 to the CC section; this distance is equal to the thickness of the protrusion 4111 (the dimension d1 of the protrusion 4111 in the first direction X). The other distance is the distance electrons travel downwards along the first direction X in the dielectric layer 300 to the other first electrode structure 100; this distance is also equal to the thickness of the protrusion 4111. The initially formed dielectric layer 300 has a certain insulating capacity. When the electron flow path is large, or even when the electron flow path is not on the same plane as the first electrode structure 100, it is difficult for the first electrode structure 100 to leak current through the dielectric layer 300 to other conductive devices.

[0089] Even at the CC section, where other conductive devices are in direct contact with the dielectric layer 300, the distance that electrons in the first electrode structure 100 travel in the dielectric layer 300 to flow upward along the first direction X to the CC section is increased.

[0090] In this embodiment, by adding a protrusion 4111 to the first surface 411, the electron flow path between the first electrode structure 100 and other conductive devices is not located on the same plane as the first electrode structure 100. This increases the electron flow path between the first electrode structure 100 and other conductive devices, making it difficult for electrons in the first electrode structure 100 to flow out through the dielectric layer 300. This helps to improve the leakage current between the first electrode structure 100 and other conductive devices through the dielectric layer 300, which is beneficial to improving the storage stability of the capacitor structure C and increasing the yield of the semiconductor structure 1000.

[0091] In some embodiments, such as Figure 4 As shown, the dimension d2 of the protrusion 4111 in the second direction Y is greater than the dimension d3 of the support column 420 in the second direction Y. The second direction Y intersects the first direction X. The embodiments of this disclosure are explained using the example of the second direction Y being perpendicular to the first direction X.

[0092] refer to Figure 3 and Figure 4 The support column 420 extends along the first direction X. Exemplarily, the support column 420 may include a cylindrical structure, a frustum-shaped structure, or a cube. When the support column 420 is a cylindrical or frustum-shaped structure, the dimension d3 of the support column 420 in the second direction Y can be understood as the radial length of the support column 420 in the second direction Y. When the support column 420 is a cubic structure, the dimension d3 of the support column 420 in the second direction Y can be understood as the width of the support column 420 in the second direction Y.

[0093] The dimension d2 of the protrusion 4111 in the second direction Y can be understood as the width of the protrusion 4111 in the second direction Y.

[0094] Continue to refer to Figure 3 and Figure 4 If the dimension d2 of the protrusion 4111 in the second direction Y is greater than the dimension d3 of the support column 420 in the second direction Y, then at the interface connecting the protrusion 4111 and the support column 420, in the second direction Y, the two side edges of the protrusion 4111 extend beyond the two side edges of the support column 420. This can be understood as the orthographic projection of the support column 420 in the first direction X being within the orthographic projection of the protrusion 4111 in the first direction X.

[0095] The above arrangement allows the first electrode structure 100 to be positioned on one side of the protrusion 4111 along the first direction X. At the interface where the protrusion 4111 connects to the support post 420, the portion of the protrusion 4111 extending beyond the support post 420 in the second direction Y can abut against the first electrode structure 100.

[0096] Furthermore, through the above arrangement, since the first electrode structure 100 is disposed on one side of the protrusion 4111 along the first direction X, the electron flow path between the first electrode structure 100 and other conductive devices is not located on the same plane as the first electrode structure 100, thereby increasing the electron flow path between the first electrode structure 100 and other conductive devices. This is beneficial to improving the leakage current generated between the first electrode structure 100 and other conductive devices through the dielectric layer 300, which is beneficial to improving the storage stability of the capacitor structure C and improving the yield of the semiconductor structure 1000.

[0097] In some embodiments, reference Figure 3 , Figure 4 and Figure 5 The sidewall of protrusion 4111 is flush with the sidewall of the first electrode structure 100 in the first direction X, that is, the sidewall of protrusion 4111 is flush with and aligned with the sidewall of the first electrode structure 100 in the first direction X. This can be understood as the sidewall of protrusion 4111 and the sidewall of the first electrode structure 100 being located on the same plane or the same curved surface. At this time, the orthographic projection of protrusion 4111 in the first direction X coincides with the orthographic projection of the first electrode structure 100 in the first direction X.

[0098] For example, when the sidewall of the first electrode structure 100 is curved, the sidewall of the protrusion 4111 is also curved. The radial length of the first electrode structure 100 is equal to the radial length of the protrusion 4111, and the central axis of the first electrode structure 100 coincides with the central axis of the protrusion 4111, so that the sidewall of the first electrode structure 100 and the sidewall of the protrusion 4111 are continuously flat and aligned in the first direction X, so that the sidewall of the first electrode structure 100 and the sidewall of the protrusion 4111 are located on the same curved surface.

[0099] For example, when the sidewall of the first electrode structure 100 is a plane, the sidewall of the protrusion 4111 is also a plane, and the sidewall of the first electrode structure 100 and the sidewall of the protrusion 4111 are located in the same plane.

[0100] In this embodiment, the sidewall of the first electrode structure 100 is aligned with the sidewall of the protrusion 4111 in the first direction X, so all the first electrode structures 100 are located on one side of the protrusion 4111 along the first direction X. Therefore, the electron flow path of the first electrode structure 100 through the dielectric layer 300 is not located on the same plane as the first electrode structure 100, thereby increasing the electron flow path between the first electrode structure 100 and other conductive devices. This makes it difficult for electrons in the first electrode structure 100 to flow out through the dielectric layer 300, which helps to improve the leakage current between the first electrode structure 100 and other conductive devices through the dielectric layer 300, and helps to improve the storage stability of the capacitor structure C and the yield of the semiconductor structure 1000.

[0101] In some embodiments, reference Figure 3 The shape of the orthographic projection of the protrusion 4111 in the first direction X is the same as the shape of the orthographic projection of the first electrode structure 100 in the first direction X. For example, the orthographic projection of the protrusion 4111 in the first direction X can be a circle, and in this case, the shape of the orthographic projection of the first electrode structure 100 in the first direction X can also be a circle.

[0102] Furthermore, when the orthographic projection of the protrusion 4111 in the first direction X has the same shape and the edges coincide with the orthographic projection of the first electrode structure 100 in the first direction X, the sidewall of the protrusion 4111 is flush with the sidewall of the first electrode structure 100 in the first direction X. Therefore, the electron flow path of the electrons in the first electrode structure 100 flowing through the dielectric layer 300 will pass through the sidewall of the protrusion 4111, thereby increasing the electron flow path between the first electrode structure 100 and other conductive devices. This makes it difficult for electrons in the first electrode structure 100 to flow out through the dielectric layer 300, which is beneficial to improving the leakage current between the first electrode structure 100 and other conductive devices through the dielectric layer 300. This is beneficial to improving the storage stability of the capacitor structure C and improving the yield of the semiconductor structure 1000.

[0103] In some embodiments, reference Figure 3 The dielectric layer 300 covers the sidewall of the first electrode structure 100. In the direction from the support pillar 420 to the first support layer 410, a portion of the dielectric layer 300 extends beyond the first electrode structure 100. Here, it can be understood that the end face of the first electrode structure 100 furthest from the protrusion 4111 is taken as the lowest plane. In this embodiment, the dielectric layer 300 extends above the first electrode structure 100 in the first direction X.

[0104] The direction from the support column 420 to the first support layer 410 is also the direction from the first electrode structure 100 to the protrusion 4111. The first electrode structure 100 is also located on one side of the protrusion 4111 along the first direction X, so the portion of the dielectric layer 300 extending beyond the first electrode structure 100 can cover the sidewall of the protrusion 4111.

[0105] With the above configuration, part of the dielectric layer 300 also covers the sidewall of the protrusion 4111. Therefore, the electron flow path of the first electrode structure 100 through the dielectric layer 300 also passes through the dielectric layer 300 covering the sidewall of the protrusion 4111, thereby increasing the electron flow path between the first electrode structure 100 and other conductive devices. This makes it difficult for electrons in the first electrode structure 100 to flow out through the dielectric layer 300, which helps to improve the leakage current between the first electrode structure 100 and other conductive devices through the dielectric layer 300. This also helps to improve the storage stability of the capacitor structure C and improve the yield of the semiconductor structure 1000.

[0106] In some embodiments, such as Figure 3 , Figure 4 and Figure 5 As shown, the first electrode structure 100 is arranged around the support column 420, which can be a cylindrical structure. The thickness of the first electrode structure 100 is the same along the circumference of the support column 420.

[0107] The above-described configuration helps maintain the consistency of the morphology of the first electrode structure 100, preserves its electrical properties, and improves its structural stability. Furthermore, since the first electrode structure 100 is located on one side of the protrusion 4111 along the first direction X, it can contact the protrusion 4111. In this case, the thickness of the first electrode structure 100 is uniform along the circumference of the support column 420, which facilitates contact and adhesion between the first electrode structure 100 and the protrusion 4111, thereby improving the stability of the semiconductor structure 1000.

[0108] In some embodiments, such as Figure 10 As shown, the cross-sectional shape of the second electrode structure 200 on the reference plane includes a circle, and the reference plane is the plane containing the second surface 412. The reference plane is perpendicular to the first direction X.

[0109] In this embodiment, reference Figure 3 and Figure 10 On the cross-section of the first support layer 410 excluding the protrusion 4111, the cross-section is perpendicular to the first direction X. The cross-sectional shape of the second electrode structure 200 is consistent with the cross-sectional shape on the reference surface, both including a circle.

[0110] refer to Figure 9 and Figure 10 When the cross-sectional shape of the second electrode structure 200 is circular, the dielectric layer 300 is disposed around the second electrode structure 200. For electrons in the first electrode structure 100 to flow through the dielectric layer 300 to another conductive device, they need to flow through an arc-shaped path within the dielectric layer 300 on this cross-section. The height position of this arc-shaped path in the first direction X is separate from the height position of the first electrode structure 100 in the first direction X; that is, this arc-shaped path is not on the same plane as the first electrode structure 100.

[0111] The above configuration helps to increase the electron flow path of electrons in the first electrode structure 100 through the dielectric layer 300, making it difficult for electrons in the first electrode structure 100 to flow out through the dielectric layer 300. This helps to improve the leakage current between the first electrode structure 100 and other conductive devices through the dielectric layer 300, improves the storage stability of the capacitor structure C, and increases the yield of the semiconductor structure 1000.

[0112] In some embodiments, such as Figure 3 As shown, the semiconductor structure 1000 further includes a second support layer 510 and a third support layer 520, both of which are perpendicular to the first direction X. The second support layer 510 is located between the first support layer 410 and the third support layer 520. The first electrode structure 100 extends through the second support layer 510 and the third support layer 520 along the first direction X.

[0113] The materials of the second support layer 510 and the third support layer 520 can be the same as the material of the first support layer 410.

[0114] In this embodiment, the second support layer 510 and the third support layer 520 can support the first electrode structure 100. Additionally, the dielectric layer 300 can cover the surfaces of the second support layer 510 and the third support layer 520. The second electrode structure 200 can be located on the side of the dielectric layer 300 facing away from the second support layer 510, and also on the side of the dielectric layer 300 facing away from the third support layer 520. The second support layer 510 and the third support layer 520 can also support the dielectric layer 300 and the second electrode structure 200. This arrangement helps prevent the capacitor structure C from bending laterally, thereby improving the structural stability of the semiconductor structure 1000.

[0115] In some embodiments, such as Figure 3 , Figure 6 , Figure 7 and Figure 8 As shown, the second electrode structure 200 includes an electrode layer 210 and a conductive structure 220, with the electrode layer 210 located between the conductive structure 220 and the dielectric layer 300. Exemplarily, the electrode layer 210 may be located on the side of the dielectric layer 300 opposite to the first electrode structure 100, on the side of the dielectric layer 300 opposite to the first support layer 410, on the side of the dielectric layer 300 opposite to the second support layer 510, and on the side of the dielectric layer 300 opposite to the third support layer 520.

[0116] The material of electrode layer 210 can be the same as that of the first electrode structure 100. The material of electrode layer 210 can be the same as or different from that of conductive structure 220. For example, electrode layer 210 can be made of a different material than conductive structure 220, such as using a cheaper material to make conductive structure 220, in order to reduce the production cost of semiconductor structure 1000.

[0117] The conductive structure 220 includes interconnected conductive pillars 221 and extension layers 222. The conductive pillars 221 penetrate the first support layer 410 and the second support layer 510 along a first direction X, and extend to the side of the third support layer 520 near the second support layer 510. The conductive pillars 221 do not penetrate the third support layer 520. The conductive pillars 221 and the extension layers 222 can be an integral structure, which is beneficial to improving the structural stability of the conductive structure 220.

[0118] A portion of the extension layer 222 is located between the first support layer 410 and the second support layer 510, and a portion of the extension layer 222 is located between the second support layer 510 and the third support layer 520. Exemplarily, the portion of the extension layer 222 may completely fill the space enclosed by the electrode layer 210 located between the first support layer 410 and the second support layer 510. The portion of the extension layer 222 may also completely fill the space enclosed by the electrode layer 210 located between the second support layer 510 and the third support layer 520.

[0119] With the above configuration, voltage can be applied to the electrode layer 210 by applying voltage to the conductive structure 220. The conductive structure 220 has a larger volume, making it easier to extract and receive electrical signals. In addition, part of the conductive structure 220 extends between the first support layer 410 and the second support layer 510, and between the second support layer 510 and the third support layer 520, thereby helping to fill and support the semiconductor structure 1000, providing support for the capacitor structure C, preventing the capacitor structure C from bending, and improving the structural stability of the semiconductor structure 1000.

[0120] In some embodiments, such as Figure 3 , Figure 6 , Figure 7 and Figure 8 As shown, a portion of dielectric layer 300 is located between extension layer 222 and first support layer 410, a portion of dielectric layer 300 is located between extension layer 222 and second support layer 510, a portion of dielectric layer 300 is located between extension layer 222 and third support layer 520, and a portion of dielectric layer 300 is located between conductive pillar 221 and third support layer 520. A portion of second electrode structure 200 is located between extension layer 222 and dielectric layer 300.

[0121] In this embodiment, the dielectric layer 300 located between the extension layer 222 and the first support layer 410 is separated from the height of the first electrode structure 100, that is, the dielectric layer 300 located between the extension layer 222 and the first support layer 410 is higher than the first electrode structure 100.

[0122] With the above configuration, the electron flow path of the first electrode structure 100 through the dielectric layer 300 is not on the same plane as the first electrode structure 100. This helps to increase the electron flow path of the first electrode structure 100 through the dielectric layer 300, making it difficult for electrons in the first electrode structure 100 to flow out through the dielectric layer 300. This helps to improve the leakage current between the first electrode structure 100 and other conductive devices through the dielectric layer 300, and helps to improve the storage stability of the capacitor structure C and improve the yield of the semiconductor structure 1000.

[0123] In some embodiments, such as Figure 3 and Figure 10 As shown, the semiconductor structure 1000 includes a plurality of first electrode structures 100, which are arranged around the conductive pillar 221 and are spaced apart from each other.

[0124] Exemplarily, multiple first electrode structures 100 can be disposed in the same layer. It should be noted that "disposed in the same layer" means that multiple patterns are on the same pattern layer. A pattern layer refers to a film layer formed through a single patterning process. A patterning process refers to a process capable of forming at least one pattern with a certain shape. For example, a thin film is formed on a substrate using any of various film deposition processes such as deposition, coating, or sputtering, and then the thin film is patterned to form a film layer containing at least one pattern; this is called a pattern layer. The patterning steps include: coating photoresist, exposure, development, etching, and photoresist stripping. In this embodiment, the positional relationship of multiple patterns belonging to the same pattern layer is referred to as "disposed in the same layer."

[0125] In this embodiment, multiple first electrode structures 100 are arranged around the conductive post 221 at intervals, so one conductive post 221 can provide support for multiple first electrode structures 100, thereby improving the utilization rate of the conductive post 221.

[0126] Furthermore, multiple first electrode structures 100 can be arranged in the same layer, and multiple first electrode structures 100 can be fabricated in one process step, thereby simplifying the fabrication process of semiconductor structure 1000, improving the fabrication efficiency of semiconductor structure 1000, and reducing the fabrication cost of semiconductor structure 1000.

[0127] In addition, setting multiple first electrode structures 100 can also improve the charge storage capacity of the capacitor structure C, thereby increasing the storage capacity of the semiconductor structure 1000.

[0128] In some embodiments, such as Figure 3 As shown, the semiconductor structure 1000 also includes a plurality of transistors T, which are stacked with a plurality of first electrode structures 100 along a first direction X, and one transistor T is connected to one first electrode structure 100.

[0129] For example, a transistor T and a first electrode structure 100 can be electrically connected via a conductive contact structure 800. The conductive contact structure 800 is disposed between the channel post of the transistor T and the first electrode structure 100.

[0130] The conductive contact structure 800 has a conductive function, thereby electrically connecting the channel pillar of the transistor T to the capacitor structure C. Exemplarily, the material of the conductive contact structure 800 can be a metal. In some embodiments, the conductive contact structure 800 can be a single-layer structure formed of one of the following materials: tungsten, aluminum, copper, silver, cobalt, platinum, nickel, titanium, tantalum, titanium nitride, tantalum nitride, titanium silicide, tantalum silicide, or tungsten silicide, or a stacked structure formed of two or more of the above materials, such as a double-layer stacked structure 600 consisting of a titanium nitride layer and a tungsten layer located on top of the titanium nitride layer.

[0131] As can be seen from some of the embodiments mentioned above, the gate of transistor T is connected to the word line, the drain of transistor T is connected to the bit line, and the source of transistor T is connected to the capacitor structure C. The voltage signal on the word line can control the transistor T to turn on or off, thereby reading the data information stored in the capacitor structure C through the bit line, or writing the data information into the capacitor structure C for storage through the bit line.

[0132] This disclosure also provides a method for fabricating a semiconductor structure 1000 in some embodiments, which is described below in conjunction with... Figures 11 to 18 The fabrication method of semiconductor structure 1000 is explained.

[0133] like Figure 11 As shown, the method for fabricating the semiconductor structure 1000 includes: S1 to S2.

[0134] S1. A support structure is formed, the support structure including a first support layer and a support column. The first support layer has a first surface and a second surface arranged along a first direction. The first surface is closer to the support column than the second surface. The first surface has a protrusion. The support column extends along the first direction and is connected to the protrusion. The first direction is parallel to the thickness direction of the first support layer.

[0135] refer to Figure 12 In this step, a stacked structure 600 can be formed on the substrate 670. The stacked structure 600 includes a plurality of support layers 500 and a plurality of sacrificial layers 610 alternately stacked along the first direction X.

[0136] For example, multiple support layers 500 and multiple sacrificial layers 610 can be formed in an alternating stacked manner through a deposition process. The deposition process includes, but is not limited to, one or more thin film deposition processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0137] The term "alternating layering" refers to forming a support layer 500, then forming a sacrificial layer 610 on top of the support layer 500, followed by forming another support layer 500 on top of the sacrificial layer 610, and so on. It should be noted that in this step, the first support layer 500 formed is the third support layer 520.

[0138] The thicknesses of the multiple support layers 500 can be the same or different, and the thicknesses of the multiple sacrificial layers 610 can also be the same or different. The thicknesses of the support layers 500 and the sacrificial layers 610 can be set according to specific process requirements. Since the sacrificial layer 610 will be removed in subsequent process steps, the material of the sacrificial layer 610 is different from the material of the support layers 500. For example, the material of the support layer 500 can be a chemically inert material, such as a nitride or silicon nitride oxide; the material of the sacrificial layer 610 can be an oxide, such as silicon oxide.

[0139] Furthermore, the support layer 500 formed through the above steps exhibits high chemical stability and etching resistance, serving as a support and resisting erosion by the etching solution. The stacked structure 600 in this step can be directly formed on the transistor T structure layer, which includes multiple transistors T. Forming a third support layer 520 on the transistor T structure layer serves as a protective layer. The third support layer 520 covers the transistor T structure layer, effectively protecting the transistor T structure layer below it from erosion by the etching solution.

[0140] refer to Figure 12 and Figure 13 After the stacked structure 600 is formed, a first structural hole 620 can be formed, which penetrates the stacked structure 600 along the first direction X.

[0141] For example, a patterned mask layer (such as a patterned photoresist layer) can be formed on the stacked structure 600. This mask layer can be formed, for example, sequentially using a coating process, an exposure process, and a development process. Subsequently, using the mask layer, a portion of the stacked structure 600 is removed to form the second structural aperture 630. In some examples, a dry etching process can be used to remove a portion of the stacked structure 600. In other examples, other processes capable of removing the stacked structure 600, such as wet etching, can also be used for removal; no specific limitation is made in this regard.

[0142] After the first structural hole 620 is formed, the mask layer can be removed by chemical mechanical polishing (CMP).

[0143] After removing the mask layer, refer to Figure 13 , Figure 14 and Figure 15 A first electrode structure 100 can be formed in the first structural hole 620. The first electrode structure 100 covers the bottom and part of the hole wall of the first structural hole 620, and the first electrode structure 100 surrounds the second structural hole 630.

[0144] For example, in this step, electrode material can be deposited in the first structural hole 620 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a first electrode layer 640, which covers the bottom and walls of the first structural hole 620. A portion of the first electrode layer 640 is removed by chemical mechanical polishing to form a first electrode structure 100, in which a portion of the sacrificial layer 610 extends beyond the first electrode structure 100 in the first direction X. Here, it can be understood that, with the third support layer 520 as the lowest plane, the portion of the sacrificial layer 610 is higher than the first electrode structure 100.

[0145] After the first electrode structure 100 is formed, insulating material can be deposited within the second structural aperture 630 and on the stacked structure 600 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form the support pillar 420 and the first support layer 410. The insulating material located within the second structural aperture 630 can form the support pillar 420, which extends along the first direction X, and the first electrode structure 100 is disposed around the support pillar 420. The insulating material located above the stacked structure 600 and the first electrode structure 100 can form the first support layer 410, which has a first surface 411 and a second surface 412 arranged along the first direction X. The first surface 411 is closer to the support pillar 420 than the second surface 412, and the first surface 411 has a protrusion 4111 connected to the support pillar 420. The sacrificial layer 610 is disposed around the protrusion 4111, which is located on one side of the first electrode structure 100 along the first direction X.

[0146] The material of the support column 420 is the same as that of the first support layer 410. For example, both the material of the support column 420 and the material of the first support layer 410 include silicon nitride.

[0147] In this step, the support pillar 420 and the first support layer 410 are formed through a single deposition process, which simplifies the fabrication steps of the semiconductor structure 1000 and also helps to improve the connection between the support pillar 420 and the first support layer 410. Furthermore, the support pillar 420 extends into and completely fills the space enclosed by the first electrode structure 100, which helps to prevent the first electrode structure 100 from bending, thereby improving the stability of the semiconductor structure 1000.

[0148] In addition, the materials of the support pillar 420 and the first support layer 410 can be silicon nitride, which is inexpensive and helps to reduce the production cost of the semiconductor structure 1000.

[0149] S2. A capacitor structure is formed, which includes a first electrode structure, a dielectric layer, and a second electrode structure. The dielectric layer is located between the first electrode structure and the second electrode structure. The capacitor structure is arranged around a support pillar. The first electrode structure is located between the dielectric layer and the support pillar. In the extension direction of the support pillar, part of the support pillar is located between the first electrode structure and the first support layer.

[0150] refer to Figure 15 and Figure 16 In this step, a dry etching process or a wet etching process can be used to remove part of the first support layer 410 to form the third structural hole 660. The third structural hole 660 penetrates the first support layer 410 to the sacrificial layer 610 along the first direction X.

[0151] Part of the sacrificial layer 610 is removed through the third structural hole 660, for example by injecting an etching solution into the third structural hole 660, or by immersing the entire structure in the etching solution to form a first filling space 710, which is connected to the third structural hole 660.

[0152] refer to Figure 16 and Figure 17 Continue to remove part of the support layer 500 and the sacrificial layer 610 through the third structural hole 660 to form the second filling space 720. The second filling space 720 is connected to the third structural hole 660. The third structural hole 660, the first filling space 710 and the second filling space 720 together constitute the filling space 700.

[0153] refer to Figure 16 , Figure 17 and Figure 18 After removing the sacrificial layer 610 and part of the support layer 500 to form the filling space 700, dielectric material, electrode material and conductive material can be sequentially deposited in the filling space 700 by using one or more thin film deposition processes including but not limited to PVD, CVD and ALD to form dielectric layer 300, second electrode layer 650 and conductive structure 220. The second electrode layer 650 and conductive structure 220 together constitute the second electrode structure 200.

[0154] The material of the second electrode layer 650 and the material of the conductive structure 220 can be the same or different.

[0155] For example, the dielectric material may include a high-k dielectric material to increase the capacitance value per unit area of ​​the capacitor structure C. In specific embodiments, the dielectric material may include, for example, HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO.

[0156] For example, the electrode material may include W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, WSi, or other suitable conductive materials.

[0157] For example, the conductive material includes, but is not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, or other suitable conductive materials.

[0158] The semiconductor structure 1000 prepared by the above steps increases the electron flow path between the first electrode structure 100 and other conductive devices by adding protrusions 4111 to the first surface 411, so that the electron flow path between the first electrode structure 100 and other conductive devices is not located on the same plane as the first electrode structure 100. This helps to improve the leakage current between the first electrode structure 100 and other conductive devices through the dielectric layer 300, which helps to improve the storage stability of the capacitor structure C and improve the yield of the semiconductor structure 1000.

[0159] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A support structure includes a first support layer and a support column. The first support layer has a first surface and a second surface arranged along a first direction. The first surface is closer to the support column than the second surface. The first surface has a protrusion. The support column extends along the first direction and is connected to the protrusion. The first direction is the thickness direction of the first support layer. A capacitor structure includes a first electrode structure, a dielectric layer, and a second electrode structure, wherein the dielectric layer is located between the first electrode structure and the second electrode structure; the capacitor structure is disposed around the support post, the first electrode structure is located between the dielectric layer and the support post, and the first electrode structure is also located on one side of the protrusion along the first direction.

2. The semiconductor structure according to claim 1, characterized in that, The protrusion is larger in size in the second direction than the support column in the second direction, and the second direction intersects the first direction.

3. The semiconductor structure according to claim 2, characterized in that, The protruding sidewall is flush with the sidewall of the first electrode structure in the first direction.

4. The semiconductor structure according to claim 2, characterized in that, The orthographic projection shape of the protrusion in the first direction is the same as the orthographic projection shape of the first electrode structure in the first direction.

5. The semiconductor structure according to claim 1, characterized in that, In the direction from the support pillar toward the first support layer, a portion of the dielectric layer extends beyond the first electrode structure.

6. The semiconductor structure according to claim 1, characterized in that, The thickness of the first electrode structure is the same along the circumference of the support column.

7. The semiconductor structure according to claim 1, characterized in that, The cross-sectional shape of the second electrode structure on the reference plane includes a circle, and the reference plane is the plane on which the second surface is located.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: a second support layer and a third support layer, both of which are perpendicular to the first direction, and the second support layer is located between the first support layer and the third support layer; The first electrode structure extends through the second support layer and the third support layer along the first direction.

9. The semiconductor structure according to claim 8, characterized in that, The second electrode structure includes an electrode layer and a conductive structure. The electrode layer is located between the conductive structure and the dielectric layer. The conductive structure includes interconnected conductive pillars and an extension layer. The conductive pillars penetrate the first support layer and the second support layer along the first direction and extend to the side of the third support layer near the second support layer. Part of the extension layer is located between the first support layer and the second support layer, and part of the extension layer is located between the second support layer and the third support layer.

10. The semiconductor structure according to claim 9, characterized in that, A portion of the dielectric layer is located between the extension layer and the first support layer, a portion of the dielectric layer is located between the extension layer and the second support layer, a portion of the dielectric layer is located between the extension layer and the third support layer, and a portion of the dielectric layer is located between the conductive pillar and the third support layer; A portion of the second electrode structure is located between the extended layer and the dielectric layer.

11. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure includes a plurality of first electrode structures arranged around the conductive pillar.

12. The semiconductor structure according to any one of claims 1-11, characterized in that, The semiconductor structure further includes a plurality of transistors, which are stacked with the plurality of first electrode structures along the first direction, and one transistor is connected to one of the first electrode structures.

13. A method for fabricating a semiconductor structure, characterized in that, include: A support structure is formed, the support structure including a first support layer and a support column, the first support layer having a first surface and a second surface arranged along a first direction, the first surface being closer to the support column than the second surface, the first surface having a protrusion, the support column extending along the first direction and the support column being connected to the protrusion, the first direction being parallel to the thickness direction of the first support layer; A capacitor structure is formed, the capacitor structure including a first electrode structure, a dielectric layer and a second electrode structure, the dielectric layer being located between the first electrode structure and the second electrode structure; the capacitor structure is arranged around the support pillar, the first electrode structure being located between the dielectric layer and the support pillar, and in the extending direction of the support pillar, a portion of the support pillar is located between the first electrode structure and the first support layer.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The formation of the support structure includes: A stacked structure is formed, the stacked structure comprising a plurality of support layers and a plurality of sacrificial layers alternately stacked along the first direction; A first structural hole is formed, and the first structural hole penetrates the stacked structure along the first direction; A first electrode structure is formed, which covers the bottom and part of the wall of the first structural hole, and the first electrode structure encloses a second structural hole. Insulating material is deposited within the second structural hole and on the stacked structure to form a support pillar and a first support layer.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, The formation of the first electrode structure includes: A first electrode layer is formed, which covers the bottom and wall of the first structural hole; A portion of the first electrode layer is removed to form a first electrode structure, wherein, in the first direction, a portion of the sacrificial layer extends beyond the first electrode structure.

16. The method for preparing a semiconductor structure according to claim 14, characterized in that, The formation of the capacitor structure includes: Remove the sacrificial layer and part of the support layer to form a filling space; Dielectric material, electrode material, and conductive material are sequentially deposited in the filled space to form a dielectric layer, a second electrode layer, and a conductive structure. The second electrode layer and the conductive structure together constitute the second electrode structure.

17. The method for preparing a semiconductor structure according to claim 16, characterized in that, The formation of the filling space includes: A third structural hole is formed, which penetrates the first support layer to the sacrificial layer along the first direction; A portion of the sacrificial layer is removed through the third structural hole to form a first filling space, which is connected to the third structural hole. A portion of the support layer and the sacrificial layer are removed through the third structural hole to form a second filling space. The second filling space is connected to the third structural hole, and the third structural hole, the first filling space, and the second filling space together constitute the filling space.

18. A storage system, characterized in that, include: The semiconductor structure according to any one of claims 1-12; A controller, the control being coupled to the semiconductor structure, to control the semiconductor structure to store data.

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