Transistor, preparation method thereof, display panel and display device
By doping the initial active layer before forming the gate layer, and by precisely controlling the doping region using the insulating and barrier layers, the problem of inaccurate transistor doping in high PPI display devices is solved, thereby improving transistor performance and signal transmission stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- KUNSHAN GO VISIONOX OPTO ELECTRONICS CO LTD
- Filing Date
- 2026-03-31
- Publication Date
- 2026-07-10
AI Technical Summary
In high PPI display devices, insufficiently precise doping of the source and drain regions of transistors can affect transistor performance.
Before forming the gate layer, the initial active layer is doped. By setting a first insulating layer and a barrier layer on the substrate, the doping region is precisely controlled to form a first implantation region, a channel region, and a second implantation region, ensuring that the doping is not affected by the gate layer.
It improves the conductivity and driving capability of transistors to meet the needs of high PPI display devices, increases the number of sub-pixels, and improves signal transmission stability.
Smart Images
Figure CN122373390A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to a transistor and its fabrication method, a display panel, and a display device. Background Technology
[0002] A transistor (Thin Film Transistor, or TFT for short) is a switching element in various display devices. It is mainly used to control the emission of light from sub-pixels in the display device, thereby enabling the display device to display images of different colors. In related technologies, the source and drain regions of the transistor need to be doped during the fabrication process to improve the transistor's conductivity.
[0003] With the development of technology, in order to further improve the fineness of the displayed image, the number of sub-pixels in the display device has increased, that is, high PPI (Pixel Per Pitch) has emerged. This has led to an increase in the number of transistors designed per unit area, resulting in a reduction in the size of a single transistor. In related processes, when doping the source and drain regions, doping is generally carried out by blocking the gate of the transistor, but this can lead to insufficient doping precision and affect the performance of the transistor. Summary of the Invention
[0004] This invention provides a transistor and its fabrication method, a display panel, and a display device to improve the technical problem of insufficient doping precision in transistors, thereby enhancing transistor performance.
[0005] In a first aspect, this application provides a method for fabricating a transistor, comprising the following steps: providing a substrate; forming an initial active layer on one side of the substrate; doping the initial active layer to form an active layer; and forming a gate layer on the side of the active layer away from the substrate; wherein the step of doping the initial active layer is performed before the step of forming the gate layer.
[0006] In some embodiments, prior to the step of forming an initial active layer on one side of the substrate, the method further includes: A first insulating layer is formed on one side of the substrate, wherein a first opening is provided on the first insulating layer; In the step of forming an initial active layer on one side of the substrate, a portion of the initial active layer is located within the first opening, and a portion of the initial active layer is located on the side of the first insulating layer away from the substrate.
[0007] In some embodiments, prior to the step of doping the initial active layer, the method further includes: forming a barrier layer within the first opening on at least a portion of the initial active layer on the side away from the first opening sidewall.
[0008] In some embodiments, the step of doping the initial active layer to form an active layer includes: doping the initial active layer such that at least a portion of the initial active layer located on the side of the first insulating layer away from the substrate forms a first implantation region, at least a portion of the initial active layer located on the sidewall side of the first opening forms a channel region, and the orthogonal projection of the channel region on the substrate at least partially overlaps with the orthogonal projection of the barrier layer on the substrate, and at least a portion of the initial active layer not covered by the barrier layer within the first opening forms a second implantation region; the first implantation region, the channel region, and the second implantation region constitute an active layer.
[0009] In some embodiments, the material of the first insulating layer is SiN. X One of SiO2 or l2O3.
[0010] In some embodiments, the thickness of the first insulating layer is 0.05 micrometers to 0.5 micrometers.
[0011] In some embodiments, prior to the step of forming a gate layer on the side of the active layer away from the substrate, the method further includes removing a barrier layer.
[0012] In some embodiments, the first insulating layer includes a sidewall facing the first opening and a bottom wall facing the substrate side, the angle between the sidewall and the bottom wall being 50°-130°.
[0013] In some embodiments, prior to the step of forming a first insulating layer on one side of the substrate, the method further includes: forming a first conductive electrode on one side of the substrate; After the step of forming a first insulating layer on one side of the substrate, the method includes: forming a second conductive electrode on the side of the first insulating layer away from the substrate; the second conductive electrode has a second opening, the orthographic projection of the second opening on the substrate at least partially overlapping the orthographic projection of the first opening on the substrate; and a portion of the first conductive electrode is exposed through the first opening. In the step of forming an initial active layer on one side of the substrate, a portion of the initial active layer is located within the first opening and is connected to the first conductive electrode.
[0014] In some embodiments, in the step of doping the initial active layer to form an active layer, at least a portion of the initial active layer located on the side of the second conductive electrode away from the substrate forms a first implantation region, and at least a portion of the initial active layer not covered by the barrier layer within the first opening forms a second implantation region, and the second implantation region is connected to the first conductive electrode.
[0015] In some embodiments, the step of forming a barrier layer on at least a portion of the initial active layer on the side away from the first opening sidewall includes: forming barrier layers on both the side of the initial active layer away from the first opening sidewall and the side away from the second opening sidewall.
[0016] In some embodiments, the step of forming a barrier layer on at least a portion of the initial active layer on the side away from the first opening sidewall further includes: An initial barrier layer is formed on the side of the initial active layer away from the substrate; the orthographic projection of the initial barrier layer on the substrate covers the orthographic projection of the initial active layer on the substrate. The initial barrier layer is patterned to form a barrier layer.
[0017] In some embodiments, the material of the initial barrier layer includes photoresist.
[0018] In some embodiments, the thickness of the initial barrier layer is 0.5 micrometers to 3 micrometers.
[0019] In some embodiments, prior to the step of doping the initial active layer, the method further includes: A second insulating layer is formed on the side of the initial active layer away from the substrate; at the first opening, a barrier layer is formed on the side of the second insulating layer away from the sidewall of the first opening. In some embodiments, before the step of forming a barrier layer on the side of the second insulating layer away from the first opening sidewall, the method further includes: forming an initial barrier layer on the side of the second insulating layer away from the substrate; The initial barrier layer is patterned to form a barrier layer.
[0020] In some embodiments, the material of the initial barrier layer includes photoresist.
[0021] In some embodiments, the thickness of the initial barrier layer is 0.5 micrometers to 3 micrometers.
[0022] In some embodiments, the step of doping the initial active layer to form an active layer includes: the ions used to dope the initial active layer include boron, phosphorus, hydrogen, etc.
[0023] In some embodiments, the ion doping concentration in the channel region is less than or equal to 1 / 2000 of the ion doping concentration in the first implantation region; or, the ion doping concentration in the channel region is less than or equal to 1 / 2000 of the ion doping concentration in the second implantation region.
[0024] In some embodiments, the active layer material includes a metal oxide semiconductor, wherein the metal oxide includes at least one of indium, zinc, gallium, tin, titanium, aluminum, hafnium, zirconium, or magnesium.
[0025] Secondly, this application provides a transistor, including a transistor fabricated by any of the methods described above.
[0026] Thirdly, this application provides a display panel including an array substrate, the array substrate including transistors fabricated by any of the transistor fabrication methods described above.
[0027] Fourthly, this application provides a display device including the aforementioned display panel.
[0028] This application sets the step of doping the initial active layer before the step of forming the gate layer, that is, doping is performed without using the gate layer as a barrier. The area of the gate layer formed subsequently can be relatively large, thereby ensuring that the performance of the transistor is not affected by the reduction of the transistor size. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1 This is a schematic flowchart of a transistor fabrication method provided in an embodiment of the present invention; Figures 2a-2h This is a schematic diagram of the fabrication process of a transistor provided in an embodiment of the present invention; Figure 3 A top view of a transistor structure provided in an embodiment of the present invention; Figure 4 for Figure 3 A schematic diagram of a cross-sectional structure of region A along BB; Figure 5 for Figure 3 A schematic diagram of another cross-sectional structure of region A along BB; Figure 6 for Figure 3 A schematic diagram of another cross-sectional structure of region A along BB; Figures 7a-7e A schematic diagram of another transistor fabrication process provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 9 This is a partial cross-sectional structural diagram of a display panel provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention.
[0031] Explanation of reference numerals in the attached figures: 100. Substrate; 200. First conductive electrode; 300, First insulating layer; 300a, Initial first insulating layer; 400a, Initial second metal layer; 410, Second conductive electrode; 420, First electrode plate; 500a, Initial active layer; 500, Active layer; 510, First injection region; 520, Channel region; 530, Second injection region; 600. Second insulation layer; 700, Gate layer; 710, Second electrode plate; 810. First planarization layer; 820. Second planarization layer; 900, pixel-limited layer; 1100, First electrode; 1200, Light-emitting layer; 1300, Second electrode 2100, First encapsulation layer; 2200, Second encapsulation layer; 2300, Third encapsulation layer; 2400a initial barrier layer, 2400, barrier layer; Display area AA; Non-display area NA; Sub-pixel SPX; First sub-pixel SPX1; Second sub-pixel SPX2; Third sub-pixel SPX3; 10. Display panel; 1. Display device. Detailed Implementation
[0032] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.
[0033] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0035] A thin-film transistor (TFT) is a switching element in various display devices, mainly used to control the emission of light from sub-pixels in the display device, thereby enabling the display device to display images of different colors. In related technologies, the source and drain regions of a transistor need to be doped during fabrication to improve its conductivity. With the development of technology, in order to further improve the detail of the displayed image, the number of sub-pixels in the display device has increased, that is, high PPI (Pixels Per Pitch) has emerged, which increases the number of transistors designed per unit area, resulting in a reduction in the size of a single transistor. In related processes, when doping the source and drain regions, doping is generally performed by blocking the gate of the transistor, but this can lead to insufficient doping precision and affect the performance of the transistor.
[0036] To address the aforementioned problems, this application provides a transistor and its fabrication method, a display panel, and a display device. The following will combine Figures 1-10 This application describes a transistor, its fabrication method, a display panel, and a display device provided in its embodiments.
[0037] Combination Figure 1 - Figure 7e This application provides a method for fabricating a transistor, comprising: Step S100: Provide substrate 100; Substrate 100 can provide support for the remaining structural layers subsequently formed. In some examples, substrate 10 can be a rigid substrate, for example, the material of substrate 100 can be glass. In other examples, substrate 100 can be a flexible substrate, and the material of substrate 100 can include at least one of polyimide (PI), polyethylene terephthalate, polyethylene naphthalate, polyethylene, polyacrylate, polyetherimide, polycarbonate, polyarylate, polyethersulfone, silicon nitride, silicon oxide, and silicon oxynitride.
[0038] In some embodiments, the substrate 100 may include a multilayer stacked structure, for example, a multilayer stacked structure formed by stacking at least one layer of polyimide and at least one layer of silicon oxide.
[0039] Step S200: An initial active layer is formed on one side of the substrate 100; wherein the initial active layer is a semiconductor layer; Step S300: Doping the initial active layer to form an active layer 500; by doping the initial active layer, some areas of the initial active layer form implantation regions, while some areas are not doped to form channel regions, thereby ensuring the control capability of the subsequent transistor formation. Step S300: Form a gate layer 700 on the side of the active layer 500 away from the substrate 100; wherein the step of doping the initial active layer is performed before the step of forming the gate layer 700.
[0040] To accommodate high PPI products, the size of the transistors is reduced to a certain extent, for example, the gate area is reduced. However, a reduced gate area can lead to leakage problems in the formed transistors. Therefore, in this embodiment, the step of doping the initial active layer is set before the step of forming the gate layer 700, that is, the doping is performed without using the gate layer 700 as a barrier. The area of the gate layer 700 formed subsequently can be relatively large, thereby ensuring that the performance of the transistor is not affected by the reduction in transistor size.
[0041] Further reference Figure 2c In some embodiments, before the step of forming an initial active layer on one side of the substrate 100, the method further includes: forming a first insulating layer 300 on one side of the substrate 100, wherein the first insulating layer 300 has a first opening; Combination Figure 2d In the step of forming an initial active layer on one side of the substrate 100, a portion of the initial active layer is located within the first opening, and a portion of the initial active layer is located on the side of the first insulating layer 300 away from the substrate 100.
[0042] Combination Figure 2f In some embodiments, prior to the step of doping the initial active layer, the method further includes: forming a barrier layer 2400 within the first opening on at least a portion of the initial active layer on the side away from the first opening sidewall.
[0043] Combination Figure 2gIn some embodiments, the step of doping the initial active layer to form the active layer 500 includes: doping the initial active layer such that at least a portion of the initial active layer on the side of the first insulating layer 300 away from the substrate 100 forms a first implantation region 510; within the first opening, at least a portion of the initial active layer not covered by the barrier layer 2400 forms a second implantation region 530; that is, during doping, the area covered by the barrier layer 2400 forms a corresponding implantation region; since the barrier layer 2400 is provided on the side of the at least portion of the initial active layer away from the sidewall of the first opening, the barrier layer 2400 blocks during doping, such that at least a portion of the initial active layer on the sidewall of the first opening forms a channel region 520, and the orthographic projection of the channel region 520 on the substrate 100 at least partially overlaps with the orthographic projection of the barrier layer 2400 on the substrate 100; the first implantation region 510, the channel region 520, and the second implantation region 530 constitute the active layer 500.
[0044] In some embodiments, the material of the first insulating layer 300 is SiN. X It is one of SiO2 or Al2O3. In addition, the first insulating layer 300 can be a single-layer structure or a multi-layer structure.
[0045] In some embodiments, the thickness of the first insulating layer 300 is 0.05 micrometers to 0.5 micrometers; for example, the thickness of the first insulating layer 300 is 0.05 micrometers, 0.08 micrometers, 0.09 micrometers, 0.1 micrometers, 0.15 micrometers, 0.2 micrometers, 0.24 micrometers, 0.25 micrometers, 0.3 micrometers, 0.32 micrometers, 0.35 micrometers, 0.4 micrometers, 0.42 micrometers, 0.45 micrometers, 0.48 micrometers, or 0.5 micrometers, etc.
[0046] It is worth noting that by providing a first opening on the first insulating layer 300, with at least a portion of the channel region 520 located within the first opening, the channel region 520 extends in the thickness direction, and a portion of the channel region 520 circumferentially surrounds the sidewall of the first opening, thereby increasing the width of the transistor and improving its driving capability. Furthermore, due to the presence of the first opening, the active layer 500 of the transistor can be designed in the thickness direction, allowing the projected area of the transistor on the substrate 100 to be further reduced compared to related technologies. This further increases the number of sub-pixels formed, thereby improving the PPI of the formed display device, for example, enabling applications in AR and VR products.
[0047] In some embodiments, the first insulating layer 300 includes a sidewall facing the first opening and a bottom wall facing the substrate 100, with the included angle between the sidewall and the bottom wall being 50°-130°. For example, the included angle between the sidewall and the bottom wall is 50°, 55°, 57°, 60°, 62°, 65°, 67.5°, 70°, 72.5°, 75°, 76°, 80°, 82°, 85°, 87.5°, 90°, 91°, 92.5°, 94°, 95°, 97.5°, 98°, 100°, 102.5°, 105°, 107°, or 110°, etc.
[0048] Furthermore, the angle between the sidewall and the bottom wall of the first insulating layer 300 is 70°-110°.
[0049] like Figure 4 As shown, the angle between the sidewall and bottom wall of the first insulating layer 300 is less than 90°; Figure 5 As shown, the angle between the sidewall and the bottom wall of the first insulating layer 300 is 90°; Figure 6 As shown, the angle between the sidewall and the bottom wall of the first insulating layer 300 is greater than 90°.
[0050] It is worth noting that if the angle between the sidewall and the bottom wall of the first opening is too small, the overall projected area of the transistor on the substrate 100 will still be large, which will show the number of sub-pixels of the display device; if the angle between the sidewall and the bottom wall of the first opening is too large, it may cause poor continuity or even breakage of the initial active layer formed subsequently at the sidewall of the first opening, resulting in the inability to form a transistor.
[0051] In some embodiments, the thickness of the first insulating layer 300 is greater than the thickness of the initial active layer in a direction perpendicular to the substrate 100.
[0052] In some embodiments, combined with Figure 3 and Figure 4 Before the step of forming the gate layer 700 on the side of the active layer 500 away from the substrate 100, the method further includes: removing the barrier layer 2400. Removing the barrier layer 2400 facilitates the subsequent formation of the gate layer 700 on the side of the active layer 500 away from the substrate 100.
[0053] refer to Figure 2a and Figure 2b In some embodiments, before the step of forming the first insulating layer 300 on one side of the substrate 100, the method further includes: forming a first conductive electrode 200 on one side of the substrate 100. Combination Figure 2cAfter the step of forming a first insulating layer 300 on one side of the substrate 100, the method includes: forming a second conductive electrode 410 on the side of the first insulating layer 300 away from the substrate 100; the second conductive electrode 410 is provided with a second opening, the orthographic projection of the second opening on the substrate 100 at least partially overlapping the orthographic projection of the first opening on the substrate 100; and a portion of the first conductive electrode 200 is exposed through the first opening.
[0054] Specifically, an initial first insulating layer 300a and an initial second metal layer 400a are formed on the side of the first conductive electrode 200 away from the substrate 100, that is, a whole initial first insulating layer 300a and a whole initial second metal layer 400a are formed. The initial first insulating layer 300a and the initial second metal layer 400a are patterned to form a stacked first insulating layer 300 and a second conductive electrode 410. The patterning process of the initial first insulating layer 300a and the initial second metal layer 400a can be performed in the same process or in steps.
[0055] In some specific embodiments, the orthographic projection of the first opening on the substrate 100 lies within the orthographic projection of the second opening on the substrate 100.
[0056] In the step of forming an initial active layer on one side of the substrate 100, a portion of the initial active layer is located within the first opening and is connected to the first conductive electrode 200; a portion of the initial active layer is located on the side of the second conductive electrode 410 away from the substrate 100 and is connected to the second conductive electrode 410.
[0057] Combination Figure 4 In some embodiments, during the step of doping the initial active layer to form the active layer 500, at least a portion of the initial active layer located on the side of the second conductive electrode 410 away from the substrate 100 forms a first implantation region 510, and the first implantation region 510 is connected to the second conductive electrode 410. Within the first opening, at least a portion of the initial active layer not covered by the barrier layer 2400 forms a second implantation region 530, and the second implantation region 530 is connected to the first conductive electrode 200. By connecting different implantation regions through the first conductive electrode 200 and the second conductive electrode 410, signals can be transmitted through the corresponding conductive electrodes to the corresponding implantation regions, thereby controlling the turn-off of the transistor.
[0058] In some specific embodiments, the first conductive electrode 200 serves as one of the source and drain, and the second conductive electrode 410 serves as the other of the source and drain.
[0059] As shown in FIG7, in some embodiments, the step of forming a barrier layer 2400 on at least a portion of the initial active layer away from the first opening sidewall includes: forming a barrier layer 2400 on at least a portion of the initial active layer on both the side away from the first opening sidewall and the side away from the second opening sidewall.
[0060] Combination Figures 2e-2g In some embodiments, before the step of forming the barrier layer 2400 on the side of the initial active layer away from the first opening sidewall, the method further includes: forming an initial barrier layer 2400a on the side of the initial active layer away from the substrate 100; wherein the orthographic projection of the initial barrier layer 2400a on the substrate 100 covers the orthographic projection of the initial active layer on the substrate 100. The initial barrier layer 2400a is patterned to form the barrier layer 2400.
[0061] Specifically, in some embodiments, the material of the initial barrier layer 2400a includes photoresist; the initial barrier layer 2400a can be patterned by exposure and development to form the barrier layer 2400. Furthermore, the thickness of the initial barrier layer 2400a is 0.5 micrometers to 3 micrometers; for example, the thickness of the initial barrier layer 2400a is 0.5 micrometers, 0.55 micrometers, 0.6 micrometers, 0.7 micrometers, 0.75 micrometers, 0.8 micrometers, 0.82 micrometers, 0.9 micrometers, 0.95 micrometers, 1 micrometer, 1.2 micrometers, 1.25 micrometers, 1.4 micrometers, 1.5 micrometers, 1.6 micrometers, 1.65 micrometers, 1.8 micrometers, 2 micrometers, 2.3 micrometers, 2.5 micrometers, 2.8 micrometers, 3 micrometers, etc.
[0062] It is worth noting that, such as Figure 2e As shown, by limiting the thickness and material of the initial barrier layer 2400a, when forming a complete initial barrier layer 2400a, although the initial barrier layer 2400a has a certain leveling effect, at the first opening, the initial barrier layer 2400a also has a groove corresponding to the first opening, and the thickness of the initial barrier layer 2400a near the sidewall of the first opening is relatively large. In the subsequent patterning process, its exposure is not sufficient, so that the final development forms the barrier layer 2400 as shown in Figure 7. Subsequently, the barrier layer 2400 is used to block the doping, thereby forming the channel region 520 at the corresponding position.
[0063] Combination Figure 4 Before the step of forming the gate layer 700 on the side of the active layer 500 away from the substrate 100, the method further includes: forming a second insulating layer 600 on the side of the active layer 500 away from the substrate 100, and the orthogonal projection of the second insulating layer 600 on the substrate 100 covers the orthogonal projection of the active layer 500 on the substrate 100. Subsequently, a gate layer 700 is formed on the side of the second insulating layer 600 away from the substrate 100; as shown Figure 4 As shown, the orthogonal projection of the second implantation region 530 on the substrate 100 is located within the orthogonal projection of the gate layer 700 on the substrate 100, and the orthogonal projection of the first implantation region 510 on the substrate 100 partially overlaps with the orthogonal projection of the gate layer 700 on the substrate 100.
[0064] Furthermore, at the sidewall of the first opening or the second opening, the vertical distance between the edge of the first injection region 510 near the substrate 100 and the substrate 100 is less than the vertical distance between the surface of the first injection region 510 away from the substrate 100 and the substrate 100.
[0065] Of course, unlike the embodiments described above, in combination with Figures 7a-7e Before the step of doping the initial active layer, the method further includes: forming a second insulating layer 600 on the side of the initial active layer away from the substrate 100, wherein the orthographic projection of the second insulating layer 600 on the substrate 100 covers the orthographic projection of the initial active layer on the substrate 100, and forming a barrier layer 2400 at the first opening on the side of the second insulating layer 600 away from the first opening sidewall, that is, the barrier layer 2400 is disposed on the side of the second insulating layer 600 away from the substrate 100.
[0066] like Figures 7b-7c As shown, in some embodiments, before the step of forming the barrier layer 2400 on the side of the second insulating layer 600 away from the first opening sidewall, the method further includes: forming an initial barrier layer 2400a on the side of the second insulating layer 600 away from the substrate 100; and patterning the initial barrier layer 2400a to form the barrier layer 2400.
[0067] Specifically, in some embodiments, the material of the initial barrier layer 2400a includes photoresist; the initial barrier layer 2400a can be patterned by exposure and development to form the barrier layer 2400. Furthermore, the thickness of the initial barrier layer 2400a is 0.5 micrometers to 3 micrometers; for example, the thickness of the initial barrier layer 2400a is 0.5 micrometers, 0.55 micrometers, 0.6 micrometers, 0.7 micrometers, 0.75 micrometers, 0.8 micrometers, 0.82 micrometers, 0.9 micrometers, 0.95 micrometers, 1 micrometer, 1.2 micrometers, 1.25 micrometers, 1.4 micrometers, 1.5 micrometers, 1.6 micrometers, 1.65 micrometers, 1.8 micrometers, 2 micrometers, 2.3 micrometers, 2.5 micrometers, 2.8 micrometers, 3 micrometers, etc.
[0068] After that, as Figure 7dAs shown, in the step of doping the initial active layer to form the active layer 500, at least a portion of the initial active layer located on the side of the second conductive electrode 410 away from the substrate 100 forms a first implantation region 510, and the first implantation region 510 is connected to the second conductive electrode 410. Within the first opening, at least a portion of the initial active layer not covered by the barrier layer 2400 forms a second implantation region 530, and the second implantation region 530 is connected to the first conductive electrode 200. By connecting different implantation regions through the first conductive electrode 200 and the second conductive electrode 410, signals can be transmitted through the corresponding conductive electrodes to the corresponding implantation regions, thereby controlling the turn-off of the transistor.
[0069] It is worth noting that, such as Figure 7b As shown, by limiting the thickness and material of the initial barrier layer 2400a, when forming a complete initial barrier layer 2400a, although the initial barrier layer 2400a has a certain leveling effect, at the first opening, the initial barrier layer 2400a also has a groove corresponding to the first opening, and the thickness of the initial barrier layer 2400a near the sidewall of the first opening is relatively large. In the subsequent patterning process, its exposure is not sufficient, so that the final development forms the barrier layer 2400 as shown in Figure 7. Subsequently, the barrier layer 2400 is used to block the doping, thereby forming the channel region 520 at the corresponding position.
[0070] Subsequently, a gate layer 700 is formed on the side of the second insulating layer 600 away from the substrate 100; as shown Figure 7d As shown, the orthogonal projection of the second implantation region 530 on the substrate 100 is located within the orthogonal projection of the gate layer 700 on the substrate 100, and the orthogonal projection of the first implantation region 510 on the substrate 100 partially overlaps with the orthogonal projection of the gate layer 700 on the substrate 100.
[0071] Furthermore, in the above embodiments, the step of doping the initial active layer to form the active layer 500 includes: the ions used to dope the initial active layer include boron, phosphorus, hydrogen, etc.
[0072] Furthermore, to ensure that the transistor maintains excellent performance while shrinking overall, the ion doping concentration of the channel region 520 is less than or equal to 1 / 2000th of the ion doping concentration of the first implantation region 510; or, the ion doping concentration of the channel region 520 is less than or equal to 1 / 2000th of the ion doping concentration of the second implantation region 530.
[0073] Preferably, the ion doping concentration of the channel region 520 is less than 1 / 10,000 of the ion doping concentration of the first implantation region 510, or the ion doping concentration of the channel region 520 is less than 1 / 10,000 of the ion doping concentration of the second implantation region 530.
[0074] In some embodiments, the active layer 500 is made of a metal oxide semiconductor, wherein the metal oxide comprises at least one of indium, zinc, gallium, tin, titanium, aluminum, hafnium, zirconium, or magnesium. Specifically, the metal oxide comprises binary compounds (ABx), ternary compounds (ABxCy), or quaternary compounds (ABxCyDz) comprising indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), or magnesium (Mg). For example, metal oxides include indium oxide (In Oxide), indium zinc oxide (In-Zn Oxide), indium tin oxide (In-Sn Oxide), indium titanium oxide (In-Ti Oxide), indium gallium oxide (In-GaOxide), indium aluminum gallium oxide (In-Ga-Al Oxide), indium gallium tin oxide (In-Ga-Sn Oxide, also written as IGTO), gallium zinc oxide (Ga-Zn Oxide, also written as GZO), aluminum zinc oxide (Al-Zn Oxide, also written as AZO), indium aluminum zinc oxide (In-Al-Zn Oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn Oxide, also written as ITZO), indium titanium zinc oxide (In-Ti-Zn Oxide), indium gallium zinc oxide (In-Ga-Zn Oxide, also written as IGZO), and indium gallium tin zinc oxide (In-Ga-Sn-Zn). Oxide, also written as IGZTO, indium gallium aluminum zinc oxide (In-Ga-Al-Zn Oxide, also written as IGAZO, IGZAO or IAGZO), gallium tin oxide (Ga-Sn Oxide), aluminum tin oxide (Al-Sn Oxide).
[0075] In addition, the active layer 500 can be a single-layer structure or a multi-layer stacked structure. For example, a single layer is IGZO or IGO; a two-layer stack is IGZO / IGO; and a three-layer stack is IGZO / IGO / IGZO or IGZO / IZO / IGZO.
[0076] Of course, in some other embodiments, the active layer 500 may be made of low-temperature polycrystalline silicon.
[0077] Furthermore, in some embodiments, the orthographic projection of the first opening onto the substrate 100 is circular, rectangular, or elliptical.
[0078] Preferably, such as Figure 3As shown, the orthographic projection of the first opening on the substrate 100 is circular, and the orthographic projection of the first opening on the substrate 100 is located within the orthographic projection of the first conductive electrode 200 on the substrate 100; the orthographic projection of the second conductive electrode 410 on the substrate 100 does not overlap with the orthographic projection of the first opening on the substrate 100; the orthographic projection of the first opening on the substrate 100 is located within the orthographic projection of the active layer 500 on the substrate 100, thereby enabling the signal to be transmitted through the first conductive electrode 200 to the active layer 500 and along the circumference of the first opening to the second conductive electrode 410, or the signal to be transmitted through the second conductive electrode 410 to the active layer 500 and along the circumference of the first opening to the first conductive electrode 200, making the entire signal transmission process more stable and uniform, and ensuring the electrical performance of the transistor.
[0079] This application provides an array substrate, which includes the transistors described in the above embodiments; there may be multiple transistors in the array substrate.
[0080] This application provides a display panel, and the display panel 10 includes the transistors in the above embodiments.
[0081] For example, the display panel 10 can be an organic light-emitting diode (OLED) display panel, a micro organic light-emitting diode (Micro OLED) display panel, a light-emitting diode (LED) display panel, a quantum dot light-emitting diode (QLED) display panel, a mini light-emitting diode (Mini LED) display panel, a micro light-emitting diode (Micro LED) display panel, or a liquid crystal display (LCD) display panel, etc.
[0082] like Figure 8 As shown, the display panel 10 includes a display area AA with display function and a non-display area NA surrounding at least a portion of the display area AA.
[0083] In some embodiments, the display area AA of the display panel 100 can be rectangular, or it can be a square, a circle, an oval, or other shapes.
[0084] The display area AA includes a plurality of sub-pixels SPX arranged in the X and Y directions, wherein both the X and Y directions are perpendicular to the thickness direction Z of the display panel 10, and the X and Y directions intersect. In some preferred embodiments, the X and Y directions are perpendicular to each other.
[0085] In some embodiments, the plurality of sub-pixels SPX includes at least a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The colors of the light emitted by the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 are all different. For example, the color of the light emitted by the first sub-pixel SPX1 is red, the color of the light emitted by the second sub-pixel SPX2 is green, and the color of the light emitted by the third sub-pixel SPX3 is blue.
[0086] Of course, in other embodiments, the plurality of sub-pixels SPX may also include yellow sub-pixels or white sub-pixels.
[0087] like Figure 9 As shown, the display panel 100 also includes an array substrate, which includes multiple pixel circuits. The pixel circuits are electrically connected to corresponding sub-pixels SPX and are used to drive the corresponding sub-pixels SPX to emit light. For example, one pixel circuit drives one or more sub-pixels to emit light.
[0088] The pixel circuit includes the transistors and capacitors in the above embodiments, such as the 2T1C pixel circuit, 7T1C pixel circuit, 8T1C pixel circuit, 8T2C pixel circuit, etc. in the related art, where T refers to transistor and C refers to capacitor.
[0089] Specifically, the capacitor includes a first electrode 420 and a second electrode 710. The first electrode 420 is disposed in the same layer as one of the first conductive electrode 200, the second conductive electrode 410, and the gate layer 700. The second electrode 710 is disposed in the same layer as the other of the first conductive electrode 200, the second conductive electrode 410, and the gate layer 700. For example, as... Figure 9 As shown, the first electrode 420 and the second conductive electrode 410 are disposed in the same layer, and the second electrode 710 and the gate layer 700 are disposed in the same layer.
[0090] In addition, the array substrate also includes a planarization layer located on the side of the gate layer 700 away from the substrate. The planarization layer includes a first planarization layer 810 and a second planarization layer 820. By setting the planarization layer, the subsequent sub-pixels SPX located above are formed on a flat surface, ensuring the light emission effect of the sub-pixels SPX. In addition, the planarization layer can also be set in one or three layers, etc.
[0091] The sub-pixel SPX includes a first electrode 1100, a light-emitting layer 1200, and a second electrode 1300 stacked together. The first electrode 1100 is located on the side of the second planarization layer 820 away from the substrate 100, and multiple first electrodes are spaced apart. The second electrode 1300 is a single, continuous layer, which reduces cost. Specifically, the first electrode 1100 is the anode, and the second electrode 1300 is the cathode.
[0092] To ensure the luminous effect of the sub-pixel SPX, such as Figure 9 As shown, it also includes a pixel limiting layer 900, which includes multiple pixel openings; at least some sub-pixels SPX are located within the corresponding pixel openings, and the pixel limiting layer 900 can effectively avoid the problem of crosstalk in light emission from adjacent sub-pixels SPX.
[0093] In addition, such as Figure 9 As shown, the display panel 10 also includes an encapsulation layer disposed on the side of the sub-pixel SPX away from the substrate 100. The encapsulation layer includes a first encapsulation layer 2100, a second encapsulation layer 2200, and a third encapsulation layer 2300 stacked sequentially. The first encapsulation layer 2100 and the third encapsulation layer 2300 are both inorganic materials, for example, the materials of the first encapsulation layer 2100 and the third encapsulation layer 2300 include at least one of silicon nitride (SiN), silicon oxide (SiO), and silicon oxynitride (SiON). The second encapsulation layer 2200 is an organic material, such as epoxy resin, acrylic resin, or other resin materials. The encapsulation layer blocks moisture, ensuring that the display panel 10 will not fail due to moisture intrusion. It is worth noting that, to ensure the encapsulation effect, in the display area AA, the surface of the second encapsulation layer 2200 on the side away from the substrate 100 in this embodiment is parallel to the plane where the substrate 100 is located; that is, in the display area AA, the upper surface of the second encapsulation layer 2200 is a plane.
[0094] In some other embodiments, the display panel 10 also includes a touch layer, a cover plate, etc., located on the side of the encapsulation layer away from the substrate 100.
[0095] This application provides a display device, such as... Figure 10As shown, the display device 1 may include the display panel 10 in the above embodiments. The display device 1 may be an electronic paper device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, smart bracelet, smartwatch, supercomputer, navigator, wireless device, personal digital assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, clock, calculator, television monitor, computer monitor, car display (e.g., odometer display, etc.), cockpit controller and / or display, camera view display (e.g., display of rearview camera in a vehicle), electronic billboard or sign, projector, and other mobile or fixed terminals.
[0096] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.
[0097] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0098] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for fabricating a transistor, characterized in that, The steps are as follows: Provide substrate; An initial active layer is formed on one side of the substrate; The initial active layer is doped to form an active layer; A gate layer is formed on the side of the active layer away from the substrate; The step of doping the initial active layer is performed before the step of forming the gate layer.
2. The method for fabricating a transistor according to claim 1, characterized in that, Prior to the step of forming an initial active layer on one side of the substrate, the method further includes: A first insulating layer is formed on one side of the substrate, wherein a first opening is provided on the first insulating layer; In the step of forming an initial active layer on one side of the substrate, a portion of the initial active layer is located within the first opening, and a portion of the initial active layer is located on the side of the first insulating layer away from the substrate. Preferably, before the step of doping the initial active layer, the method further includes: forming a barrier layer in the first opening on at least a portion of the initial active layer away from the sidewall of the first opening; Preferably, the step of doping the initial active layer to form an active layer includes: doping the initial active layer such that at least a portion of the initial active layer located on the side of the first insulating layer away from the substrate forms a first implantation region, at least a portion of the initial active layer located on the sidewall side of the first opening forms a channel region, and the orthographic projection of the channel region on the substrate at least partially overlaps with the orthographic projection of the barrier layer on the substrate; and within the first opening, at least a portion of the initial active layer not covered by the barrier layer forms a second implantation region; the first implantation region, the channel region, and the second implantation region constitute the active layer; Preferably, the material of the first insulating layer is SiN. X One of SiO2 or l2O3; Preferably, the thickness of the first insulating layer is 0.05 micrometers to 0.5 micrometers; Preferably, before the step of forming a gate layer on the side of the active layer away from the substrate: the method further includes removing the barrier layer; Preferably, the first insulating layer includes a sidewall facing the first opening and a bottom wall facing the substrate, wherein the angle between the sidewall and the bottom wall is 50°-130°.
3. The method for fabricating a transistor according to claim 2, characterized in that, Before the step of forming a first insulating layer on one side of the substrate, the method further includes: forming a first conductive electrode on one side of the substrate; After the step of forming a first insulating layer on one side of the substrate, the method includes: forming a second conductive electrode on the side of the first insulating layer away from the substrate; the second conductive electrode has a second opening, the orthographic projection of the second opening on the substrate at least partially overlapping the orthographic projection of the first opening on the substrate; and a portion of the first conductive electrode is exposed through the first opening. In the step of forming an initial active layer on one side of the substrate, a portion of the initial active layer is located within the first opening and is connected to the first conductive electrode. Preferably, in the step of doping the initial active layer to form an active layer, at least a portion of the initial active layer located on the side of the second conductive electrode away from the substrate forms the first implantation region, and at least a portion of the initial active layer not covered by the barrier layer within the first opening forms the second implantation region, and the second implantation region is connected to the first conductive electrode. Preferably, the step of forming a barrier layer on at least a portion of the initial active layer away from the first opening sidewall includes: forming barrier layers on at least a portion of the initial active layer on both the side away from the first opening sidewall and the side away from the second opening sidewall.
4. The method for fabricating a transistor according to claim 2, characterized in that, The step of forming a barrier layer on at least a portion of the initial active layer on the side away from the first opening sidewall further includes: An initial barrier layer is formed on the side of the initial active layer away from the substrate; the orthographic projection of the initial barrier layer on the substrate covers the orthographic projection of the initial active layer on the substrate. The initial barrier layer is patterned to form a barrier layer; Preferably, the material of the initial barrier layer includes photoresist; Preferably, the thickness of the initial barrier layer is 0.5 micrometers to 3 micrometers.
5. The method for fabricating a transistor according to claim 2, characterized in that, Before the step of doping the initial active layer, the method further includes: A second insulating layer is formed on the side of the initial active layer away from the substrate; at the first opening, a barrier layer is formed on the side of the second insulating layer away from the sidewall of the first opening; Preferably, before the step of forming a barrier layer on the side of the second insulating layer away from the first opening sidewall, the method further includes: forming an initial barrier layer on the side of the second insulating layer away from the substrate; The initial barrier layer is patterned to form a barrier layer; Preferably, the material of the initial barrier layer includes photoresist; Preferably, the thickness of the initial barrier layer is 0.5 micrometers to 3 micrometers.
6. The method for fabricating a transistor according to any one of claims 2-5, characterized in that, The step of doping the initial active layer to form an active layer includes: the ions used to dope the initial active layer include boron, phosphorus, hydrogen, etc. Preferably, the ion doping concentration of the channel region is less than or equal to 1 / 2000 of the ion doping concentration of the first implantation region; or, the ion doping concentration of the channel region is less than or equal to 1 / 2000 of the ion doping concentration of the second implantation region.
7. The method for fabricating a transistor according to any one of claims 1-5, characterized in that, The active layer is made of a metal oxide semiconductor, wherein the metal oxide comprises at least one of indium, zinc, gallium, tin, titanium, aluminum, hafnium, zirconium, or magnesium.
8. A transistor, characterized in that, Transistors prepared by the method of any one of claims 1-7.
9. A display panel, characterized in that, It includes an array substrate, wherein the array substrate comprises a transistor prepared by the method for preparing a transistor according to any one of claims 1-7.
10. A display device, characterized in that, Includes the display panel as described in claim 9.