Display panel

Abstract

An embodiment discloses a display panel and a display device including the display panel. The display panel includes: a first display area, wherein a plurality of pixels are disposed; and a second display area, which includes a plurality of pixel areas disposed of the plurality of pixels and a plurality of light-transmitting areas disposed between the plurality of pixel areas, wherein the second display area includes: a plurality of first pixels disposed in the plurality of pixel areas; a plurality of second pixels disposed in the plurality of light-transmitting areas; and a plurality of first electrodes extending from the plurality of pixel areas to the plurality of light-transmitting areas to electrically connect the plurality of first pixels to the plurality of second pixels.

Description

[0001] This application is a divisional application of the original invention patent application No. 202110988441.7 (filed on August 26, 2021, invention title: display panel and display device including the display panel). Technical Field

[0002] The embodiments relate to a display panel and a display device including the display panel. Background Technology

[0003] Based on the material of the light-emitting layer, electroluminescent display devices are divided into inorganic light-emitting display devices and organic light-emitting display devices. Active-matrix organic light-emitting display devices include organic light-emitting diodes (OLEDs). OLEDs are self-emissive and have advantages in fast response time, high luminous efficiency, high brightness, and wide viewing angle. Organic light-emitting display devices have an OLED formed in each pixel. Organic light-emitting display devices can represent black grayscale as perfect black and have fast response time, high luminous efficiency, high brightness, and wide viewing angle, thus exhibiting excellent contrast and color gamut.

[0004] Multimedia capabilities on mobile devices have improved. For example, cameras are now largely built into smartphones, and their resolution is reaching the level of existing digital cameras. However, the front-facing camera on smartphones limits screen design, making it challenging. To reduce the space occupied by the camera, screen designs including notches or punch holes have been adopted in smartphones, but screen size remains limited due to the camera, making full-screen display difficult to achieve.

[0005] To achieve full-screen display, a method has been proposed in which an imaging area with pixels is prepared in the screen of the display panel, and a camera and / or various sensors are arranged at a position below the display panel facing the imaging area.

[0006] However, because pixels are located in the imaging area, there is a problem of reduced light transmittance and decreased performance of the camera and / or various sensors. Furthermore, when the number of pixels in the imaging area is reduced to improve light transmittance, the light-emitting area decreases, resulting in reduced display performance and requiring brightness compensation. Summary of the Invention

[0007] The embodiments are intended to provide a display panel and display device with an increased luminous area in the imaging region.

[0008] The implementation also aims to provide a display panel and display device that can ensure sufficient light-transmitting area in the imaging region.

[0009] The implementation also aims to provide display panels and display devices with improved pixel lifespan.

[0010] The implementation also aims to provide display panels and display devices with reduced manufacturing costs.

[0011] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0012] According to one aspect of this disclosure, a display panel is provided, the display panel comprising: a first display area having a plurality of pixels disposed thereon; and a second display area having a plurality of pixel areas having the plurality of pixels disposed thereon and a plurality of light-transmitting areas disposed between the plurality of pixel areas, wherein the second display area comprises: a plurality of first pixels disposed in the plurality of pixel areas, a plurality of second pixels disposed in the plurality of light-transmitting areas, and a plurality of first electrodes extending from the plurality of pixel areas to the plurality of light-transmitting areas to electrically connect the plurality of first pixels to the plurality of second pixels.

[0013] The second display area may include a second electrode that covers multiple pixel areas and includes multiple openings corresponding to multiple light-transmitting areas.

[0014] The second electrode can extend into the interior of each of the multiple openings to electrically connect the multiple first pixels to the multiple second pixels.

[0015] The number of pixels per unit area of ​​the pixels set in the first display area can be the same as or different from the number of pixels per unit area of ​​the pixels set in the second display area.

[0016] The number of sub-pixels in each of the second pixels can be equal to or less than the number of sub-pixels in each of the first pixels.

[0017] Each of the second pixels set in the light-transmitting area may include a first sub-pixel, a second sub-pixel, and a third sub-pixel.

[0018] The first sub-pixel of the second pixel can be electrically connected to the first sub-pixel of the first pixel region in a plurality of pixel regions surrounding the light-transmitting region, and the second sub-pixel of the second pixel can be electrically connected to the second sub-pixel of the first pixel region.

[0019] The first sub-pixel of the second pixel can be electrically connected to the first sub-pixel of the first pixel region in a plurality of pixel regions surrounding the light-transmitting region, and the second sub-pixel of the second pixel can be electrically connected to the second sub-pixel of the second pixel region in a plurality of pixel regions surrounding the light-transmitting region.

[0020] Each of the second pixels in the light-transmitting region may include a first unit sub-pixel and a second unit sub-pixel that emit the same color. The first unit sub-pixel may be electrically connected to the second sub-pixel of the first pixel region in a plurality of pixel regions surrounding the light-transmitting region, and the second unit sub-pixel may be electrically connected to the second sub-pixel of the second pixel region in a plurality of pixel regions surrounding the light-transmitting region. Attached Figure Description

[0021] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein: Figure 1 This is a conceptual diagram of a display device according to one embodiment of the present disclosure; Figures 2A to 2D It is a view showing the various arrangements and shapes of the second display area; Figure 3 This is a schematic cross-sectional view showing a display panel according to one embodiment of the present disclosure; Figure 4 This is a view showing the pixel arrangement in a display area according to one embodiment of the present disclosure; Figure 5 This is a view showing the pixels of the second display area and the light-transmitting area according to the first embodiment of this disclosure; Figure 6 This is a plan view showing the first electrode disposed in the second display area; Figure 7 This is a plan view showing the second electrode disposed in the second display area; Figure 8 This is a view showing the conventional imaging area; Figure 9 This is a view showing the pixels of the second display area and the light-transmitting area according to the second embodiment of this disclosure; Figure 10 This is a view showing the pixels of the second display area and the light-transmitting area according to a third embodiment of the present disclosure; Figure 11 This is a view showing the pixels of the second display area and the light-transmitting area according to the fourth embodiment of this disclosure; Figure 12 This is a plan view showing the second electrode according to the fourth embodiment of the present disclosure; Figure 13 This is a view showing the pixels of the second display area and the light-transmitting area according to the fifth embodiment of this disclosure; Figure 14 This is a view showing the pixels of the second display area and the light-transmitting area according to the sixth embodiment of this disclosure; Figure 15 This is a view showing the pixels of the second display area and the light-transmitting area according to the seventh embodiment of this disclosure; Figure 16 This is a view showing the pixels of the first and second display areas; Figure 17 This is a block diagram illustrating a display panel and a display panel driving unit according to one embodiment of the present disclosure; Figure 18 This is a schematic block diagram showing the configuration of the driver integrated circuit (IC); Figure 19 This is a circuit diagram showing an example of a pixel circuit; Figure 20 This is a circuit diagram showing another example of a pixel circuit; Figure 21 It shows the driver Figure 19 and Figure 20 A schematic diagram of the pixel circuit method shown; Figure 22 It is a cross-sectional view showing in detail the cross-sectional structure of a pixel region in a display panel according to one embodiment of the present disclosure; Figure 23 yes Figure 5 An enlarged view of section M1; Figure 24 It shows along Figure 23 A view of the cross-sectional structure of the portion intercepted by lines A-A' and B-B'; Figure 25 It shows along Figure 23 A view of the cross-sectional structure of the portion intercepted by lines A-A' and C-C'; Figure 26 yes Figure 25 Examples of variations; Figure 27 This is a view showing various electronic devices arranged in the second display area; Figure 28 yes Figure 27 An enlarged view of section M2; and Figure 29 yes Figure 27 An enlarged view of the M3 section. Detailed Implementation

[0022] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below and can be implemented in various different variations. The embodiments are provided merely to allow those skilled in the art to fully understand the scope of this disclosure, and this disclosure is limited only by the scope of the claims.

[0023] The figures, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings to describe embodiments of the present disclosure are merely illustrative and are not limited to the matters shown in the present disclosure. Throughout the disclosure, the same reference numerals denote the same elements. Furthermore, in describing the present disclosure, detailed descriptions of prior art will be omitted where it is determined that a description of prior art may unnecessarily obscure the essential points of the present disclosure.

[0024] Terms such as “including,” “having,” and “consisting of” used herein are intended to allow for the addition of other elements, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0025] Even if not explicitly stated, the components will be interpreted as including the normal error range.

[0026] When describing positional relationships, for example, when the positional relationship between two components is described as "above", "over", "below", and "next to", one or more components may be inserted between them, unless the terms "immediately adjacent" or "directly" are used in the expression.

[0027] In the description of the embodiments, the terms "first," "second," etc., may be used herein to describe various elements, which are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, without departing from the teachings of this disclosure, the first component discussed below may be referred to as the second component.

[0028] Throughout the disclosure, the same reference numerals denote the same elements.

[0029] Features of various implementations may be partially or wholly combined or integrated with each other. Implementations may interoperate and be performed in technically different ways, and may be performed independently or in conjunction with each other.

[0030] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0031] Figure 1 This is a conceptual diagram of a display device according to one embodiment of the present disclosure. Figures 2A to 2D This is a view showing the various arrangements and shapes of the second display area. Figure 3This is a schematic cross-sectional view showing a display panel according to an embodiment of the present disclosure, and Figure 4 This is a view showing the pixel arrangement in a display area according to one embodiment of the present disclosure.

[0032] Reference Figure 1 The display device may include a display panel 100 and a housing, and the front surface of the display panel 100 may be configured as a display area. Therefore, full-screen display can be achieved.

[0033] The display area may include a first display area DA and a second display area CA. Both the first display area DA and the second display area CA may output images, but their resolutions may differ. For example, the resolution of a plurality of second pixels disposed in the second display area CA may be lower than the resolution of a plurality of first pixels disposed in the first display area DA. A sufficient amount of light, commensurate with the degree of resolution reduction in the plurality of second pixels disposed in the second display area CA, may be injected into the electronic devices 41 and 42 disposed in the second display area CA.

[0034] However, this disclosure is not limited to this, and the resolution of the first display area DA and the resolution of the second display area CA can be substantially the same.

[0035] The second display area CA can be an area where one or more electronic devices 41 and 42 are disposed. The second display area CA is an area that overlaps with the various electronic devices, and therefore can be smaller in area than the first display area DA that outputs most of the image.

[0036] Electronic devices 41 and 42 may include at least one of an image sensor, an infrared sensor, a proximity sensor, a lighting sensor, a gesture sensor, a motion sensor, a fingerprint sensor, and a biometric sensor. As an example, the first electronic device 41 may be a lighting sensor, and the second electronic device 42 may be an image sensor configured to capture images or videos, but this disclosure is not limited thereto.

[0037] Reference Figures 2A to 2D The second display area CA can be set in various locations where light needs to be incident. As an example, the second display area CA can be as follows: Figure 2A As shown, the second display area CA is positioned at the upper left corner of the display area. Figure 2B As shown, the second display area CA is positioned at the upper right corner of the display area. Figure 2C The second display area CA is positioned at the top of the entire display area, and its width can be as shown. Figure 2D Various modifications can be made as shown. However, this disclosure is not limited to this, and the second display area CA can be located in the middle part of the display area or at the bottom of the display area.

[0038] Reference Figure 3 and Figure 4 The first display area DA and the second display area CA may include a pixel array with pixels for writing pixel data. To ensure the light transmittance of the second display area CA, the number of pixels per unit area (pixels per inch (PPI)) of the second display area CA may be lower than the number of pixels per unit area of ​​the first display area DA. However, this disclosure is not limited to this, and the PPI of each of the first display area DA and the second display area CA may be formed in the same or similar manner.

[0039] In the second display area CA, external light can pass through the display panel 100 through a light-transmitting area with high light transmittance and can be received by a sensor placed below the display panel 100.

[0040] Since both the first display area DA and the second display area CA include pixels, the input image can be reproduced on both the first display area DA and the second display area CA.

[0041] Each pixel in the first display area DA and the second display area CA may include sub-pixels of different colors to achieve the color of the image. Sub-pixels may include red (red sub-pixels), green (green sub-pixels), and blue (blue sub-pixels). Although not illustrated, each pixel may also include white sub-pixels. Each sub-pixel within a pixel area may include pixel circuitry and a light-emitting element (organic light-emitting diode: OLED).

[0042] The second display area CA may include pixels and a camera module disposed below the screen of the display panel 100. The pixels of the second display area CA can display an input image by writing pixel data of the input image in display mode.

[0043] The camera module can capture external images in imaging mode to output picture or video image data. The lens of the camera module can face the second display area (CA).

[0044] External light is incident on the lens 30 of the camera module through the second display area CA, and the lens 30 can converge the light onto the image sensor (not shown in the figure). The camera module can capture external images in imaging mode to output picture or video image data.

[0045] The display panel 100 has a width in the X-axis direction, a length in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 may include a circuit layer 12 disposed on a substrate 10 and a light-emitting element layer 14 disposed on the circuit layer 12. A polarizer 18 may be disposed on the light-emitting element layer 14, and a cover glass 20 may be disposed on the polarizer 18.

[0046] The circuit layer 12 may include pixel circuits connected to lines such as data lines, gating lines, and power lines, as well as gating drive units connected to gating lines.

[0047] The circuit layer 12 may include circuit elements, such as transistors implemented as thin-film transistors (TFTs) and capacitors. The lines and circuit elements of the circuit layer 12 may be implemented by multiple insulating layers, two or more metal layers separated from each other with insulating layers therebetween, and an active layer including semiconductor material.

[0048] The light-emitting element layer 14 may include a light-emitting element driven by pixel circuitry. The light-emitting element may be implemented as an OLED. The OLED may include an organic compound layer formed between an anode and a cathode.

[0049] The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), a light emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but this disclosure is not limited thereto.

[0050] When a voltage is applied to the anode and cathode of an OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emissive layer (EML) to generate excitons, which can then emit visible light from the EML.

[0051] The light-emitting element layer 14 may also include a color filter array disposed on the pixel, the color filter array selectively transmitting red, green and blue wavelengths.

[0052] The light-emitting element layer 14 may be covered by a protective film, and the protective film may be covered by an encapsulation layer.

[0053] Protective films and encapsulation layers can have a structure with alternating layers of organic and inorganic films. Inorganic films can block the penetration of moisture or oxygen. Organic films can planarize the surface of inorganic films.

[0054] When organic and inorganic membranes are stacked in multiple layers, the increased length of the movement path of moisture or oxygen compared to a single layer effectively blocks the penetration of moisture / oxygen that affects the light-emitting element layer 14.

[0055] The polarizer 18 can be adhered to the encapsulation layer. The polarizer 18 can improve the outdoor visibility of the display device. The polarizer 18 can reduce light reflection from the surface of the display panel 100 and block light reflected from the metal of the circuit layer 12, thereby improving pixel brightness. The polarizer 18 can be implemented as a linear polarizer, a polarizer combined with a phase retardation film, or a circular polarizer.

[0056] Reference Figure 4 The first display area DA may include pixels PIX1 and PIX2 arranged in a matrix. Each of pixels PIX1 and PIX2 may be implemented as a real-type pixel, where the R, G, and B sub-pixels of the three primary colors form a pixel.

[0057] Each of pixels PIX1 and PIX2 may also include W sub-pixels (omitted in the diagram). Furthermore, a sub-pixel rendering algorithm can be used to combine two sub-pixels into one pixel. For example, the first pixel PIX1 may include R and G sub-pixels, and the second pixel PIX2 may include B and G sub-pixels. Insufficient color representation in each of pixels PIX1 and PIX2 can be compensated for by averaging the corresponding color data between adjacent pixels.

[0058] Figure 5 This is a view showing the pixels of the second display area and the light-transmitting area according to the first embodiment of this disclosure. Figure 6 This is a plan view showing the first electrode disposed in the second display area. Figure 7 This is a plan view showing the second electrode disposed in the second display area, and Figure 8 This is a view showing the conventional imaging area.

[0059] Reference Figure 5 and Figure 6 The second display area CA may include multiple pixel areas PA and multiple light-transmitting areas AG disposed between the pixel areas PA. The light-transmitting areas AG may include a transparent medium with high light transmittance but without metal, allowing light to enter with minimal loss. The light-transmitting areas AG can be defined as areas made of a transparent insulating material that does not contain metal lines or pixels. As the light-transmitting areas AG increase, the light transmittance of the second display area CA can be higher.

[0060] The shape of the light-transmitting area AG is shown as circular, but this disclosure is not limited thereto. For example, the light-transmitting area AG can be designed in various shapes, such as circular, elliptical, or polygonal.

[0061] The pixels disposed in the second display area CA may include a first pixel P1 disposed in multiple pixel areas PA and a second pixel P2 disposed in multiple light-transmitting areas AG. According to this embodiment, the pixels may also be disposed in the light-transmitting areas AG. Therefore, the actual light-transmitting area of ​​the light-transmitting areas AG can be the area excluding the area where the second pixel P2 is disposed.

[0062] According to this embodiment, since the pixels are disposed in the light-transmitting area AG, the number of pixels per unit area (PPI) of the second display area CA can be the same as the number of pixels per unit area of ​​the first display area DA. In this case, pixels can be formed in one step using a fine metal mask (FMM) in both the first display area DA and the second display area CA, thereby reducing manufacturing costs and shortening manufacturing time.

[0063] A first electrode AND, disposed in multiple pixel regions PA and connected to multiple first pixels P1, can extend to a light-transmitting region AG to be electrically connected to multiple second pixels P2. Therefore, due to the first electrode AND, pixel data applied to the first pixel P1 through the first electrode AND can be equivalently applied to the second pixel P2.

[0064] Therefore, the image output from the first pixel P1 in pixel region PA can be the same as the image output from the second pixel P2 in light-transmitting region AG. That is, the first pixel can be a driving pixel that includes pixel circuitry and a light-emitting element (OLED), while the second pixel P2 can be a dummy pixel that only includes the light-emitting element (OLED) of the first pixel P1.

[0065] According to this configuration, when the first pixel P1 is driven, the second pixel P2 also emits light along with the first pixel P1, increasing the luminous area and thus increasing brightness. Furthermore, the resolution of the second display area CA can be improved. With increased resolution, the deviation in pixel data values ​​applied between adjacent pixels may be small; therefore, in terms of resolution, outputting similar images may be more advantageous compared to the case without adjacent pixels. The resolution can be further increased when the predetermined area including the first and second pixels outputs the same image.

[0066] Typically, when the number of pixels per unit area in the second display area CA is less than the number of pixels per unit area in the first display area DA, the brightness of the second display area CA can be less than the brightness of the first display area DA. Therefore, to compensate for the brightness of the second display area CA, a higher data voltage can be applied to the pixels of the second display area CA. However, in this case, there is a problem that the light-emitting element (OLED) may be damaged.

[0067] However, according to this embodiment, since the number of pixels per unit area of ​​the first display area DA is the same as or similar to the number of pixels per unit area of ​​the second display area CA, it is not necessary to further increase the voltage level applied to the pixels of the second display area CA. Therefore, the lifespan of the device can be improved.

[0068] The first electrode AND may include a first sub-electrode AND1 that connects a first sub-pixel R1 of pixel region PA to a first virtual pixel R2 of light-transmitting region AG, a second sub-electrode AND2 that connects a second sub-pixel G1 of pixel region PA to a second virtual pixel G2 of light-transmitting region AG, and a third sub-electrode AND3 that connects a third sub-pixel B1 of pixel region PA to a third virtual pixel B2 of light-transmitting region AG.

[0069] In this case, the lengths of the first sub-electrode AND1 and the third sub-electrode AND3 can be the same, and the length of the second sub-electrode AND2 can be greater than the length of each of the first sub-electrode AND1 and the third sub-electrode AND3.

[0070] The first sub-electrode AND1 to the third sub-electrode AND3 extend in one direction and electrically connect the first pixel P1 to the second pixel P2. Therefore, the area of ​​the first electrode AND is increased, thereby reducing the current density and improving the lifespan of the light-emitting element.

[0071] The first electrode AND can be made of various metallic materials with excellent conductivity, but it can also be made of a transparent electrode with excellent light transmittance. When the first electrode AND is made as a transparent electrode, the light transmittance in the light-transmitting region AG can be increased. The transparent electrode can be made of metal oxides such as ITO or IZO, but this disclosure is not limited to this.

[0072] Reference Figure 7 The second electrode CAT, connected to the first pixel P1 and the second pixel P2, can cover the pixel region PA and includes multiple openings H2 corresponding to multiple light-transmitting regions AG. Because the second electrode CAT is formed over the entire second display region CA, a material with high conductivity can be selected. Therefore, due to the relatively low light transmittance, it is desirable to form openings H2 corresponding to the light-transmitting regions AG. In this embodiment, the light-transmitting region AG can be defined as the region corresponding to the openings H2 of the second electrode CAT.

[0073] However, this disclosure is not limited thereto, and when the second electrode CAT is fabricated as a transparent electrode, the transmittance in the transparent region AG can be increased. Metal oxides such as ITO or IZO can be applied to the transparent electrode, but this disclosure is not limited thereto.

[0074] The second electrode CAT may include multiple sub-electrodes CAT1, CAT2 and CAT3 extending to multiple light-transmitting areas AG, to electrically connect multiple first pixels P1 and multiple second pixels P2, respectively.

[0075] The first electrode AND and the second electrode CAT can each have a corresponding shape and overlap vertically on multiple light-transmitting areas AG.

[0076] Reference Figure 8 Since the conventional second display area CA is arranged in the order of RGBG, the pixel area is relatively wide, resulting in a decrease in the diameter D2 of each light-transmitting area AG. However, according to this embodiment, the pixel area is arranged compactly in a square, allowing the diameter of the light-transmitting area to be manufactured to be relatively wide. Therefore, even when the pixels are arranged in the light-transmitting area as in the embodiment and the light-transmitting area is partially reduced, a light-transmitting area similar to that of a conventional light-transmitting area can be ensured.

[0077] Figure 9 This is a view showing the pixels of the second display area and the light-transmitting area according to the second embodiment of this disclosure, and Figure 10 This is a view showing the pixels of the second display area and the light-transmitting area according to the third embodiment of this disclosure.

[0078] Reference Figure 9 The second pixel P2 disposed in the light-transmitting area AG may include a first virtual pixel R2, a second virtual pixel G2, and a third virtual pixel B2. As an example, the first virtual pixel R2 may be a red pixel, the second virtual pixel G2 may be a green pixel, and the third virtual pixel B2 may be a blue pixel, but this disclosure is not limited to these.

[0079] The first virtual pixel R2 of the second pixel P2 can be electrically connected to the first sub-pixel R1 of the first pixel region PA1 among the multiple pixel regions PA surrounding the light-transmitting region AG.

[0080] The second virtual pixel G2 of the second pixel P2 can be electrically connected to the second sub-pixel G1 of the first pixel region PA1. Furthermore, the third virtual pixel B2 of the second pixel P2 can be electrically connected to the third sub-pixel B1 of the first pixel region PA1.

[0081] In other words, the virtual pixels R2, G2, and B2 of the second pixel P2 can be electrically connected to the sub-pixels R1, G1, and B1 of the first pixel region PA1, respectively. Therefore, when the first pixel P1 outputs the input image, the second pixel P2 can also output the same image. The terms virtual pixel and sub-pixel are used only to distinguish them from each other, and both virtual pixels and sub-pixels can be sub-pixels forming an RGB pixel group.

[0082] There is no particular limit to the number of pixel regions PA surrounding any light-transmitting area AG. Figure 9 The illustration shows four pixel regions PA surrounding a light-transmitting region AG, but this disclosure is not limited to this and six, eight or more pixel regions PA can be set to surround a light-transmitting region AG. That is, the number of surrounding pixel regions PA can vary depending on the size of the light-transmitting region AG.

[0083] Reference Figure 10 The first virtual pixel R2 of the second pixel P2 can be electrically connected to the first sub-pixel R1 of the first pixel region PA1 in the plurality of pixel regions PA surrounding the light-transmitting region AG.

[0084] Furthermore, the third virtual pixel B2 of the second pixel P2 can be electrically connected to the third sub-pixel B1 of the first pixel region PA1 surrounding the light-transmitting region AG.

[0085] However, the second virtual pixel G2 of the second pixel P2 can be electrically connected to the second sub-pixel G1 of the second pixel region PA2 surrounding the light-transmitting region AG.

[0086] In other words, the first virtual pixel R2 and the third virtual pixel B2 of the second pixel P2 can be connected to the first pixel region PA1, while the second virtual pixel G2 of the second pixel P2 can be connected to the second pixel region PA2. Therefore, the second pixel P2, which is located in the first light-transmitting region AG, can output an image that is different from the image in the adjacent pixel region PA.

[0087] With this configuration, the light-transmitting region AG, located between the first pixel region PA1 and the second pixel region PA2, can output a mixed image in which the image output from the first pixel P1 and the image output from the second pixel P2 are blended. Therefore, compared to the case where no image is output from the light-transmitting region AG at all, resolution and brightness can be increased.

[0088] Figure 11 This is a view showing the pixels of the second display area and the light-transmitting area according to the fourth embodiment of this disclosure, and Figure 12 This is a plan view showing the second electrode according to the fourth embodiment of the present disclosure.

[0089] Reference Figure 11 and Figure 12The second virtual pixel G2 may include a first unit virtual pixel G21 and a second unit virtual pixel G22. The second virtual pixel G2 may be a green pixel. Green pixels have the greatest impact on brightness, and therefore multiple green pixels can be implemented. Furthermore, multiple green pixels can be set to implement a matrix of pixels. However, this disclosure is not limited to this, and the first unit virtual pixel G21 and the second unit virtual pixel G22 may be white sub-pixels.

[0090] The first unit virtual pixel G21 can be electrically connected to the second sub-pixel G1 of the second pixel region PA2 among the plurality of pixel regions PA surrounding the light-transmitting region AG, and the second unit virtual pixel G22 can be electrically connected to the second sub-pixel G1 of the first pixel region PA1 among the plurality of pixel regions PA surrounding the light-transmitting region AG. Alternatively, the connection can be reversed as described above.

[0091] The sub-electrodes of the second electrode CAT may include a first unit sub-electrode CAT21 corresponding to the first unit virtual pixel G21 and a second unit sub-electrode CAT22 corresponding to the second unit virtual pixel G22. In this case, the first unit sub-electrode CAT21 and the second unit sub-electrode CAT22 can be spaced apart from each other. Therefore, since the second electrode CAT is not located in the central region H2a of the opening H2, the area of ​​the light-transmitting region AG can be further increased. As a result, the amount of light incident is relatively increased, thereby improving the camera performance.

[0092] Figure 13 This is a view showing the pixels of the second display area and the light-transmitting area according to the fifth embodiment of this disclosure, and Figure 14 This is a view showing the pixels of the second display area and the light-transmitting area according to the sixth embodiment of this disclosure.

[0093] Reference Figure 13 According to this embodiment, the second display area CA can be implemented using only sub-pixels of a single color. As an example, the second pixel P2 can be formed solely from green pixels, which are most sensitive to brightness.

[0094] In this embodiment, the second pixel P2 is formed only by green pixels to increase brightness, while the red and blue pixels can be omitted, thereby increasing the area of ​​the light-transmitting region AG. That is, since the first electrode AND and the second electrode CAT used to connect the red or blue pixels to the light-transmitting region AG can be omitted, the area of ​​the light-transmitting region AG can be increased.

[0095] However, this disclosure is not limited thereto, and when the first pixel P1 and the second pixel P2 include white sub-pixels, the second pixel P2 may be a white sub-pixel.

[0096] Reference Figure 14 The first unit virtual pixel G21 can be electrically connected to the second sub-pixel G1 of the second pixel region PA2 among the multiple pixel regions PA surrounding the light-transmitting region AG, and the second unit virtual pixel G22 can be electrically connected to the second sub-pixel G1 of the first pixel region PA1 among the multiple pixel regions PA surrounding the light-transmitting region AG.

[0097] With this structure, since the second electrode CAT is not located in the intermediate region between the first unit virtual pixel G21 and the second unit virtual pixel G22, the area of ​​the light-transmitting region AG can be increased. Therefore, the amount of light incident is relatively increased, thereby further improving camera performance.

[0098] Figure 15 This is a view showing the pixels of the second display area and the light-transmitting area according to the seventh embodiment of this disclosure.

[0099] Reference Figure 15 The second pixel P2 can be configured by omitting at least one of the red, green, and blue pixels.

[0100] As an example, red pixel R2 and green pixel G2 can be disposed in the first light-transmitting area AG1 located at the center of the attached diagram, and each can be electrically connected to a sub-pixel of pixel area PA. With this configuration, all red pixels R2, green pixels G2, and blue pixels B2 can emit light in pixel area PA, while only red pixels R2 and green pixels G2 can emit light in the first light-transmitting area AG1.

[0101] Furthermore, green and blue pixels can be disposed in a second light-transmitting region AG2, positioned relative to the first light-transmitting region AG1 along the 1 o'clock direction, and a third light-transmitting region AG3, positioned relative to the first light-transmitting region AG1 along the 5 o'clock direction. Additionally, red and green pixels can be disposed in a fourth light-transmitting region AG4, positioned relative to the first light-transmitting region AG1 along the 7 o'clock direction, and a fifth light-transmitting region AG5, positioned relative to the first light-transmitting region AG1 along the 11 o'clock direction. However, this disclosure is not limited to these provisions, and different sub-pixels can be randomly disposed in each light-transmitting region.

[0102] According to this implementation, different sub-pixels can be set in adjacent light-transmitting areas AG to improve overall brightness, and the light-emitting area of ​​the light-transmitting areas AG can be increased to improve display performance.

[0103] Furthermore, compared to the case where red, green, and blue pixels are set in all light-transmitting areas (AG), the area of ​​the light-transmitting area (AG) can be increased, thereby improving camera performance.

[0104] Figure 16This is a view showing the pixels of the first and second display areas.

[0105] Reference Figure 16 In both the first display area DA and the second display area CA, the number of pixels per unit area can be the same. Therefore, when using an FMM mask to form pixels, there is an advantage that pixels in both the first display area DA and the second display area CA can use the same FMM mask.

[0106] With this configuration, an FMM mask can be used as is, which has the advantages of reducing manufacturing costs and manufacturing time. The second display area CA also has the same light-emitting area as the first display area DA, which enables full display. Furthermore, the increased light-emitting area can improve the lifespan of the pixels in the second display area CA.

[0107] However, this disclosure is not limited to this, and the number of pixels in the second display area CA can be adjusted differently. As an example, the number of pixels set in the light-transmitting area AG can be reduced as the distance from the first display area DA increases.

[0108] A second pixel can be placed within all light-transmitting areas AG at the boundary between the first display area DA and the second display area CA, making the boundary region between the first display area DA and the second display area CA invisible. When the number of pixels changes abruptly at the boundary between the first display area DA and the second display area CA, the boundary of the second display area CA may become visible due to the resolution difference.

[0109] Furthermore, as the distance from the first display area DA increases, the number of pixels in the light-transmitting area AG can be reduced. With this configuration, as the light-transmitting area AG reaches the area where the camera is located, the number of pixels in the light-transmitting area AG decreases, thereby increasing the amount of incident light.

[0110] Figure 17 This is a block diagram illustrating a display panel and a display panel driving unit according to one embodiment of the present disclosure, and Figure 18 This is a schematic block diagram showing the configuration of the driver integrated circuit (IC).

[0111] Reference Figure 17 and Figure 18 The display device may include a display panel 100 having a pixel array disposed on the screen and a display panel driving unit, etc.

[0112] The pixel array of the display panel 100 may include data lines DL, gating lines GL intersecting the data lines DL, and pixels P arranged in a matrix form defined by the data lines DL and the gating lines GL. The pixel array may also include power lines, such as... Figure 20 The VDD line PL1, Vini line PL2, and VSS line PL3 are shown.

[0113] Pixel arrays can be divided into, for example Figure 3 The circuit layer 12 and the light-emitting element layer 14 are shown. A touch sensor array can be disposed on the light-emitting element layer 14. As described above, each pixel of the pixel array can include two to four sub-pixels. Each sub-pixel can include pixel circuitry disposed on the circuit layer 12.

[0114] The screen on the display panel 100 that reproduces the input image may include a first display area DA and a second display area CA.

[0115] Each sub-pixel in each of the first display area DA and the second display area CA may include a pixel circuit. The pixel circuit may include a driving element configured to supply current to the light-emitting element OLED, multiple switching elements configured to sample a threshold voltage of the driving element and switch the current path of the pixel circuit, and a capacitor configured to maintain the gate voltage of the driving element, etc. The pixel circuit may be disposed below the light-emitting element.

[0116] The second display area CA may include a light-transmitting area AG disposed between pixel groups and a camera module 400 disposed below the second display area CA. In imaging mode, the camera module 400 can use an image sensor to perform photoelectric conversion on the light incident through the second display area CA, and convert the pixel data of the image output from the image sensor into digital data to output imaging image data.

[0117] The display panel driving unit can write pixel data of the input image to pixel P. Pixel P can be interpreted as a pixel group comprising multiple sub-pixels.

[0118] The display panel driving unit may include a data driving unit 306 configured to provide data voltages for pixel data to the data line DL, and a gating driving unit 120 configured to sequentially provide gating pulses to the gating line GL. The data driving unit 306 may be integrated into the driver IC 300. The display panel driving unit may also include a touch sensor driving unit (not shown in the figure).

[0119] The driver IC 300 can be attached to the display panel 100. The driver IC 300 receives pixel data and timing signals of the input image from the host system 200, provides data voltages of the pixel data to the pixels, and synchronizes the data driving unit 306 with the gating driving unit 120.

[0120] The driver IC 300 can be connected to the data line DL via the data output channel to provide the data voltage of the pixel data to the data line DL. The driver IC 300 can also output a gating timing signal for controlling the gating drive unit 120 via the gating timing signal output channel.

[0121] The gating timing signal generated by the timing controller 303 may include a gating start pulse VST and a gating shift clock CLK. The gating start pulse VST and the gating shift clock CLK can oscillate between the gating on voltage VGL and the gating off voltage VGH.

[0122] The gating timing signals (VST and CLK) output from the level shifter 307 can be applied to the gating drive unit 120 to control the shifting operation of the gating drive unit 120.

[0123] The gating drive unit 120 may include a shift register formed together with the pixel array on the circuit layer of the display panel 100. The shift register of the gating drive unit 120 may sequentially provide gating signals to the gating line GL under the control of a timing controller. The gating signals may include EM pulses and scan pulses of the emission signal.

[0124] The shift register may include a scan drive unit configured to output scan pulses and an EM drive unit configured to output EM pulses. Figure 18 In this context, "GVST" and "GCLK" are signals included in the gating timing signals input to the scan drive unit. "EVST" and "ECLK" are signals included in the gating timing signals input to the EM drive unit.

[0125] The driver IC 300 can be connected to the host system 200, the first memory 301, and the display panel 100. The driver IC 300 may include a data receiving and computing unit 308, a timing controller 303, a data driving unit 306, a gamma-compensated voltage generating unit 305, a power supply unit 304, and a second memory 302, etc.

[0126] The data receiving and computing unit 308 may include a receiving unit configured to receive pixel data as a digital signal input from the host system 200, and a data computing unit configured to process the pixel data input through the receiving unit to improve image quality.

[0127] The data calculation unit may include a data recovery unit configured to perform recovery by decoding compressed pixel data, and an optical compensation unit configured to add preset optical compensation values ​​to the pixel data. The optical compensation value can be set to compensate for the brightness of each pixel data based on the screen brightness measured from camera images captured during manufacturing.

[0128] The timing controller 303 can provide pixel data of the input image received from the host system 200 to the data driving unit 306. The timing controller 303 can generate a gating timing signal for controlling the gating driving unit 120 and a source timing signal for controlling the data driving unit 306, so as to control the operation timing of the gating driving unit 120 and the data driving unit 306.

[0129] The data driver unit 306 can use a digital-to-analog converter (DAC) to convert digital data, including pixel data received from the timing controller 303, into a gamma-compensated voltage and output a data voltage. The data voltage output from the data driver unit 306 can be provided to the data line DL of the pixel array through the output buffer connected to the data channel of the driver IC 300.

[0130] The gamma compensation voltage generating unit 305 can generate a gamma compensation voltage for each grayscale level by dividing the gamma reference voltage received from the power supply unit 304 via a voltage divider circuit. The gamma compensation voltage is an analog voltage, in which a voltage is set for each grayscale of the pixel data. The gamma compensation voltage output from the gamma compensation voltage generating unit 305 can be provided to the data driving unit 306.

[0131] The power supply unit 304 can use a DC-DC converter to generate the power required to drive the driver IC 300, the gating drive unit 120, and the pixel array of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, and a boost converter, etc.

[0132] The power supply unit 304 can generate DC voltages, such as gamma reference voltage, gating on voltage VGL, gating off voltage VGH, pixel drive voltage VDD, low-potential power supply voltage VSS, and initialization voltage Vini, by adjusting the DC input voltage received from the host system 200.

[0133] The gamma reference voltage can be provided to the gamma compensation voltage generating unit 305. The gating on voltage VGL and the gating off voltage VGH can be provided to the level shifter 307 and the gating drive unit 120. Pixel power supply voltages such as the pixel drive voltage VDD, the low-level power supply voltage VSS, and the initialization voltage Vini can be jointly provided to the pixel P.

[0134] The initialization voltage Vini can be set to a DC voltage that is lower than the pixel drive voltage VDD and lower than the threshold voltage of the OLED to initialize the main node of the pixel circuit and suppress the OLED's emission.

[0135] When power is supplied to the driver IC 300, the second memory 302 can store compensation values ​​and register setting data received from the first memory 301.

[0136] The compensation value can be applied to various algorithms to improve image quality. The compensation value may include optical compensation. Register setting data can define the operation of the data drive unit 306, timing controller 303, and gamma compensation voltage generation unit 305, etc. The first memory 301 may include flash memory. The second memory 302 may include static random access memory (SRAM).

[0137] The host system 200 can be implemented as an application processor (AP). The host system 200 can send pixel data of the input image to the driver IC 300 via a Mobile Industrial Processor Interface (MIPI). The host system 200 can be connected to the driver IC 300 via a flexible printed circuit (e.g., a flexible printed circuit (FPC)).

[0138] The display panel 100 can be implemented as a flexible panel suitable for flexible displays. Flexible displays can have screens whose size can be varied by rolling, folding or bending flexible panels, and can be easily manufactured in a variety of designs.

[0139] Flexible displays can be made into rollable displays, foldable displays, bendable displays, or sliding displays, etc.

[0140] Flexible panels can be manufactured into so-called "plastic OLED panels." A plastic OLED panel can include a backplane and a pixel array formed on an organic film adhered to the backplane. A touch sensor array can be formed on the pixel array.

[0141] The backsheet can be a polyethylene terephthalate (PET) substrate. The pixel array and touch sensor array can be formed on the organic film. The backsheet can prevent moisture from penetrating into the organic film, thus protecting the pixel array from moisture exposure.

[0142] The organic film can be a polyimide (PI) substrate. The multilayer buffer film can be formed from an insulating material (not shown) on the organic film. The circuit layer 12 and the light-emitting element layer 14 can be stacked on the organic film.

[0143] In the display device of this disclosure, the pixel circuit and gating drive unit disposed on the circuit layer 12 may include a plurality of transistors. The transistors may be implemented as oxide thin-film transistors (TFTs) including oxide semiconductors and LTPS TFTs including low-temperature polycrystalline silicon (LTPS). Each transistor may be implemented as a p-channel thin-film transistor (TFT) or an n-channel TFT. The following embodiments are described using an example of implementing the transistors concentrated in the pixel circuit as p-channel TFTs, but this disclosure is not limited thereto.

[0144] A transistor is a three-electrode device consisting of a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. Charge carriers in a transistor can flow from the source. The drain is the electrode through which charge carriers are drained from the transistor to the outside.

[0145] In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, the charge carriers are electrons, so the source voltage is lower than the drain voltage, causing electrons to flow from the source to the drain. In an n-channel transistor, current flows from the drain to the source.

[0146] In the case of a p-channel transistor (PMOS), the charge carriers are holes, so the source voltage is higher than the drain voltage, causing holes to flow from the source to the drain. In a p-channel transistor, because holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the positions of the source and drain of a transistor are not fixed. For example, depending on the applied voltage, the source and drain can be interchanged. Therefore, this disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0147] The gating pulse can oscillate between the gating on voltage and the gating off voltage. The gating on voltage can be set above the transistor's threshold voltage, and the gating off voltage can be set below the transistor's threshold voltage.

[0148] A transistor can turn on in response to a gating on voltage and turn off in response to a gating off voltage. In the case of an n-channel transistor, the gating on voltage can be a high gating voltage VGH, and the gating off voltage can be a low gating voltage VGL. In the case of a p-channel transistor, the gating on voltage can be a low gating voltage VGL, and the gating off voltage can be a high gating voltage VGH.

[0149] The driving element of a pixel circuit can be implemented as a transistor. The driving element should have uniform electrical characteristics across all pixels, but due to variations in process technology and component characteristics, there may be differences in electrical characteristics between pixels, and the electrical characteristics may change over time as the display drives the device.

[0150] To compensate for variations in the electrical characteristics of the driving element, the display device may include internal and external compensation circuitry. Internal compensation circuitry can be added to the pixel circuitry in each sub-pixel to sample the threshold voltage Vth and / or mobility μ of the driving element, which vary according to its electrical characteristics, and to compensate for these variations in real time.

[0151] The external compensation circuit can send the threshold voltage and / or mobility of the driving element sensed by the sensing line connected to each sub-pixel to the external compensation unit. The external compensation unit of the external compensation circuit can reflect the sensing results to modulate the pixel data of the input image, thereby compensating for changes in the electrical characteristics of the driving element.

[0152] It can sense pixel voltages that vary according to the electrical characteristics of the driving elements, and can modulate the data of the input image in an external compensation circuit based on the sensed voltages, thereby compensating for the changes in the electrical characteristics of the driving elements between pixels.

[0153] Figure 19 This is a circuit diagram illustrating an example of a pixel circuit, and Figure 20 This is a circuit diagram showing another example of a pixel circuit. Figure 21 It shows the driver Figure 19 and Figure 20 The diagram shows a method for using pixel circuits.

[0154] Figure 19 and Figure 20 The pixel circuit shown can be similarly applied to the pixel circuits of the first display area DA and the second display area CA. The pixel circuit suitable for this disclosure can be implemented as follows: Figure 19 and Figure 20 The circuit shown is not limited thereto.

[0155] Reference Figures 19 to 21 The pixel circuit may include a light-emitting element (OLED), a driving element (DT) configured to supply current to the OLED, and an internal compensation circuit configured to sample the threshold voltage Vth of the driving element (DT) using a plurality of switching elements M1 to M6 and to compensate the gate voltage of the driving element (DT) to a degree commensurate with the threshold voltage Vth of the driving element (DT). Each of the driving element (DT) and the switching elements M1 to M6 may be implemented as a p-channel TFT.

[0156] like Figure 21 As shown, the driving period of the pixel circuit using the internal compensation circuit can be divided into the initialization period Tini, the sampling period Tsam, the data writing period Twr, and the emission period Tem.

[0157] During the initialization period Tini, a pulse of the (N-1)th scan signal SCAN(N-1) is generated as the gating on-state voltage VGL, and the voltage of each of the Nth scan signal SCAN(N) and the emission signal EM(N) is the gating off-state voltage VGH. During the sampling period Tsam, a pulse of the Nth scan signal SCAN(N) is generated as the gating on-state voltage VGL, and the voltage of each of the (N-1)th scan signal SCAN(N-1) and the emission signal EM(N) is the gating off-state voltage VGH. During the data writing period Twr, the voltage of each of the (N-1)th scan signal SCAN(N-1), the Nth scan signal SCAN(N), and the emission signal EM(N) is the gating off-state voltage VGH. During at least a portion of the emission period Tem, the emission signal EM(N) as the gating on-state voltage VGL can be generated, and the voltage of each of the (N-1)th scan signal SCAN(N-1) and the Nth scan signal SCAN(N) as the gating off-state voltage VGH can be generated.

[0158] During the initialization period Tini, the fifth switching element M5 can be turned on according to the gating voltage VGL of the (N-1)th scan signal SCAN (N-1) to initialize the pixel circuit. During the sampling period Tsam, the first switching element M1 and the second switching element M2 can be turned on according to the gating voltage VGL of the Nth scan signal SCAN (N), so that the threshold voltage of the driving element DT can be sampled and stored in the storage capacitor Cst1. At the same time, the sixth switching element M6 can be turned on during the sampling period Tsam to reduce the voltage of the fourth node n4 to the reference voltage Vref, thereby suppressing the emission of the light-emitting element OLED. During the data writing period Twr, the first switching element M1 to the sixth switching element M1 to M6 can be kept in the off state. During the emission period Tem, the third switching element M3 and the fourth switching element M4 can be turned on, so that the light-emitting element OLED can emit light. During the light emission period Tem, in order to accurately represent the brightness of the low gray level using the duty cycle of the light emission signal EM(N), the light emission signal EM(N) can swing between the gate turn-on voltage VGL and the gate turn-off voltage VGH with a predetermined duty cycle to repeatedly turn on or off the third switching element M3 and the fourth switching element M4.

[0159] OLEDs can be implemented as organic light-emitting diodes or inorganic light-emitting diodes. An example of an OLED implemented as an organic light-emitting diode will be described below.

[0160] An OLED (Optical Display Cell) may include an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but this disclosure is not limited thereto. When a voltage is applied to the anode and cathode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emissive layer (EML) to generate excitons, and thus visible light can be emitted from the emissive layer (EML).

[0161] The anode of the OLED is connected to a fourth node n4 between the fourth switching element M4 and the sixth switching element M6. The fourth node n4 is connected to the anode of the OLED, the second electrode of the fourth switching element M4, and the second electrode of the sixth switching element M6. The cathode of the OLED can be connected to the VSS line PL3, to which a low-potential power supply voltage VSS is applied. The OLED emits light using a current Ids flowing according to the gate-source voltage Vgs of the driving element DT. The third switching element M3 and the fourth switching element M4 can switch the current path of the OLED.

[0162] Storage capacitor Cst1 can be connected between VDD line PL1 and the second node n2. Data voltage Vdata, compensated to a degree equivalent to the threshold voltage Vth of the driving element DT, can be charged into storage capacitor Cst1. Since the data voltage Vdata in each sub-pixel is compensated to a degree equivalent to the threshold voltage Vth of the driving element DT, the characteristic deviation of the driving element DT in each sub-pixel can be compensated.

[0163] The first switching element M1 can be turned on in response to the gating voltage VGL of the Nth scan signal SCAN(N) to connect the second node n2 to the third node n3. The second node n2 can be connected to the gate electrode of the driving element DT, the first electrode of the storage capacitor Cst1, and the first electrode of the first switching element M1. The third node n3 can be connected to the second electrode of the driving element DT, the second electrode of the first switching element M1, and the first electrode of the fourth switching element M4. The gate electrode of the first switching element M1 is connected to the first gating line GL1 to receive the Nth scan signal SCAN(N). The first electrode of the first switching element M1 can be connected to the second node n2, and its second electrode can be connected to the third node n3.

[0164] The first switching element M1 can be turned on only for a very short horizontal period 1H within one frame period, during which the Nth scan signal SCAN(N) is generated as the gate voltage VGL, and therefore can remain in the off state for approximately one frame period. This can potentially lead to leakage current in the off state of the first switching element M1. To suppress the leakage current of the first switching element M1, the first switching element M1 can be implemented as a dual-gate transistor with two transistors M1a and M1b connected in series, such as... Figure 20 As shown.

[0165] The second switching element M2 can be turned on in response to the gating voltage VGL of the Nth scan signal SCAN(N) to provide a data voltage Vdata to the first node n1. The gate electrode of the second switching element M2 can be connected to the first gating line GL1 to receive the Nth scan signal SCAN(N). The first electrode of the second switching element M2 can be connected to the first node n1. The second electrode of the second switching element M2 can be connected to the data line DL to which the data voltage Vdata is applied. The first node n1 can be connected to the first electrode of the second switching element M2, the second electrode of the third switching element M3, and the first electrode of the driving element DT.

[0166] The third switching element M3 can be turned on in response to the gating voltage VGL of the light-emitting signal EM(N) to connect the VDD line PL1 to the first node n1. The gate electrode of the third switching element M3 can be connected to the third gating line GL3 to receive the light-emitting signal EM(N). The first electrode of the third switching element M3 can be connected to the VDD line PL1. The second electrode of the third switching element M3 can be connected to the first node n1.

[0167] The fourth switching element M4 can be turned on in response to the gating voltage VGL of the light-emitting signal EM(N) to connect the third node n3 to the anode of the light-emitting element OLED. The gate electrode of the fourth switching element M4 can be connected to the third gating line GL3 to receive the light-emitting signal EM(N). The first electrode of the fourth switching element M4 can be connected to the third node n3, and its second electrode can be connected to the fourth node n4.

[0168] The fifth switching element M5 can be turned on in response to the gating voltage VGL of the (N-1)th scan signal SCAN (N-1) to connect the second node n2 to the Vini line PL2. The gate electrode of the fifth switching element M5 can be connected to the second gating line GL2 to receive the (N-1)th scan pulse SCAN (N-1). The first electrode of the fifth switching element M5 can be connected to the second node n2, and its second electrode can be connected to the Vini line PL2. To suppress the leakage current of the fifth switching element M5, the fifth switching element M5 can be implemented as a dual-gate transistor with two transistors M5a and M5b connected in series, such as... Figure 20 As shown.

[0169] The sixth switching element M6 can be turned on in response to the gating voltage VGL of the Nth scan signal SCAN(N) to connect the Vini line PL2 to the fourth node n4. The gate electrode of the sixth switching element M6 can be connected to the first gating line GL1 to receive the Nth scan signal SCAN(N). The first electrode of the sixth switching element M6 can be connected to the Vini line PL2, and its second electrode can be connected to the fourth node n4.

[0170] The driving element DT can adjust the current Ids flowing into the light-emitting element OLED according to the gate-source voltage Vgs to drive the light-emitting element OLED. The driving element DT may include a gate electrode connected to the second node n2, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0171] like Figure 21 As shown, during the initialization period Tini, the (N-1)th scan signal SCAN(N-1) can be generated as the gating on-state voltage VGL. During the initialization period Tini, the Nth scan signal SCAN(N) and the emission signal EM(N) can each be held at the gating off-state voltage VGH. Therefore, during the initialization period Tini, the fifth switching element M5 can be turned on, so that the second node n2 can be initialized to "Vini". The holding period Th can be set between the initialization period Tini and the sampling period Tsam. During the holding period Th, SCAN(N) and EM(N) can remain in their previous states.

[0172] During the sampling period Tsam, an Nth scan signal SCAN(N) can be generated as the gating on-state voltage VGL. The Nth scan signal SCAN(N) can be synchronized with the data voltage Vdata of the Nth pixel line. During the sampling period Tsam, the (N-1)th scan signal SCAN(N-1) and the light emission signal EM(N) can each be maintained at the gating off-state voltage VGH. Therefore, during the sampling period Tsam, the first switching element M1 and the second switching element M2 can be turned on.

[0173] During the sampling period Tsam, the gate voltage DTG of the driving element DT can rise due to the current flowing through the first switching element M1 and the second switching element M2. When the driving element DT is turned off, the gate voltage DTG is Vdata - |Vth|. In this case, the voltage of the first node n1 is Vdata. During the sampling period Tsam, the gate-source voltage Vgs of the driving element DT is |Vgs| = Vdata - (Vdata - |Vth|) = |Vth|.

[0174] During the data writing period Twr, the Nth scan signal SCAN(N) can be inverted to the gating cutoff voltage VGH. During the data writing period Twr, the (N-1)th scan signal SCAN(N-1) and the light emission signal EM(N) can each be maintained at the gating cutoff voltage VGH. Therefore, during the data writing period Twr, all switching elements M1 to M6 can remain in the off state.

[0175] During the emission period Tem, an emission signal EM(N) can be generated as a gating voltage VGL. During the emission period Tem, to improve low grayscale performance, the emission signal EM(N) can be turned on or off with a predetermined duty cycle, oscillating between the gating voltage VGL and the gating voltage VGH. Therefore, for at least a portion of the emission period Tem, an emission signal EM(N) as a gating voltage VGL can be generated.

[0176] When the emission signal EM(N) is at the gate turn-on voltage VGL, current flows between "VDD" and the OLED, allowing the OLED to emit light. During the emission period Tem, the (N-1)th scan pulse SCAN(N-1) and the Nth scan pulse SCAN(N) can each be maintained at the gate turn-off voltage VGH. During the emission period Tem, the third switching element M3 and the fourth switching element M4 can be repeatedly turned on and off according to the voltage of the emission signal EM(N). When the emission signal EM(N) is at the gate turn-on voltage VGL, the third switching element M3 and the fourth switching element M4 are turned on, allowing current to flow in the OLED. In this case, the "Vgs" of the driving element DT satisfies |Vgs|=VDD-(Vdata-|Vth|), and the current flowing in the OLED is K(VDD-Vdata)2. "K" is a constant determined by the charge mobility, parasitic capacitance, and channel capacitance of the driving element DT.

[0177] Figure 22 This is a cross-sectional view showing in detail the cross-sectional structure of a pixel region in a display panel according to one embodiment of the present disclosure.

[0178] The cross-sectional structure of the display panel 100 is not limited to Figure 22 The structure within. In Figure 22 In this context, "TFT" represents the driving element DT of the pixel circuit.

[0179] Reference Figure 22 Circuit layers and light-emitting element layers can be stacked on substrates PI1 and PI2 within the pixel region (PIX). Substrates PI1 and PI2 can include a first PI substrate PI1 and a second PI substrate PI2. An inorganic film IPD can be formed between the first PI substrate PI1 and the second PI substrate PI2. The inorganic film IPD can block the penetration of moisture.

[0180] A first buffer layer BUF1 can be formed on the second PI substrate PI2. A first metal layer can be formed on the first buffer layer BUF1, and a second buffer layer BUF2 can be formed on the first metal layer. The first metal layer can be a first light-blocking layer LS.

[0181] Each of the first buffer layer BUF1 and the second buffer layer BUF2 may be made of inorganic insulating material and may be formed by one or more insulating layers.

[0182] The active layer ACT can be made of semiconductor material deposited on the second buffer layer BUF2 and can be patterned by photolithography. The active layer ACT can include active patterns for each of the TFTs in the pixel circuit and the TFTs in the gating drive unit.

[0183] A portion of the active layer ACT can be metallized through ion doping. The metallized portion can be used as a jumper pattern, which connects the metal layer at some nodes of the pixel circuit to connect the components of the pixel circuit.

[0184] A gate insulating layer GI can be formed on the second buffer layer BUF2 to cover the active layer ACT. The gate insulating layer GI can be made of an inorganic insulating material.

[0185] A second metal layer can be formed on the gate insulating layer GI. The second metal layer can be patterned using a photolithography process. The second metal layer may include gate lines, gate electrode patterns GATE, the lower electrode of the storage capacitor Cst1, and jumper patterns connecting the patterns of the first metal layer and the third metal layer, etc.

[0186] A first interlayer insulating layer ILD1 can be formed on the gate insulating layer GI to cover the second metal layer. A third metal layer can be formed on the first interlayer insulating layer ILD1, and a second interlayer insulating layer ILD2 can cover the third metal layer.

[0187] The third metal layer can be patterned using photolithography. The third metal layer may include a metal pattern TM, such as the upper electrode of a storage capacitor Cst1. The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may each comprise an inorganic insulating material.

[0188] A fourth metal layer can be formed on the second interlayer insulating layer ILD2, and an inorganic insulating layer PAS1 and a first planarization layer PLN1 can be stacked on the fourth metal layer. A fifth metal layer can be formed on the first planarization layer PLN1.

[0189] Some patterns of the fifth metal layer can be connected to the fourth metal layer through contact holes passing through the first planarization layer PLN1 and the inorganic insulating layer PAS1. The first planarization layer PLN1 and the second planarization layer PLN2 can each be made of an organic insulating material capable of planarizing their surfaces.

[0190] The fourth metal layer may include the first and second electrodes of the TFT, which are connected to the active pattern of the TFT through contact holes passing through the second interlayer insulating layer ILD2. Data lines DL and power lines PL1, PL2, and PL3 may be implemented using the pattern SD1 of the fourth metal layer or the pattern SD2 of the fifth metal layer.

[0191] An anode AND, serving as the first electrode of an OLED (OLED light-emitting element), can be formed on the second planarization layer PLN2. The anode AND can be connected to the electrode of a TFT (TFT-based TFT) used as a switching or driving element via contact holes through the second planarization layer PLN2. The anode AND can be made of a transparent or translucent electrode material.

[0192] Pixel-limiting film (BNK) can cover the anode and AND of an OLED light-emitting element. The BNK can be formed into a pattern that defines a light-emitting area (or an opening area), through which light passes from each pixel to the outside.

[0193] Spacer structures (SPCs) can be formed on the pixel-defined film (BNK). The BNK and SPCs can be integrated using the same organic insulating material. The SPCs ensure a gap between the fine metal mask (FMM) and the anode AND, preventing the FMM from contacting the anode AND during the deposition of the organic compound EL.

[0194] Organic compound EL can be formed in the light-emitting area defined by the pixel-defining film BNK in each pixel. A cathode CAT, which serves as the second electrode of the light-emitting element OLED, can be formed on the entire surface of the display panel 100 to cover the pixel-defining film BNK, the spacer SPC, and the organic compound EL.

[0195] The cathode CAT can be connected to the VSS line PL3 formed by any of the underlying metal layers. The capping layer CPL can cover the cathode CAT. The capping layer CPL can be made of inorganic insulating material to prevent air penetration and degassing of the organic insulating material applied to the capping layer CPL, thereby protecting the cathode CAT.

[0196] The inorganic insulating layer PAS2 can cover the capping layer CPL, and the planarization layer PCL can be formed on the inorganic insulating layer PAS2. The planarization layer PCL can include an organic insulating material. An inorganic insulating layer PAS3, which is an encapsulation layer, can be formed on the planarization layer PCL.

[0197] Figure 23 yes Figure 5 An enlarged view of the M1 section, and Figure 24 It shows along Figure 23 A view of the cross-sectional structure of the portion intercepted by lines A-A' and B-B'.

[0198] Reference Figure 23 and Figure 24 It can be confirmed that the first electrode AND and the second electrode CAT, which are connected to each of the sub-pixels R1, G1 and B1 set in the pixel area PA, extend to the light-transmitting area AG and are connected to the virtual pixels R2, G2 and B2 set in the light-transmitting area.

[0199] The first light-blocking layer LS can be formed from a metal that has a low absorption coefficient for the laser wavelength used in the laser ablation process compared to the metal layer (e.g., cathode) to be removed from the light-transmitting region AG.

[0200] The first light-blocking layer LS can also be used as a light-shielding layer to block the laser beam LB during laser ablation. In the area where the light-transmitting region AG of the pixel is set, the first light-blocking layer LS can be set as a whole, thereby preventing the electrode or pixel from being removed by the laser.

[0201] Figure 25 It shows along Figure 23 A view of the cross-sectional structure of the portion intercepted by lines A-A' and C-C', and Figure 26 yes Figure 25 Examples of variations.

[0202] Reference Figure 25In the light-transmitting region AG, an opening H2 can be formed in the cathode CAT. The opening H2 can be formed by forming the cathode CAT on the pixel-defining film BNK and then etching both the cathode CAT and the pixel-defining film BNK in a single step. Therefore, a first groove RC1 can be formed in the pixel-defining film BNK, and the opening H2 of the cathode CAT can be formed on the first groove RC1. However, this disclosure is not limited to this, and the cathode CAT can be disposed on the second planarization layer PLN2 instead of forming the pixel-defining film on the light-transmitting region AG.

[0203] In the light-transmitting region AG, a first light-transmitting pattern 18d can be formed in the polarizer 18. The first light-transmitting pattern 18d can be formed by using a laser to discolor the polarizer 18b, or by partially removing the polarizer 18b.

[0204] Polarizer 18b can be made of dichroic materials, such as iodine and organic dyes. Organic dyes may include azo dyes, stilbene dyes, pyrazolone dyes, triphenylmethane dyes, quinolinyl dyes, oxazine dyes, thiazine dyes, or anthraquinone dyes, but this disclosure is not limited to these. When a laser of a specific wavelength is irradiated onto the dichroic material, the light absorption rate in the visible light region may decrease.

[0205] According to this embodiment, in the light-transmitting region AG, due to the irradiated laser, a first light-transmitting pattern 18d is formed in the polarizing plate 18, and an opening H2 is formed in the cathode, thereby improving light transmittance. Therefore, a sufficient amount of light can be introduced into the camera module 400, thereby improving camera performance. Furthermore, noise in the image data can be reduced.

[0206] Reference Figure 26 The pixel region may include a first light-blocking layer LS1 and a second light-blocking layer LS2 disposed between the first light-blocking layer LS1 and the substrates PI1 and PI2, to prevent light from incident on the thin-film transistor.

[0207] The first light-blocking layer LS1 can block external light, preventing light from shining on the active layer of the TFT, thereby preventing the TFT formed in the pixel area from generating photocurrent. The first light-blocking layer LS1 can be disposed only in the pixel area PA, and can be excluded from the light-transmitting area AG.

[0208] The first buffer layer BUF1 can be disposed between the first light-shielding layer LS1 and the second light-shielding layer LS2, so that the first light-shielding layer LS1 and the second light-shielding layer LS2 can be electrically insulated from each other. Therefore, the first light-shielding layer LS1 can maintain the TFT characteristics unchanged.

[0209] The second light-blocking layer LS2 can extend into the light-transmitting region AG and can be patterned. The second light-blocking layer LS2 can be formed of a metal with a low absorption coefficient for the laser wavelength used in the laser ablation process compared to the metal layer (e.g., cathode) to be removed from the light-transmitting region AG.

[0210] Therefore, when the second light-blocking layer LS2 is pre-patterned and then laser is irradiated from the rear surface, the second electrode CAT can be removed from the light-transmitting area AG, excluding the area where the second pixel is formed.

[0211] According to this embodiment, the first light-shielding layer LS1 can be used to block light from entering the TFT, and the second light-shielding layer LS2 can be used to pattern the second electrode CAT in the light-transmitting region AG.

[0212] Figure 27 This is a view showing various electronic devices arranged in the second display area. Figure 28 yes Figure 27 An enlarged view of the M2 section, and Figure 29 yes Figure 27 An enlarged view of the M3 section.

[0213] Reference Figure 27 The display panel may include multiple electronic devices disposed in the second display area CA. For example, the multiple electronic devices may include an ambient light sensor for determining ambient brightness, a proximity sensor, a first camera module 42a having an image sensor embedded therein, and a second camera module 42b configured to receive infrared light. The first camera module 42a may be provided with an infrared filter, thus blocking the infrared band and receiving visible light, while the second camera module 42b may receive infrared light.

[0214] At this point, compared to the first camera module 42a, the second camera module 42b can perform relatively accurate measurements even with less light. Therefore, the patterns of the second pixel P2 set on the first camera module 42a and the second pixel P2 set on the second camera module 42b can be set differently.

[0215] For example, in the area where the second camera module 42b is located in the second display area CA, such as Figure 28 As shown, red pixel R2, green pixel G2, and blue pixel B1 can all be placed in the light-transmitting area AG. Conversely, in the area where the first camera module 42a is located, such as Figure 29 As shown, only the green pixel G2 can be placed in the light-transmitting area AG. Furthermore, in the area where the first camera module 42a is located, pixels are not placed in certain areas of the light-transmitting area AG, thereby maximizing the light-transmitting area.

[0216] According to the implementation method, display performance can be improved by increasing the light-emitting area in the imaging region.

[0217] Camera performance can also be improved by ensuring sufficient light transmission in the imaging area.

[0218] It can also improve the lifespan of pixels.

[0219] The same fine metal mask (FMM) can also be used to form pixels in both the display and imaging areas to reduce manufacturing costs.

[0220] The effects of the embodiments according to this disclosure are not limited to the above-described examples, and many more effects are included in this specification.

[0221] While embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments, and various modifications and variations can be made without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed herein are to be considered descriptive and not limiting of the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. Thus, the above embodiments should be understood as exemplary and not limiting in any way. The scope of the present disclosure should be interpreted by the appended claims, and all technical spirit within its equivalents should be interpreted as included within the scope of the present disclosure.

[0222] Cross-references to related applications

[0223] This application claims priority and benefit to Korean Patent Application No. 2020-0112527, filed on September 3, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A display panel, the display panel comprising: A first display area, wherein a plurality of pixels are provided in the first display area; as well as The second display area includes multiple pixel areas having multiple pixels and multiple light-transmitting areas disposed between the multiple pixel areas. The second display area includes: A plurality of first pixels, wherein the plurality of first pixels are respectively disposed in the plurality of pixel regions. A plurality of second pixels, wherein the plurality of second pixels are respectively disposed in the plurality of light-transmitting areas. A plurality of first electrodes, each extending from a plurality of pixel regions to a plurality of light-transmitting regions, respectively electrically connect each of the plurality of first pixels to each of the plurality of second pixels. A second electrode, which covers the plurality of first electrodes. In the plurality of light-transmitting regions, the first electrode and the second electrode have corresponding shapes and overlap in the vertical direction.

2. The display panel according to claim 1, wherein, The pixel data applied to each of the first pixels is applied equally to the corresponding second pixel through the plurality of first electrodes, such that the image output from each of the first pixels is the same as the image output from the corresponding second pixel.

3. The display panel according to claim 1, wherein, The first pixel is a driving pixel that includes a pixel circuit and a light-emitting element, while the second pixel is a virtual pixel of the first pixel, and the virtual pixel only includes a light-emitting element.

4. The display panel according to claim 1, wherein, The second display area includes a second electrode that covers the plurality of pixel areas and includes a plurality of openings corresponding to the plurality of light-transmitting areas. The second electrode extends into the interior of each of the plurality of openings to electrically connect each of the plurality of first pixels to each of the plurality of second pixels, respectively.

5. The display panel according to claim 1, wherein, The number of pixels per unit area in the first display area is the same as the number of pixels per unit area in the second display area.

6. The display panel according to claim 1, wherein, The number of pixels per unit area in the first display area is different from the number of pixels per unit area in the second display area.

7. The display panel according to claim 1, wherein, in, Each of the first pixels includes a plurality of sub-pixels, and each of the second pixels includes a plurality of sub-pixels, wherein the number of sub-pixels in each of the second pixels is equal to or less than the number of sub-pixels in each of the first pixels.

8. The display panel according to claim 1, wherein, Each of the second pixels disposed in the light-transmitting area includes a first sub-pixel and a second sub-pixel. The first sub-pixel of the second pixel is electrically connected to the first sub-pixel of the first pixel region surrounding the corresponding light-transmitting region among the plurality of pixel regions, and The second sub-pixel of the second pixel is electrically connected to the second sub-pixel of the first pixel region.

9. The display panel according to claim 1, wherein, Each of the second pixels disposed in the light-transmitting area includes a first sub-pixel and a second sub-pixel. The first sub-pixel of the second pixel is electrically connected to the first sub-pixel of the first pixel region surrounding the corresponding light-transmitting region among the plurality of pixel regions, and The second sub-pixel of the second pixel is electrically connected to the second sub-pixel of the second pixel region surrounding the corresponding light-transmitting region among the plurality of pixel regions.

10. The display panel according to claim 1, wherein, Each of the second pixels in the light-transmitting area includes a first unit sub-pixel and a second unit sub-pixel that output the same color. The first unit sub-pixel is electrically connected to the second sub-pixel of the first pixel region surrounding the corresponding light-transmitting region among the plurality of pixel regions, and The second unit sub-pixel is electrically connected to the second sub-pixel of the second pixel region surrounding the corresponding light-transmitting region among the plurality of pixel regions, and In this configuration, the first unit sub-pixel, the second unit sub-pixel, and the second sub-pixel output the same color.

11. The display panel according to claim 10, wherein, The first electrode includes a first unit sub-electrode corresponding to the first unit sub-pixel and a second unit sub-electrode corresponding to the second unit sub-pixel in each light-transmitting region, and the first unit sub-electrode and the second unit sub-electrode are spaced apart from each other.

12. The display panel according to claim 10 or 11, wherein, Each of the first pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. Each of the second pixels is configured such that at least one of the first sub-pixel, the second sub-pixel, and the third sub-pixel is omitted, and Different subpixels are set in adjacent second pixels.

13. A display panel, the display panel comprising: A first display area, wherein a plurality of pixels are provided in the first display area; as well as The second display area includes a pixel area with multiple pixels and a light-transmitting area adjacent to the pixel area. The second display area includes: A plurality of first electrodes, the plurality of first electrodes extending from the pixel region to the light-transmitting region, and A second electrode, which covers the plurality of first electrodes. The shape of the second electrode disposed in the light-transmitting area is different from the shape of the second electrode disposed in the pixel area.

14. The display panel according to claim 13, wherein, The first electrode electrically connects the pixel disposed in the light-transmitting area to the pixel disposed in the pixel area.

15. The display panel according to claim 14, wherein, The second electrode includes an opening corresponding to the light-transmitting area, and the first electrode extends into the opening.

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