A semiconductor thermoelectric device and its fabrication method

Abstract

This invention discloses a semiconductor thermoelectric device and its fabrication method. The semiconductor thermoelectric device includes a thermoelectric module and a packaging structure. The thermoelectric module includes a first ultrathin thermally conductive substrate, a first ultrathin thermally conductive insulating layer, a thermoelectric unit, a second ultrathin thermally conductive insulating layer, and a second ultrathin thermally conductive substrate stacked sequentially. The thermoelectric unit includes p-type thermoelectric legs and n-type thermoelectric legs, which are respectively provided with a first electrical input electrode and a second electrical input electrode. A high thermal conductivity outer package is disposed on the outer surface of the thermoelectric unit between the first and second ultrathin thermally conductive insulating layers. The first electrical input wire and the second electrical input wire pass through the high thermal conductivity outer package and are respectively connected to the first electrical input electrode and the second electrical input electrode. This invention overcomes the bottlenecks of the prior art, improves the thermal stability, mechanical structure performance, and packaging compatibility of the semiconductor thermoelectric cooling device, ensures excellent cooling performance and temperature control level under a wide temperature range, and expands the working environment.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically, it relates to a semiconductor thermoelectric device and its preparation method, and more specifically, it relates to a semiconductor thermoelectric cooling device and its preparation method. Background Technology

[0002] Semiconductor thermoelectric coolers (TECs) based on the Peltier effect can achieve active cooling or heating. They offer advantages such as miniaturization, noiselessness, zero pollution, precise temperature control, and high reliability, and have been widely used for active temperature control in optoelectronic fusion devices such as fifth-generation communication transmission optical modules, data center optical communications, lasers / modulators / receivers, and photonic integrated chips. Especially in high-speed optical modules and automotive lidar applications involving optical wavelength or frequency detection communication, semiconductor thermoelectric coolers have become essential temperature control devices, accounting for more than 15% of the total cost. Semiconductor thermoelectric coolers typically consist of p-type and n-type thermoelectric legs connected in thermal parallel and electrical series with metal electrodes. Their cooling performance is expressed as the maximum cooling density (q). c_max The unit is W cm -2 Maximum cooling temperature difference ΔT max The coefficient of performance (COP; dimensionless) is used to measure these parameters. These three parameters primarily depend on the figure of merit (zT = S) of the semiconductor thermoelectric material. 2 σT / κ; where S is the Seebeck coefficient, σ is the electrical conductivity, κ is the thermal conductivity, and T is the ambient temperature), the contact resistance and thermal resistance of the thermoelectric leg-metal electrode interface, and the device fill factor (the ratio of the total area of ​​the thermoelectric material to the device area). Therefore, high-performance semiconductor thermoelectric devices need to simultaneously consider either the material zT or the power factor S. 2 σ, interface contact design and device physical architecture, thereby obtaining q c_max or ΔT max .

[0003] In recent years, thin-film microdevices fabricated using microelectronic compatible processes such as silicon-based complementary metal-oxide-semiconductor (CMOS), physical vapor deposition (PVD, including magnetron sputtering, thermal evaporation, atomic layer deposition, and molecular beam epitaxy), chemical vapor deposition (CVD), and electrochemical deposition (ECD) have been reported. For example, thermoelectric microdevices such as silicon nanowires, polycrystalline silicon, and polycrystalline silicon-germanium fabricated using CMOS combined with CVD processes can achieve a thickness of 1 mm. 2 On-chip power conversion; Ge-doped silicon-based microdevices using a 65nm CMOS process can achieve up to 85 μW cm⁻¹ -2 K -2 The normalized power density is high, but the thermoelectric performance of the aforementioned silicon-based μTEC is still limited by the intrinsically high thermal conductivity of the silicon substrate. At room temperature, the thermal conductivity of single-crystal silicon is approximately 150 W / m². -1 K -1 The thermal conductivity of polycrystalline bismuth telluride is approximately 3 W / m. -1 K -1 Furthermore, BiTeSe / Te-based microdevices fabricated using semiconductor lithography combined with ECD achieved high-density integration of 5500 thermoelectric legs per square centimeter and a maximum cooling temperature difference of 6 °C, while reducing the thermal response time to less than 1 ms. Bi2Te3-based superlattice thermoelectric thin film microdevices (p-type Bi2Te3 / Sb2Te3, n-type Bi2Te3 / Sb2Te3) were also fabricated using metal-organic chemical vapor deposition. 2.7 Se 0.3 While achieving high z-T, 16 pairs of thermoelectric legs were constructed, and the COP was increased to 15 under a 2 °C cooling temperature difference. Benefiting from the compatibility and large-scale fabrication advantages of semiconductor processes such as PVD, Ag-doped n-type Bi₂Te₃ thin films deposited by magnetron sputtering achieved a thermoelectric figure of merit of 1.2 and a coefficient of performance (COP) of 22 μW / cm². -2 K -2 The normalized power density was achieved; α-MgAgSb prepared by molecular beam epitaxy achieved a thermoelectric figure of 0.8 and a power density of 4.9 μW / cm². -2 K -2 The normalized power density.

[0004] As optical module transmission rates exceed gigabytes per second, total heat dissipation increases dramatically. Matching semiconductor temperature control devices urgently need to meet requirements such as large cooling capacity, fast temperature response, and high temperature control accuracy. While the aforementioned work has improved the performance of thermoelectric devices and refined manufacturing methods to some extent, the core issues that urgently need to be addressed for precision thermoelectric temperature control are: ① How to reduce substrate thermal resistance and interface thermal resistance to minimize thermal conductivity barriers; ② How to improve overall cooling performance through thermal topology engineering design, given the limited or optimal performance of semiconductor thermoelectric materials; ③ How to improve the overall effective thermal conductivity of the device through packaging materials and structural design; ④ How to maintain high-efficiency thermal conductivity and operational stability over extended periods. Summary of the Invention

[0005] The purpose of this invention is to address the above-mentioned shortcomings by providing a semiconductor thermoelectric device and its fabrication method. This semiconductor thermoelectric device utilizes an ultra-thin thermally conductive substrate to reduce thermal resistance and promote heat conduction; an ultra-thin thermally conductive insulating layer to provide electrical isolation and reduce thermal expansion stress at heterogeneous interfaces while increasing bonding strength; thermal topology engineering to design the device's physical structure and achieve optimal matching and maximization of thermoelectric material performance; and high thermal conductivity inner and outer encapsulation to solidify the thermoelectric cooling device, thereby improving the device's passive effective thermal conductivity and impact resistance. This overcomes the technical bottlenecks of traditional thermoelectric cooling devices, such as low coefficient of performance, small cooling capacity, small cooling temperature difference, large substrate thermal resistance, poor passive thermal conductivity, poor impact resistance, difficulty in weight reduction, and incompatibility of common substrate packaging processes. Simultaneously, it significantly improves the thermal stability, mechanical structure performance, and packaging compatibility of the semiconductor thermoelectric cooling device, ensuring excellent cooling performance and temperature control levels over a wide temperature range, and expanding its operating environment.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0007] In a first aspect, the present invention provides a semiconductor thermoelectric device, including a thermoelectric module and a packaging structure;

[0008] The thermoelectric module includes a first ultrathin thermally conductive substrate, a first ultrathin thermally conductive insulating layer, a thermoelectric unit, a second ultrathin thermally conductive insulating layer, and a second ultrathin thermally conductive substrate stacked sequentially.

[0009] The packaging structure includes a high thermal conductivity inner package and a high thermal conductivity outer package;

[0010] The thermoelectric unit includes p-type thermoelectric legs and n-type thermoelectric legs; the p-type thermoelectric legs at the top of adjacent thermoelectric units are electrically connected to the n-type thermoelectric legs through the upper electrode, and the p-type thermoelectric legs at the bottom are electrically connected to the n-type thermoelectric legs through the lower electrode; adjacent thermoelectric units adopt high thermal conductivity internal encapsulation to achieve thermal filling and electrical insulation;

[0011] The p-type and n-type thermoelectric legs on both sides of the bottom of the thermoelectric module are respectively provided with a first electrical input electrode and a second electrical input electrode. A high thermal conductivity outer package is provided on the outer surface of the thermoelectric unit between the first ultra-thin thermally conductive insulation layer and the second ultra-thin thermally conductive insulation layer. The first electrical input wire and the second electrical input wire pass through the high thermal conductivity outer package and are respectively connected to the first electrical input electrode and the second electrical input electrode.

[0012] In the above technical solution, the ultrathin thermally conductive insulating layer is disposed between the ultrathin thermally conductive substrate and the electrode. On the one hand, it establishes electrical insulation between the ultrathin thermally conductive substrate and the electrode, avoiding secondary electrical connection between the p-type thermoelectric leg and the n-type thermoelectric leg; on the other hand, it provides a stress buffer layer, reducing the thermal expansion stress at the heterogeneous interface and increasing the bonding strength, thereby realizing mechanical support and heterogeneous interface integration between the ultrathin thermally conductive substrate and the electrode.

[0013] The high thermal conductivity inner encapsulation and the high thermal conductivity outer encapsulation serve the same purpose: firstly, to improve the passive thermal conductivity of the device at the filler material level based on the effective dielectric theory, and to achieve rapid heat homogenization and conduction under active cooling conditions; secondly, to improve the internal electrical insulation properties, impact resistance, and high-temperature and high-humidity operating stability of the device. The physical principle is as follows: Semiconductor thermoelectric materials often pursue a high figure of merit zT to satisfy a large theoretical maximum cooling temperature difference ΔT. max However, the inherently low thermal conductivity of thermoelectric materials is not conducive to passive heat conduction and space heat equalization. Therefore, it is necessary to improve the overall thermal conductivity and heat equalization capability of the device by encapsulating or filling it with high thermal conductivity materials.

[0014] In this invention, the thermal conductivity of both the high thermal conductivity inner package and the high thermal conductivity outer package is greater than 5 W·m. -1 ·K -1 ;

[0015] Furthermore, the p-type thermoelectric leg includes at least one of the p-type high-temperature thermoelectric leg, the p-type medium-temperature thermoelectric leg, and the p-type low-temperature thermoelectric leg, and a barrier layer is provided between different p-type thermoelectric legs;

[0016] The n-type thermoelectric leg includes at least one of the n-type high-temperature thermoelectric leg, the n-type medium-temperature thermoelectric leg, and the n-type low-temperature thermoelectric leg, and a barrier layer is provided between different n-type thermoelectric legs.

[0017] Furthermore, the barrier layer is in the form of powder, film, or foil, with a thickness of [0.01 μm, 0.1 mm], and is made of one or more of the following metals: Au, Ag, Ta, Cu, Ti, TiN, TiW, Ni, and Mo. Specifically, the barrier layers at the same level between adjacent p-type and n-type thermoelectric legs have the same thickness, material, and form.

[0018] For example, the p-type thermoelectric leg can be configured to include, from top to bottom, a first barrier layer, a p-type high-temperature thermoelectric leg, a second barrier layer, a p-type medium-temperature thermoelectric leg, a third barrier layer, a p-type low-temperature thermoelectric leg, and a fourth barrier layer; the n-type thermoelectric leg can be configured to include, from top to bottom, a fifth barrier layer, an n-type high-temperature thermoelectric leg, a sixth barrier layer, an n-type medium-temperature thermoelectric leg, a seventh barrier layer, an n-type low-temperature thermoelectric leg, and an eighth barrier layer. The first and fifth barrier layers have the same thickness, material, and form; the second and sixth barrier layers have the same thickness, material, and form; the third and seventh barrier layers have the same thickness, material, and form; and the fourth and eighth barrier layers have the same thickness, material, and form.

[0019] In the above technical solution, the barrier layer effectively prevents elemental diffusion between the thermoelectric material and the electrode during welding; it also enhances the interfacial bonding strength, forming a good ohmic contact and reducing contact resistance. The barrier layer material has good composition, structure, and thermal matching with the thermoelectric material, and forms a compound with the thermoelectric material powder during densification sintering, creating an interlocking structure at the interface, increasing bonding strength, reducing cracks, blocking element migration at the contact interface, lowering contact resistance, and increasing carrier extraction capability.

[0020] Furthermore, the thickness of the high thermal conductivity inner package is [0.01 mm, 0.1 mm], and the fill rate is [5%, 95%].

[0021] The dimensions of each side of the p-type high-temperature thermoelectric leg are [0.1μm, 1cm], the dimensions of each side of the p-type medium-temperature thermoelectric leg are [0.1μm, 1cm], and the dimensions of each side of the p-type low-temperature thermoelectric leg are [0.1μm, 1cm].

[0022] The dimensions of each side of the n-type high-temperature thermoelectric leg are [0.1μm, 1cm], the dimensions of each side of the n-type medium-temperature thermoelectric leg are [0.1μm, 1cm], and the dimensions of each side of the n-type low-temperature thermoelectric leg are [0.1μm, 1cm].

[0023] In this invention, the high temperature range of the p-type high-temperature thermoelectric leg and the n-type high-temperature thermoelectric leg is above 300 °C; the medium temperature range of the p-type medium-temperature thermoelectric leg and the n-type medium-temperature thermoelectric leg is 100~300 °C; and the medium temperature range of the p-type low-temperature thermoelectric leg and the n-type low-temperature thermoelectric leg is below 100 °C.

[0024] In this invention, the cross-sectional area ratio of the p-type thermoelectric leg to the n-type thermoelectric leg can be adjusted according to the thermal conductivity and electrical conductivity of the material to maximize the theoretical thermoelectric performance of the device. The physical principle is as follows:

[0025] Semiconductor thermoelectric devices are typically constructed by connecting p-type and n-type thermoelectric legs with metal electrodes in a thermally parallel and electrically series configuration. Given the known thermal conductivity of the thermoelectric material (…),… , ) and conductivity ( , Under these conditions, when the cross-sectional area of ​​the thermoelectric leg satisfies a specific proportional relationship ( Only in this way can the figure of merit zT of the thermoelectric device be maximized; where A p Let A be the cross-sectional area of ​​the p-type thermoelectric leg. n The cross-sectional area of ​​the n-type thermoelectric leg. The thermal conductivity of the n-type thermoelectric leg. The thermal conductivity of the p-type thermoelectric leg. The conductivity of the n-type thermoelectric leg. Let be the conductivity of the p-type thermoelectric leg. Therefore, for a given thermoelectric material, it is necessary to actively design the device topology geometry to improve the theoretical maximum cooling temperature difference ΔT. max And the coefficient of performance (COP). In this invention, the cross-sectional shape of the p-type thermoelectric leg and the n-type thermoelectric leg can be cylindrical, prismatic, or other irregular shapes, as long as the ratio of the cross-sectional area of ​​the p-type thermoelectric leg to the n-type thermoelectric leg meets the requirements.

[0026] Furthermore, the material of the p-type thermoelectric leg is one or more of the following: p-type telluride, p-type chalcogenide, p-type silicide, p-type Zintl phase compound, p-type semi-Hessler compound, p-type cobaltite compound, p-type oxide material, p-type III-V compound, ZnSb, CeS, InSb, LiCdN, LiCdP, LiCdAs, LiCdSb, LiCdBi, p-type nickel-based alloy, p-type cage compound, p-type magnesium-based compound, and p-type high-entropy alloy; wherein, the p-type telluride includes Bi2Te3, BiSbTe, Bi 0.5 Sb 1.5 Te3, (Bi,Sb)2Te3, AgSbTe2, AgSbTe3, PbTe, GeTe, SnTe; the p-type chalcogenides include SnSe, Cu2Se, PbSe, Cu 1.8 S, Cu2S; the p-type silicides include SiGe alloys, MnSi 1.74 MnSi 1.73 β-FeSi2, Mg2Si 0.3 Sn 0.7 CrSi2; the p-type Zintl phase compound includes Yb 14 MnSb 11Ca5Al2Sb6, YbCd2Sb2, Zn4Sb3; the p-type semi-Hessler compounds include TiCoSb, HfCoSb, ZrCoSb, NbFeSb, NbFe 1-x Mn x Sb, FeNbSb, PdScAs, NiLuAs; the p-type cobaltite compound includes CoSb3 and CeFe4Sb 12 Yb 0.3 Co4Sb 12 The p-type oxide materials include NaCo2O4, Ca3Co4O9, and BiCuSeO; the p-type III-V compounds include GaN, GaP, GaSb, and GaAs; the p-type nickel-based alloys include Cu-Ni-based alloys, Ni-Au-based alloys, Ni-Ge alloys, and Ni-Cr-based alloys; the p-type cage compounds include Ba8Ga 16 Ge 30 Ba8Cu 14 Ge6P 26 The p-type magnesium-based compounds include Mg3Sb2, etc.

[0027] More preferably, the material of the p-type high-temperature thermoelectric leg is a p-type PbTe-based material or a p-type squartzite compound; the material of the p-type medium-temperature thermoelectric leg is a p-type Bi2Te3-based material; and the material of the p-type low-temperature thermoelectric leg is a p-type Mg3Sb2-based material.

[0028] Furthermore, the material of the n-type thermoelectric leg is one or more of the following: n-type telluride, n-type chalcogenide, n-type silicide, n-type magnesium-based compound, n-type Zintl phase compound, n-type cobaltite compound, n-type Half-Heusler compound, n-type oxide, La3Te4, n-type III-V compound, n-type II-VI compound, n-type organic semiconductor, n-type nickel-based alloy, Bi-Sb alloy, and n-type high-entropy alloy; wherein the n-type telluride includes Bi2SeTe2, Bi2(Te,Se)3, and Bi2Te 2.7 Se 0.3 ,PbTe,Sb2Te3,AgBiPbSe2S,Ag 20 S7Te3; the n-type chalcogenides include SnSe, PbSe, CuFeS2; the n-type silicides include Si 70 Ge 30 Si 80 Ge 20 Mg2Si, Mg2Sn, Mg2Sn 0.75 Ge 0.25 The n-type magnesium-based compound includes Mg3Sb. 2、Mg3(Sb,Bi)2, Mg 3.15 Bi 1.46 Sb 0.5 Te 0.04 Mg2Si 0.3 Sn 0.7 The n-type Zintl phase compounds include Ca5Al2Sb6, KSnBi, RbSnBi, and NaGeP; the n-type guarbitrate compounds include CoSb3, Yb-CoSb3, and La. 0.9 Ni x Co 4-x Sb 12 The n-type Half-Heusler compounds include ZrNiSn, TiNiSn, HfNiSn, NbCoSn, and NbCo. 1-x Ni x Sn, Nb 0.8 CoSb, NiScAs; the n-type oxides include ZnO, SrTiO3, CaMnO3, In2O3; the n-type III-V compounds include GaAs, GaN, etc.; the n-type II-VI compounds include CdSe, CdTe; the n-type organic semiconductors include poly(nickel-ethylenetetrasulfate) and poly(nickel-ethylenetetrathiol); the n-type nickel-based alloys include Cu-Ni alloys, Ni-Cr alloys, Ni-Al alloys, and Ni-Si alloys.

[0029] More preferably, the material of the n-type high-temperature thermoelectric leg is an n-type PbTe-based material or an n-type scoparite compound; the material of the n-type medium-temperature thermoelectric leg is an n-type Mg3Sb2-based material or an n-type Sb2Te3-based material; and the material of the n-type low-temperature thermoelectric leg is an n-type Bi-Sb-based material or an n-type Mg3(Sb,Bi)2-based material.

[0030] Furthermore, both the first and second ultrathin thermally conductive insulating layers are composite materials of electrical insulation and stress buffer layer; the first ultrathin thermally conductive insulating layer is fixed between the upper electrode and the first ultrathin thermally conductive substrate, and the second ultrathin thermally conductive insulating layer is fixed between the lower electrode and the second ultrathin thermally conductive substrate.

[0031] Furthermore, the thickness of the first and second ultrathin thermally conductive substrates is [0.01 mm, 0.1 mm], and the material is one or more of metals Al, Cu, Au, Mo, W, Cu-based alloys, Ni-based alloys, Al-based alloys, and Mg-based alloys, or one or more combinations of Cu-Al2O3 composite materials, Cu-AlN composite materials, Cu-SiC composite materials, Cu-diamond composite materials, Ag-Al2O3 composite materials, Ag-AlN composite materials, Ag-SiC composite materials, Ag-diamond composite materials, Au-Al2O3 composite materials, Au-AlN composite materials, Au-SiC composite materials, Au-diamond composite materials, Al-diamond composite materials, BAs-based composite materials, and θ-TaN-based composite materials.

[0032] In the above technical solution, the ultra-thin thermally conductive substrate reduces thickness, shortens heat transfer distance, and lowers thermal resistance and heat dissipation. It also improves thermal conductivity, promotes heat conduction per unit area, and further reduces thermal resistance and heat dissipation, maximizing the efficient transfer of cooling capacity from the refrigeration device to the target temperature control device. The physical principle is as follows: According to the thermoelectric constitutive equation, the theoretical maximum cooling temperature difference of a semiconductor thermoelectric device... T c This represents the cold end temperature, but in practical applications, the thermal resistance of the substrate and the interface must be considered. Assume the effective thermal conductivity of the substrate and interface is κ. s The area to thickness ratio is A / t s The cold end heat flux density is q c Then the actual temperature difference that the refrigeration device can obtain is Therefore, improving the thermal conductivity κ of the substrate s And reduce the substrate thickness t s This reduces the thermal resistance between the substrate and the interface, and is expected to significantly improve the actual cooling temperature difference.

[0033] In this invention, the thickness of the first ultrathin thermally conductive insulating layer and the second ultrathin thermally conductive insulating layer is [0.01 mm, 0.1 mm], and the material is one or a combination of several of the following: polytetrafluoroethylene (PTFE), perfluoroethylene propylene (FEP), polystyrene composite material (PBI), polyimide (PI), polyimide-silica microsphere composite material, polyether ether ketone (PEEK), polyurethane (PU), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN).

[0034] Furthermore, the upper electrode, lower electrode, first electrical input electrode, and second electrical input electrode are made of the same material, namely, metals Au, Ag, Mo, W, Fe, Pd, Pt, Al, Cu, Ni, or Ti.

[0035] Furthermore, the first electrical input wire and the second electrical input wire are made of the same material, which is a polyvinyl chloride insulated copper core wire;

[0036] The high thermal conductivity inner package and the high thermal conductivity outer package are made of the same material, namely high thermal conductivity carbon fiber or graphite-epoxy resin thermally conductive composite material (GEC).

[0037] In this invention, within the scope defined by the above-mentioned scheme, and determined according to the requirements of the actual working environment, the thickness and fill rate of the high thermal conductivity inner package and the high thermal conductivity outer package can be adjusted, and the high thermal conductivity inner package or the high thermal conductivity outer package can be set separately; the physical dimensions and number of p-type high temperature thermoelectric legs, the physical dimensions and number of p-type medium temperature thermoelectric legs, the physical dimensions and number of p-type low temperature thermoelectric legs, the physical dimensions and number of n-type high temperature thermoelectric legs, the physical dimensions and number of n-type medium temperature thermoelectric legs, and the physical dimensions and number of n-type low temperature thermoelectric legs can be adjusted; the thickness of the first ultra-thin thermally conductive substrate, the thickness of the first ultra-thin thermally conductive insulating layer, and the thickness of the first ultra-thin thermally conductive substrate can be adjusted. The thickness of the upper electrode, the thickness of the first barrier layer, the thickness of the second barrier layer, the thickness of the third barrier layer, the thickness of the fourth barrier layer, the thickness of the fifth barrier layer, the thickness of the sixth barrier layer, the thickness of the seventh barrier layer, the thickness of the eighth barrier layer, the thickness of the lower electrode, the thickness of the second ultra-thin thermally conductive insulating layer, and the thickness of the second ultra-thin thermally conductive substrate can be adjusted according to the cooling output parameters required in actual applications. The number of thermoelectric units in the thermoelectric module, the number of thermoelectric modules in the thermoelectric device, and the configuration of multiple thermoelectric devices in series, parallel, or a combination of series and parallel connections can be selected. A power management module can also be selected.

[0038] Secondly, the present invention also provides a method for preparing the thermoelectric device described in the first aspect, comprising:

[0039] Raw materials are weighed according to a preset ratio to prepare p-type thermoelectric rods and n-type thermoelectric rods;

[0040] The corresponding topological structure dimensions are determined according to the performance parameters of p-type thermoelectric crystal rods and n-type thermoelectric crystal rods, and p-type thermoelectric crystal rods and n-type thermoelectric crystal rods are cut respectively to form p-type thermoelectric legs and n-type thermoelectric legs;

[0041] The surface of the ultrathin thermally conductive substrate is pretreated by acid and alkali solution cleaning or reactive plasma etching, and an ultrathin thermally conductive insulating layer is prepared on the surface of the pretreated ultrathin thermally conductive substrate by chemical vapor deposition.

[0042] According to the size ratio of p-type thermoelectric legs and n-type thermoelectric legs, the upper electrode and the lower electrode are deposited on the ultrathin thermally conductive insulating layer.

[0043] Solder is applied to the surfaces of the upper and lower electrodes respectively. The p-type thermoelectric leg and n-type thermoelectric leg are fixed between the upper and lower electrodes. Reflow soldering is then performed to complete the assembly of multiple thermoelectric units.

[0044] By connecting the first electrical input wire and the second electrical input wire to the first electrical input electrode and the second electrical input electrode respectively, a thermoelectric module is obtained;

[0045] A high thermal conductivity inner package is filled inside the thermoelectric module, and a high thermal conductivity outer package is fixed on the surface of the high thermal conductivity inner package.

[0046] Furthermore, in the above method, the raw material for preparing the p-type thermoelectric crystal rod can be one or at least two of the following: p-type high-temperature thermoelectric material, p-type medium-temperature thermoelectric material, and p-type low-temperature thermoelectric material; the corresponding barrier layer can be two or three layers; the forming process of the p-type thermoelectric crystal rod can be one or more of the following: hot pressing sintering, discharge plasma sintering, hot melt extrusion sintering, and thermal gradient method single crystal growth.

[0047] Furthermore, in the above method, the raw materials for preparing the n-type thermoelectric crystal rod can be one or at least two of the following: n-type high-temperature thermoelectric materials, n-type medium-temperature thermoelectric materials, and n-type low-temperature thermoelectric materials, and the corresponding barrier layer can be two or three layers; the forming process of the n-type thermoelectric crystal rod can be one or more of the following: zone melting pulling, discharge plasma sintering, hot melt extrusion sintering, and thermal gradient method single crystal growth.

[0048] Furthermore, in the above methods, diamond wire cutting of p-type and n-type thermoelectric rods can be used, or nano / femtosecond laser processing technology can be used for cutting.

[0049] Furthermore, in the above method, the pretreatment of the surface of the ultrathin thermally conductive substrate can be carried out by acid and alkali solution cleaning or reactive plasma etching, and the preparation process of the ultrathin thermally conductive insulating layer can be any one of chemical vapor deposition, glass mold casting, spin coating, roll-to-roll coating, and continuous curing.

[0050] Furthermore, in the above method, the upper and lower electrodes can be fabricated using deposition, plasma spraying, evaporation, or sputtering.

[0051] The principle underlying this invention is as follows: Under the action of input current, holes and electrons within the p-type and n-type thermoelectric legs of a semiconductor thermoelectric temperature control device migrate, transporting heat from one end to the other. By changing the direction of the input current, reverse heat transport can be achieved, i.e., cooling or heating. High-temperature, medium-temperature, and low-temperature segmented thermoelectric materials are used to maximize the optimal thermoelectric performance within their respective temperature ranges. An ultra-thin thermally conductive substrate is used to reduce thermal resistance and promote heat conduction. An ultra-thin thermally conductive insulating layer provides electrical isolation, reduces thermal expansion stress at heterogeneous interfaces, and increases bonding strength. High thermal conductivity internal and external encapsulations solidify the thermoelectric cooling device, enhancing its passive effective thermal conductivity, heat dissipation capability, and impact resistance.

[0052] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0053] The high-performance thermoelectric device provided by this invention overcomes the technical bottlenecks of traditional thermoelectric devices, such as low coefficient of performance, small cooling capacity, small cooling temperature difference, large substrate thermal resistance, poor passive thermal conductivity, poor impact resistance, difficulty in lightweighting, and incompatibility of common substrate packaging processes. It also significantly improves the thermal stability, mechanical performance, and packaging compatibility of semiconductor thermoelectric devices, ensuring excellent cooling performance and temperature control over a wide temperature range, and expanding the operating environment. The device can operate stably for extended periods in important fields such as electronic information, artificial intelligence data centers, and autonomous driving. This is achieved by employing an ultra-thin thermally conductive substrate to reduce thermal resistance and promote heat conduction; using an ultra-thin thermally conductive insulating layer to provide electrical isolation and reduce thermal expansion stress at heterogeneous interfaces while increasing bonding strength; using thermal topology engineering to design the device's physical structure and achieve optimal matching and maximization of thermoelectric material performance; and using high thermal conductivity packaging materials to solidify the thermoelectric cooling device and improve its passive effective thermal conductivity and impact resistance.

[0054] This invention employs an ultra-thin thermally conductive substrate, significantly reducing thermal resistance from both the thickness and material thermal conductivity perspectives, achieving a resistance as low as 0.001 °C·cm. 2 / W, breaking through the limitations of traditional semiconductor thermoelectric temperature control devices that are restricted by the ultra-high thermal resistance (0.1 ℃·cm) of ceramic substrates. 2 The inefficient thermal conductivity caused by the / W) is a key problem, namely, good material properties but poor device thermal conductivity. Furthermore, the direct welding and interface alloying of the ultrathin thermal conductive substrate with the heat source and heat sink avoids the secondary metallization process of traditional ceramic substrates, effectively reducing the interface thermal resistance. The large-scale rolling process of the ultrathin thermal conductive substrate itself has a cost advantage, avoiding the intrinsic brittleness of ceramic substrates and dependence on atmosphere sintering, effectively controlling costs while improving the cooling and thermal conductivity of the device.

[0055] This invention employs an ultra-thin thermally conductive insulating layer to achieve physical insulation and electrical isolation between the ultra-thin thermally conductive substrate and the electrodes, thereby reducing thermal resistance in terms of thickness and further promoting thermal conductivity. At the same time, it provides a substrate to realize the metallization of the electrode array of the thermoelectric unit, and improves interface stability by physically nesting to buffer the thermal expansion stress at the heterogeneous interface.

[0056] This invention employs sized p-type and n-type thermoelectric legs, guiding the design of the thermoelectric leg topology and geometry from the thermoelectric constitutive equation level to achieve the best match of the intrinsic properties of p-type and n-type thermoelectric materials, maximizing the overall performance of the thermoelectric materials; it also maximizes the thermoelectric module fill ratio or fill factor (the ratio of the total cross-sectional area of ​​the thermoelectric legs to the device area), effectively improving the device's cooling performance and heat flux density.

[0057] This invention employs a high thermal conductivity inner encapsulation and a high thermal conductivity outer encapsulation to fill a semiconductor thermoelectric temperature control device. This breaks through the application inertia of traditional devices that are limited to filling with low thermal conductivity materials. It improves the overall effective thermal conductivity of the device from the perspective of macroscopic heat flow conduction and effective medium theory, achieving effective heat uniformity and efficient heat conduction in the spatial dimension. At the same time, fixing the thermoelectric module structure helps to buffer the mechanical compression and thermal stress existing in the internal structure of the thermoelectric device, buffer the mechanical impact between the thermoelectric device and the external environment, so that the thermoelectric device has a certain self-healing function and can work better in various harsh environments. Attached Figure Description

[0058] Figure 1 This is a schematic diagram of the structure of a high-performance semiconductor thermoelectric device provided in Embodiment 1 of the present invention;

[0059] Figure 2 This is a front view of a high-performance semiconductor thermoelectric device provided in Embodiment 1 of the present invention;

[0060] Figure 3 The substrate thermal resistance test results of a high-performance semiconductor thermoelectric device provided in Embodiment 1 of the present invention;

[0061] Figure 4 The results of the cooling temperature difference test for a high-performance semiconductor thermoelectric device provided in Embodiment 1 of the present invention;

[0062] Figure 5 This is a process flow diagram of the fabrication process of a high-performance semiconductor thermoelectric device provided in Embodiment 1 of the present invention;

[0063] Figure 6 The image shows a physical picture of a high-performance semiconductor thermoelectric device provided in Embodiment 1 of the present invention.

[0064] Figure 7A schematic diagram of an ultrathin thermally conductive substrate and an ultrathin thermally conductive insulating layer structure for a high-performance semiconductor thermoelectric device provided in an embodiment of the present invention;

[0065] Figure 8 for Figure 7 The top view is a schematic diagram of an ultrathin thermally conductive substrate covered with an ultrathin thermally conductive insulating layer;

[0066] Figure 9 This is a schematic diagram of an ultrathin thermally conductive substrate covered with an upper electrode array and an ultrathin thermally conductive insulating layer.

[0067] Figure 10 A schematic diagram of an ultrathin thermally conductive substrate covered with a lower electrode array and an ultrathin thermally conductive insulating layer;

[0068] Figure 11 This is a schematic diagram of the structure of a high-performance semiconductor thermoelectric device provided in Embodiment 2 of the present invention;

[0069] Figure 12 This is a front view of a high-performance semiconductor thermoelectric device provided in Embodiment 2 of the present invention;

[0070] Figure 13 This is a finite element simulation full parameter scan diagram of a high-performance semiconductor thermoelectric device provided in Embodiment 2 of the present invention;

[0071] Figure 14 This is a schematic diagram of the structure of a high-performance semiconductor thermoelectric device provided in Embodiment 3 of the present invention;

[0072] Figure 15 This is a front view of a high-performance semiconductor thermoelectric device provided in Embodiment 3 of the present invention;

[0073] Figure 16 This is a front view of the cold side of a high-performance semiconductor thermoelectric device provided in Embodiment 3 of the present invention;

[0074] Figure 17 This is a front view of the hot side of a high-performance semiconductor thermoelectric device provided in Embodiment 3 of the present invention;

[0075] Figure 18 This is a schematic diagram of the thermoelectric unit structure of a high-performance semiconductor thermoelectric device provided in Embodiment 3 of the present invention;

[0076] Figure 19 This is a schematic diagram illustrating the working principle of the semiconductor thermoelectric device with forward input current described in this invention.

[0077] Figure 20 This is a schematic diagram illustrating the working principle of the semiconductor thermoelectric device with reverse input current described in this invention.

[0078] In the diagram: 1. Thermoelectric module; 10. Thermoelectric unit; 1010. P-type thermoelectric leg; 1020. N-type thermoelectric leg; 1011. First barrier layer; 1012. P-type high-temperature thermoelectric leg; 1013. Second barrier layer; 1014. P-type medium-temperature thermoelectric leg; 1015. Third barrier layer; 1016. P-type low-temperature thermoelectric leg; 1017. Fourth barrier layer; 1021. Fifth barrier layer; 1022. N-type high-temperature thermoelectric leg; 1023. Sixth barrier layer; 1024. N-type medium-temperature thermoelectric leg; 1025. ... Seventh barrier layer; 1026, n-type low-temperature thermoelectric leg; 1027, eighth barrier layer; 108, high thermal conductivity inner package; 109, upper electrode; 110, high thermal conductivity outer package; 111, lower electrode; 1111, first electrical input electrode; 1112, second electrical input electrode; 1121, first electrical input wire; 1122, second electrical input wire; 201, first ultrathin thermally conductive insulating layer; 202, first ultrathin thermally conductive substrate; 203, second ultrathin thermally conductive insulating layer; 204, second ultrathin thermally conductive substrate. Detailed Implementation

[0079] Preferred embodiments of the present invention will now be described in more detail with reference to the accompanying drawings and specific examples.

[0080] In the following description, certain specific details are set forth for the purpose of illustrating various disclosed embodiments in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that embodiments may be practiced without one or more of these specific details. In other instances, well-known apparatuses, structures, and techniques associated with this application may not have been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0081] Unless the context requires otherwise, throughout the specification and claims, the word “comprising” and its variations, such as “including” and “having”, shall be understood to have an open, inclusive meaning, that is, to be interpreted as “including, but not limited to”.

[0082] Throughout this specification, references to "an embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, the appearance of "in an embodiment" or "an embodiment" in various places throughout the specification does not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic may be combined in any manner in one or more embodiments.

[0083] The singular forms “a” and “the” used in this specification and the appended claims include plural references unless otherwise expressly stated herein. It should be noted that the term “or” is generally used to mean “and / or” unless otherwise expressly stated herein.

[0084] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0085] Example 1

[0086] This embodiment provides a high-performance semiconductor thermoelectric device capable of cooling, such as... Figure 1 and Figure 2 As shown, the thermoelectric device has a square structure, including a thermoelectric module 1 and a packaging structure. The thermoelectric module is formed by stacking a first ultrathin thermally conductive substrate 202, a first ultrathin thermally conductive insulating layer 201, a thermoelectric unit 10, a second ultrathin thermally conductive insulating layer 203, and a second ultrathin thermally conductive substrate 204 in sequence. Thermoelectric unit 10 includes a p-type thermoelectric leg 1010, an n-type thermoelectric leg 1020, electrodes, and a high thermal conductivity inner encapsulation 108; the p-type thermoelectric leg 1010 and the n-type thermoelectric leg 1020 are electrically connected through an upper electrode 109 and thermally filled and electrically insulated by the high thermal conductivity inner encapsulation 108; the p-type thermoelectric leg 1010 includes a first barrier layer 1011, a p-type low-temperature thermoelectric leg 1016, and a fourth barrier layer 1017 arranged sequentially from top to bottom, and the n-type thermoelectric leg 1020 includes a fifth barrier layer 1021, an n-type low-temperature thermoelectric leg 1026, and an eighth barrier layer 1027 arranged sequentially from top to bottom; the n-type low-temperature thermoelectric leg 1026 of adjacent thermoelectric units 10 and the p-type thermoelectric leg 1010 are electrically connected through an upper electrode 109 and the high thermal conductivity inner encapsulation 108 is used for thermal filling and electrical insulation; the p-type thermoelectric leg 1010 includes a first barrier layer 1011, a p-type low-temperature thermoelectric leg 1016, and a fourth barrier layer 1017 arranged sequentially from top to bottom; the n-type low-temperature thermoelectric leg 1026 of adjacent thermoelectric units 10 and the p-type thermoelectric leg 1020 are electrically connected through an upper electrode 109 and a p-type thermoelectric leg 1020. The p-type low-temperature thermoelectric leg 1016 achieves electrical connection through the lower electrode 111 and uses a high thermal conductivity inner encapsulation 108 to achieve thermal filling and electrical insulation. The p-type low-temperature thermoelectric leg 1016 and n-type low-temperature thermoelectric leg 1026 on both sides of the bottom end of the thermoelectric module are respectively provided with a first electrical input electrode 1111 and a second electrical input electrode 1112. A high thermal conductivity outer encapsulation 110 is provided on the outer surface of the thermoelectric unit 10 between the first ultra-thin thermally conductive insulation layer 201 and the second ultra-thin thermally conductive insulation layer 203. The first electrical input wire 1121 and the second electrical input wire 1122 pass through the high thermal conductivity outer encapsulation 110 and are respectively connected to the first electrical input electrode 1111 and the second electrical input electrode 1112.

[0087] like Figure 7 As shown, the first ultrathin thermally conductive insulating layer 201 fixes the upper electrode 109 and the first ultrathin thermally conductive substrate 202, and the second ultrathin thermally conductive insulating layer 203 fixes the lower electrode 111 and the second ultrathin thermally conductive substrate 204. The ultrathin thermally conductive insulating layer serves two purposes: firstly, it establishes electrical insulation between the ultrathin thermally conductive substrate and the electrode, preventing secondary electrical connection between the p-type thermoelectric leg 1010 and the n-type thermoelectric leg 1020; secondly, it provides a stress buffer layer, reducing the thermal expansion stress at the heterogeneous interface and increasing the bonding strength, thereby achieving mechanical support and heterogeneous interface integration between the ultrathin thermally conductive substrate and the electrode.

[0088] In this embodiment, the first ultra-thin thermally conductive insulating layer 201 and the second ultra-thin thermally conductive insulating layer 203 are made of perfluoroethylene propylene, which can achieve both electrical insulation and stress buffering; the thickness of both is 0.1 mm.

[0089] In this embodiment, the first ultra-thin thermally conductive substrate 202 and the second ultra-thin thermally conductive substrate 204 are made of Cu metal with a thickness of 0.1 mm. This reduces the thickness, shortens the heat transfer distance, and lowers thermal resistance and heat dissipation. Furthermore, it improves thermal conductivity, promoting heat transfer per unit volume and reducing thermal resistance and heat dissipation, thus maximizing the efficient transfer of cooling capacity from the cooling device to the target temperature control device. Figure 3 As shown, compared to the ultra-high thermal resistance of 0.1 °C·cm on ceramic substrates, 2 / W, the thermal resistance of the ultrathin thermally conductive substrate used in this embodiment is 0.001 °C·cm. 2 / W decreased by two orders of magnitude. For example... Figure 4 As shown, compared to ceramic substrate semiconductor thermoelectric cooling devices, this embodiment uses an ultra-thin thermally conductive substrate to achieve a larger cooling temperature difference of 70 °C over a wide temperature range.

[0090] In this embodiment, the thickness of both the high thermal conductivity inner package 108 and the high thermal conductivity outer package 110 is 0.1 mm, and the fill rate is 15%. The high thermal conductivity inner package 108 and the high thermal conductivity outer package 110 are made of the same material, which is graphite-epoxy resin thermally conductive composite material.

[0091] In this embodiment, the upper electrode 109, the lower electrode 111, the first electrical input electrode 1111, and the second electrical input electrode 1112 are all made of the same material, namely metal Ag.

[0092] The first electrical input wire 1121 and the second electrical input wire 1122 are made of the same material, which can both be polyvinyl chloride insulated copper core wires.

[0093] In this embodiment, the p-type low-temperature thermoelectric leg 1016 is made of p-type Bi2Te3-based material, with a height of 1 mm and a cross-sectional area of ​​0.4 mm². 2 The n-type low-temperature thermoelectric leg 1026 is made of n-type Bi-Sb based material, with a height of 1 mm and a cross-sectional area of ​​0.5 mm². 2 .

[0094] In this embodiment, the first barrier layer 1011 and the fifth barrier layer 1021 are 1 μm thick, are thin film, and are made of the same material, Au metal; the fourth barrier layer 1017 and the eighth barrier layer 1027 are 1 μm thick, are thin film, and are made of the same material, Au metal.

[0095] This embodiment also provides a method for fabricating the high-performance semiconductor thermoelectric device, such as... Figure 5 As shown, the actual thermoelectric device produced is as follows: Figure 6 As shown, the preparation method specifically includes the following steps:

[0096] ST01: Weigh the elemental powder according to the stoichiometric ratio of each element in the p-type low-temperature thermoelectric material as raw material, and weigh the material powder of each layer of the first barrier layer and the fourth barrier layer respectively.

[0097] ST02: The barrier layer powder and thermoelectric material powder are sequentially laid in the mold and hot-pressed and sintered to form a p-type thermoelectric crystal rod;

[0098] ST03: Weigh the elemental powder according to the stoichiometric ratio of each element in the n-type low-temperature thermoelectric material as raw material, and weigh the material powder of each layer of the fifth and eighth barrier layers respectively.

[0099] ST04: The above-mentioned barrier layer powder and thermoelectric material powder are sequentially laid in the mold, and zone melting and pulling are performed to form an n-type thermoelectric crystal rod;

[0100] ST05: Determine the corresponding topological structure size according to the performance parameters of p-type thermoelectric crystal rod and n-type thermoelectric crystal rod, and use diamond wire cutting to cut p-type and n-type thermoelectric crystal rods in ST01 and ST02 respectively to form p-type thermoelectric legs and n-type thermoelectric legs;

[0101] ST06: See also Figure 7 and Figure 8 An ultra-thin thermally conductive substrate is selected, and the surface is pretreated by acid and alkali solution cleaning or reactive plasma etching. An ultra-thin thermally conductive insulating layer is prepared on the surface of the pretreated ultra-thin thermally conductive substrate by chemical vapor deposition.

[0102] ST07: See also Figure 9 and Figure 10 According to the size ratio of p-type thermoelectric legs and n-type thermoelectric legs, the upper electrode and the lower electrode are deposited on the ultrathin thermally conductive insulating layer to realize the electrode metallization of the ultrathin thermally conductive substrate.

[0103] ST08: Solder is applied to the surfaces of the upper and lower electrodes respectively. The p-type and n-type thermoelectric legs are precisely positioned between the upper and lower electrodes using die bonding and chip mounting processes. Reflow soldering is then performed to complete the assembly of multiple thermoelectric units.

[0104] ST09: Connect the first electrical input wire and the second electrical input wire to the first electrical input electrode and the second electrical input electrode respectively to obtain the thermoelectric module.

[0105] ST10: A high thermal conductivity inner package is formed by filling the thermoelectric module with a high thermal conductivity material using a high-temperature sealant; a high thermal conductivity outer package material is fixed on the surface of the high thermal conductivity inner package, and the interface is fixed with sealant to prepare a high thermal conductivity outer package.

[0106] In some other embodiments, the forming processes of p-type thermoelectric crystal rods and n-type thermoelectric crystal rods can also employ discharge plasma sintering, hot melt extrusion sintering, thermal gradient method single crystal growth, etc.

[0107] In some other embodiments, nano / femtosecond laser processing technology can also be used for cutting in step ST05.

[0108] In some other embodiments, the preparation process of the ultrathin thermally conductive insulating layer in step ST06 can also be any one of glass mold casting, spin coating, roll-to-roll coating, or continuous curing.

[0109] In some other embodiments, the electrode metallization process in step ST07 can also employ methods such as plasma spraying, evaporation, or sputtering to prepare the upper and lower electrodes.

[0110] Example 2

[0111] This embodiment provides a high-performance semiconductor thermoelectric device capable of generating electricity. The thermoelectric device has an overall square structure, such as... Figure 11 and Figure 12As shown, it includes a thermoelectric module 1 and a packaging structure; the thermoelectric module 1 is formed by stacking a first ultrathin thermally conductive substrate 202, a first ultrathin thermally conductive insulating layer 201, a thermoelectric unit 10, a second ultrathin thermally conductive insulating layer 203, and a second ultrathin thermally conductive substrate 204 in sequence. The thermoelectric unit 10 includes a p-type thermoelectric leg 1010, an n-type thermoelectric leg 1020, electrodes, and a high thermal conductivity inner encapsulation 108. The p-type thermoelectric leg 1010 and the n-type thermoelectric leg 1020 are electrically connected through an upper electrode 109 and thermally filled and electrically insulated by the high thermal conductivity inner encapsulation 108. The p-type thermoelectric leg 1010 includes, from top to bottom, a first barrier layer 1011, a p-type high-temperature thermoelectric leg 1012, a second barrier layer 1013, a p-type medium-temperature thermoelectric leg 1014, and a fourth barrier layer 1017. The n-type thermoelectric leg 1020 includes, from top to bottom, a fifth barrier layer 1021, an n-type high-temperature thermoelectric leg 1022, a sixth barrier layer 1023, an n-type medium-temperature thermoelectric leg 1024, and an eighth barrier layer 1027. The n-type medium-temperature thermoelectric leg 1024 and p-type medium-temperature thermoelectric leg 1014 of adjacent thermoelectric units 10 are electrically connected through the lower electrode 111 and thermally filled and electrically insulated by a high thermal conductivity inner encapsulation 108. The p-type medium-temperature thermoelectric leg 1014 and n-type medium-temperature thermoelectric leg 1024 on both sides of the bottom end of the thermoelectric module are respectively provided with a first electrical input electrode 1111 and a second electrical input electrode 1112. A high thermal conductivity outer encapsulation 110 is provided on the outer surface of the thermoelectric unit 10 between the first ultra-thin thermally conductive insulation layer 201 and the second ultra-thin thermally conductive insulation layer 203. The first electrical input wire 1121 and the second electrical input wire 1122 pass through the high thermal conductivity outer encapsulation 110 and are respectively connected to the first electrical input electrode 1111 and the second electrical input electrode 1112.

[0112] The first ultrathin thermally conductive insulating layer 201 fixes the upper electrode 109 and the first ultrathin thermally conductive substrate 202, and the second ultrathin thermally conductive insulating layer 203 fixes the lower electrode 111 and the second ultrathin thermally conductive substrate 204. The ultrathin thermally conductive insulating layer serves two purposes: firstly, it establishes electrical insulation between the ultrathin thermally conductive substrate and the electrode, preventing secondary electrical connection between the p-type thermoelectric leg 1010 and the n-type thermoelectric leg 1020; secondly, it provides a stress buffer layer, reducing the thermal expansion stress at the heterogeneous interface and increasing the bonding strength, thereby achieving mechanical support and heterogeneous interface integration between the ultrathin thermally conductive substrate and the electrode.

[0113] In this embodiment, the first ultra-thin thermally conductive insulating layer 201 and the second ultra-thin thermally conductive insulating layer 203 are made of polytetrafluoroethylene, which can achieve both electrical insulation and stress buffering; the thickness of both is 0.01 mm.

[0114] In this embodiment, the first ultrathin thermally conductive substrate 202 and the second ultrathin thermally conductive substrate 204 are made of Cu-AlN composite material with a thickness of 0.1 mm. On the one hand, by reducing the thickness, the heat transfer distance is shortened, and thermal resistance and heat dissipation are reduced; on the other hand, by improving the thermal conductivity, the heat transfer per unit area is promoted, and thermal resistance and heat dissipation are reduced, so as to maximize the efficient transfer of the cooling capacity of the refrigeration device to the target temperature control device.

[0115] In this embodiment, the thickness of both the high thermal conductivity inner package 108 and the high thermal conductivity outer package 110 is 0.01 mm, and the fill rate is 5%; the high thermal conductivity inner package 108 and the high thermal conductivity outer package 110 are made of the same material, which is high thermal conductivity carbon fiber.

[0116] In this embodiment, the upper electrode 109, the lower electrode 111, the first electrical input electrode 1111, and the second electrical input electrode 1112 are all made of the same material, namely, metal Au;

[0117] The first electrical input wire 1121 and the second electrical input wire 1122 are made of the same material, which can both be polyvinyl chloride insulated copper core wires.

[0118] Therefore, in this embodiment, the p-type high-temperature thermoelectric leg 1012 is made of p-type PbTe-based material, with a height of 10.5 mm and a cross-sectional area of ​​2.4 mm². 2 The p-type medium-temperature electric leg 1014 is made of p-type Bi2Te3-based material, with a height of 2.5 mm and a cross-sectional area of ​​2.4 mm². 2 The n-type high-temperature thermoelectric leg 1022 is made of n-type PbTe-based material, with a height of 9 mm and a cross-sectional area of ​​4 mm². 2 The n-type medium-temperature electric leg 1024 is made of n-type Bi2Te3-based material, with a height of 4 mm and a cross-sectional area of ​​4 mm². 2 .

[0119] In this embodiment, the first barrier layer 1011 and the fifth barrier layer 1021 have a thickness of 1 μm, are thin films, and are made of the same material, Au metal; the second barrier layer 1013 and the sixth barrier layer 1023 have a thickness of 1 μm, are thin films, and are made of the same material, Au metal; the fourth barrier layer 1017 and the eighth barrier layer 1027 have a thickness of 1 μm, are thin films, and are made of the same material, Ni metal.

[0120] Since the optimal performance of thermoelectric materials is specifically dependent on their operating temperature range, especially over a wide range, combining high-temperature and medium-temperature thermoelectric legs with specific material thermoelectric properties plays a crucial role in improving the average performance parameters across the entire temperature range. Therefore, accurately obtaining the physical topological dimensions of high-temperature and low-temperature thermoelectric legs and their thermal and electrical variations is key to guiding the design of devices with optimal performance.

[0121] In this embodiment, based on the preferred high-temperature PbTe-based thermoelectric material and the medium-temperature Bi2Te3-based thermoelectric material, under the temperature conditions of 800K at the hot end and 300K at the cold end, the geometric dimensions and thermal and electrical parameters of the high-temperature thermoelectric leg and the medium-temperature thermoelectric leg are scanned by full parameter scanning through finite element simulation. The device topology design scheme with the maximum thermoelectric efficiency is given: the cross-sectional area ratio of the p-type thermoelectric leg to the n-type thermoelectric leg is A. p / A n = 0.6, the height ratio of the p-type medium-temperature thermoelectric leg to the p-type high-temperature thermoelectric leg is H p-Bi2Te3 / H p-PbTe = 0.2, the height ratio of the n-type medium-temperature thermoelectric leg to the n-type high-temperature thermoelectric leg is H n-Bi2Te3 / H n-PbTe = 0.4. For example... Figure 13 As shown, the thermoelectric efficiency of this embodiment is 17.8%, which is higher than the efficiency of the corresponding device using a single high-temperature PbTe-based thermoelectric material (comparative device).

[0122] The fabrication method of the thermoelectric device described in this embodiment is the same as that in Embodiment 1, except that the selection of thermoelectric materials and barrier layer materials follows the thermoelectric device structure described in this embodiment.

[0123] Example 3

[0124] This embodiment provides a high-performance semiconductor thermoelectric device. The thermoelectric device has an overall square structure, such as... Figure 14 and Figure 15 As shown, it includes a thermoelectric module 1 and a packaging structure; the thermoelectric module 1 is formed by sequentially stacking a first ultrathin thermally conductive substrate 202, a first ultrathin thermally conductive insulating layer 201, a thermoelectric unit 10, a second ultrathin thermally conductive insulating layer 203, and a second ultrathin thermally conductive substrate 204. Figure 18As shown, the thermoelectric unit 10 includes a p-type thermoelectric leg 1010, an n-type thermoelectric leg 1020, electrodes, and a high thermal conductivity inner encapsulation 108. The p-type thermoelectric leg 1010 and the n-type thermoelectric leg 1020 are electrically connected through an upper electrode 109 and thermally filled and electrically insulated by the high thermal conductivity inner encapsulation 108. The p-type thermoelectric leg 1010 includes, from top to bottom, a first barrier layer 1011, a p-type high-temperature thermoelectric leg 1012, a second barrier layer 1013, a p-type medium-temperature thermoelectric leg 1014, a third barrier layer 1015, a p-type low-temperature thermoelectric leg 1016, and a fourth barrier layer 1017. The n-type thermoelectric leg 1020 includes, from top to bottom, a fifth barrier layer 1021, an n-type high-temperature thermoelectric leg 1022, a sixth barrier layer 1023, an n-type medium-temperature thermoelectric leg 1024, and a seventh barrier layer 1025. 5. n-type low-temperature thermoelectric leg 1026 and eighth barrier layer 1027; the n-type low-temperature thermoelectric leg 1026 and p-type low-temperature thermoelectric leg 1016 of adjacent thermoelectric units 10 are electrically connected through the lower electrode 111 and thermally filled and electrically insulated by a high thermal conductivity inner encapsulation 108; the p-type low-temperature thermoelectric leg 1016 and n-type low-temperature thermoelectric leg 1026 on both sides of the bottom end of the thermoelectric module are respectively provided with a first electrical input electrode 1111 and a second electrical input electrode 1112; a high thermal conductivity outer encapsulation 110 is provided on the outer surface of the thermoelectric unit 10 between the first ultra-thin thermally conductive insulation layer 201 and the second ultra-thin thermally conductive insulation layer 203; the first electrical input wire 1121 and the second electrical input wire 1122 pass through the high thermal conductivity outer encapsulation 110 and are respectively connected to the first electrical input electrode 1111 and the second electrical input electrode 1112.

[0125] The first ultrathin thermally conductive insulating layer 201 fixes the upper electrode 109 and the first ultrathin thermally conductive substrate 202, and the second ultrathin thermally conductive insulating layer 203 fixes the lower electrode 111 and the second ultrathin thermally conductive substrate 204. The ultrathin thermally conductive insulating layer serves two purposes: firstly, it establishes electrical insulation between the ultrathin thermally conductive substrate and the electrode, preventing secondary electrical connection between the p-type thermoelectric leg 1010 and the n-type thermoelectric leg 1020; secondly, it provides a stress buffer layer, reducing the thermal expansion stress at the heterogeneous interface and increasing the bonding strength, thereby achieving mechanical support and heterogeneous interface integration between the ultrathin thermally conductive substrate and the electrode.

[0126] Figure 16 A front view of the cold side of the thermoelectric device described in this embodiment. Figure 17 This is a front view of the hot side of the thermoelectric device described in this embodiment. The cold side is the side where the semiconductor device obtains a lower temperature when the electrical input is connected, and the hot side is the side where the semiconductor device obtains a higher temperature when the electrical input is connected. The relative temperature of the cold and hot sides can be adjusted by changing the polarity and phase of the electrical input.

[0127] The principle underlying this invention is that, under the action of an input current, holes and electrons within the p-type and n-type thermoelectric legs of a semiconductor thermoelectric temperature control device migrate, transporting heat from one end to the other. Reversing the direction of the input current achieves reverse heat transport, i.e., cooling or heating. Figure 19 and Figure 20 As shown.

[0128] In this embodiment, the first ultra-thin thermally conductive insulating layer 201 and the second ultra-thin thermally conductive insulating layer 203 are made of polyurethane, which can achieve both electrical insulation and stress buffering; the thickness of both is 0.05mm.

[0129] In this embodiment, the first ultrathin thermally conductive substrate 202 and the second ultrathin thermally conductive substrate 204 are made of Cu-based alloy with a thickness of 0.05 mm. On the one hand, by reducing the thickness, the heat transfer distance is shortened, and thermal resistance and heat dissipation are reduced; on the other hand, by improving thermal conductivity, the heat transfer per unit area is promoted, and thermal resistance and heat dissipation are reduced, so as to maximize the efficient transfer of the cooling capacity of the refrigeration device to the target temperature control device.

[0130] In this embodiment, the thickness of both the high thermal conductivity inner package 108 and the high thermal conductivity outer package 110 is 0.05 mm, and the fill rate is 20%. The high thermal conductivity inner package 108 and the high thermal conductivity outer package 110 are made of the same material, which is high thermal conductivity carbon fiber.

[0131] In this embodiment, the upper electrode 109, the lower electrode 111, the first electrical input electrode 1111, and the second electrical input electrode 1112 are all made of the same material, namely, metal Au;

[0132] The first electrical input wire 1121 and the second electrical input wire 1122 are made of the same material, which can both be polyvinyl chloride insulated copper core wires.

[0133] In this embodiment, the p-type high-temperature thermoelectric leg 1012 is made of p-type cobaltite compound, with a height of 2 mm and a cross-sectional area of ​​2.4 mm². 2 The p-type medium-temperature electric leg 1014 is made of p-type Bi2Te3-based material, with a height of 1.5 mm and a cross-sectional area of ​​2.4 mm². 2 The p-type low-temperature thermoelectric leg 1016 is made of p-type Mg3Sb2-based material, with a height of 2.5 mm and a cross-sectional area of ​​2.4 mm². 2 The n-type high-temperature thermoelectric leg 1022 is made of n-type cobaltite compound, with a height of 2 mm and a cross-sectional area of ​​4 mm². 2 The n-type medium-temperature electric leg 1024 is made of n-type Sb2Te3-based material, with a height of 1.5 mm and a cross-sectional area of ​​4 mm². 2The n-type low-temperature thermoelectric leg 1026 is made of n-type Mg3(Sb,Bi)2-based material, with a height of 2.5 mm and a cross-sectional area of ​​4 mm². 2 .

[0134] In this embodiment, the first barrier layer 1011 and the fifth barrier layer 1021 have a thickness of 0.035 mm, are in powder form, and are made of the same material, namely, metallic Au; the second barrier layer 1013 and the sixth barrier layer 1023 have a thickness of 0.015 mm, are in powder form, and are made of the same material, namely, metallic Fe; the third barrier layer 1015 and the seventh barrier layer 1025 have a thickness of 0.015 mm, are in powder form, and are made of the same material, namely, metallic Ni; the fourth barrier layer 1017 and the eighth barrier layer 1027 have a thickness of 0.015 mm, are in powder form, and are made of the same material, namely, metallic Ni.

[0135] The fabrication method of the thermoelectric device described in this embodiment is the same as that in Embodiment 1, except that the selection of thermoelectric materials and barrier layer materials follows the thermoelectric device structure described in this embodiment.

[0136] In some other embodiments, the thickness of the high thermal conductivity inner package 108 and the high thermal conductivity outer package 110 can be 0.02 mm, 0.03 mm, 0.04 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, etc., and the fill rate can be 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, etc.

[0137] In some other embodiments, the dimensions of each side of each p-type thermoelectric leg 1010 and n-type thermoelectric leg 1020 can be 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 200μm, 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, 1mm, 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 8mm, 9mm, 1cm, etc.

[0138] In some other embodiments, the thickness of each barrier layer can be 0.02 mm, 0.03 mm, 0.04 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, etc., and the material can be one or an alloy of several of the metals Au, Ag, Ta, Cu, Ti, TiN, TiW, Ni and Mo.

[0139] In some other embodiments, the thickness of each ultrathin thermally conductive substrate can be 0.02 mm, 0.03 mm, 0.04 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, etc.; the thickness of each ultrathin thermally conductive insulating layer can be 0.02 mm, 0.03 mm, 0.04 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, etc.

[0140] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and principles of the described embodiments, and these modifications and variations should also be considered within the scope of protection of the present invention.

Claims

1. A semiconductor thermoelectric device, characterized in that, Includes a thermoelectric module (1) and a packaging structure; The thermoelectric module (1) includes a first ultrathin thermally conductive substrate (202), a first ultrathin thermally conductive insulating layer (201), a thermoelectric unit (10), a second ultrathin thermally conductive insulating layer (203), and a second ultrathin thermally conductive substrate (204) stacked sequentially. The packaging structure includes a high thermal conductivity inner package (108) and a high thermal conductivity outer package (110). The thermoelectric unit (10) includes a p-type thermoelectric leg (1010) and an n-type thermoelectric leg (1020); the p-type thermoelectric leg (1010) and the n-type thermoelectric leg (1020) at the top of adjacent thermoelectric units are electrically connected through an upper electrode (109), and the p-type thermoelectric leg (1010) and the n-type thermoelectric leg (1020) at the bottom are electrically connected through a lower electrode (111); adjacent thermoelectric units are thermally filled and electrically insulated by a high thermal conductivity inner encapsulation (108); The p-type thermoelectric leg (1010) and n-type thermoelectric leg (1020) on both sides of the bottom of the thermoelectric module are respectively provided with a first electrical input electrode (1111) and a second electrical input electrode (1112). A high thermal conductivity outer package (110) is provided on the outer surface of the thermoelectric unit (10). The first electrical input wire (1121) and the second electrical input wire (1122) pass through the high thermal conductivity outer package (110) and are respectively connected to the first electrical input electrode (1111) and the second electrical input electrode (1112).

2. The semiconductor thermoelectric device according to claim 1, characterized in that, The p-type thermoelectric leg (1010) includes at least one of p-type high-temperature thermoelectric leg (1012), p-type medium-temperature thermoelectric leg (1014) and p-type low-temperature thermoelectric leg (1016), and a barrier layer is provided between different p-type thermoelectric legs (1010); The n-type thermoelectric leg (1020) includes at least one of the n-type high-temperature thermoelectric leg (1022), the n-type medium-temperature thermoelectric leg (1024), and the n-type low-temperature thermoelectric leg (1026), and a barrier layer is provided between different n-type thermoelectric legs (1020).

3. The semiconductor thermoelectric device according to claim 2, characterized in that, The barrier layer is in the form of powder, film or foil, with a thickness of [0.01μm, 0.1mm], and is made of one or more of the following metals: Au, Ag, Ta, Cu, Ti, TiN, TiW, Ni and Mo.

4. The semiconductor thermoelectric device according to claim 2, characterized in that, The thickness of the high thermal conductivity inner package (108) is [0.01 mm, 0.1 mm], and the fill rate is [5%, 95%]; And / or, the dimensions of each side of the p-type high-temperature thermoelectric leg (1012) are [0.1μm, 1cm], the dimensions of each side of the p-type medium-temperature thermoelectric leg (1014) are [0.1μm, 1cm], and the dimensions of each side of the p-type low-temperature thermoelectric leg (1016) are [0.1μm, 1cm]. And / or, the dimensions of each side of the n-type high-temperature thermoelectric leg (1022) are [0.1μm, 1cm], the dimensions of each side of the n-type medium-temperature thermoelectric leg (1024) are [0.1μm, 1cm], and the dimensions of each side of the n-type low-temperature thermoelectric leg (1026) are [0.1μm, 1cm].

5. The semiconductor thermoelectric device according to claim 1, characterized in that, The material of the p-type thermoelectric leg (1010) is one or more of the following: p-type telluride, p-type chalcogenide, p-type silicide, p-type Zintl phase compound, p-type semi-Hessler compound, p-type cobaltite compound, p-type oxide material, p-type III-V compound, ZnSb, CeS, InSb, LiCdN, LiCdP, LiCdAs, LiCdSb, LiCdBi, p-type nickel-based alloy, p-type cage compound, p-type magnesium-based compound, and p-type high entropy alloy; And / or, the material of the n-type thermoelectric leg (1020) is one or more of the following: n-type telluride, n-type chalcogenide, n-type silicide, n-type magnesium-based compound, n-type Zintl phase compound, n-type squartzite compound, n-type Half-Heusler compound, n-type oxide, La3Te4, n-type III-V compound, n-type II-VI compound, n-type organic semiconductor, n-type nickel-based alloy, Bi-Sb alloy and n-type high-entropy alloy.

6. The semiconductor thermoelectric device according to claim 1, characterized in that, The first ultrathin thermally conductive insulating layer (201) and the second ultrathin thermally conductive insulating layer (203) are both electrical insulation and stress buffer composite material layers; the first ultrathin thermally conductive insulating layer (201) is fixed between the upper electrode (109) and the first ultrathin thermally conductive substrate (202), and the second ultrathin thermally conductive insulating layer (203) is fixed between the lower electrode (111) and the second ultrathin thermally conductive substrate (204).

7. The semiconductor thermoelectric device according to claim 6, characterized in that, The thickness of the first ultrathin thermally conductive substrate (202) and the second ultrathin thermally conductive substrate (204) is [0.01 mm, 0.1 mm], and the material is one or more of metals Al, Cu, Au, Mo, W, Cu-based alloys, Ni-based alloys, Al-based alloys and Mg-based alloys, or one or more combinations of Cu-Al2O3 composite materials, Cu-AlN composite materials, Cu-SiC composite materials, Cu-diamond composite materials, Ag-Al2O3 composite materials, Ag-AlN composite materials, Ag-SiC composite materials, Ag-diamond composite materials, Au-Al2O3 composite materials, Au-AlN composite materials, Au-SiC composite materials, Au-diamond composite materials, Al-diamond composite materials, BAs-based composite materials and θ-TaN-based composite materials; And / or, the thickness of the first ultrathin thermally conductive insulating layer (201) and the second ultrathin thermally conductive insulating layer (203) is [0.01 mm, 0.1 mm], and the material is one or a combination of polytetrafluoroethylene, perfluoroethylene propylene, polystyrene composite material, polyimide, polyimide-silica microsphere composite material, polyetheretherketone, polyurethane, polyethylene terephthalate and polyethylene naphthalate.

8. The semiconductor thermoelectric device according to claim 1, characterized in that, The upper electrode (109), lower electrode (111), first electrical input electrode (1111), and second electrical input electrode (1112) are made of the same material, namely metals Au, Ag, Mo, W, Fe, Pd, Pt, Al, Cu, Ni, or Ti.

9. The semiconductor thermoelectric device according to claim 1, characterized in that, The first electrical input wire (1121) and the second electrical input wire (1122) are made of the same material, which is a polyvinyl chloride insulated copper core wire; And / or, the high thermal conductivity inner package (108) and the high thermal conductivity outer package (110) are made of the same material, namely, high thermal conductivity carbon fiber or graphite-epoxy resin thermally conductive composite material.

10. A method for fabricating a semiconductor thermoelectric device according to any one of claims 1 to 9, characterized in that, include: Raw materials are weighed according to a preset ratio to prepare p-type thermoelectric rods and n-type thermoelectric rods; p-type thermoelectric rods and n-type thermoelectric rods are cut separately to form p-type thermoelectric legs (1010) and n-type thermoelectric legs (1020). The surface of the ultrathin thermally conductive substrate is pretreated, and then an ultrathin thermally conductive insulating layer is prepared on the surface of the pretreated ultrathin thermally conductive substrate. According to the size ratio of p-type thermoelectric leg (1010) and n-type thermoelectric leg (1020), the upper electrode (109) and the lower electrode (111) are prepared on the ultrathin thermally conductive insulating layer. Solder is applied to the surfaces of the upper electrode (109) and the lower electrode (111) respectively. The p-type thermoelectric leg (1010) and the n-type thermoelectric leg (1020) are fixed between the upper electrode (109) and the lower electrode (111). The assembly of multiple thermoelectric units (10) is completed by reflow soldering. The first electrical input wire (1121) and the second electrical input wire (1122) are respectively connected to the first electrical input electrode (1111) and the second electrical input electrode (1112) to obtain the thermoelectric module (1); A high thermal conductivity inner package (108) is filled inside the thermoelectric module (1), and a high thermal conductivity outer package (110) is fixed on the surface of the high thermal conductivity inner package (108).

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