Semiconductor packaging

Abstract

A semiconductor package includes one or more semiconductor dies and a cap located on the semiconductor die. One or more thermoelectric coolers are located on or in the cap, and each thermoelectric cooler is located at a predetermined hot spot of the semiconductor die.

Description

Technical Field

[0001] This utility model relates to semiconductor packaging, and more particularly to the structure and cooling method of semiconductor packaging. Background Technology

[0002] The following content pertains to semiconductor packaging such as wafer-on-wafer packaging, substrate-on-wafer packaging, integrated fan-out packaging, and other heat-generating semiconductor packaging, methods for cooling semiconductor packaging, and similar content. Utility Model Content

[0003] In a non-limiting exemplary embodiment, the semiconductor package includes one or more semiconductor dies; and a cap located on the semiconductor die. One or more thermoelectric coolers are located on or within the cap. Each thermoelectric cooler is located at a predetermined hot spot of the semiconductor die.

[0004] In a non-limiting exemplary embodiment, the one or more thermoelectric coolers consist of two or more thermoelectric coolers.

[0005] In a non-limiting exemplary embodiment, the cap includes an integral vapor chamber having a capillary layer formed on or located on the inner surface of the integral vapor chamber.

[0006] In a non-limiting exemplary embodiment, the semiconductor package further includes: a substrate on which one or more semiconductor dies are located; a thermal interface material between the one or more semiconductor dies and the cap; and a ring surrounding the one or more semiconductor dies and the ring being fixed to or integrally formed with the cap.

[0007] In a non-limiting exemplary embodiment, the cover includes: an integral vapor chamber having a capillary layer formed on or located on the inner surface of the integral vapor chamber; and a plurality of hot fins located on the surface of the cover away from the one or more semiconductor grains, wherein the one or more thermoelectric coolers are located between the integral vapor chamber and the plurality of hot fins.

[0008] In a non-limiting exemplary embodiment, the semiconductor package further includes one or more sidewall thermoelectric coolers located on or within the sidewall of the cover.

[0009] In a non-limiting exemplary embodiment, the height of the cap is at least twice the height of the one or more semiconductor chips.

[0010] In a non-limiting exemplary embodiment, the semiconductor package includes a substrate; one or more semiconductor dies; a ring located on the substrate and surrounding the semiconductor dies; a cap located on the semiconductor dies and the ring; and one or more thermoelectric coolers located on or in the cap, wherein the area of ​​each thermoelectric cooler is less than or equal to 40% of the total lateral area of ​​the semiconductor dies.

[0011] In a non-limiting exemplary embodiment, the cap includes: a plurality of thermal fins; an integral vapor chamber having a capillary layer formed on or located on the inner surface of the integral vapor chamber; and a thermal interface material located between the one or more semiconductor grains and the cap.

[0012] In a non-limiting exemplary embodiment, the one or more semiconductor dies include an integrated drive circuit connected to operate the one or more thermoelectric coolers located on or within the cover based on an input containing a temperature measured by a temperature sensor and / or the functions operated by the semiconductor package. Attached Figure Description

[0013] Figure 1 and Figure 2 This is a cross-sectional view of a semiconductor package. Figure 1 ) and simplified perspective ( Figure 2 Furthermore, the semiconductor package cap contains a thermoelectric cooler.

[0014] Figure 1A yes Figure 1 A schematic diagram of a thermoelectric cooler.

[0015] Figure 3 , Figure 4 ,and Figure 5 These are some non-limiting illustrative examples of a top view of a semiconductor package cap, wherein the semiconductor package has one or more thermoelectric coolers located on or in the cap.

[0016] Figure 6A and Figure 6B This is a cross-sectional view of the cap of a semiconductor package. Figure 6A ) and the top view ( Figure 6B The cover includes two thermoelectric coolers.

[0017] Figure 7A and Figure 7B This is a cross-sectional view of the cap of a semiconductor package. Figure 7A ) and the top view ( Figure 7B The cover includes two thermoelectric coolers and two sidewall thermoelectric coolers located on or in the sidewalls of the cover.

[0018] Figure 8This is a flowchart of a method for operating a thermoelectric cooler on or in the cover of a semiconductor package to cool the predetermined hot spot, based on feedback from a measured temperature of a predetermined hot spot or near the hot spot contained in the semiconductor package.

[0019] Figure 9 It is based on feedback from the operation of a monitored semiconductor package, operating a thermoelectric cooler on or in the cover of the semiconductor package to cool the hot spots of the semiconductor package.

[0020] The reference numerals in the attached figures are explained as follows:

[0021] D, S1, S2: Dimensions

[0022] H: Height

[0023] TH: Critical Upper Limit

[0024] TL: Critical Lower Limit

[0025] 10: Semiconductor Packaging

[0026] 11, 12, 13: Semiconductor grains

[0027] 14: Intermediary layer

[0028] 16: Epoxy molding compounds

[0029] 20, 28: Through holes

[0030] 22, 30: Engagement bumps

[0031] 24: Substrate

[0032] 26: Bottom Filling Material

[0033] 32: Embedded surface

[0034] 40: Capping

[0035] 42: Heat fins

[0036] 44: Thermal interface materials

[0037] 46: Ring

[0038] 48: Adhesive

[0039] 52: Steam chamber

[0040] 54: Capillary layer

[0041] 56, 561, 562: Hotspot reservations

[0042] 58: Components

[0043] 60, 601, 602: Thermoelectric coolers

[0044] 61: Sidewall Thermoelectric Cooler

[0045] 62, 64: Electrical conductors

[0046] 66: P-type region

[0047] 68: n-type region

[0048] 70: Current

[0049] 72: Voltage source

[0050] 74: First side

[0051] 76: Second side

[0052] 80: Integrated driver circuit

[0053] 82: Conductor

[0054] 84: Temperature sensor

[0055] 90, 102: Methods

[0056] 92, 94, 96: Steps

[0057] 95, 97, 100, 104, 106, 108: Operations Detailed Implementation

[0058] The following detailed description, accompanied by accompanying drawings, will aid in understanding all aspects of this utility model. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity.

[0059] The different embodiments or examples provided below can implement different structures of the present invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the present invention. For example, a description of forming a first component on a second component includes direct contact between the two, or the two being spaced apart by other additional components rather than in direct contact. Various embodiments of the present invention may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0060] In addition, spatial relative terms such as “below,” “lower,” “above,” “higher,” or similar terms are used to describe the relationship between some elements or structures in a diagram and another element or structure. These spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned in a different orientation (rotated 90 degrees or other orientations), the spatial relative adjectives used will also be interpreted according to the orientation after the turn.

[0061] Thermal power management is a primary consideration in semiconductor package design. The thermal power management methods described herein facilitate the strategic placement of one or more thermoelectric coolers at predetermined hot spots within the semiconductor package to provide locally controlled active thermal management. These predetermined hot spots are intended to be localized areas that generate the most heat, at least when the semiconductor package is performing a specific function. For example, in a system-on-a-chip (SoC) containing a complete graphics processor, the predetermined hot spot may be located at the location of the complete graphics processor on the SoC, i.e., when the graphics processor generates a significant amount of heat during complex computational video rendering. It is anticipated that other areas of the SoC will not generate such a large amount of heat. Therefore, in a non-limiting exemplary example, the thermoelectric cooler may be located on or within the cover of the semiconductor package containing the graphics processor portion of the SoC. This allows for localized cooling of the graphics processor's hot spot.

[0062] Furthermore, the thermal power management method disclosed herein facilitates time-dependent active cooling using these thermoelectric coolers. In the aforementioned example, the graphics processor (GPU) is a predetermined hotspot, but it only generates a high thermal load (i.e., becomes an actual hotspot) during video rendering operations, and the GPU may not generate this actual hotspot at other times. The advantage of the corresponding GPU thermoelectric cooler is that it operates only during semiconductor package operations such as video rendering, for example, when an actual hotspot exists. This control can be based on monitoring the operation of the semiconductor package (e.g., operating the thermoelectric cooler of the GPU portion of the system-on-chip during video rendering, but not operating the thermoelectric cooler at other times when the GPU load is low). This control can additionally or alternatively be based on active temperature monitoring, which employs temperature diodes, thermocouples, or other temperature sensors that can be integrated into the semiconductor package and located at the predetermined hotspot. For example, the temperature sensor can be located on or within the cover of the semiconductor package, or integrated into the integrated circuit die near the GPU.

[0063] In some embodiments, the thermal power management methods disclosed herein can be tightly integrated with a semiconductor package. For example, the power driver used to operate the thermoelectric cooler can be integrated into one or more semiconductor dies within the semiconductor package. While this method increases the total heat generated by the semiconductor package (because the thermoelectric cooler driver itself generates some heat), it facilitates targeted cooling of predetermined hot spots, thereby improving the thermal power management efficiency of the semiconductor package.

[0064] Figure 1 This is a non-limiting exemplary embodiment of the semiconductor package 10. Figure 1 Showing a cross-sectional view of semiconductor package 10. (e.g.) Figure 1As shown, the semiconductor package 10 includes one or more (three in the diagram) semiconductor dies 11, 12, and 13 located on an interposer 14. More specifically, the one or more semiconductor dies 11, 12, and 13 are located on a first major surface (such as a top surface or front surface) of the interposer 14. The one or more semiconductor dies 11, 12, and 13 can generally include any type of semiconductor die or a combination of multiple semiconductor dies. By way of some non-limiting examples, the one or more semiconductor dies 11, 12, and 13 can include integrated circuit dies such as microprocessors, microcontrollers, system-on-a-chip dies, central processing unit dies, graphics processing unit dies, solid-state memory dies, special-purpose integrated circuits, field-programmable gate arrays, photonic dies (such as semiconductor light-emitting diodes, lasers, or photodetectors), combinations of the above, and / or the like. These are merely some non-limiting illustrative examples. One or more semiconductor grains 11, 12, and 13 may be silicon or silicon-based grains, III-V semiconductor grains, silicon-germanium and / or silicon carbide grains, combinations thereof, or the like. Although each of the semiconductor grains 11, 12, and 13 in the figures is a single grain, it can be conceived as a stack of two (or more) semiconductor grains of a given semiconductor grain itself. An epoxy molding compound 16 or the like may surround one or more semiconductor grains 11, 12, and 13 and help support the structure of the semiconductor grains 11, 12, and 13 on the interposer layer 14.

[0065] Interposer 14 may be a silicon interposer, but sapphire interposers, silicon carbide interposers, or interposers of other materials are also considered. Electrical vias 20 pass through interposer 14. In the example of a silicon interposer, via 20 may include through-silicon vias (TSVs) to pass through interposer 14 (as in the example silicon interposer). In some non-limiting exemplary embodiments, the TSVs may be composed of copper. Interposer 14 may also include a redistribution layer (not shown) on its front and / or back sides. The inclusion of a redistribution layer, where appropriate, provides electrical paths for redistributing electrical signals and / or power transmission between one or more semiconductor dies 11, 12, and 13 and a second set of bonding bumps located on the back side of interposer 14.

[0066] On the back side of the interposer 14, bonding bumps 22 can electrically and mechanically bond one or more semiconductor dies 11, 12, and 13 to the first major surface (such as the top or front surface) of the substrate 24 where the interposer 14 is assembled. Underfill material 26, such as an epoxy underfill material in some non-limiting exemplary embodiments, can be filled between the bonding bumps 22 and between the back side of the interposer 14 and the front side of the substrate 24 to support the structure of the bonding bumps 22 and assist in bonding the back side of the interposer 14 to the front side of the substrate 24.

[0067] Substrate 24 may be a silicon substrate (such as a wafer or chip), but sapphire substrates, silicon carbide substrates, or substrates of other materials are also considered. Electrical vias 28, metallization layers, or other electrical conductors pass through substrate 24 to electrically connect bonding bumps 22 on the front side of substrate 24 to back-side or package-level bonding bumps 30 on a second primary surface (subsurface or back surface) of substrate 24. In the example of a silicon substrate, vias 28 may include through-silicon vias (TSVs) passing through substrate 24 (as in the example silicon substrate). In some non-limiting exemplary embodiments, the TSVs are composed of copper. Substrate 24 may also include front-side and / or back-side redistribution layers, which, where applicable, provide electrical paths for redistributing electrical signals to match the pad arrays of other mounting surfaces 32 on a printed circuit board or semiconductor package. The bonding bump 22 may be a solder bump, tin bump, tin-containing copper bonding ball, or the like, and may be arranged in a ball grid array to match the bonding pad array of the printed circuit board or other embedded surface 32.

[0068] During operation, one or more semiconductor dies 11, 12, and 13 of the semiconductor package 10 can generate a significant amount of heat. For example, the average operating power consumption of a system-on-a-chip (SoC) or graphics processor chip can be several watts, and power consumption can increase significantly during intensive computational operations (such as video rendering by a graphics processor) or complex computations (such as AI training by an SoC), such as increasing to tens of watts, hundreds of watts, or higher at peak power consumption. A large portion of this operating power is converted into heat, causing the one or more semiconductor dies 11, 12, and 13 and the semiconductor package 10 to heat up as a whole.

[0069] To provide thermal management, the semiconductor package 10 further includes a cap 40 to facilitate heat dissipation and descaling. The cap 40 may be composed of a thermally conductive material. As a non-limiting example, the thermally conductive material of the cap 40 may be copper, a copper alloy, copper-tungsten, aluminum or an aluminum alloy, aluminum silicon carbide, or the like. Hot fins 42 may be located on the surface of the cap 40, and this surface is away from one or more semiconductor chips 11, 12, and 13. The cap 40 is located on one or more semiconductor chips 11, 12, and 13, and a thermal interface material 44 is located between one or more semiconductor chips 11, 12, and 13 and the cap 40 to provide a tight thermally conductive contact between the one or more semiconductor chips 11, 12, and 13 and the cap 40. As some non-limiting examples, the thermal interface material 44 may include indium, silver, copper, an indium alloy, a silver alloy, a copper alloy, or a solder material.

[0070] Ring 46 surrounds one or more semiconductor dies 11, 12, and 13, and provides additional structural support for the cap 40 on the substrate 24 and / or provides a seal to protect the internal components of the semiconductor package 10 from environmental contamination. The periphery of the cap 40 is secured to ring 46, or the periphery of the cap 40 is supported by ring 46. In some non-limiting exemplary embodiments, the sealing and / or supporting ring 46 may comprise copper, nickel-iron alloys such as Alloy-42, stainless steel such as SUS420, nickel, tungsten, copper-tungsten, copper-molybdenum, invariant steel, or the like. In exemplary embodiments, adhesive 48 may bond the sealing and / or supporting ring 46 to the substrate 24. Ring 46 may also be secured to the cap 40 by an adhesive (not shown), or ring 46 may be integrally formed with the cap 40 (i.e., the cap 40 and ring 46 may be constructed as a single component).

[0071] The cap 40 includes an integral vapor chamber 52 containing a working fluid. A capillary layer 54 forms on and / or lies on the inner surface of the vapor chamber 52 to facilitate capillary transport of the working fluid. The capillary layer 54 provides a high surface area to facilitate capillary action. As a non-limiting exemplary example, the capillary layer 54 may include a braid of small-diameter wire (such as copper or copper alloy wire), sintered metal powder (such as copper powder), or the like. In some non-limiting exemplary embodiments, the thickness of the capillary layer 54 may be between about 0.1 mm and 0.5 mm, but larger or smaller thicknesses outside this range are contemplated. The working fluid contained in the vapor chamber 52 may vaporize near the walls of one or more semiconductor grains 11, 12, and 13, and may condense at a lower temperature in the portion of the vapor chamber 52 away from the walls. Therefore, a heat flow can be generated along the capillary layer 54, such as… Figure 1 The arrow along capillary layer 54 is shown in the diagram. The advantage of the working fluid is that it has a high latent heat to facilitate heat dissipation. In some non-limiting exemplary examples, the working fluid contained in the vapor chamber 52 may include propylene glycol, water, methanol, or a mixture thereof.

[0072] The vapor chamber 52 and its capillary layer 54 operate as a heat sink, utilizing a working fluid to transfer heat from the hot surfaces near one or more semiconductor grains 11, 12, and 13 to cooler distal surfaces within the vapor chamber 52. In some embodiments, the lateral region of the vapor chamber 52 is greater than or equal to the lateral region of one or more semiconductor grains 11, 12, and 13, such as... Figure 1 As shown. Generally speaking, Figure 1 and Figure 2Each illustration represents a Cartesian XYZ orientation system. In this system, the lateral direction or region lies in the XY plane, while the vertical direction lies in the Z direction (or is parallel to the Z direction). Therefore, in some embodiments, the lateral area of ​​the vapor chamber 52 is greater than or equal to the lateral area of ​​one or more semiconductor grains 11, 12, and 13, such as... Figure 1 Examples are provided.

[0073] The steam chamber 52 and its capillary layer 54 thus effectively function as a lateral radiator, generating heat flow and diffusion in the XY plane (or in a plane parallel to the XY plane), such as capillary flow of the working fluid along the capillary layer 54. However, the steam chamber 52 and its capillary layer 54 in the Z direction (i.e., Figure 1 The heat transfer efficiency in the vertical direction is relatively low. The vaporized working fluid flowing from the surface of one or more semiconductor grains 11, 12, and 13 to the distal portion of the vapor chamber 52 can support heat transfer in the Z direction, such as... Figure 1 As indicated by the curved arrow. Furthermore, the steam condensation capacity may be limited. For example, if the temperature of the distal portion of the steam chamber 52 is higher than the vaporization temperature of the working fluid, the working fluid will not condense. The steam chamber 52 and its capillary layer 54 may experience localized dryness, and the heat transfer efficiency at the dry points may be reduced.

[0074] Figure 1 This illustrates a predetermined hot spot 56 within semiconductor die 12. The predetermined hot spot 56 is a localized region of semiconductor die 12, designated as a location where a significant amount of heat is generated by semiconductor package 10 when performing at least some functions of the semiconductor package. In other examples (not shown), the predetermined hot spot may be the entire semiconductor die, generating more heat than other semiconductor dies within the semiconductor package. The predetermined hot spot 56 may be an actual hot spot when semiconductor package 10 is operating, or it may only be an actual hot spot when semiconductor package 10 performs specific functions. As a non-limiting illustrative example, semiconductor die 12 may include a graphics processor portion corresponding to the predetermined hot spot 56, where the predetermined hot spot 56 may be an actual hot spot when the graphics processor portion performs computationally intensive video rendering processing, and not an actual hot spot when the graphics processor portion is not operating or performing simple calculations for rendering. In another example, semiconductor die 12 may be a system-on-a-chip (SoC) die used for training artificial intelligence models, and the predetermined hot spot 56 may be a location where the SoC performs computationally intensive processing. The predetermined hotspots here refer to the actual hotspots used when training these AI models, and are not predetermined hotspots when not training AI models. These are non-limiting illustrative examples.

[0075] The so-called predetermined hot spot 56 can be predetermined in several ways. In one method, a circuit simulation program can be used to simulate the integrated circuit layout of one or more semiconductor dies 11, 12, and 13 to determine which region of one or more semiconductor dies 11, 12, and 13 will generate the most heat (and is therefore the predetermined hot spot). In another method, the integrated circuit layout can be analyzed to confirm this. For example, it is known that the graphics processor portion of the integrated circuit is an actual hot spot during image rendering, so the location of the graphics processor portion can be the predetermined hot spot. In yet another method, a prototype of the semiconductor package 10 can be created and imaged using a thermal imaging camera during operation to empirically identify the predetermined hot spot 56. Combinations of these methods can also be used to leverage their advantages.

[0076] like Figure 1 and Figure 2 As shown, in order to address these and other issues, the cover 40 further includes at least one thermoelectric cooler 60 located within or on the cover 40. Figure 2 A simplified perspective view of the semiconductor package 10 is shown, in which the cap 40 is indicated by a diagrammatic box, and the lower component 58 of the semiconductor package 10 is indicated by a diagrammatic box.

[0077] like Figure 1A As shown, the thermoelectric cooler 60 can be configured as a Peltier cooling device, including a p-type region 66 and an n-type region 68 connected in series by electrical interconnects of electrical conductors 62 and 64. In response to a current 70 driven by a voltage source 72 connected across the thermoelectric cooler 60 and flowing through the series-connected p-type and n-type regions 66 and 68, a thermoelectric effect can transfer heat from the first side 74 to the second side 76. The p-type region 66 and the n-type region 68 are suitable p-type semiconductor regions doped with p-type and suitable n-type semiconductor regions doped with n-type, respectively. By way of some non-limiting examples, the semiconductor material of the p-type region 66 and the n-type region 68 can be bismuth telluride, lead telluride, silicon germanium, bismuth antimonide alloy, or the like, but other semiconductor materials are contemplated. In some embodiments, an electrically insulating but thermally conductive plate (not shown) can provide a thermal contact. For example, the electrically insulating but thermally conductive plate can include a ceramic plate such as a beryllium oxide ceramic plate.

[0078] like Figure 1 As shown, the thermoelectric cooler 60 is located within or above the cover 40. Figure 1In an exemplary example, the thermoelectric cooler 60 is located within a cover 40 between the integral vapor chamber 52 and the heat fins 42, and at a predetermined hot spot 56 of one or more semiconductor chips 11, 12, and 13. In this position, the thermoelectric cooler 60 (electrically turned on and operated by the voltage source 72) facilitates the active transfer of heat in the vertical direction (i.e., the Z-direction) from the predetermined hot spot 56 toward the heat fins 42, which can then radiate heat to the surrounding air (or other surrounding fluid). Note that the cover 40 is thinner in the vertical or Z-direction compared to its lateral area in the XY plane. Therefore, the thermoelectric cooler 60 is positioned at approximately the same XY location as the corresponding predetermined hot spot 56, and at the predetermined hot spot 56 (ideally located by...). Figure 2 As can be seen in the perspective view, it is located at the predetermined hot spot 56 (in its lateral position) and the distance between it and the predetermined hot spot 56 is approximately equal to or less than the thickness of the cap 40 (the thinner thickness). In the indicated location between the integral steam chamber 52 and the hot fins 42, the thermoelectric cooler 60 helps cool the distal surface of the steam chamber 52, facilitates increasing the steam condensation capacity of the steam chamber 52, and reduces the possibility of localized dryness. It is estimated that approximately 10% of the cooling capacity of the cap 40 can be promoted when the predetermined hot spot 56 is activated.

[0079] Although not shown, the thermoelectric cooler can be located at the XY position corresponding to the predetermined hot spot 56, but vertically (i.e. in the Z direction) between the predetermined hot spot 56 and the steam chamber 52, which is beneficial for transferring heat from the predetermined hot spot 56 to the proximal surface of the steam chamber 52.

[0080] It should be further noted that in some embodiments, the cap does not contain an integral vapor chamber, but instead relies on...

[0081] The thermal conductivity of the cap, made of copper, copper alloy, aluminum, or other materials, and the active heat transfer provided by the thermoelectric cooler 60. Other methods are advantageous for reducing the overall thickness of the cap, thus allowing the thermoelectric cooler to be placed at the predetermined hot spot (its lateral position) and closer to the hot spot (because the cap is thinner).

[0082] In another proposed variation, instead of omitting the overall vapor chamber, it is replaced by another overall passive thermal management mechanism, such as a set of microchannels in the cap to provide convective heat transfer, embedded carbon nanowires to increase the thermal conductivity of the cap along the nanowire direction, or a similar mechanism.

[0083] It should be understood Figure 1 and Figure 2The semiconductor package 10 is a non-limiting exemplary example. Generally, a semiconductor package includes one or more semiconductor dies, a cap located on one or more semiconductor dies, and one or more thermoelectric coolers located on or within the cap, with the thermoelectric coolers situated at predetermined hot spots of the one or more semiconductor dies. In some other non-limiting examples, the semiconductor package may be a wafer-on-a-chip package, a substrate-on-wafer-on-a-chip package (as illustrated), an integrated fan-out package, or substantially any other heat-generating semiconductor package with a cap. Furthermore, while the exemplary thermoelectric cooler is located on or within the cap 40, it is conceivable that the thermoelectric cooler may be located within the semiconductor package, such as on or within the substrate 24.

[0084] As described above, the thermoelectric cooler 60 is located within or on the cover 40. For example, the thermoelectric cooler 60 may be attached to the outer surface of the cover 40 and between two adjacent heat fins 42. In another example, the thermoelectric cooler 60 may be located within a recess in the outer surface of the cover 40, such as between two adjacent heat fins 42. In yet another example, the thermoelectric cooler 60 may be embedded in the cover 40. These are merely some non-limiting illustrative examples.

[0085] exist Figure 1 and Figure 2 In an exemplary example, a single predetermined hot spot 56 is present, and a single thermoelectric cooler 60 is located on or within the cover 40 and situated at the predetermined hot spot 56. In other embodiments, two or more thermoelectric coolers may be present. Figure 3 , Figure 4 ,and Figure 5 The top view displays three non-restrictive illustrative examples. Figures 3 to 5 The top view shows the XYZ orientation system representing the transverse XY plane, while the XYZ orientation system is as follows: Figure 1 and Figure 2 As indicated. Figure 3 , Figure 4 ,and Figure 5 The diagram also shows the predetermined hot spot 56 corresponding to the thermoelectric cooler.

[0086] Figure 3 The example shown corresponds to Figure 1 and Figure 2 It has a single predetermined hot spot 56 and a single thermoelectric cooler 60 located on or in the cover 40 and on the single predetermined hot spot 56. Figure 4 The example shown has two predetermined hot spots 56 and two thermoelectric coolers 60, each of which is located on or in the cover 40 and in the corresponding predetermined hot spot 56. Figure 5The example shown has three predetermined hot spots 56 and three thermoelectric coolers 60, each of which is located on or in the cover 40 and at its corresponding predetermined hot spot 56. These are merely non-limiting illustrative examples, and four, five, six, or more hot spots and corresponding thermoelectric coolers can be deduced by analogy, depending on the number of predetermined hot spots.

[0087] exist Figure 3 , Figure 4 ,and Figure 5 In the example, each of the predetermined hot spots 56 is circular, and the corresponding thermoelectric cooler 60 is square or rectangular. However, non-square and non-rectangular thermoelectric coolers can be used to better match the shape of the corresponding hot spots.

[0088] Figure 6A and Figure 6B Here is an example. Figure 6A This is a cross-sectional view of a cover 40 according to one embodiment, which includes heat fins 42 and an integral vapor chamber 52 and its capillary layer 54, as configured... Figure 1 The above explains the content. In this example, one or more semiconductor chips (not shown in the figure) Figure 6A Thermoelectric cooler 601 is located on or in the cover 40 and is located (laterally) on the predetermined hot spot 561 of one or more semiconductor chips. Thermoelectric cooler 602 is located on or in the cover 40 and is located (laterally) on the predetermined hot spot 562 of one or more semiconductor chips.

[0089] Especially Figure 6B The top view of the cover 40 shown again, which again labels the XYZ direction system, shows that in this non-limiting illustrative example, the thermoelectric cooler 601 is a square or rectangle with side lengths such as dimensions S1 and S2 (if S1 = S2, the thermoelectric cooler 601 is square; if S1 ≠ S2, the thermoelectric cooler 601 is rectangular). Conversely, in this non-limiting illustrative example, the thermoelectric cooler 602 is a circle with a diameter such as dimension D. If the corresponding predetermined hot spot 562 (see...) Figure 6A If the thermoelectric cooler 602 is circular, its advantage lies in that its diameter, such as dimension D, can match the diameter of the predetermined circular hot spot 562, thereby effectively cooling the area of ​​the hot spot. The thermoelectric cooler can be conceived as other shapes, such as oval, hexagonal, octagonal, or other shapes. In some embodiments, the shape and its dimensions (such as S1, S2, D, or similar dimensions) are selected to match the shape and dimensions of the corresponding predetermined hot spot.

[0090] In some non-limiting exemplary embodiments, the dimensions of each thermoelectric cooler (e.g., S1, S2, D, or similar dimensions) are between 1.5 and 2 times the corresponding dimensions of the predetermined hot spots. This facilitates ensuring that the corresponding thermoelectric cooler can actively cool all hot spots, while also providing localized cooling. In some non-limiting exemplary embodiments, the dimensions of each thermoelectric cooler (e.g., S1, S2, D, or similar dimensions) are between 10 mm and 40 mm. In some embodiments, the lateral area of ​​each thermoelectric cooler is less than or equal to 40% of the total lateral area of ​​one or more semiconductor dies 11, 12, and 13, thus facilitating localized active cooling for one or more predetermined hot spots.

[0091] Figure 7A and Figure 7B In another embodiment, a cross-sectional view of the cover 40 is shown. Figure 7A ) and the top view ( Figure 7B In this embodiment, the cap 40 again includes the heat fins 42 and the integral vapor chamber 52 and its capillary layer 54, as configured... Figure 1 The above description clarifies that two predetermined hot spots 561 and 562 have corresponding thermoelectric coolers 601 and 602 located above or within the cover 40, and the thermoelectric coolers 601 and 602 are located (laterally) on the predetermined hot spots 561 and 562. Figure 7B In the embodiment shown, thermoelectric coolers 601 and 602 are both square or rectangular with dimensions S1 and S2.

[0092] like Figure 7A As shown, the difference between the cover 40 here and the aforementioned exemplary embodiment is that it further includes one or more (two in the figures) sidewall thermoelectric coolers 61 located on or within the sidewall of the cover 40. The advantage of the sidewall thermoelectric coolers 61 is that they enhance the vapor condensation of the working fluid in the integral steam chamber 52 on the surrounding peripheral sidewall of the steam chamber 52. Figure 7A Some embodiments shown facilitate increasing the thickness or height H of the cap 40 in the vertical or Z direction. It is worth noting that the thickness or height H excludes the height of the heat fins 42, see [link to previous section]. Figure 7A The increased thickness or height H will increase the volume of the steam chamber 52 and the total surface area of ​​the capillary layer 54, thereby increasing the cooling capacity and steam condensation capacity of the steam chamber 52.

[0093] In some non-limiting exemplary embodiments, Figure 7A and Figure 7B In the embodiments, the height H of the cap 40 can be approximately 5 mm to approximately 15 mm.

[0094] In some non-limiting exemplary embodiments, Figure 7A and Figure 7BIn the embodiments, the thickness or height H of the cap 40 is at least twice the thickness or height (in the Z direction) of one or more semiconductor grains.

[0095] In some non-limiting exemplary embodiments, Figure 7A and Figure 7B In the embodiments, the height H of the cap 40 is between 2 and 10 times the thickness of the package without the cap 40 (such as the thickness of a sub-package containing one or more semiconductor dies 11, 12, and 13, interposer 14, and substrate 24).

[0096] In some non-limiting exemplary embodiments, the area of ​​the sidewall thermoelectric cooler 61 is 40% or less of the area of ​​the peripheral wall of the sidewall of the cover 40.

[0097] like Figure 1 As shown, the thermoelectric cooler 60 is operated by a voltage source 72 connected to both ends of the thermoelectric cooler 60, and during operation, the thermoelectric cooler 60 can transfer heat from the first side 74 to the second side 76 through the thermoelectric effect, and then transfer heat from the steam chamber to the heat fins 42. Figure 1 In an exemplary example, one or more semiconductor dies (specifically, semiconductor die 11 in the exemplary example) include an integrated drive circuit 80 connected to operate one or more thermoelectric coolers 60 on or within the cover 40. The integrated drive circuit 80 can thus serve as a voltage source 72. A drive voltage can be supplied from the integrated drive circuit 80 to the thermoelectric cooler 60 via exemplary conductors 82 and associated conductors formed in the substrate 24 and embedded in or located on the cover 40. Figure 1A One embodiment includes a single thermoelectric cooler 60 driven by an integrated drive circuit 80, but Figure 4 , Figure 5 , Figure 6A ,and Figure 7A The embodiments may have two or more thermoelectric coolers, and the corresponding integrated drive circuit 80 may be used for each individual thermoelectric cooler. For example, the integrated drive circuit 80 may be a fixed voltage source integrated circuit or the like, primarily a metal-oxide-semiconductor field-effect transistor. In some embodiments, the advantage of the integrated drive circuit 80 is that it can be monolithically fabricated on the semiconductor die along with on-chip system circuitry, graphics processor circuitry, or other functional circuitry of the semiconductor die.

[0098] Although Figure 1 In an exemplary example, the integrated drive circuit 80 is integrated into one or more semiconductor dies 11, 12, and 13, which may instead provide the voltage source 72 in other ways, such as directly from a printed circuit board or from other mounting surfaces 32 on which the semiconductor package 10 is embedded.

[0099] In some embodiments, one or more thermoelectric coolers 60 may operate continuously or only when the semiconductor package 10 is in operation. This facilitates effective, targeted, and proactive cooling of predetermined hot spots 56, thereby improving the cooling capacity of the cap 40.

[0100] In some embodiments, one or more thermoelectric coolers 60 may be operated only when the predetermined hot spot 56 is activated to further increase the cooling capacity of the cover 40. In one method, one or more (one in the figure) temperature sensors 84 may monitor the temperature of the cover 40 of the predetermined hot spot 56, and the monitored temperature may be used to control an integrated drive circuit 80 to activate the thermoelectric cooler 60 when the monitored temperature exceeds a critical upper limit TH and deactivate the thermoelectric cooler 60 when the monitored temperature falls below a critical lower limit TL. Although the exemplary temperature sensor 84 is located in the cover 40, it may instead be monolithically integrated into one or more semiconductor dies 11, 12, and 13, such as, where appropriate, an integrated circuit monolithically fabricated within the semiconductor die along with system-on-a-chip circuitry, graphics processor circuitry, or other functional circuitry of the semiconductor die. In embodiments having two or more predetermined hot spots and corresponding two or more thermoelectric coolers, each predetermined hot spot may be monitored by a separate temperature sensor. For example, the temperature sensor 84 may be a temperature diode, a thermocouple, or the like.

[0101] like Figure 8 As shown, the method 90 used for each predetermined hot spot 56 can control the corresponding thermoelectric cooler 60 based on the temperature sensed by the temperature sensor 84. Step 92 monitors the temperature of the predetermined hot spot 56 or its vicinity, which can be achieved using the temperature sensor 84. In decision step 94, it is confirmed whether the monitored temperature is higher than a critical upper limit TH. If it is higher than the critical upper limit TH, the integrated drive circuit 80 in operation 95 turns on (i.e. operates) the thermoelectric cooler 60 located at the predetermined hot spot 56 to perform active targeted cooling of the predetermined hot spot 56. If it is lower than the critical upper limit TH, in decision step 96, it is confirmed whether the monitored temperature is lower than a critical lower limit TL. If it is lower than the critical lower limit TL, the integrated drive circuit 80 in operation 97 turns off (i.e. does not operate) the thermoelectric cooler 60 located at the predetermined hot spot 56, and does not perform active targeted cooling of the predetermined hot spot 56.

[0102] In some embodiments, the critical upper limit TH and the critical lower limit TL may be the same. In other embodiments, the critical upper limit TH is higher than the critical lower limit TL. This provides a hysteresis effect, meaning that once operation 95 turns on the thermoelectric cooler 60 at the temperature of the critical upper limit TH, the hysteresis will continue until the temperature drops below the temperature of the critical lower limit TL. This avoids frequent switching of the thermoelectric cooler 60 and facilitates smooth operation. If the monitored temperature is close to the critical temperature (and the critical upper limit TH = the critical lower limit TL), the thermoelectric cooler 60 may switch on and off frequently.

[0103] Figure 9 Another control method is described, which turns the thermoelectric cooler on or off based on the functional operation of the semiconductor package. In operation 100, the operation of the semiconductor package 10 is monitored. Method 102 is performed for each predetermined hot spot 56 to operate the thermoelectric cooler 60 located at the predetermined hot spot based on package functional information. In operation 104, it is confirmed whether the semiconductor package 10 is operating a function that generates heat at the predetermined hot spot. If this function is operating, operation 106 turns on (i.e., operates) the thermoelectric cooler 60 located at the predetermined hot spot 56. If this function is not operating, operation 108 turns off (i.e., does not operate) the thermoelectric cooler 60 located at the predetermined hot spot 56.

[0104] For example, considering the predetermined hot spot 56 of the graphics processor section of the corresponding system-on-a-chip (SoC) die, in operation 104, it is determined whether the SoC is performing video rendering. If it is determined that video rendering is being performed, operation 106 is called to operate the thermoelectric cooler 60, which is located at the predetermined hot spot 56 of the corresponding graphics processor section. If video rendering is not being performed, operation 108 is called without operating the thermoelectric cooler 60, which is located at the predetermined hot spot 56 of the corresponding graphics processor section. This method is based on the premise that the predetermined hot spot 56 of the corresponding graphics processor section is expected to be turned on (i.e., generate a large amount of heat) only during video rendering.

[0105] Figure 9 The advantage of this control method is that it eliminates the need for a temperature sensor 84. If an integrated drive circuit 80 is used, it can be integrated into one or more semiconductor chips 11, 12, and 13, and then 100 and 104 can be programmed to operate the functional integrated circuits of one or more semiconductor chips 11, 12, and 13. In the above example, once graphics rendering is started, the integrated drive circuit 80 can be turned on to operate the thermoelectric cooler 60 corresponding to the predetermined hot spot 56 of the graphics processor section. Once graphics rendering is stopped, the integrated drive circuit 80 can be turned off to stop operating the thermoelectric cooler 60 corresponding to the predetermined hot spot 56 of the graphics processor section.

[0106] Some other embodiments are described below.

[0107] In a non-limiting exemplary embodiment, the semiconductor package is characterized by comprising one or more semiconductor dies; and a cap located on the semiconductor die. One or more thermoelectric coolers are located on or within the cap. Each thermoelectric cooler is located at a predetermined hot spot of the semiconductor die.

[0108] In some embodiments, the thermoelectric cooler consists of two or more thermoelectric coolers.

[0109] In some embodiments, the cover includes an integral vapor chamber having a capillary layer formed on or located on the inner surface of the integral vapor chamber.

[0110] In some embodiments, the semiconductor package further includes: a substrate, wherein a semiconductor die is located on the substrate; a thermal interface material located between the semiconductor die and a cap; and a ring surrounding the semiconductor die, wherein the ring is fixed to or integrally formed with the cap.

[0111] In some embodiments, the cover includes an integral vapor chamber having a capillary layer formed on or located on the inner surface of the integral vapor chamber; and a plurality of hot fins located on the surface of the cover away from the semiconductor grain, wherein a thermoelectric cooler is located between the integral vapor chamber and the hot fins.

[0112] In some embodiments, the semiconductor package further includes one or more sidewall thermoelectric coolers located on or within the sidewalls of the cover.

[0113] In some embodiments, the height of the cap is at least twice the height of the semiconductor die.

[0114] In some embodiments, the lateral area of ​​the cover is greater than or equal to the total lateral area of ​​the semiconductor die; and the lateral area of ​​each thermoelectric cooler is less than or equal to 40% of the total lateral area of ​​the semiconductor die.

[0115] In some embodiments, the thermoelectric coolers are each square, rectangular, circular, oval, hexagonal, or octagonal.

[0116] In some embodiments, the semiconductor die includes connected integrated drive circuitry to operate a thermoelectric cooler located on or within the cap.

[0117] In some embodiments, each predetermined hot spot is a location on the semiconductor die where heat is generated when the semiconductor package operates a function to generate heat at the predetermined hot spot; and the semiconductor die is configured to operate the thermoelectric cooler located at each predetermined hot spot only when the semiconductor die operates a function to generate heat at the predetermined hot spot.

[0118] In some embodiments, the semiconductor package further includes one or more temperature sensors, wherein the semiconductor die is configured to operate a thermoelectric cooler located at each predetermined hot spot based on feedback from the temperature sensors.

[0119] In some embodiments, each thermoelectric cooler includes a plurality of p-type semiconductor regions and a plurality of n-type semiconductor regions with electrical interconnects.

[0120] In a non-limiting exemplary embodiment, the method of operating the semiconductor package includes the function of operating one or more semiconductor dies of the semiconductor package. During operation, one or more predetermined hot spots of the semiconductor die are cooled by operating a thermoelectric cooler located at each of the other predetermined hot spots.

[0121] In some embodiments, the step of cooling predetermined hot spots includes operating a thermoelectric cooler located at each of the other predetermined hot spots only when the function of the semiconductor package generates heat at the predetermined hot spots.

[0122] In some embodiments, the step of cooling predetermined hot spots includes: measuring the temperature of each predetermined hot spot during operation; and operating a thermoelectric cooler located at each other predetermined hot spot based on the measured temperature of the hot spot during operation.

[0123] In some embodiments, the semiconductor die includes an integrated driving circuit; and the cooling step includes operating a thermoelectric cooler using the integrated driving circuit of the semiconductor die.

[0124] In a non-limiting exemplary embodiment, the semiconductor package is characterized by including a substrate; one or more semiconductor dies; a ring located on the substrate and surrounding the semiconductor dies; a cap located on the semiconductor dies and the ring; and one or more thermoelectric coolers located on or in the cap, wherein the area of ​​each thermoelectric cooler is less than or equal to 40% of the total lateral area of ​​the semiconductor dies.

[0125] In some embodiments, the cap includes a plurality of thermal fins; an integral vapor chamber having a capillary layer formed on or located on the inner surface of the integral vapor chamber; and a thermal interface material located between the semiconductor die and the cap.

[0126] In some embodiments, the semiconductor die includes connected integrated drive circuitry to operate a thermoelectric cooler located on or within the cover based on an input containing a temperature measured by a temperature sensor and / or the function operated by the semiconductor package.

[0127] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor package, characterized by, include: One or more semiconductor chips; A cap is located on one or more semiconductor chips; as well as One or more thermoelectric coolers are located on or in the cover, and each of the one or more thermoelectric coolers is located at a predetermined hot spot of the one or more semiconductor chips.

2. The semiconductor package of claim 1, wherein, The one or more thermoelectric coolers consist of two or more thermoelectric coolers.

3. The semiconductor package of claim 1 or 2, wherein, The cap includes an integral vapor chamber having a capillary layer formed on or located on the inner surface of the integral vapor chamber.

4. The semiconductor package of claim 3, wherein, Including: A substrate, wherein the one or more semiconductor chips are located on the substrate; A thermal interface material is located between the one or more semiconductor grains and the cap; and A ring surrounds one or more semiconductor grains, and the ring is fixed to the cap or integrally formed with the cap.

5. The semiconductor package of claim 1 or 2, wherein, The cap includes: An integral steam chamber having a capillary layer formed on or located on the internal surface of the integral steam chamber; and Multiple heat fins are located on the surface of the cap that is away from the one or more semiconductor grains. The one or more thermoelectric coolers are located between the overall steam chamber and the multiple heat fins.

6. The semiconductor package of claim 1 or 2, wherein, Including: One or more sidewall thermoelectric coolers are located on or in the sidewall of the cover.

7. The semiconductor package of claim 6, wherein the semiconductor package is a flip chip semiconductor package. The height of the cap is at least twice the height of the one or more semiconductor chips.

8. A semiconductor package, characterized by, include: One substrate; One or more semiconductor chips; A ring, located on the substrate and surrounding the one or more semiconductor grains; A cap, located on the one or more semiconductor chips and the ring; and One or more thermoelectric coolers are located on or in the cover. The area of ​​each of the one or more thermoelectric coolers is less than or equal to 40% of the total lateral area of ​​the one or more semiconductor grains.

9. The semiconductor package of claim 8, wherein the semiconductor package is a flip chip semiconductor package. The cap includes: Multiple heat fins; An integral steam chamber having a capillary layer formed on or located on the internal surface of the integral steam chamber; and A thermal interface material is located between the one or more semiconductor grains and the cap.

10. The semiconductor package as described in claim 8 or 9, characterized in that, The one or more semiconductor chips include an integrated drive circuit connected to operate the one or more thermoelectric coolers located on or in the cover based on an input containing a temperature measured by a temperature sensor and / or the functions operated by the semiconductor package.

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