Method for avoiding slit defects in mask patterns of a self-aligned double patterning process

Abstract

This application provides a method for avoiding slit defects in mask patterns during self-aligned dual-patterning processes, comprising: Step 1, providing a substrate, and sequentially forming an interlayer dielectric layer, an anti-reflection coating, a titanium nitride layer, a TEOS layer, and a patterned sacrificial layer on the substrate; Step 2, forming a mask layer within the gaps between the patterned sacrificial layers; Step 3, after removing the patterned sacrificial layers, performing a first etching using the mask layer as a mask until the exposed TEOS layer is removed, wherein the mask layer is not etched through during the first etching process; Step 4, performing a second etching using the TEOS layer as a mask until the exposed titanium nitride layer is removed, thereby forming the mask pattern. According to this application, the generation of slit defects can be effectively avoided, while simultaneously expanding the CD window (distance between lithographic patterns).

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and specifically to a method for avoiding slit defects in mask patterns during self-aligned dual patterning processes. Background Technology

[0002] The principle of self-aligned double patterning (SADP) is to deposit a mask layer in the groove between the lithographic patterns after a single photolithography step, and then achieve frequency doubling of the spatial pattern through etching. This technology involves only one photolithography step, and therefore is not affected by the overlay error between two photolithography steps.

[0003] like Figure 1 and Figure 2 As shown, when the spacing between photolithographic patterns is too large, the thickness of the mask layer is limited by a set value. After deposition, the middle part of the mask layer formed in the grooves between the photolithographic patterns is concave. During subsequent etching, slit defects will appear in the mask pattern. After etching, the copper metal filling the slit defects causes bridging, resulting in circuit failure. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method to avoid slit defects in mask patterns formed by self-aligned dual patterning process, so as to solve the problem of slit defects in mask patterns formed by existing self-aligned dual patterning process.

[0005] To achieve the above and other related objectives, this application provides a method for avoiding slit defects in mask patterns during self-aligned dual-patterning processes, comprising: Step 1: Provide a substrate, and sequentially form an interlayer dielectric layer, an anti-reflective coating, a titanium nitride layer, a TEOS layer, and a patterned sacrificial layer on the substrate; Step two: Form a mask layer within the gaps between the patterned sacrificial layers; Step 3: After removing the patterned sacrificial layer, the first etching is performed using the mask layer as a mask until the exposed TEOS layer is removed. During the first etching process, the mask layer is not etched through. Step four: Using the TEOS layer as a mask, perform the second etching until the exposed titanium nitride layer is removed, forming the mask pattern.

[0006] Preferably, in step three, the process conditions of the first etching are adjusted to change the etching selectivity ratio of the first etching to the mask layer and the TEOS layer, so as to ensure that the mask layer is not etched through during the implementation of the first etching.

[0007] Preferably, adjusting the process conditions for the first etching includes adjusting the ESC temperature distribution, RF power, bias voltage, and gas ratio.

[0008] Preferably, the thickness of the TEOS layer is reduced during step one to ensure that the mask layer is not etched through during the first etching process.

[0009] Preferably, the thickness of the mask layer is increased during step two to ensure that the mask layer is not etched through during the first etching process.

[0010] Preferably, in step two, the mask layer material is first deposited to fill the gaps between the patterned sacrificial layers, and then the mask layer material outside the gaps is removed by an etch-back process. The mask layer material includes titanium oxide.

[0011] Preferably, after the second etching is completed, the mask layer on the TEOS layer is completely removed, and the resulting mask pattern consists of titanium nitride layers and TEOS layers stacked from bottom to top.

[0012] Preferably, the first and second etching processes are anisotropic dry etching.

[0013] Preferably, after step four, the anti-reflective coating and interlayer dielectric layer are etched using the mask pattern as a mask. After etching, the gaps between the patterns are filled with metallic copper.

[0014] Preferably, the material of the patterned sacrificial layer includes amorphous silicon.

[0015] As described above, the method for avoiding slit defects in mask patterns in self-aligned dual-patterning processes provided in this application has the following beneficial effects: it can effectively avoid the generation of slit defects and at the same time expand the CD window of the spacing between lithographic patterns. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a partial cross-sectional structure of a device showing the formation process of slit defects within a mask pattern during the implementation of a self-aligned dual patterning process. Figure 2 Displayed as Figure 1 An electronic photograph of the slit defect shown in the image; Figure 3 The flowchart shown is a method for avoiding slit defects in mask patterns in a self-aligned dual-patterning process provided in an embodiment of this application. Figure 4 Displayed as implementation Figure 3A schematic diagram of a partial cross-sectional structure of the device after step three; Figure 5 Displayed as implementation Figure 3 A schematic diagram of the partial cross-sectional structure of the device after step four. Detailed Implementation

[0018] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0019] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0023] Please see Figure 3 The diagram illustrates a flowchart of a method for avoiding slit defects in mask patterns in a self-aligned dual-patterning process, as provided in an embodiment of this application.

[0024] like Figure 3 As shown, the method for avoiding slit defects in mask patterns during self-aligned dual-patterning processes includes the following steps: Step 1: Provide a substrate, and sequentially form an interlayer dielectric layer, an anti-reflective coating, a titanium nitride layer, a TEOS layer, and a patterned sacrificial layer on the substrate; Step two: Form a mask layer within the gaps between the patterned sacrificial layers; Step 3: After removing the patterned sacrificial layer, the first etching is performed using the mask layer as a mask until the exposed TEOS layer is removed. During the first etching process, the mask layer is not etched through. Step four: Using the TEOS layer as a mask, perform the second etching until the exposed titanium nitride layer is removed, forming the mask pattern.

[0025] In step one, a substrate is provided. Optionally, the substrate may be a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the substrate material may also include other materials, such as gallium arsenide or other III-V compounds. Those skilled in the art can select the substrate material according to the type of device structure formed on the substrate, therefore the type of substrate should not limit the scope of protection of this invention.

[0026] Optionally, the material of the interlayer dielectric layer may include, but is not limited to: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ethers, or other materials with low dielectric constants (<3.9).

[0027] For example, an interlayer dielectric layer is formed using a chemical vapor deposition process.

[0028] For example, an anti-reflective coating is formed using a spin coating process, and a titanium nitride (TIN) layer and a TEOS layer are formed using a deposition process.

[0029] As an example, the steps for forming a patterned sacrificial layer include: sequentially forming a sacrificial layer and a patterned photoresist layer on a TEOS layer; etching the sacrificial layer using the photoresist layer as a mask; and removing the photoresist layer.

[0030] For example, the material of the sacrificial layer includes amorphous silicon.

[0031] In step two, the mask layer material is first deposited to fill the gaps between the patterned sacrificial layers, and then the mask layer material located outside the gaps is removed by the etch-back process.

[0032] For example, the mask layer material includes titanium dioxide (TIO).

[0033] In step three, to ensure that the mask layer is not etched through during the first etching process (the TEOS layer is not exposed below any part of the mask layer), there are three solutions: The first approach involves adjusting the process conditions of the first etching step, changing the etching selectivity ratio of the mask layer and the TEOS layer, such as adjusting the ESC temperature distribution, RF power, bias voltage, and gas ratio. The second approach is to reduce the thickness of the TEOS layer without adjusting the process conditions of the first etching step. The third approach involves appropriately increasing the thickness of the mask layer without adjusting the process conditions of the first etching step, for example, increasing the mask layer thickness from 140 Å to 150 Å. With the increased mask layer thickness, it is necessary to adjust the feature size of the trenches between the patterns formed in different regions of the substrate.

[0034] For example, the first etching is anisotropic dry etching.

[0035] After step three is completed, as follows Figure 4 As shown, the TEOS layer is exposed without passing through any part of the mask layer.

[0036] In step four, after the second etching is completed, as follows: Figure 5 As shown, the mask layer on the TEOS layer was completely removed, and the resulting mask pattern consisted of titanium nitride layers and TEOS layers stacked from bottom to top. No slit defects were formed in the mask pattern.

[0037] For example, the second etching is anisotropic dry etching.

[0038] After step four is completed, the anti-reflective coating and interlayer dielectric layer are etched using the mask pattern as a mask. After etching is completed, the gaps between the patterns are filled with metallic copper.

[0039] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0040] In summary, the method provided in this application for avoiding slit defects in mask patterns during self-aligned dual-patterning processes can effectively prevent the generation of slit defects while simultaneously expanding the CD window between lithographic patterns. Therefore, this application effectively overcomes various shortcomings of the prior art and has high industrial applicability.

[0041] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A method for avoiding slit defects in mask patterns during self-aligned double patterning processes, characterized in that, The method includes: Step 1: Provide a substrate, and sequentially form an interlayer dielectric layer, an anti-reflective coating, a titanium nitride layer, a TEOS layer, and a patterned sacrificial layer on the substrate; Step 2: Form a mask layer within the gaps between the patterned sacrificial layers; Step 3: After removing the patterned sacrificial layer, the first etching is performed using the mask layer as a mask until the exposed TEOS layer is removed. During the first etching process, the mask layer is not etched through. Step four: Using the TEOS layer as a mask, perform a second etching until the exposed titanium nitride layer is removed, forming a mask pattern.

2. The method according to claim 1, characterized in that, In step three, the process conditions of the first etching are adjusted to change the etching selectivity ratio of the first etching on the mask layer and the TEOS layer, so as to ensure that the mask layer is not etched through during the implementation of the first etching.

3. The method according to claim 2, characterized in that, The process conditions for adjusting the first etching include adjusting the ESC temperature distribution, RF power, bias voltage, and gas ratio.

4. The method according to claim 1, characterized in that, When performing step one, the thickness of the TEOS layer is reduced to ensure that the mask layer is not etched through during the first etching process.

5. The method according to claim 1, characterized in that, When performing step two, the thickness of the mask layer is increased to ensure that the mask layer is not etched through during the first etching process.

6. The method according to claim 1, characterized in that, In step two, a deposition process is first used to fill the gaps between the patterned sacrificial layers with mask layer material, and then a back etching process is used to remove the mask layer material located outside the gaps. The mask layer material includes titanium oxide.

7. The method according to claim 1, characterized in that, After the second etching is completed, the mask layer on the TEOS layer is completely removed, and the resulting mask pattern is composed of the titanium nitride layer and the TEOS layer stacked from bottom to top.

8. The method according to claim 1, characterized in that, The first etching and the second etching are anisotropic dry etching.

9. The method according to claim 1, characterized in that, After step four is completed, the anti-reflective coating and the interlayer dielectric layer are etched using the mask pattern as a mask. After etching, the gaps between the patterns are filled with metallic copper.

10. The method according to claim 1, characterized in that, The patterned sacrificial layer is made of amorphous silicon.

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