Chip packaging structure, chip and electronic device

Abstract

This application discloses a chip packaging structure, a chip, and an electronic device, relating to the field of semiconductor technology. The chip packaging structure includes: a first chip; and a redistribution structure stacked on top of the first chip. The redistribution structure includes a first dielectric layer, in which multiple three-dimensional porous structures are embedded. Each three-dimensional porous structure has pores filled with metal, and the three-dimensional porous structures are conductive with a coefficient of thermal expansion less than that of the metal. The leads of the first chip extend from a first surface of the redistribution structure to a second surface of the redistribution structure through at least a portion of the multiple first conductive structures. The second surface is positioned opposite to the first surface, and the first surface is in contact with the first chip. The chip packaging structure provided by this application can alleviate the warpage problem of the redistribution layer, thereby improving the reliability of the chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a chip packaging structure, a chip, and an electronic device. Background Technology

[0002] With the development of technologies such as communication and artificial intelligence, the demand for massive data flow and transfer is increasing. Hardware supporting applications such as 5G and artificial intelligence needs to have functions such as high-speed computing, low latency, high bandwidth, and system integration. To meet the functional requirements of hardware devices, existing semiconductor technologies typically use redistribution layers (RDLs) to interconnect active or passive devices within a chip, or to interconnect multiple chips or between a chip and a carrier board (such as an adapter board or circuit board) during chip packaging.

[0003] Existing Reliable Array Connectors (RDLs) use conductive lines on an insulating medium to achieve interconnections within or between chips. The insulating medium is typically made of materials such as silicon (Si) or silicon dioxide (SiO2), while the conductive lines formed on it are usually made of metal. However, the coefficient of thermal expansion of metals is much higher than that of the surrounding insulating medium. The stress accumulated due to this mismatch in thermal expansion coefficients within the RDL layers cannot be released, leading to warping. This warping deformation can cause problems such as circuit cracks, solder deformation, and poor soldering / misalignment, and these issues become increasingly severe with increasing interconnect density, the number of RDL layers, and the structural size. Ultimately, this can lead to connection failures within or between chips, resulting in chip malfunction. Therefore, improving chip reliability is a problem that needs to be addressed. Summary of the Invention

[0004] The chip packaging structure, chip, and electronic device provided in this application can alleviate the chip warpage problem. To achieve the above objective, the embodiments of this application adopt the following technical solution:

[0005] In a first aspect, embodiments of this application provide a chip packaging structure, comprising: a first chip; and a redistribution structure stacked on top of the first chip. The redistribution structure includes a first dielectric layer, in which a plurality of three-dimensional porous structures are embedded. Each of the three-dimensional porous structures has pores filled with metal. The three-dimensional porous structures are conductive, and their coefficient of thermal expansion is less than that of the metal. The leads of the first chip extend from a first surface of the redistribution structure to a second surface of the redistribution structure through at least a portion of the three-dimensional porous structures. The second surface is opposite to the first surface, and the first surface is in contact with the first chip. The three-dimensional porous structures are continuous.

[0006] In the chip packaging structure provided in this application embodiment, since the thermal expansion coefficient of the three-dimensional porous structure is smaller than that of metals, for example, the thermal expansion coefficient of copper is 16ppm, and the thermal expansion coefficient of graphene is negative (-7ppm) in the temperature range of 100K to 1000K, and the three-dimensional porous structure is soft and deformable, the conductive structure in the first dielectric layer of the redistribution structure is set as a three-dimensional porous structure filled with metal. The three-dimensional porous structure can buffer the stress generated by the expansion of metal. Macroscopically, this results in a reduction in the overall equivalent thermal expansion coefficient of the three-dimensional porous structure, reducing the problem of thermal expansion coefficient mismatch between the materials of each layer. This can reduce the warpage of the redistribution structure. Compared with the prior art, this is beneficial to alleviate problems such as circuit cracks, solder deformation, poor soldering / misalignment, etc., and thus improve chip reliability.

[0007] In one possible implementation, the three-dimensional porous structure is a continuous structure with multiple pores formed on its surface.

[0008] In one possible implementation, the three-dimensional porous structure has multiple blades that are connected together in a stacked or horizontally arranged manner to form a continuous structure, and the gaps between the multiple blades form multiple pores in the three-dimensional porous structure.

[0009] In one possible implementation, the material of the three-dimensional porous structure is a carbon-based derivative.

[0010] In one possible implementation, the redistribution structure further includes a second dielectric layer and a third dielectric layer stacked sequentially on top of the first dielectric layer; the second dielectric layer has a plurality of vias, and the third dielectric layer has a plurality of conductive structures, the vias being used to connect the plurality of three-dimensional porous structures and the plurality of conductive structures; the lead-out terminals of the first chip are led out from the first surface of the redistribution structure to the second surface of the redistribution structure through at least a portion of the three-dimensional porous structures in the first dielectric layer, at least a portion of the vias in the second dielectric layer, and at least a portion of the conductive structures in the third dielectric layer.

[0011] In one possible implementation, each of the multiple conductive structures can be a three-dimensional porous structure, identical to the three-dimensional porous structure in the first dielectric layer, i.e., the pores are filled with metal. The three-dimensional porous structure is conductive, and its coefficient of thermal expansion is less than that of the metal. By setting the conductive structure as a three-dimensional porous structure, the warpage of the redistribution structure can be further reduced, which helps to alleviate problems such as circuit cracks, solder deformation, poor soldering / misalignment, etc., thereby improving chip reliability.

[0012] In one possible implementation, each of the multiple vias can contain a three-dimensional porous structure. This three-dimensional porous structure is identical to the one in the first dielectric layer, meaning the pores are filled with metal. The three-dimensional porous structure is conductive, and its coefficient of thermal expansion is less than that of the metal. By using a three-dimensional porous structure for the conductive components in the vias, warpage of the redistribution structure can be further reduced, which helps to alleviate problems such as circuit cracks, solder deformation, poor soldering / misalignment, and thus improves chip reliability.

[0013] In one possible implementation, a conductive thin film is further disposed between each three-dimensional porous structure in the first dielectric layer and the first dielectric layer; when the conductive structure in the second dielectric layer is a three-dimensional porous structure, a conductive thin film is further disposed between each conductive structure in the third dielectric layer and the third dielectric layer; when each through-hole contains a three-dimensional porous structure, a conductive thin film is further disposed between the three-dimensional porous structure in each through-hole and the hole wall of the through-hole. The material of the conductive thin film can be, for example, a metal, including but not limited to: titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or copper (Cu), etc.

[0014] By setting a conductive film between each three-dimensional porous structure in the first dielectric layer and the first dielectric layer, or between each conductive structure in the third dielectric layer and the third dielectric layer, or between each three-dimensional porous structure in a through hole and the hole wall of the through hole, the conductive film can act as a conductive medium, which is beneficial for the rapid filling of the metal in the conductive film into the three-dimensional porous structure during the formation of the three-dimensional porous structure.

[0015] In one possible implementation, the chip package structure further includes a second chip, which is stacked on top of the first chip; the second chip includes conductive pillars penetrating the upper and lower surfaces of the second chip, and the second chip is connected to the first chip through the conductive pillars; wherein the conductive pillars are three-dimensional porous structures.

[0016] By setting the conductive pillars in the second chip as a three-dimensional porous structure filled with metal, the stress generated by the expansion of the metal in the second chip can be buffered. Macroscopically, this results in a reduction in the overall equivalent thermal expansion coefficient of the chip, reducing the problem of thermal expansion coefficient mismatch between different layers of materials. This can reduce chip warpage and help alleviate the aforementioned problems such as circuit cracks, solder deformation, poor soldering / misalignment, etc., thereby improving chip reliability.

[0017] In one possible implementation, the chip package structure further includes a third chip; the lead-out terminals of the third chip are led out from the first surface of the redistribution structure to the second surface of the redistribution structure through at least a portion of the three-dimensional porous structure in the first dielectric layer, at least a portion of the through-hole in the second dielectric layer, and at least a portion of the conductive structure in the third dielectric layer.

[0018] In one possible implementation, the first chip is interconnected with the third chip through at least a portion of a three-dimensional porous structure in a first dielectric layer, at least a portion of a through-hole in a second dielectric layer, and at least a portion of a conductive structure in a third dielectric layer.

[0019] In one possible implementation, the chip package structure includes one of the following: a fan-out chip package structure, a fan-in chip package structure, a 2.5D chip package structure, or a 3D chip package structure.

[0020] Secondly, embodiments of this application provide a chip, the chip comprising: a semiconductor structure having a plurality of semiconductor devices disposed thereon; a redistribution structure disposed on the semiconductor structure, the redistribution structure including a dielectric layer having a plurality of three-dimensional porous structures embedded therein, each of the plurality of three-dimensional porous structures having pores filled with metal, the three-dimensional porous structures being conductive, and the coefficient of thermal expansion of the three-dimensional porous structures being less than the coefficient of thermal expansion of the metal; the plurality of semiconductor devices being interconnected through a plurality of conductive structures.

[0021] In this embodiment, by setting the conductive structure in the rewiring structure of the chip as a three-dimensional porous structure filled with metal, the problem of thermal expansion coefficient mismatch between the metal in the rewiring structure and the surrounding insulating material can be alleviated, thereby avoiding warping of the rewiring structure and deformation, thus improving the reliability of the chip.

[0022] In one possible implementation, the three-dimensional porous structure is a continuous structure with multiple pores formed on its surface.

[0023] In one possible implementation, the three-dimensional porous structure has multiple blades that are connected together in a stacked or horizontally arranged manner to form a continuous structure, and the gaps between the multiple blades form multiple pores in the three-dimensional porous structure.

[0024] In one possible implementation, the semiconductor structure is made of silicon and has multiple through-silicon vias (TSVs). Multiple semiconductor devices are connected to the redistribution structure through these TSVs. The conductive structure in each TSV is a three-dimensional porous structure.

[0025] By setting the conductive structure of the through-silicon via (TSV) in a semiconductor structure as a three-dimensional porous structure filled with metal, the problem of thermal expansion coefficient mismatch between the metal in the TSV and the surrounding silicon material can be alleviated. This can avoid warping around the TSV and thus avoid TSV deformation, thereby improving chip reliability.

[0026] In one possible implementation, the material of the three-dimensional porous structure is a carbon-based derivative.

[0027] In one possible implementation, the plurality of semiconductor devices include at least one of the following: a transistor, a resistor, or a capacitor.

[0028] Thirdly, embodiments of this application provide an electronic device, which includes a circuit board and a chip packaging structure as described in the first aspect; the chip packaging structure is disposed on the circuit board by a plurality of solders, the plurality of solders including one of the following: pads or microbumps.

[0029] In one possible implementation, the circuit board has through-holes, and the conductive structure in the through-holes is a three-dimensional porous structure. The pores of the three-dimensional porous structure are filled with metal. The three-dimensional porous structure is conductive, and the coefficient of thermal expansion of the three-dimensional porous structure is less than that of the metal. The chip package structure is connected to the through-holes on the circuit board through multiple solders to bring the leads of the packaged chip to the surface of the circuit board away from the chip package structure.

[0030] In one possible implementation, the three-dimensional porous structure is a continuous structure with multiple pores formed on its surface.

[0031] In one possible implementation, the three-dimensional porous structure has multiple blades that are connected together in a stacked or horizontally arranged manner to form a continuous structure, and the gaps between the multiple blades form multiple pores in the three-dimensional porous structure.

[0032] This application embodiment, by setting the conductive structure in the through hole as a three-dimensional porous structure filled with metal, can alleviate the problem of thermal expansion coefficient mismatch between the metal in the through hole and the surrounding molding material, thereby avoiding warping around the through hole and thus avoiding circuit board deformation and other problems, thereby improving the reliability of electronic devices.

[0033] Fourthly, embodiments of this application provide a method for fabricating a chip packaging structure. The method includes: providing a chip, forming a redistribution structure on the chip, the redistribution structure including a first dielectric layer, embedding a plurality of three-dimensional porous structures in the first dielectric layer, each of the plurality of three-dimensional porous structures having pores filled with metal, the three-dimensional porous structures being conductive, and the coefficient of thermal expansion of the three-dimensional porous structures being less than the coefficient of thermal expansion of the metal; wherein, the lead-out end of the first chip extends from the first surface of the redistribution structure to the second surface of the redistribution structure through at least a portion of the plurality of three-dimensional porous structures, the second surface being disposed opposite to the first surface, and the first surface being in contact with the first chip.

[0034] In one possible implementation, the three-dimensional porous structure is a continuous structure with multiple pores formed on its surface.

[0035] In one possible implementation, the three-dimensional porous structure has multiple blades that are connected together in a stacked or horizontally arranged manner to form a continuous structure, and the gaps between the multiple blades form multiple pores in the three-dimensional porous structure.

[0036] In one possible implementation, forming a redistribution structure on a first chip includes: sequentially forming a first dielectric layer, a second dielectric layer, and a third dielectric layer on the first chip, wherein the second dielectric layer is disposed between the first dielectric layer and the third dielectric layer; the second dielectric layer has a plurality of vias, and the third dielectric layer has a plurality of conductive structures, the vias being used to connect the plurality of three-dimensional porous structures and the plurality of conductive structures; and the leads of the first chip are led out from the first surface of the redistribution structure to the second surface of the redistribution structure through at least a portion of the three-dimensional porous structures in the first dielectric layer, at least a portion of the vias in the second dielectric layer, and at least a portion of the conductive structures in the third dielectric layer.

[0037] In one possible implementation, each of the multiple conductive structures comprises a three-dimensional porous structure.

[0038] In one possible implementation, the conductive structure in each of the multiple vias is a three-dimensional porous structure.

[0039] In one possible implementation, the material of the three-dimensional porous structure is a carbon-based derivative.

[0040] Fifthly, embodiments of this application provide a method for fabricating a chip, the method comprising: providing a substrate; forming a plurality of semiconductor devices on the substrate to form a semiconductor structure; forming a redistribution structure on the semiconductor structure, the redistribution structure including a dielectric layer, a plurality of three-dimensional porous structures embedded in the dielectric layer, each of the plurality of three-dimensional porous structures having pores filled with metal, the three-dimensional porous structures being conductive and having a coefficient of thermal expansion of less than that of the metal; and interconnecting the plurality of semiconductor devices through a plurality of conductive structures.

[0041] In one possible implementation, the three-dimensional porous structure is a continuous structure with multiple pores formed on its surface.

[0042] In one possible implementation, the three-dimensional porous structure has multiple blades that are connected together in a stacked or horizontally arranged manner to form a continuous structure, and the gaps between the multiple blades form multiple pores in the three-dimensional porous structure.

[0043] It should be understood that the third and fourth aspects of this application are consistent with the technical solutions of the first aspect of this application, and the fifth aspect of this application is consistent with the technical solutions of the second aspect of this application. The beneficial effects obtained by each aspect and the corresponding feasible implementation are similar, and will not be described again. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0045] Figure 2 This is a schematic diagram of a three-dimensional porous structure provided in an embodiment of this application;

[0046] Figure 3 This is yet another schematic diagram of the chip packaging structure provided in the embodiments of this application;

[0047] Figure 4 This is yet another schematic diagram of the chip packaging structure provided in the embodiments of this application;

[0048] Figure 5 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0049] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0050] Figure 7 The embodiments provided in this application are as follows Figure 1 The flowchart shown is a method for fabricating the chip packaging structure.

[0051] Figures 8A-8J Is it like this? Figure 1 The diagram shows the various structures involved in the fabrication process of the chip packaging structure. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this application.

[0053] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0054] The terms "first" and "second," etc., in the specification and drawings of the embodiments of this application are used to distinguish different objects or to distinguish different treatments of the same object, rather than to describe a specific order of objects.

[0055] Furthermore, the terms "comprising" and "having," and any variations thereof, used in the description of the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0056] It should be noted that in the description of the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0057] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0058] The chip packaging structure provided in this application can be of various types, including but not limited to: fan-out packaging structure, fan-in packaging structure, packaging structure formed based on damask / bi-damask process, 2.5D packaging structure, 3D packaging structure, etc. Furthermore, the chip packaging structure provided in this application can be a single-chip package or a multi-chip package. When multiple chips are packaged in the chip packaging structure, the chip packaging structure can be a system-in-package (SIP), that is, multiple chips can be packaged in the same package. In specific implementations, the aforementioned fan-out packaging structure can also be, for example, a fan-out-package-on-package (FO-PoP) packaging structure, that is, some chips are stacked on top of other chips. The chip described in this application can be a bare die, or a chip formed by simple packaging of a bare die with other chips or components (active or passive devices, etc.), or a chip packaging structure formed after packaging; no limitation is made here. The following describes... Figures 1-5 The embodiments shown illustrate the chip packaging structure described in this application.

[0059] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application. For example... Figure 1 The chip package structure 100 shown includes along Figure 1 The chip 10 and redistribution structure 20 are stacked in the x-direction shown. Figure 1 In the indicated direction x, chip 10 includes opposing surfaces D1 and D2, and redistribution structure 20 includes opposing surfaces S1 and S2. Surface D2 of chip 10 contacts surface S1 of redistribution structure 20. Chip 10 can bring out more input / output pins through redistribution structure 20, and can be soldered onto a circuit board through redistribution structure 20 to connect with other components, common power supplies, and common grounds on the circuit board. In one possible implementation, a plurality of leads 11 are formed on surface D2 of chip 10, and the plurality of leads 11 on chip 10 contacts redistribution structure 20. The leads 11 on surface D2 of chip 10 can be one of pads, micro-bumps, and copper pillars.

[0060] The rerouting structure 20 may include at least one routing layer. For example, the rerouting structure 20 may include three, four, or more routing layers. Figure 1 The diagram schematically illustrates two wiring layers. In this embodiment, the rewiring structure 20 includes two wiring layers as an example, but this is not intended to limit the scope of the solution. Figure 1As shown, the redistribution structure 20 includes a dielectric layer 21, a dielectric layer 22, and a dielectric layer 23. Dielectric layers 21 and 23 are wiring layers, each containing a conductive structure. Dielectric layer 22 is a via layer, containing vias. Specifically, dielectric layer 21 is disposed in the redistribution structure 20 on the side away from the surface D2 of the chip 10; dielectric layer 23 is disposed in the redistribution structure 20 on the side close to the surface D2 of the chip 10, and is in contact with the surface D2 of the chip 10. Dielectric layer 22 is disposed between dielectric layers 21 and 23. Multiple conductive structures 211 are disposed in dielectric layer 21, embedded within it and isolated from each other by the dielectric layer 21. Multiple conductive structures 213 are disposed in dielectric layer 23, embedded within it and isolated from each other by the dielectric layer 23. The dielectric layer 22 has multiple vias 212, each of which contains a conductive structure. Multiple conductive structures 213 in the dielectric layer 23 communicate with the multiple vias 212 in the dielectric layer 22. Multiple conductive structures 211 in the dielectric layer 21 communicate with the multiple vias 212 in the dielectric layer 22. Thus, the multiple vias 212 connect the multiple conductive structures 211 in the dielectric layer 21 to the multiple conductive structures 213 in the dielectric layer 23. In one possible implementation, the dielectric layers 21, 22, and 23 can be made of the same material.

[0061] The dielectric layer 21 can be an insulating layer formed of one or more materials. The materials of the dielectric layer 21 may include, but are not limited to, silicon dioxide (SiO2), silicon oxynitride (SiNO), silicon nitride (SiN), and silicon carbide (SiCN). Each conductive structure 211 can be a three-dimensional porous structure, and a specific structural diagram of this three-dimensional porous structure is shown below. Figure 2 As shown. From Figure 2 As shown in the diagram, the three-dimensional porous structure is an irregular and continuous structure with multiple pores formed on its surface. In one possible implementation, the three-dimensional porous structure has multiple blades connected in a stacked or horizontally arranged manner to form a continuous structure, with the gaps between the blades forming the multiple pores. In another possible implementation, the three-dimensional porous structure may also have multiple supports, all directly connected to form a continuous structure, with the gaps between the supports forming the multiple pores. Figure 2The diagram schematically illustrates a three-dimensional porous structure comprising multiple continuous blades, with multiple openings between these blades. These openings are open openings, meaning they are exposed on the outer surface of the three-dimensional porous structure and extend into its interior. In other possible implementations, the three-dimensional porous structure can also be a regular architecture, such as, but not limited to, cuboid, cubic, cylindrical, and conical structures. This application does not impose specific limitations on these embodiments. Figure 2 The pores of the illustrated three-dimensional porous structure are filled with metal. The material of the three-dimensional porous structure is electrically conductive, and the coefficient of thermal expansion (CTE) of the three-dimensional porous structure is less than that of the metal filling it. In one possible implementation, the material of the three-dimensional porous structure can be a carbon-based derivative, such as, but not limited to, graphene, carbon nanotubes, or mixtures thereof. The metal filling the three-dimensional porous structure can be, for example, Cu, aluminum (Al), cobalt (Co), nickel (Ni), or mixtures thereof.

[0062] In existing technologies, the conductive structure in each layer of a redistribution structure is a metal (e.g., Cu, Al, Ni, or Co). The coefficient of thermal expansion of the metal is much higher than that of the surrounding dielectric layers (e.g., SiNO, SiN, or SiCN), resulting in a coefficient of thermal expansion mismatch (CTE). The stress accumulated in the materials of each layer within the redistribution structure due to the CTE cannot be released, leading to warpage. Warpage deformation can cause problems such as linecracks, solder deformation formation, and poor soldering / misalignment, and these issues become increasingly severe with increases in interconnect density, number of RDL layers, and structural size.

[0063] In the chip packaging structure provided in this application embodiment, since the thermal expansion coefficient of the three-dimensional porous structure is smaller than that of metals, for example, the thermal expansion coefficient of copper is 16ppm, and the thermal expansion coefficient of graphene is negative (-7ppm) in the temperature range of 100K to 1000K, and the three-dimensional porous structure is soft and deformable, the conductive structure in each conductive layer of the redistribution structure 20 is set as a three-dimensional porous structure filled with metal. The three-dimensional porous structure can buffer the stress generated by the expansion of metal. Macroscopically, this results in a reduction in the overall equivalent thermal expansion coefficient of the conductive structure, reducing the problem of thermal expansion coefficient mismatch between the materials of each layer. This can reduce the warpage of the redistribution structure 20, which is beneficial to alleviating the above-mentioned problems such as line cracks, solder deformation, poor soldering / misalignment, etc., and thus improving chip reliability.

[0064] In one possible implementation of the embodiments of this application, Figure 1 The conductive structure 213 shown can be a metallic structure; it can also be a three-dimensional porous structure / metal composite wire structure, i.e., the same structure as the conductive structure 211. Preferably, the conductive structure 213 is the same as the conductive structure 211. Figure 1 The diagram schematically illustrates a case where conductive structure 213 has the same structure as conductive structure 211. The specific structure of conductive structure 213 and its beneficial effects are described in the relevant description of conductive structure 211, and will not be repeated here.

[0065] In one possible implementation of the embodiments of this application, Figure 1 The conductive structure filling the through-hole 212 can be a metallic structure; or it can be a three-dimensional porous structure / metal composite wire structure, i.e., the same structure as the conductive structure 211. Preferably, the conductive structure filling the through-hole 212 is the same as the conductive structure 211. Figure 1 The diagram schematically illustrates a case where the through-hole 212 has the same structure as the conductive structure 211. The specific structure of the conductive structure filling the through-hole 212 and the beneficial effects it achieves are described in the relevant description of the conductive structure 211, and will not be repeated here.

[0066] In one possible implementation of this application, a conductive thin film can be disposed between each of the above-mentioned conductive structures and the surrounding dielectric layer. The material of the conductive thin film can be a metal, including but not limited to: titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or copper (Cu). For example, a conductive thin film is disposed between conductive structure 211 and dielectric layer 21, between conductive structure 213 and dielectric layer 23, and between the conductive structure filled in through-hole 212 and dielectric layer 22. The conductive thin film can serve as a conductive medium, allowing the metal in the conductive thin film to fill the three-dimensional porous structure during the generation process.

[0067] In one possible implementation of this application embodiment, at least one dielectric layer in the redistribution structure 20 may include a multilayer stacked structure. Taking dielectric layer 21 as an example, dielectric layer 21 may include a dielectric layer and a passivation layer, and the passivation layer may also be called an etch stop layer. The material of the dielectric layer may include, but is not limited to, SiO2, SiNO, SiN, or SiCN as described above; the material of the passivation layer may include, but is not limited to, SiN, SiO2, and SiCN. The passivation layer may be a thin film, disposed between the dielectric layer 22 and the dielectric layer in dielectric layer 21. By providing the passivation layer, when etching the dielectric layer, the metal structure and conductive lines of each layer can be avoided, and oxidation of each metal structure can be suppressed.

[0068] Continue to refer to Figure 1 ,from Figure 1 As can be seen, the multiple leads 11 of chip 10 are respectively in contact with the multiple conductive structures 213 in the dielectric layer 23 of the redistribution structure 20. Within the redistribution structure 20, the multiple conductive structures 213 in the dielectric layer 23 are respectively in contact with the multiple vias 212 in the dielectric layer 22; furthermore, the multiple conductive structures 211 in the dielectric layer 21 are respectively in contact with the multiple vias 212 in the dielectric layer 22. Thus, each lead 11 of chip 10 is led out from the surface S1 near the redistribution structure 20 to the surface S2 of the redistribution structure 20 through the contacting conductive structures 213, vias 212, and conductive structures 211. Furthermore, as... Figure 1 In the chip package structure 100 shown, the redistribution structure 20, projected onto the chip 10, completely covers the chip 10. The size of the redistribution structure 20 is larger than the size of the chip 10; that is to say, as shown... Figure 1 The chip package structure 100 shown is a fan-out package structure. Therefore, Figure 1 In the chip package structure 100 shown, I / O pin routing can be designed in areas outside the chip 10 dimensions, increasing the number of I / O contacts. It is understandable that if there are high requirements for layout area and low requirements for the number of I / O contacts, routing can be implemented in these areas. Figure 1 Based on the chip package structure 100 shown, the size of the redistribution structure 20 is reduced, so that the orthogonal projection of the redistribution structure 20 onto the chip 10 coincides with or is located within the chip 10, thus a fan-in package structure can be adopted.

[0069] It is understood that the chip package structure 100 may also include more structures, such as multiple solder pads and molding compound 12. Multiple solder pads may be, for example, solder pads or microbumps. In this embodiment, the solder pads on the chip package structure are described as microbumps, but this is not intended to limit the solution. Multiple microbumps 30 are disposed in the redistribution structure 20 on the surface S2 away from the chip 10. These multiple microbumps 30 may be, for example, solder balls, such as... Figure 1 As shown, microbumps 30 are disposed on conductive structures 211 in the dielectric layer 21. One or more microbumps 30 may be disposed on a conductive structure 211. Figure 1The diagram schematically illustrates a conductive structure 211 with a microbump 30. Thus, the leads of chip 10 are connected to multiple microbumps 30 via a redistribution structure 20, and the I / O terminals of chip 10 are led to the multiple microbumps 30. The multiple microbumps 30 are used to solder the chip package structure 100 to a circuit board, thereby enabling chip 10 to interconnect with power terminals, ground terminals, and other chips or components on the circuit board via the redistribution structure 20 and the multiple microbumps 30. A molding compound 12 is disposed on the redistribution structure 20 to encapsulate chip 10 and protect it. Additionally, in other possible implementations, the chip package structure 10 may also include a heat sink disposed on the surface D1 of chip 10 to dissipate heat from chip 10.

[0070] above Figure 1 The illustration schematically shows a chip package structure 100 that packages one chip. The chip package structure provided in this application embodiment can package more chips, such as two chips, three chips, etc. Please refer to... Figure 3 , Figure 3 This is a schematic diagram of a chip packaging structure 200 provided in an embodiment of this application. Figure 1 The chip packaging structure 100 shown is different from the one shown. Figure 3 The chip package structure 200 shown contains two chips, chip 101 and chip 102. Chips 101 and 102 are arranged on the same layer, that is, chips 101 and 102 are arranged along the same layer. Figure 3 The y-direction horizontal interval is shown. Figure 3 The chip package structure 200 shown includes a redistribution structure 20. Among them, Figure 3 The redistribution structure 20 shown may also include multiple dielectric layers. Figure 3 The diagram schematically shows the three dielectric layers 21, 22 and 23. Figure 3 The redistribution structure 20 shown includes various dielectric layers, conductive structures within those layers, and vias. Figure 1 The rewiring structure 20 shown is similar, that is to say, Figure 3 The conductive structures 211 in dielectric layer 21, 213 in dielectric layer 23, and 212 in the via of dielectric layer 22 shown can all be three-dimensional porous structures filled with metal. These three-dimensional porous structures are as follows: Figure 2 As shown. Additionally... Figure 3 The specific structure of the redistribution structure 20 shown, the connection relationships between the structures, the materials of each structure, and the beneficial effects it brings are all related to... Figure 1 The rewiring structure shown in Figure 20 is the same as or similar to the one shown in Figure 20. Please refer to the following for details. Figure 1 The relevant descriptions will not be repeated here.

[0071] Multiple leads 111 of chip 101 can make corresponding contact with multiple conductive structures 213 in the dielectric layer 23 of the redistribution structure 20; similarly, multiple leads 112 of chip 102 can also make corresponding contact with multiple conductive structures 213 in the dielectric layer 23 of the redistribution structure 20. Within the redistribution structure 20, multiple conductive structures 213 in the dielectric layer 23 make corresponding contact with multiple vias 212 in the dielectric layer 22; furthermore, multiple conductive structures 211 in the dielectric layer 21 make corresponding contact with multiple vias 212 in the dielectric layer 22. Therefore, each lead-out terminal 111 of chip 101 is led out from the surface S1 near the redistribution structure 20 to the surface S2 of the redistribution structure 20 through the contacting conductive structure 213, through-hole 212, and conductive structure 211, and is connected to a plurality of micro-bumps 30 provided on the surface S2 of the redistribution structure 20; each lead-out terminal 112 of chip 102 is led out from the surface S1 near the redistribution structure 20 to the surface S2 of the redistribution structure 20 through the contacting conductive structure 213, through-hole 212, and conductive structure 211, and is connected to a plurality of micro-bumps 30 provided on the surface S2 of the redistribution structure 20. In addition, the lead-out terminals 111 of chip 101 are also connected to the lead-out terminals 112 of chip 102 through the redistribution structure 20, thereby realizing the interconnection between chip 101 and chip 102. Figure 3 As shown, one of the leads 111 of chip 101 is connected to the conductive structure 211 in dielectric layer 21 through the conductive structure 213 and via 212 of redistribution structure 20; similarly, one of the leads 112 of chip 102 is connected to the conductive structure 211 in dielectric layer 21 through the conductive structure 213 and via 212 of redistribution structure 20. That is to say, both the lead 111 of chip 101 and the lead 112 of chip 102 are connected to the conductive structure 213, thereby achieving interconnection between chip 101 and chip 102 through the conductive structure 213.

[0072] Figure 3 The illustration schematically shows two chips disposed in a chip package structure 200, with the two chips arranged on the same layer. The chip package structure shown in this embodiment can also be a 2.5D package structure or a 3D package structure. The following uses a 2.5D package structure as an example, combined with... Figure 4 The chip package structure 300 shown is described below. Figure 4 The chip package structure 300 shown may include multiple chips, some of which are arranged along... Figure 4 The x-axis stacking settings are shown. Figure 4The diagram schematically illustrates three chips, 103, 102, and 101, stacked along the x-direction. Chip 103 is disposed on the redistribution structure 20, chip 102 is stacked on top of chip 103, and chip 101 is stacked on top of chip 102. It is understood that... Figure 4 The number of chip stacks shown is illustrative and should be set according to the needs of a real-world scenario. Along Figure 4 In the horizontal direction y shown, chips 104 are arranged at horizontal intervals from the stacked chips described above. That is to say, chips 104 are disposed on top of and in contact with the redistribution structure 20.

[0073] Figure 4 In the chip package structure 300 shown, among the multiple chips stacked along the x-direction, except for chip 101 which is away from the redistribution structure 20, each chip has a conductive post 13 that penetrates the upper and lower surfaces of the chip. Furthermore, along the x-direction, the lower surface of each chip has multiple microbumps 14. It is understood that in other possible implementations, the microbumps 14 can also be pads. The conductive posts 13 on the chip contact the microbumps 14 of the upper-layer chip and the microbumps 14 of the chip itself, respectively, to connect the upper-layer chip and the chip. Taking chip 102 as an example, chip 102 has multiple mutually isolated conductive posts 13 that penetrate the upper and lower surfaces of chip 102; the lower surface of chip 101 has multiple microbumps 14, and chip 101 is mounted on chip 102 through these microbumps 14. Furthermore, the lower surface of chip 102 is provided with multiple microbumps 14, and multiple conductive pillars 13 on chip 102 are connected to the microbumps on the lower surface of chip 101 and the microbumps 14 on the lower surface of chip 102, realizing the interconnection between chip 101 and chip 102. Based on the same structure and principle, chip 103 is interconnected with chip 102, thereby realizing the interconnection between chip 101, chip 102 and chip 103. In one possible implementation, the conductive pillars 13 in chip 102 and chip 103 can be copper pillars or three-dimensional porous structures filled with metal, such as... Figure 2 As shown. Preferably, the conductive pillars 13 in chips 102 and 103 are three-dimensional porous structures filled with metal. The specific structure and material of the three-dimensional porous structure are consistent with... Figure 1 The three-dimensional porous structure shown is the same as that described above, referencing Figure 1The relevant descriptions in the text will not be repeated here. By setting the conductive pillars 13 in chips 102 and 103 as a three-dimensional porous structure filled with metal, the stress generated by the expansion of the metal in chips 102 and 103 can be buffered. Macroscopically, this results in a reduction in the overall equivalent coefficient of thermal expansion of the chip, reducing the problem of mismatch in the coefficients of thermal expansion of the materials in each layer. This can reduce chip warpage and help alleviate the aforementioned problems such as circuit cracks, solder deformation, poor soldering / misalignment, etc., thereby improving chip reliability.

[0074] In addition, such as Figure 4 In the chip package structure 300 shown, among the stacked chips, the bottommost chip 103 is disposed on the redistribution structure 20 via multiple microbumps 14 and contacts the surface S1 of the redistribution structure 20; chip 104 is disposed on the redistribution structure 20 via multiple microbumps 14 and contacts the surface S1 of the redistribution structure 20. Furthermore, the surface S2 of the redistribution structure 20 is also provided with multiple microbumps 30. Figure 4 The redistribution structure 20 shown includes a via 241 penetrating the dielectric layer 24 and a multilayer wiring structure 242. A conductive post is disposed within the via 241. In one possible implementation, the conductive post in the via 241 can also be a three-dimensional porous structure filled with metal, such as... Figure 2 As shown. The specific structure, materials, and beneficial effects of the three-dimensional porous structure are detailed in the reference [reference needed]. Figure 1 The relevant descriptions in the diagram will not be repeated here. Multiple vias 241 are isolated from each other. The vias 241 connect the microbumps 14 on surface S1 of the redistribution structure 20 to the microbumps 30 on surface S2 of the redistribution structure 20. The vias 241 located in the region where stacked chips are disposed lead from one side of surface S1 of the redistribution structure 20 to one side of surface S2 of the redistribution structure 20, connecting to the microbumps 30 on surface S2; the vias 241 located in the region where chip 104 is disposed lead from one side of surface S1 of the redistribution structure 20 to one side of surface S2 of the redistribution structure 20, connecting to the microbumps 30 on surface S2. Additionally, conductive structures 242 inside the redistribution structure 20 are used to connect the multiple stacked chips to chip 104. Three conductive structures 242 are schematically shown in the figure, and these three conductive structures 242 are located in different layers. Understandable, Figure 4 The chip package structure 300 shown may include more or fewer conductive structures 242; this application does not impose specific limitations. Each conductive structure 242 may be a three-dimensional porous structure filled with metal, such as... Figure 2As shown. The specific structure, materials, and beneficial effects of the three-dimensional porous structure are detailed in the reference [reference needed]. Figure 1 The relevant descriptions in [the document] will not be repeated here. For example... Figure 4 As shown, each conductive structure 242 is embedded in the dielectric layer 24 and extends from the stacked chip side to the chip 104 side; wherein, on the stacked chip side, the conductive structure 242 is connected to multiple stacked chips through microbumps 14, and on the chip 104 side, the conductive structure 242 is connected to the chip 104 through microbumps 14, thereby achieving chip interconnection between multiple stacked chips and chip 104.

[0075] The above embodiments schematically illustrate chip packaging structures with various possible implementations. In each chip packaging structure, at least one of the conductive structure and via of the redistribution structure 20 employs a three-dimensional porous structure filled with metal. Furthermore, a 2.5D package is also shown where the conductive pillars inside the chip employ a three-dimensional porous structure filled with metal. In one possible implementation of this application, the metal-filled three-dimensional porous structure provided in this application can also be used in the wafer fabrication process, such as in the chip interconnection of the back-end of line (BEOL) process. Please refer to... Figure 5 , Figure 5 This is a schematic diagram of the chip provided in an embodiment of this application. For example... Figure 5 As shown, chip 400 includes semiconductor structure 40 and redistribution layer 50. Semiconductor structure 40 may integrate multiple semiconductor devices, which may include, but are not limited to, transistors, resistors or capacitors. Figure 5 The diagram schematically illustrates the configuration of transistors 41 and 42 in semiconductor structure 40. It is understood that, depending on the needs of the actual scenario, semiconductor structure 40 may include more semiconductor devices.

[0076] The transistors 41 and 42 disposed in the semiconductor structure 40 can be formed in a silicon substrate using standard front-end of line (FEOL) processes and materials during wafer fabrication. These standard processes include, but are not limited to, epitaxial growth, oxidation, deposition, doping, ion implantation, and planarization, and are not specifically limited in this embodiment. The transistors 41 and 42 disposed in the semiconductor structure 40 do not have leads. The electrodes of transistors 41 and 42 in the semiconductor structure 40 are interconnected according to requirements through a redistribution structure 50 to form an integrated circuit with a specific function. Furthermore, the redistribution structure 50 can also lead the electrodes of transistors 41 and 42 to a side of the redistribution structure 50 away from the semiconductor structure 40, thereby enabling subsequent chip 400 packaging and other processes.

[0077] like Figure 5 In the chip 400 shown, transistors 41 and 42 can be formed in a silicon substrate, so that the electrodes in transistors 41 and 42 can be connected to the redistribution structure 40 through through-silicon vias (TSVs) 43. In this embodiment, the TSV 43 can be filled with a conductive structure, such as a copper pillar. In one possible implementation, the conductive structure in the TSV 43 can be a three-dimensional porous structure filled with metal, such as... Figure 2 As shown. That is to say, the source 411, drain 412, and gate 413 in transistor 41 can be connected to the redistribution structure 50 through a three-dimensional porous structure filled with metal, respectively; the source 421, drain 422, and gate 423 in transistor 42 can be connected to the redistribution structure 50 through a three-dimensional porous structure filled with metal, respectively. In this embodiment, by setting the conductive structure of the through-silicon via 43 in the semiconductor structure 40 as a three-dimensional porous structure filled with metal, the problem of thermal expansion coefficient mismatch between the metal in the through-silicon via and the surrounding silicon material can be alleviated, thereby avoiding warping around the through-silicon via and thus avoiding problems such as deformation of the through-silicon via, thereby improving the reliability of the chip.

[0078] like Figure 5 In the chip 400 shown, the redistribution structure 50 can be formed using a damascene process or a double damascene process. The redistribution structure 50 can include multiple wiring layers and multiple via layers. The figure schematically shows wiring layers 51 and 53, and via layer 52. The redistribution structure 50 in chip 400 can be connected to… Figure 1The redistribution structure 20 in the chip package structure 100 shown has a similar structure and process. For a detailed description of the redistribution structure 50, please refer to... Figure 1 The description of the redistribution structure 20 will not be repeated here. That is to say, the interconnect layer of chip 400 can be implemented through the redistribution structure 50; at least one of the conductive structure 511, conductive structure 531, and via 521 in the redistribution structure 50 can be a three-dimensional porous structure filled with metal, such as... Figure 2 As shown, a detailed description of the three-dimensional porous structure can be found in the reference section. Figure 1 The relevant description is as follows. By configuring at least one of the conductive structures 511, 531, and vias 521 in the redistribution structure 50 of chip 400 as a three-dimensional porous structure filled with metal, the problem of thermal expansion coefficient mismatch between the metal in the redistribution structure 50 and the surrounding insulating material can be alleviated, thereby avoiding warping and deformation of the redistribution structure 50, and thus improving the reliability of the chip. In addition, microbumps 60 are provided on the surface of the redistribution structure 50 away from the semiconductor structure 40. Transistors 41 and 42 in the semiconductor structure 40 are connected to the microbumps 60 through silicon vias 43, conductive structures 511, vias 521, and conductive structures 531 in the redistribution structure 50 to bring out the electrodes of transistors 41 and 42.

[0079] In one possible implementation of this application embodiment, chip 400 can be configured as follows: Figure 1 , Figure 3 or Figure 4 The chip is packaged using the shown chip packaging structure; that is to say, chip 400 can be... Figure 1 The chip 10 shown can also be Figure 3 The chip 101 or chip 102 shown can also be Figure 4 Any one of the chips 101, 102, 103 or 104 shown.

[0080] Based on any of the above embodiments, this application also provides an electronic device, which may include, for example: Figure 1 , Figure 3 or Figure 4 The illustrated chip package structure, in addition to the electronic device itself, also includes a circuit board, which may be, for example, a printed circuit board (PCB). The electronic device includes... Figure 3 The chip package structure 200 shown is used as an example for description. The structure of the electronic device 500 is as follows: Figure 6 As shown, Figure 5This is a schematic diagram of the structure of an electronic device 500 provided in an embodiment of this application. The PCB 70 may include surfaces P1 and P2 disposed opposite to each other. The chip package structure 200 is disposed on surface P1 of the PCB 70 via a plurality of microbumps 30. The PCB 70 may be a single-layer board or a multi-layer board, and each layer may have patterned conductive lines. The plurality of microbumps 30 of the chip package structure 200 are connected to the patterned conductive lines on the PCB 70 for interconnection with power lines, ground lines, or other components on the PCB 70.

[0081] In some possible implementations, power lines, ground lines, or other conductive lines are disposed on surface S2 of PCB 70. In one possible implementation, PCB 70 may include multiple through-holes 71 penetrating the upper and lower surfaces of the PCB. When the material of PCB 70 is plastic, the through-holes 71 may also be called plastic-encapsulated through-holes. Thus, the through-holes 71 in PCB 70 can lead at least some of the leads of the chip 101 or chip 102 packaged in the chip package structure 200 from surface P1 of PCB 70 to surface P2 of PCB 70, thereby achieving communication with power supply, common ground, and at least one of other chips. Specifically, surface P2 of PCB 70 is provided with multiple solder balls 80, which may be, for example, solder balls. The through-holes 71 can be connected to the microbumps 30 and the solder balls 80 respectively.

[0082] In one possible implementation, the conductive structure in the through-hole 71 can be a three-dimensional porous structure filled with metal, such as... Figure 2 As shown. The specific structure and materials of the three-dimensional porous structure are described. Figure 1 The three-dimensional porous structure shown is similar; please refer to the relevant description for details, which will not be repeated here. In this embodiment, by setting the conductive structure in the through-hole 71 as a three-dimensional porous structure filled with metal, the problem of thermal expansion coefficient mismatch between the metal in the through-hole 71 and the surrounding molding compound can be alleviated. This avoids warping around the through-hole 71, thereby preventing circuit board deformation and other problems, and thus improving the reliability of the electronic device 500.

[0083] The electronic device 500 provided in this application includes the chip packaging structure described in any of the above embodiments. The chip packaged in any of the above chip packaging structures may include, but is not limited to, chips such as: System on Chip (SoC), memory, discrete devices, application processors (APs), micro-electro-mechanical systems (MEMS), microwave radio frequency chips, and application-specific integrated circuits (ASICs). In specific applications, the aforementioned application processors or ASICs may be central processing units (CPUs), graphics processing units (GPUs), artificial intelligence processors, such as network processing units (NPUs). The memory may be cache memory, random access memory (RAM), read-only memory (ROM), or other types of memory. Discrete devices may include, but are not limited to, field-effect transistors (FETs) and bipolar transistors (BJTs). Furthermore, Figure 5 The chip 400 shown can also be any of the above-mentioned types of chips. For example, when using... Figure 3 When the chip package structure 200 is shown, the chip 101 and chip 102 packaged in the chip package structure 200 can be an application processing chip and a discrete device, respectively; for example, when using Figure 4 When the chip package structure 300 is shown, the chips 101 to 103 packaged in the chip package structure 300 can be memory; chip 104 can be an application processing chip. The electronic device 500 can also be an integrated circuit product, wherein the integrated circuit product may include other integrated circuits in addition to the chip package structure described in the embodiments of this application, so that the chip package structure shown in the embodiments of this application can cooperate with other integrated circuits to realize various circuit functions.

[0084] The chip packaging structures described in the above embodiments can be fabricated using various packaging processes, including but not limited to: chip-first forward packaging, chip-later forward packaging, chip-first flip-chip packaging, or chip-later flip-chip packaging. The following example uses the chip-first flip-chip packaging process to illustrate the resulting chip packaging structure. Figure 1 As shown in the figure, combined with Figure 7 The process shown in step 700, and Figures 8A to 8JThe structures shown in the fabrication process are described in detail, illustrating the fabrication process flow of the chip packaging structure. This process flow 700 includes the following steps:

[0085] Step 701: Form a molding compound 12 on the chip 10.

[0086] In this step, a temporary carrier board can be provided first, and the chip 10 can be mounted on the temporary carrier board a1 using temporary bonding adhesive. Then, a molding compound 12 is formed on the chip 10 and the temporary carrier board a1, encapsulating the chip 10. Finally, the carrier board a1 is removed. This step is followed by... Figure 8A As shown.

[0087] Step 702: Deposit dielectric material on chip 10 to form dielectric layer 23.

[0088] In this step, a dielectric material can be deposited using methods such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition. This dielectric material can include, but is not limited to, SiO2, SiNO, SiN, and SiCN. The dielectric material has insulating properties. Following this step... Figure 8B As shown.

[0089] Step 703: A plurality of grooves a2 are formed on the dielectric layer 23.

[0090] In this step, photoresist is first coated on the dielectric layer 23, followed by exposure and development processes to obtain an etching mask layer on the dielectric layer 23. Then, the dielectric material is etched using plasma, ion beam, or other methods to obtain the groove a2. Finally, the photoresist is removed using wet dissolution or dry etching. During this process, the dielectric layer 23 is etched through, exposing the leads 11 of the chip 10. This step is as follows... Figure 8C As shown.

[0091] Step 704: A seed layer a3 is formed on the walls and bottom of the multiple grooves a2.

[0092] In this step, methods such as PVD and ALD can be used to deposit a seed layer. The material of this seed layer can be, but is not limited to, Ti, Ta, TiN, TaN, Cu, etc. This seed layer a3 is used as the conductive medium for subsequent electroplating. This step is as follows... Figure 8D As shown.

[0093] Step 705: A three-dimensional porous structure filled with metal is formed in multiple grooves a2.

[0094] This step may further include the following steps: Step 1, preparing a suspension. The suspension can be prepared based on the material used in the three-dimensional porous structure. This application uses graphene as an example. Specifically, graphite can be first oxidized and exfoliated with a strong acid; then, graphene can be obtained by low-temperature reduction; next, graphene particles can be obtained by freeze-drying; finally, the graphene particles can be dispersed using a deionized water solvent to obtain a suspension. Step 2, applying the prepared suspension to groove a2. Step 3, rapidly freezing the structure formed in Step 2 to solidify the suspension. The rapid freezing temperature can be below -20°C; furthermore, excessive suspension should be avoided in groove a2, as excessive suspension will expand during rapid freezing and may easily break the dielectric layer 23. Step 4, performing low-temperature vacuum evaporation on the structure formed in Step 3. The vacuum environment is less than 100 Pa and the temperature is below 0°C, thus preventing the solid formed in Step 3 from melting into a liquid. After completing steps one through four above, the following can be prepared: Figure 2 The three-dimensional porous structure shown refers to the fact that after the suspension in groove a2 is rapidly frozen into a solid, multiple pores can spontaneously form due to the inherent properties of the material. Step five involves using an electroplating process to gradually fill the pores of the three-dimensional porous structure, starting from the surface, with the metal from the seed layer a3 formed in step 704, thus forming a metal-filled three-dimensional porous structure. This metal-filled three-dimensional porous structure is... Figure 1 The conductive structure 213 is shown in the figure. The structure formed by this step is as follows: Figure 8E As shown.

[0095] Step 706: Remove the metal and three-dimensional porous structure from the surface of dielectric layer 23 to expose dielectric layer 23.

[0096] In this step, a chemical mechanical polishing process can be used to remove the metal and three-dimensional porous structure from the surface of the dielectric layer 23, thereby making the surface of the conductive structure 213 flush with the surface of the dielectric layer 23. The structure formed after this step is as follows: Figure 8F As shown.

[0097] Step 707: Dielectric layer 22 and dielectric layer 21 are sequentially formed on dielectric layer 23 and conductive structure 213. This step can employ a similar process to that used in step 702 to form dielectric layer 23, and will not be described in detail here. After this step, the resulting structure is as follows: Figure 8G As shown.

[0098] Step 708 involves etching dielectric layers 21 and 22 to form a through-hole 212 penetrating the upper and lower surfaces of dielectric layer 22, and a groove a3 penetrating the upper and lower surfaces of dielectric layer 21. The through-hole 212 and groove a3 can be fabricated using the same process, and are connected. This step can utilize a similar process to that used in step 703 for forming groove a2, and will not be described further. After etching, dielectric layers 21 and 22 expose the conductive structure 213. Following this step, the resulting structure is as follows: Figure 8H As shown.

[0099] Step 709 involves forming a conductive structure in the through-hole 212 and a conductive structure 213 in the groove a3. This step can employ a process similar to steps 704 to 706 to form the conductive structure in the through-hole 212 and the groove a3, which will not be described in detail here. The structure formed after this step is as follows: Figure 8J As shown.

[0100] Step 710: A plurality of microbumps are formed on the surface of the dielectric layer 221.

[0101] Therefore, through steps 701 to 710 above, the following can be prepared: Figure 1 The chip packaging structure 100 shown is shown.

[0102] In one possible implementation of this application embodiment, before step 707, a passivation layer may be deposited on the surface of the conductive structure 213 and the dielectric layer 23. This can be achieved using methods such as CVD, PVD, and ALD to deposit thin films of SiN, SiO2, or SiCN on the surface of the conductive structure 213 and the dielectric layer 23, thereby suppressing oxidation of the metal traces. Thus, the dielectric layer 22 and dielectric layer 21 are sequentially deposited on the passivation layer. In another possible implementation, in step 707, a passivation layer is disposed between the dielectric layer 22 and the dielectric layer 21, and a passivation layer is deposited on the dielectric layer 21. Therefore, when etching the dielectric layer 22 and dielectric layer 21 in step 708, it is also necessary to etch the passivation layer between the dielectric layer 23 and the dielectric layer 22, the passivation layer between the dielectric layer 22 and the dielectric layer 21, and the passivation layer on the dielectric layer 21.

[0103] In this embodiment of the application, it is based on Figure 1 The redistribution structure 20 in the chip package structure 100 shown has two conductive layers and a via layer as an example, and the fabrication process method is described accordingly. In other possible implementations, the redistribution structure 20 may include more conductive layers and via layers. When it is necessary to fabricate more conductive layers and via layers, the process steps shown in steps 702 to 709 above can be used for fabrication.

[0104] It is understood that, in the embodiments of this application, if it is necessary to prepare such... Figure 3 The chip packaging structure 200 shown can be formed simultaneously on chip 101 and chip 102 in step 701 above, with the remaining steps being the same as in process 700 above. If it is necessary to prepare... Figure 4 The chip packaging structure 300 shown can be constructed by first forming conductive pillars 13 on chips 102 and 103 using steps 704 to 705 described above, then forming 3D stacked chips 101 to 103 using standard processes, followed by forming a redistribution structure 20 on a temporary substrate using at least some of the steps 702 to 709 described above, and finally placing the 3D stacked chips 101 to 103 and chip 104 on the redistribution structure 20, thereby achieving interconnection between the chips. If it is necessary to fabricate a chip package structure 300 as described above... Figure 5 The chip shown can first form a semiconductor structure 40 by forming multiple devices on a silicon substrate using standard wafer front-end processes. Then, redistribution structures 50 are fabricated on the semiconductor structure 40 using the steps shown in steps 702 to 709 above, thereby realizing the interconnection between multiple devices.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A chip packaging structure, characterized in that, include: First chip; A redistribution structure is stacked with the first chip. The redistribution structure includes a first dielectric layer. A plurality of three-dimensional porous structures are embedded in the first dielectric layer. The pores of each of the plurality of three-dimensional porous structures are filled with metal. The three-dimensional porous structures are conductive and the coefficient of thermal expansion of the three-dimensional porous structures is less than the coefficient of thermal expansion of the metal. Wherein, the lead-out end of the first chip is led out from the first surface of the redistribution structure to the second surface of the redistribution structure through at least a portion of the three-dimensional porous structures among the plurality of three-dimensional porous structures, the second surface is disposed opposite to the first surface, and the first surface is in contact with the first chip.

2. The chip packaging structure according to claim 1, characterized in that, The three-dimensional porous structure is a continuous structure, and the surface of the continuous structure has multiple pores.

3. The chip packaging structure according to claim 2, characterized in that, The three-dimensional porous structure has multiple blades, which are connected together in a stacked or horizontally arranged manner to form the continuous structure. The gaps between the multiple blades form multiple holes in the three-dimensional porous structure.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that, The material of the three-dimensional porous structure is a carbon-based derivative.

5. The chip packaging structure according to any one of claims 1 to 4, characterized in that, The rewiring structure further includes a second dielectric layer and a third dielectric layer that are stacked sequentially on the first dielectric layer; The second dielectric layer has a plurality of through holes, and the third dielectric layer has a plurality of conductive structures. The plurality of through holes are used to connect the plurality of three-dimensional porous structures and the plurality of conductive structures. The lead-out terminals of the first chip are led out from the first surface of the redistribution structure to the second surface of the redistribution structure through at least a portion of the three-dimensional porous structure in the first dielectric layer, at least a portion of the through-hole in the second dielectric layer, and at least a portion of the conductive structure in the third dielectric layer. Wherein, each of the plurality of conductive structures is the three-dimensional porous structure; and / or Each of the plurality of through holes is provided with the three-dimensional porous structure.

6. The chip packaging structure according to claim 5, characterized in that, A conductive thin film is also disposed between the three-dimensional porous structure in the first dielectric layer and the first dielectric layer; When the conductive structure is the three-dimensional porous structure, a conductive thin film is further disposed between the conductive structure and the third dielectric layer; When the three-dimensional porous structure is provided in the through hole, a conductive thin film is also provided between the three-dimensional porous structure in the through hole and the hole wall.

7. The chip packaging structure according to any one of claims 1 to 6, characterized in that, The chip packaging structure further includes a second chip, which is stacked on top of the first chip; The second chip includes conductive pillars extending through its upper and lower surfaces, and the second chip is connected to the first chip via these conductive pillars; wherein, The conductive pillar is a three-dimensional porous structure.

8. The chip packaging structure according to any one of claims 2 to 7, characterized in that, The chip packaging structure also includes a third chip; The lead-out terminal of the third chip is led out from the first surface of the redistribution structure to the second surface of the redistribution structure through at least a portion of the three-dimensional porous structure in the first dielectric layer, at least a portion of the through-hole in the second dielectric layer, and at least a portion of the conductive structure in the third dielectric layer.

9. A chip, characterized in that, include: A semiconductor structure in which multiple semiconductor devices are formed; A redistribution structure stacked with the semiconductor structure includes a dielectric layer, in which a plurality of three-dimensional porous structures are embedded. The pores of the three-dimensional porous structures are filled with metal. The three-dimensional porous structures are conductive and their coefficient of thermal expansion is less than that of the metal. The plurality of semiconductor devices are interconnected through the plurality of three-dimensional porous structures.

10. The chip according to claim 9, characterized in that, The three-dimensional porous structure is a continuous structure, and the surface of the continuous structure has multiple pores.

11. The chip according to claim 10, characterized in that, The three-dimensional porous structure has multiple blades, which are connected together in a stacked or horizontally arranged manner to form the continuous structure. The gaps between the multiple blades form multiple holes in the three-dimensional porous structure.

12. The chip according to any one of claims 9 to 11, characterized in that, The semiconductor structure also includes multiple through-silicon vias (TSVs), through which the multiple semiconductor devices are connected to the redistribution structure; wherein... The conductive structure in each through-silicon via is the three-dimensional porous structure.

13. The chip according to any one of claims 9 to 12, characterized in that, The material of the three-dimensional porous structure is a carbon-based derivative.

14. The chip according to any one of claims 9 to 13, characterized in that, The plurality of semiconductor devices include at least one of the following: a transistor, a resistor, or a capacitor.

15. An electronic device, characterized in that, Includes a circuit board and a chip packaging structure as described in any one of claims 1 to 8; The chip packaging structure is disposed on the circuit board by a plurality of solders, the solders including one of the following: pads or microbumps.

16. The electronic device according to claim 15, characterized in that, The circuit board has through holes, and the conductive structure in the through holes is a three-dimensional porous structure. The pores of the three-dimensional porous structure are filled with metal. The three-dimensional porous structure is conductive, and the coefficient of thermal expansion of the three-dimensional porous structure is less than the coefficient of thermal expansion of the metal. The chip packaging structure is connected to the through holes on the circuit board via the plurality of solders to bring the leads of the packaged chip to the surface of the circuit board away from the chip packaging structure.

17. The electronic device according to claim 16, characterized in that, The three-dimensional porous structure is a continuous structure, and multiple holes are formed on the continuous structure.

18. The electronic device according to claim 17, characterized in that, The three-dimensional porous structure has multiple blades, which are connected together in a stacked or horizontally arranged manner to form the continuous structure. The gaps between the multiple blades form multiple holes in the three-dimensional porous structure.

19. A method for fabricating a chip packaging structure, characterized in that, include: Provide a chip; A redistribution structure is formed on the chip. The redistribution structure includes a first dielectric layer in which a plurality of three-dimensional porous structures are embedded. The pores of each of the plurality of three-dimensional porous structures are filled with metal. The three-dimensional porous structures are conductive and the coefficient of thermal expansion of the three-dimensional porous structures is less than that of the metal. Wherein, the lead-out end of the first chip is led out from the first surface of the redistribution structure to the second surface of the redistribution structure through at least a portion of the three-dimensional porous structures among the plurality of three-dimensional porous structures, the second surface is disposed opposite to the first surface, and the first surface is in contact with the first chip.

20. The method according to claim 19, characterized in that, Each of the three-dimensional porous structures is a continuous structure, and the surface of the continuous structure has multiple pores.

21. The method according to claim 20, characterized in that, The three-dimensional porous structure has multiple blades, which are connected together in a stacked or horizontally arranged manner to form the continuous structure. The gaps between the multiple blades form multiple holes in the three-dimensional porous structure.

22. The method according to any one of claims 19 to 21, characterized in that, The process of forming a redistribution structure on the first chip includes: A first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially formed on the first chip, wherein the second dielectric layer is disposed between the first dielectric layer and the third dielectric layer; The second dielectric layer has a plurality of through holes, and the third dielectric layer has a plurality of conductive structures. The plurality of through holes are used to connect the plurality of three-dimensional porous structures and the plurality of conductive structures. The lead-out terminals of the first chip are led out from the first surface of the redistribution structure to the second surface of the redistribution structure through at least a portion of the three-dimensional porous structure in the first dielectric layer, at least a portion of the through-holes in the second dielectric layer, and at least a portion of the conductive structure in the third dielectric layer; wherein, In the plurality of conductive structures, each conductive structure is the three-dimensional porous structure; and / or Each of the plurality of through holes is provided with the three-dimensional porous structure.

23. The method according to any one of claims 19 to 22, characterized in that, The material of the three-dimensional porous structure is a carbon-based derivative.

24. A method for fabricating a chip, characterized in that, include: Provide a substrate; The plurality of semiconductor devices are formed on the substrate to form a semiconductor structure; A redistribution structure is formed on the semiconductor structure. The redistribution structure includes a dielectric layer in which a plurality of three-dimensional porous structures are embedded. The pores of each of the plurality of three-dimensional porous structures are filled with metal. The three-dimensional porous structures are conductive and the coefficient of thermal expansion of the three-dimensional porous structures is less than the coefficient of thermal expansion of the metal. The plurality of semiconductor devices are interconnected through the plurality of conductive structures.

25. The method according to claim 24, characterized in that, Each of the three-dimensional porous structures is a continuous structure, and the surface of the continuous structure has multiple pores.

26. The method according to claim 25, characterized in that, The three-dimensional porous structure has multiple blades, which are connected together in a stacked or horizontally arranged manner to form the continuous structure. The gaps between the multiple blades form multiple holes in the three-dimensional porous structure.

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