An integrated package substrate based on ceramic core board and a method for manufacturing the same

Abstract

The application belongs to the technical field of semiconductor packaging, and discloses an integrated packaging substrate based on a ceramic core plate and a preparation method thereof. The integrated packaging substrate comprises a ceramic core plate and an ABF composite layer, the upper and lower sides of the ceramic core plate are provided with the ABF composite layer, a conductive medium layer is arranged between the ABF composite layer and the ceramic core plate, and the upper and lower surfaces of the ceramic core plate are embedded with electronic components. The preparation method comprises the following steps: S10, providing a ceramic substrate; S20, embedding electronic components; S30, arranging a copper electroplating film layer on the surface of the ceramic substrate; S40, arranging the ABF composite layer on the upper and lower sides of the ceramic substrate; S50, arranging a solder resist layer on the surface of the outermost ABF layer; and S60, arranging a surface treatment layer on the outer side of the solder resist layer. Compared with the traditional packaging substrate, the integrated density and reliability of the application are significantly improved, and the signal transmission performance is optimized.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to an integrated packaging substrate based on a ceramic core board and its preparation method. Background Technology

[0002] Traditional packaging substrates mostly use single resin or ceramic substrates. While resin substrates offer advantages such as low cost and ease of processing, they suffer from low thermal conductivity and poor high-temperature resistance, making them unsuitable for the heat dissipation requirements of high-power chips. Pure ceramic substrates, on the other hand, have high thermal conductivity and excellent insulation, but their wiring layers are difficult to fabricate, failing to meet the high-density interconnect requirements of advanced packaging. Furthermore, chips and passive devices are often surface-mounted, making them susceptible to external environmental interference, which can lead to decreased reliability. In addition, existing composite substrates often fail to achieve deep integration between devices and the substrate, resulting in issues such as low integration density and high signal transmission loss, making it difficult to simultaneously meet the requirements of high-power heat dissipation, high-density interconnection, and high reliability. Summary of the Invention

[0003] The purpose of this invention is to provide an integrated packaging substrate based on a ceramic core board and its preparation method, so as to solve the above-mentioned problems existing in the prior art.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: On one hand, the present invention provides an integrated packaging substrate based on a ceramic core board, including a ceramic core board and an ABF composite layer. An ABF composite layer is disposed above and below the ceramic core board, and a conductive dielectric layer is disposed between the ABF composite layer and the ceramic core board. Electronic components are embedded on the upper and lower surfaces of the ceramic core board. The ceramic core board includes a ceramic substrate and an electroplated copper coating layer. The ceramic substrate has a plurality of interconnecting holes, and the interconnecting holes penetrate the upper and lower surfaces of the ceramic substrate. The electroplated copper coating layer is provided on the upper and lower surfaces of the ceramic substrate and on the walls of the interconnecting holes. The interconnecting holes are also filled with ink. The ABF composite layer includes several stacked ABF layers. Each ABF layer has a copper clad laminate layer on its outer side. The copper clad laminate layer has several copper clad laminate grooves. Each ABF layer at the copper clad laminate groove has a blind via, and a copper pillar is placed inside the blind via. A solder resist layer is provided on the surface of the outermost ABF layer. A surface treatment layer is provided on the outer side of the solder resist layer. The surface treatment layer also has blind vias with built-in copper pillars. The electroplated copper film layer, copper clad laminate layer, and surface treatment layer are all metal layers. Each metal layer is provided with several interconnecting pads. The interconnecting pads of different copper clad laminate layers and the interconnecting pads of the copper clad laminate layer and the electroplated copper film layer are electrically connected through corresponding copper pillars.

[0005] As a preferred technical solution of the present invention, the ceramic substrate is prepared from electronic ceramics, glass ceramics, LTCC ceramics, HTCC ceramics, MLCC ceramics, alumina ceramics, aluminum nitride ceramics, silicon nitride ceramics, silicon carbide ceramics, or diamond ceramics.

[0006] As a preferred technical solution in this invention, the electronic ceramic is 90 ceramic, 92 ceramic, 95 ceramic, 96 ceramic or 99 ceramic.

[0007] As a preferred technical solution of the present invention, both the upper and lower surfaces of the ceramic core plate are provided with ceramic core plate grooves, and electronic components are disposed in the ceramic core plate grooves.

[0008] As a preferred technical solution of the present invention, the electronic components are embedded in the groove of the ceramic core plate by low-temperature sintering or flip-chip bonding process.

[0009] As a preferred technical solution of the present invention, the electronic component is a chip or a passive device.

[0010] On the other hand, the present invention also provides a method for preparing an integrated packaging substrate, used to manufacture the integrated packaging substrate according to any one of the preceding claims, comprising the following steps: S10, Provides a ceramic substrate; S20. Embedding electronic components: Ceramic core plate grooves are provided on both the upper and lower surfaces of the ceramic core plate, and electronic components are embedded in the ceramic core plate grooves. S30. An electroplated copper coating layer is formed on the surface of the ceramic substrate: Several interconnecting holes are formed on the ceramic substrate, so that the interconnecting holes penetrate the upper and lower surfaces of the ceramic substrate. Then, an electroplated copper coating layer is formed on the upper and lower surfaces of the ceramic substrate and on the walls of the interconnecting holes. The interconnecting holes are filled with ink. S40. An ABF composite layer is disposed above and below the ceramic substrate. A conductive dielectric layer is disposed between the ABF composite layer and the ceramic core board. The ABF composite layer includes several stacked ABF layers. A copper clad laminate layer is disposed on the outer side of each ABF layer. Several copper clad laminate grooves are disposed on the copper clad laminate layer. Blind vias are disposed on the ABF layer at each copper clad laminate groove. Copper pillars are disposed in the blind vias. Several interconnected pads are formed on the copper clad laminate layer. S50. A solder resist layer is provided on the surface of the outermost ABF layer; S60. A surface treatment layer is provided on the outside of the solder mask layer, covering the outside of the solder mask layer and exposing only the pad area of ​​the solder mask layer with openings.

[0011] Beneficial effects: Compared with traditional packaging substrates, the core technical advantages of this invention are reflected in: Significantly improved integration density and reliability: 500 electronic components (chips or passive devices) are embedded in the grooves of the ceramic core board, avoiding the exposure risk of surface mounting. At the same time, the integrated structure of "ceramic core board-ABF layer-copper cladding layer" reduces the overall package size by 40%-60% and increases the integration density per unit area by more than 50%. Signal transmission performance optimization: The low dielectric loss characteristics of the ABF layer and the short-path interconnect design reduce signal transmission delay and crosstalk amplitude. In high-speed signal transmission scenarios, the bit error rate is far superior to that of traditional composite substrates. Attached Figure Description

[0012] Figure 1 This is a cross-sectional structural diagram of the present invention.

[0013] In the diagram: 001 - Ceramic packaging substrate; 100 - Ceramic core board; 101 - Ceramic substrate; 210 - Electroplated copper coating layer; 220 - Conductive dielectric layer; 230 - Blind via; 240 - Copper clad laminate groove; 250 - Surface treatment layer; 300 - ABF composite layer; 310 - Interconnect via; 320 - ABF layer; 330 - Solder resist layer; 500 - Electronic components. Detailed Implementation

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in conjunction with the accompanying drawings and descriptions of the embodiments or the prior art. Obviously, the following description of the structure of the accompanying drawings is only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the description of these embodiments is for the purpose of helping to understand the present invention, but does not constitute a limitation of the present invention.

[0015] Example: like Figure 1As shown, this embodiment provides an integrated packaging substrate based on a ceramic core board, including a ceramic core board 100 and an ABF composite layer 300. ABF composite layers 300 are disposed above and below the ceramic core board 100. A conductive dielectric layer 220 is disposed between the ABF composite layer 300 and the ceramic core board 100. Electronic components 500, which are chips or passive devices, are embedded on both the upper and lower surfaces of the ceramic core board 100. Through an innovative structural design of "ceramic core board device integration - ABF layer stacking wiring - copper layer interconnection," the multifunctional integration of the packaging substrate is achieved. The specific solution is as follows: 1. Ceramic core board pretreatment and device mounting: Ceramic core board grooves are provided on both the upper and lower surfaces of the ceramic core board 100. Electronic components 500 are disposed within these grooves. Specifically, the electronic components 500 are embedded into the ceramic core board grooves through low-temperature sintering or flip-chip bonding processes, forming an integrated "ceramic core board-device" carrier.

[0016] Compared to traditional packaging substrates, the core technological advantages of this invention are reflected in: Significantly improved integration density and reliability: 500 electronic components (chips or passive devices) are embedded in the grooves of the ceramic core board, avoiding the exposure risk of surface mounting. At the same time, the integrated structure of "ceramic core board-ABF layer-copper cladding layer" reduces the overall package size by 40%-60% and increases the integration density per unit area by more than 50%. Signal transmission performance optimization: The low dielectric loss characteristics of the ABF layer and the short-path interconnect design reduce signal transmission delay and crosstalk amplitude. In high-speed signal transmission scenarios, the bit error rate is far superior to that of traditional composite substrates.

[0017] The ceramic core board 100 includes a ceramic substrate 101 and an electroplated copper coating layer 210. The ceramic substrate 101 has a plurality of interconnecting holes 310, which penetrate the upper and lower surfaces of the ceramic substrate 101. The electroplated copper coating layer 210 is provided on the upper and lower surfaces of the ceramic substrate 101 and on the hole walls of the interconnecting holes 310. The interconnecting holes 310 are also filled with ink. The copper coating on the surface of the ceramic packaging substrate 001 is a key link connecting the "insulation / high reliability substrate characteristics" of the ceramic core board with the "conductivity / interconnection requirements" of external electronic components. Although the surface of the ceramic core board is hard, it has micropores or defects and is easily damaged by external environment (such as moisture, chemical corrosion) or mechanical stress (such as pressing during assembly). The copper coating can play the role of "protective layer".

[0018] The ABF composite layer 300 includes several stacked ABF layers 320. Each ABF layer 320 has a copper-clad laminate layer on its outer side. The copper-clad laminate layer has several copper-clad laminate grooves 240. Each ABF layer 320 at a copper-clad laminate groove 240 has a blind via 230, and a copper pillar is placed within the blind via 230. This overcomes the shortcomings of ceramic materials in high-density wiring, cost control, and packaging compatibility, while retaining the core advantages of the ceramic core board. The ABF composite layer 300 possesses good flexibility and compatibility, allowing passive components (resistors, capacitors, inductors) to be mounted on its surface or inside, or serving as a "transition layer" connecting the ceramic core board 100 with other organic substrates (such as PCBs), solving the "rigidity matching" problem between ceramic and organic materials. In terms of performance, it balances "high-speed signal integrity" and "high heat dissipation." In terms of reliability, it improves "thermal stress matching" and "mechanical protection."

[0019] A solder mask layer 330 is disposed on the outermost ABF layer 320. This solder mask layer is a key step in ensuring packaging reliability and achieving precise soldering. The solder mask layer 330 protects the ABF layer 320 and copper wiring, isolating them from external damage and environmental corrosion. During the packaging process, soldering (such as chip bump soldering, solder ball placement, and passive component mounting) needs to be performed on the copper pads of the ABF layer 320. The solder mask layer 330 uses a "window design" to precisely define the soldering area. The ABF layer 320 itself has low hardness (Shore hardness D≈60-70), making it easily scratched during packaging handling and pressing. After curing, the solder mask layer 330 has high hardness (Shore hardness D≈85-90), which can resist minor mechanical friction or impact. The ABF layer 320 and copper wiring are protected from physical damage. The exposed copper pads in the windowed area are roughened, significantly improving wettability with solder (contact angle ≤30°), reducing defects such as cold solder joints and poor solder joints. At the same time, the solder mask layer 330 prevents solder from spreading to non-pad areas, ensuring that the solder joint volume (e.g., Solder Ball diameter deviation ≤±10%) and shape meet packaging requirements, improving soldering reliability. The fully cured solder mask layer 330 has excellent resistance to damp heat (no blistering or peeling of the coating and no corrosion of copper wiring after 1000 hours in an 85℃ / 85%RH environment) and chemical resistance (resistant to immersion in common cleaning agents such as soldering flux, alcohol, and acetone), preventing the ABF layer 320 and copper wiring from failing due to environmental factors.

[0020] A surface treatment layer 250 is disposed on the outer side of the solder resist layer 330. The surface treatment layer 250 also has blind vias 230 with built-in copper pillars, exposing only the "pad area" of the solder resist layer 330 (used for subsequent chip soldering or interconnection between the substrate and PCB). The core function of the surface treatment layer 250 is to address the performance defects of the "pads on the outer side of the solder resist layer" and to connect with subsequent packaging processes. The copper pads of the solder resist layer 330 are directly exposed to air and are prone to rapid oxidation (forming CuO / Cu2O). Oxidized copper pads cannot reliably bond with solder (such as solder paste or gold wire). The packaging substrate needs to adapt to different application scenarios (such as the humid and hot environment of consumer electronics and the high and low temperature cycling of automotive electronics), and the surface treatment layer 250 can resist external environmental corrosion. Both the ABF composite layer (organic resin-based) and the solder resist layer (epoxy resin-based) are organic materials, and the surface treatment layer can indirectly protect their structure. Different surface treatment layers can be matched with different soldering / bonding processes, improving the versatility of the substrate.

[0021] The electroplated copper coating layer 210, the copper clad laminate layer, and the surface treatment layer 250 are all metal layers. Each metal layer is provided with a number of interconnecting pads. The interconnecting pads of different copper clad laminate layers and the interconnecting pads between the copper clad laminate layer and the electroplated copper coating layer 210 are electrically connected through corresponding copper pillars.

[0022] As a preferred embodiment of this invention, it should be further noted that the ceramic substrate 101 is made of electronic ceramics (such as 90 ceramic, 92 ceramic, 95 ceramic, 96 ceramic or 99 ceramic), glass ceramics, LTCC ceramics, HTCC ceramics, MLCC ceramics, alumina ceramics, aluminum nitride ceramics, silicon nitride ceramics, silicon carbide ceramics or diamond ceramics. As the core substrate for carrying devices and transmitting signals in electronic devices, the ceramic substrate 101 has unique material properties and performance advantages, making it irreplaceable in high-precision and high-reliability electronic fields (such as aerospace, automotive electronics, 5G communication).

[0023] On the other hand, the present invention also provides a method for preparing an integrated packaging substrate, used to manufacture the integrated packaging substrate according to any one of the preceding claims, comprising the following steps: S10, Provide a ceramic substrate 101; S20, Embedded Electronic Components 500: Ceramic core board grooves are provided on both the upper and lower surfaces of the ceramic core board 100, and electronic components 500 are embedded in the ceramic core board grooves. Applications: Constructing the functional core of the substrate, reducing reliance on external components; adapting to high-density wiring in the ABF layer, shortening signal transmission paths; improving device protection levels, adapting to harsh application environments.

[0024] S30. An electroplated copper coating layer 210 is formed on the surface of the ceramic substrate 101: A plurality of interconnecting holes 310 are formed on the ceramic substrate 101, such that the interconnecting holes 310 penetrate the upper and lower surfaces of the ceramic substrate 101, and then an electroplated copper coating layer 210 is formed on the upper and lower surfaces of the ceramic substrate 101 and on the hole walls of the interconnecting holes 310; the interconnecting holes 310 are filled with ink. S40. An ABF composite layer 300 is disposed above and below the ceramic substrate 101. A conductive dielectric layer 220 is disposed between the ABF composite layer 300 and the ceramic core board 100. The ABF composite layer 300 includes a plurality of stacked ABF layers 320. A copper clad laminate layer is disposed on the outer side of each ABF layer 320. A plurality of copper clad laminate grooves 240 are disposed on the copper clad laminate layer. A blind via 230 is disposed on the ABF layer 320 at each copper clad laminate groove 240. A copper pillar is disposed in the blind via 230. A plurality of interconnecting pads are formed on the copper clad laminate layer. S50. A solder resist layer is provided on the outermost ABF layer 320 surface; S60. A surface treatment layer 250 is provided on the outside of the solder mask layer 330. The surface treatment layer 250 covers the outside of the solder mask layer, exposing only the pad area of ​​the solder mask layer with openings.

[0025] Compared with traditional packaging substrates, the core technical advantages of this invention are as follows: Significantly improved integration density and reliability: 500 electronic components (chips or passive devices) are embedded in the grooves of the ceramic core board, avoiding the exposure risk of surface mounting. At the same time, the integrated structure of "ceramic core board-ABF layer-copper cladding layer" reduces the overall package size by 40%-60% and increases the integration density per unit area by more than 50%. Signal transmission performance optimization: The low dielectric loss characteristics of the ABF layer and the short-path interconnect design reduce signal transmission delay and crosstalk amplitude. In high-speed signal transmission scenarios, the bit error rate is far superior to that of traditional composite substrates.

[0026] Finally, it should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An integrated packaging substrate based on a ceramic core board, characterized in that, It includes a ceramic core plate (100) and an ABF composite layer (300). The ABF composite layer (300) is provided above and below the ceramic core plate (100). A conductive dielectric layer (220) is provided between the ABF composite layer (300) and the ceramic core plate (100). Electronic components (500) are embedded on the upper and lower surfaces of the ceramic core plate (100). The ceramic core board (100) includes a ceramic substrate (101) and an electroplated copper coating layer (210). The ceramic substrate (101) is provided with a plurality of interconnect holes (310), and the interconnect holes (310) penetrate the upper surface and the lower surface of the ceramic substrate (101). The electroplated copper coating layer (210) is provided on the upper surface and the lower surface of the ceramic substrate (101) and on the hole wall of the interconnect holes (310). The interconnect holes (310) are also filled with ink. The ABF composite layer (300) includes several stacked ABF layers (320). Each ABF layer (320) has a copper clad laminate layer on its outer side. The copper clad laminate layer has several copper clad laminate grooves (240). Each copper clad laminate groove (240) has a blind via (230) on the ABF layer (320) and a copper pillar inside the blind via (230). The outermost ABF layer (320) has a solder mask layer (330) on its surface. The solder mask layer (330) has a surface treatment layer (250) on its outer side. The surface treatment layer (250) also has blind vias (230) with built-in copper pillars. The electroplated copper coating layer (210), the copper clad laminate layer and the surface treatment layer (250) are all metal layers. Each metal layer is provided with several interconnecting pads. The interconnecting pads of different copper clad laminate layers and the interconnecting pads between the copper clad laminate layer and the electroplated copper coating layer (210) are electrically connected through corresponding copper pillars.

2. The integrated packaging substrate according to claim 1, characterized in that, The ceramic substrate (101) is made of electronic ceramics, glass ceramics, LTCC ceramics, HTCC ceramics, MLCC ceramics, alumina ceramics, aluminum nitride ceramics, silicon nitride ceramics, silicon carbide ceramics, or diamond ceramics.

3. The integrated packaging substrate according to claim 2, characterized in that, The electronic ceramic is of grade 90, grade 92, grade 95, grade 96, or grade 99.

4. The integrated packaging substrate according to claim 1, characterized in that, The upper and lower surfaces of the ceramic core plate (100) are provided with ceramic core plate grooves, and the electronic components (500) are disposed in the ceramic core plate grooves.

5. The integrated packaging substrate according to claim 4, characterized in that, The electronic components (500) are embedded in the grooves of the ceramic core plate by low-temperature sintering or flip-chip bonding.

6. The integrated packaging substrate according to claim 1, characterized in that, The electronic component (500) is a chip or a passive device.

7. A method for preparing an integrated packaging substrate, used to manufacture the integrated packaging substrate according to any one of claims 1-6, characterized in that, Includes the following steps: S10, Provide a ceramic substrate (101); S20, Embedding electronic components (500): Ceramic core plate grooves are provided on both the upper and lower surfaces of the ceramic core plate (100) to embed electronic components (500) into the ceramic core plate grooves; S30. An electroplated copper coating layer (210) is formed on the surface of the ceramic substrate (101): Several interconnect holes (310) are formed on the ceramic substrate (101) so that the interconnect holes (310) penetrate the upper and lower surfaces of the ceramic substrate (101). Then, an electroplated copper coating layer (210) is formed on the upper and lower surfaces of the ceramic substrate (101) and on the hole walls of the interconnect holes (310). The interconnect holes (310) are filled with ink. S40. An ABF composite layer (300) is provided above and below the ceramic substrate (101). A conductive dielectric layer (220) is provided between the ABF composite layer (300) and the ceramic core board (100). The ABF composite layer (300) includes several stacked ABF layers (320). A copper clad laminate layer is provided on the outer side of each ABF layer (320). Several copper clad laminate grooves (240) are provided on the copper clad laminate layer. Blind vias (230) are provided on the ABF layer (320) at each copper clad laminate groove (240). Copper pillars are provided in the blind vias (230). Several interconnected pads are formed on the copper clad laminate layer. S50. A solder resist layer is provided on the outermost ABF layer (320) surface; S60. A surface treatment layer (250) is provided on the outside of the solder mask layer (330). The surface treatment layer (250) covers the outside of the solder mask layer, and only exposes the pad area of ​​the solder mask layer with openings.

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