A one-frame monochrome instrument

Abstract

This invention discloses a single-frame-one-color monochromator, relating to the field of optical instrument technology. The monochromator includes a timing synchronization control unit and a monochromator... LED The system includes an array unit, an integrated optical coupling and homogenizing unit, and a multi-mode output interface unit. A timing synchronization control unit serves as the control center, electrically connected to the other three units; monochrome... LED The optical output terminal of the array unit is connected to the optical input terminal of the integrated optical coupling and homogenizing unit; the optical output terminal of the integrated optical coupling and homogenizing unit is connected to the optical input terminal of the multi-mode output interface unit. This invention... FPGA To achieve nanosecond-level timing synchronization control, a distributed constant current driver architecture is adopted. LED The array, combined with an integrated optical system, achieves efficient coupling and uniform light, enabling high-speed one-frame-one-color imaging. It also has multi-mode output capabilities and is suitable for various fields such as spectral analysis, materials detection, and biomedical imaging.

Description

Technical Field

[0001] This invention relates to the field of optical instrument technology, specifically to a monochromatic light generating device, and more specifically to a monochromator with one color per frame. Background Technology

[0002] A monochromator is a core optical instrument capable of generating monochromatic light, widely used in fields such as spectral analysis, materials testing, and biomedical imaging. Current mainstream monochromators are divided into two categories: prism-based and grating-based. Both achieve selective output of light of different wavelengths through the mechanical rotation of prisms or gratings. These traditional monochromators rely entirely on mechanical moving parts for light dispersion, resulting in inherent drawbacks such as slow wavelength switching speed, easy wear and tear of mechanical parts, short equipment lifespan, high maintenance costs, complex optical paths, large size, and stringent requirements for vibration and temperature control. Consequently, they cannot meet the application requirements of high-speed, one-frame-one-color imaging.

[0003] In recent years, based on LED Multispectral light sources using arrays are gradually emerging, but they generally suffer from problems such as low spectral purity, fixed and non-scalable wavelength count, and poor light intensity uniformity. Existing... LED The control circuits of light sources mostly use simple switching control architectures, which cannot achieve precise timing synchronization at the nanosecond level, resulting in... LED An uncontrollable time difference exists between the emission time and the camera exposure time, severely affecting image quality and spectral resolution. Furthermore, existing... LED Light sources generally lack dedicated optical coupling and homogenization designs, have low fiber coupling efficiency, and produce uneven output light intensity distribution, making it difficult to meet the requirements of high-precision scientific research and industrial testing.

[0004] The English abbreviations, full English names, and Chinese names involved in this invention are as follows: FPGA : Field Programmable Gate Array Field Programmable Gate Array MOSFET : Metal - Oxide - Semiconductor Field - Effect Transistor Metal-oxide-semiconductor field-effect transistor DAC : Digital - to - Analog Converter Digital-to-analog converter ADC : Analog - to - Digital Converter Analog-to-digital converter LVDS : Low - Voltage Differential Signaling Low-voltage differential signal SPI : Serial Peripheral Interface Serial peripheral interface I 2 C : Inter - Integrated Circuit Integrated circuit bus USB : Universal Serial Bus Universal Serial Bus DMD : Digital Micromirror Device Digital micromirror device TEC : Thermoelectric Cooler Thermoelectric coolers. Summary of the Invention

[0005] The technical problem to be solved by this invention includes at least one of the following: solving the problems of slow wavelength switching speed, easy wear of mechanical parts, and short equipment life of traditional mechanical spectrophotometers; solving the problems of existing... LED The array of multispectral light sources suffers from low timing synchronization accuracy, narrow intensity modulation range, and inability to achieve independent channel adjustment; this addresses the existing problems. LED This addresses the problems of low fiber coupling efficiency and poor uniformity of output light intensity in light sources; and solves the problem of existing monochromators having a single output mode and being incompatible with multiple application scenarios.

[0006] To address the aforementioned technical problems, the present invention provides the following technical solutions.

[0007] A single-frame-one-color monochromator includes: The timing synchronization control unit serves as the control center and is connected to the monochrome circuitry via electrical connection lines. LED The array unit, integrated optical coupling and homogenizing unit, and multi-mode output interface unit are connected; monochrome LED Array units are used to provide multiple monochromatic lights of different wavelengths in a high-density matrix arrangement; An integrated optical coupling and homogenizing unit is used for collimation, spatial light modulation, fiber coupling, and homogenization of the monochromatic light; and A multi-mode output interface unit is used to output processed monochromatic light in multiple modes, including direct imaging, fiber optic output, or integrating sphere homogenization output. The timing synchronization control unit includes FPGA Main control unit and LED Drive array units; The FPGA The main control unit includes: The timing generation unit is used to generate drive signals and trigger signals for nanosecond-level timing. Wavelength sequence storage unit, used to store wavelength switching sequences containing multiple wavelength points; and The light intensity modulation unit employs digital-to-analog conversion technology for each... LED The drive channel provides an independent reference voltage; The LED The drive array unit contains multiple independent LED Drive channel, each LED The drive channel is used to independently drive the monochrome. LED One of the corresponding array cells LED chip.

[0008] In a preferred embodiment of the present invention, the LED The drive array unit adopts a distributed constant current drive architecture, and each of the... LED The drive channel includes a current setting section, a constant current regulation section, and a high-speed switching section.

[0009] In a preferred embodiment of the present invention, the current setting section includes a digital-to-analog converter, which is connected to the [unclear - likely a device name] via a serial peripheral interface bus. FPGA The main control unit is used to receive digital code values ​​and output the reference voltage.

[0010] In a preferred embodiment of the present invention, the constant current regulation section includes: Current sampling resistor; Constant current control MOSFET ;as well as Operational amplifier; The non-inverting input of the operational amplifier receives the reference voltage, the inverting input is connected to one end of the current sampling resistor, and the output is connected to the constant current control. MOSFET The gate; The constant current control MOSFET The drain is connected to the corresponding LED The cathode and source of the chip are connected to the other end of the current sampling resistor.

[0011] In a preferred embodiment of the present invention, the high-speed switching section includes a high-speed switch. MOSFET The high-speed switch MOSFET The drain is connected to the current sampling resistor away from the constant current control. MOSFET One end has its source grounded, and its gate connected to the digital isolator. FPGA Main control unit.

[0012] In a preferred embodiment of the present invention, the LED The drive array unit communicates with the [other unit] via a serial bus. FPGAThe main control unit is connected, and the serial bus includes a serial data line, a shift clock line, a latch clock line, and an output enable line. Control commands are shifted into the shift register chain in the form of serial data, and the latch clock line enables synchronous output of all channels.

[0013] In a preferred embodiment of the present invention, the LED The drive array unit also includes an overcurrent protection circuit, each of which LED The drive channel is equipped with an overcurrent comparator, and the outputs of all overcurrent comparators are connected to the aforementioned via wired-AND logic. FPGA Main control unit.

[0014] In a preferred embodiment of the present invention, the integrated optical coupling and homogenizing unit includes an optical path delay compensation module, which includes multiple fiber optic reels driven by stepper motors for adjusting the length of corresponding optical fibers to compensate for the time delay difference of light of different wavelengths propagating in the optical fibers.

[0015] In a preferred embodiment of the present invention, the monochromatic... LED Array cells include narrowband LED Chip array unit, thermal management unit, spectral calibration unit and LED Array mounting and positioning unit; the narrowband LED The chip array units adopt a high-density matrix arrangement, each LED The chip is surrounded by a metal shielding wall.

[0016] In a preferred embodiment of the present invention, the integrated optical coupling and homogenizing unit includes LED The system includes a collimation unit, a spatial light modulation unit, an optical fiber coupling unit, an integrating sphere homogenizing unit, and an optical switching unit. The optical switching unit comprises two high-speed motorized optical shutters and a rotatable plane mirror, used to switch between different output modes.

[0017] In a preferred embodiment of the present invention, the multi-mode output interface unit includes a direct imaging output unit, an optical fiber output unit, an integrating sphere homogenizing output unit, and an extended output unit; the direct imaging output unit integrates a filter wheel, and the optical fiber output unit has multiple standard optical fiber interfaces.

[0018] Compared with the prior art, the present invention utilizes a narrow band without mechanical moving parts. LED As a beam-splitting element, the array completely eliminates mechanical wear problems, improving the service life and operational reliability of the equipment; through a method based on... FPGA The high-precision timing synchronization control architecture achieves nanosecond-level wavelength switching and camera trigger synchronization, significantly improving the speed and quality of multispectral imaging; through a distributed constant current drive architecture, it realizes the synchronization of each... LEDIndependent high-precision adjustment of channel light intensity; by integrating optical coupling and homogenizing units, the fiber coupling efficiency and spatial uniformity of output light intensity are effectively improved; through multi-mode output interface units, it can be compatible with various application scenarios such as direct imaging, fiber illumination, and integrating sphere homogenizing output, greatly expanding the applicability of monochromator. Attached Figure Description

[0019] Figure 1 The overall logic structure block diagram of the monochromator with one frame and one color provided by the present invention.

[0020] Figure 2 The internal logic structure block diagram of the timing synchronization control unit provided by the present invention is shown.

[0021] Figure 3 Provided by the present invention FPGA Block diagram of the internal logic structure of the main control unit.

[0022] Figure 4 This is a schematic diagram of the system signal connection provided by the present invention.

[0023] Figure 5 Provided by the present invention LED A schematic diagram showing the connection between the drive array and the control unit.

[0024] Figure 6 This is a block diagram of the internal logic structure of the camera triggering unit provided by the present invention.

[0025] Figure 7 The present invention provides a high-speed switch with digital isolation. DAC Controlled linear LED Schematic diagram of constant current drive circuit.

[0026] Figure 8 This is a schematic diagram of the constant current feedback loop provided by the present invention.

[0027] Figure 9 This is a functional diagram of the digital isolation and switch control section provided by the present invention.

[0028] Figure 10 The connection logic diagram of the clock reference unit provided by the present invention.

[0029] Figure 11 The connection logic diagram of the camera triggering unit provided by the present invention.

[0030] Figure 12 The connection logic diagram of the device synchronization expansion unit provided by the present invention.

[0031] Figure 13 The connection logic diagram of the spectral calibration unit provided by the present invention.

[0032] Figure 14 The connection logic diagram of the spatial light modulation unit provided by the present invention.

[0033] Figure 15 The connection logic diagram of the communication interface unit provided by the present invention.

[0034] Figure 16 Provided by the present invention DDR 3 SDRAM Memory connection logic diagram.

[0035] Figure 17 Provided by the present invention JTAG Debugging interface connection diagram.

[0036] Figure 18 Provided by the present invention SPI Flash Configuration interface connection diagram.

[0037] Figure 19 The configuration control and status pin connection diagram provided for this invention.

[0038] Figure 20 The voltage domain requirement diagram provided for this invention.

[0039] The labels for each figure are as follows: 1: Timing synchronization control unit; 11: Clock reference unit; 12: FPGA Main control unit; 121: Timing generation unit; 122: Wavelength sequence storage unit; 123: Intensity tuning unit; 124: Communication interface unit; 13: LED 14: Camera trigger unit; 15: Device synchronization extension unit; 2: Monochrome LED Array unit; 3: Integrated optical coupling and homogenization unit; 32: Spatial light modulation unit; 33: Fiber optic coupling unit; 35: Optical switching unit; 4: Multi-mode output interface unit. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0042] like Figures 1 - 6 As shown, the first embodiment of the present invention provides a monochromator with one frame and one color, including a timing synchronization control unit 1 and a monochromator. LEDArray unit 2, integrated optical coupling and homogenization unit 3, and multi-mode output interface unit 4. The units are interconnected via electrical connection lines and optical-mechanical interfaces.

[0043] Clock reference unit 11 employs a composite clock architecture combining a temperature-controlled crystal oscillator and a satellite positioning system discipline unit. The temperature-controlled crystal oscillator provides short-term frequency stability better than 1×10⁻⁶. -11 The local clock signal is provided at 1 / second. The satellite positioning system discipline unit corrects the long-term frequency drift of the temperature-controlled crystal oscillator by receiving the second pulse signal from the Global Positioning System. The clock reference unit 11 outputs two synchronous clock signals, one of which is 100... MHz The system master clock, the other is 1 Hz The second pulse synchronization signal is sent to respectively FPGA Main control unit 12 and equipment synchronization expansion unit 15.

[0044] FPGA The main control unit 12 adopts a parallel processing architecture to enable multiple tasks to be executed simultaneously. FPGA The main control unit 12 integrates a timing generation unit 121, a wavelength sequence storage unit 122, a light intensity adjustment unit 123, and a communication interface unit 124. The units are connected via a global clock bus, an address bus, a data bus, and dedicated control signal lines.

[0045] The timing generation unit 121 generates a time sequence based on a preset wavelength switching sequence and exposure time. LED The driving timing and camera triggering timing are preferably configured with a time resolution of 1 nanosecond.

[0046] Wavelength sequence storage unit 122 stores multiple sets of different wavelength switching sequences, each set of sequences can contain multiple wavelength points.

[0047] Communication interface unit 124 provides USB 3.0, Ethernet and RS It features three RS-485 communication interfaces, supporting data transmission and control command interaction with host computers, cameras, and other external devices.

[0048] Non-limitingly, the communication interface unit 124 is connected to the timing generation unit 121, the wavelength sequence storage unit 122, and the optical intensity modulation unit 123 via a 32-bit wide internal data bus and a 16-bit wide internal address bus, respectively. Simultaneously, the communication interface unit 124 is connected to the timing generation unit 121, the wavelength sequence storage unit 122, and the optical intensity modulation unit 123 via a dedicated interrupt signal line, used to notify the timing generation unit 121, the wavelength sequence storage unit 122, and the optical intensity modulation unit 123 that new instructions or data have arrived.

[0049] The first set of data output terminals of the communication interface unit 124 is connected to the data input terminal of the wavelength sequence storage unit 122, the address output terminal is connected to the address input terminal of the wavelength sequence storage unit 122, and the write enable output terminal is connected to the write enable input terminal of the wavelength sequence storage unit 122. The host computer writes the preset wavelength switching sequence, the exposure time and light intensity setting value for each wavelength into the designated address space of the wavelength sequence storage unit 122 through the communication interface unit 124. The second set of data output terminals of the communication interface unit 124 is connected to the control register input terminal of the timing generation unit 121, used to send start, stop, pause, and other control commands to the timing generation unit 121. The third set of data output terminals of the communication interface unit 124 is connected to the calibration register input terminal of the light intensity adjustment unit 123, used to write the light intensity calibration parameters and temperature compensation coefficient.

[0050] The data input terminals of the communication interface unit 124 are respectively connected to the status register output terminal of the timing generation unit 121, the data output terminal of the wavelength sequence storage unit 122, and the feedback register output terminal of the light intensity adjustment unit 123. The host computer can read the current operating status of the timing generation unit 121, the sequence data stored in the wavelength sequence storage unit 122, and the real-time light intensity feedback value of the light intensity adjustment unit 123 through the communication interface unit 124. The interrupt input terminals of the communication interface unit 124 are respectively connected to the interrupt output terminals of the timing generation unit 121, the wavelength sequence storage unit 122, and the light intensity adjustment unit 123.

[0051] When any one of the timing generation unit 121, wavelength sequence storage unit 122, and light intensity adjustment unit 123 malfunctions or completes a specified operation, an interrupt signal is sent to the communication interface unit 124. The communication interface unit 124 then packages the interrupt information and sends it to the host computer.

[0052] Preferably, the wavelength sequence storage unit 122 consists of 128 KB The on-chip block random access memory is divided into 1024 memory blocks, each 1024 bytes in size, capable of storing a wavelength switching sequence containing 256 wavelength points. Each wavelength point occupies 4 bytes of storage space, of which 2 bytes are used to store the light intensity setting value, 1 byte is used to store the exposure time, and 1 byte is used to store... LED Drive channel number.

[0053] The address input terminal of the wavelength sequence storage unit 122 is connected to the address output terminal of the timing generation unit 121, the data output terminal is connected to the data input terminal of the timing generation unit 121 and the data input terminal of the intensity modulation unit 123, and the read enable input terminal is connected to the read enable output terminal of the timing generation unit 121. When the timing generation unit 121 starts executing a wavelength switching sequence, it sends address signals and read enable signals to the wavelength sequence storage unit 122 in a preset order. After receiving the address signals and read enable signals, the wavelength sequence storage unit 122 simultaneously outputs the wavelength point data stored at the corresponding address to both the timing generation unit 121 and the intensity modulation unit 123.

[0054] The write address input, write data input, and write enable input of the wavelength sequence storage unit 122 are all connected to the corresponding outputs of the communication interface unit 124. The host computer can perform read and write operations on any address of the wavelength sequence storage unit 122 through the communication interface unit 124 to realize online updating and recall of the wavelength switching sequence.

[0055] Optionally, the wavelength sequence storage unit 122 integrates a write protection logic circuit, with the write protection input connected to the operating status output of the timing generation unit 121. When the timing generation unit 121 is in the operating state, the write protection logic circuit locks the write operation of the wavelength sequence storage unit 122 to prevent accidental modification of sequence data during sequence execution, which could lead to system failure.

[0056] Preferably, the timing generation unit 121 consists of a 32-bit free-running counter, multiple comparators, and a state machine circuit. The address output of the timing generation unit 121 is connected to the address input of the wavelength sequence storage unit 122, the read enable output is connected to the read enable input of the wavelength sequence storage unit 122, and the data input is connected to the data output of the wavelength sequence storage unit 122. After reading wavelength point data from the wavelength sequence storage unit 122, the timing generation unit 121 parses the exposure time corresponding to that wavelength point. LED Drive channel number.

[0057] The first set of control output terminals of the timing generation unit 121 is connected to multiple independent strobe signal lines. LED Corresponding to drive array unit 13 LED The switch control input of the drive channel is used to control each LED The driving channel is turned on and off. The second set of control output terminals of the timing generation unit 121 is connected to the trigger input terminal of the camera trigger unit 14 to generate a camera trigger signal. The third set of control output terminals of the timing generation unit 121 is connected to the synchronization input terminal of the light intensity adjustment unit 123 to send a synchronization trigger signal to the light intensity adjustment unit 123.

[0058] The light intensity modulation unit 123 adopts 16-bit digital-to-analog converter technology for each LED The light intensity of each channel is independently adjustable, with an adjustment range of 0.01% to 100%. The light intensity adjustment unit 123 consists of multiple... SPI Host interface and DAC Control logic consists of, each LED Each channel corresponds to a separate 16-bit channel. DAC (like TIDAC 8562), FPGA pass SPI The bus writes the light intensity digital code value into the corresponding DAC The register, DAC Output an analog reference voltage to the constant current loop for precise setting. LED Current. The data input terminal of the light intensity modulation unit 123 is connected to the data output terminal of the wavelength sequence storage unit 122, and the synchronization input terminal is connected to the synchronization output terminal of the timing generation unit 121. The light intensity modulation unit 123 internally contains a... SPI The data conversion engine, upon receiving a synchronization signal, reads the light intensity setting value for the current wavelength point from the wavelength sequence storage unit and automatically generates the corresponding... DAC of SPI Write frames (containing address, command, and 16-bit data) via multiplexing SPI Bus sent to LED Each of the drive array units 13 DAC Each SPI The bus connects multiple chips in a daisy chain configuration. DAC The bus clock frequency is 20. MHz .

[0059] When the timing generation unit 121 sends a synchronization trigger signal to the intensity modulation unit 123, the intensity modulation unit 123 latches the light intensity setting value read from the wavelength sequence storage unit 122 and converts the setting value into a corresponding 16-bit digital code value. This code value is sent to the serial peripheral interface bus. LED Corresponding to drive array unit 13 LED The digital-to-analog converter (DAC) of the drive channel converts digital code values ​​into analog voltages, which serve as the reference voltage for the constant current source, thereby achieving... LED Simulated adjustment of light intensity.

[0060] All of the light intensity modulation unit 123 SPI Host interface and DAC The control logic shares the same synchronous trigger signal (from timing generation unit 121), ensuring that all LED The light intensity modulation action of the drive channel is updated and latched to each at the same time. DAC The output register is used to achieve synchronization between channels.

[0061] In a more preferred embodiment, LED The drive array unit 13 adopts a distributed constant current drive architecture, each LED The drive channel is equipped with an independent high-speed constant current driver.

[0062] Schematic, the distributed constant current driving architecture is a type of architecture for multiple LED The circuit topology for powering the light source in the drive channel aims to equip each light-emitting unit with an independent and complete constant current control loop, rather than having multiple light-emitting units share the same constant current source and switch it via a switch. This architecture allows each light-emitting unit to... LED The drive channel is capable of achieving fully decoupled current supply and regulation.

[0063] Specifically, see Figures 7 - 9 In a monochromator with one color per frame, the distributed constant current driving architecture is implemented as follows.

[0064] First, each monochrome LED chip corresponds to an independent LED Drive channel. Each LED The internal structure of the drive channel can be divided into three main parts: the current setting section, the constant current regulation section, and the high-speed switching section.

[0065] In the current setting section, a digital-to-analog converter is used for each... LED The drive channel provides an independent reference voltage. The input of this digital-to-analog converter is connected to a serial peripheral interface bus. FPGA Main control unit 12, FPGA The main control unit 12, based on the preset wavelength sequence and light intensity requirements, directs light to each... LED Different digital code values ​​are written to the digital-to-analog converter (DAC) of the drive channel. The analog voltage output by the DAC serves as the current setting reference for the corresponding constant current source.

[0066] Figure 7 Demonstrated with digital isolation, high-speed switching DAC Controlled linear LED Schematic diagram of constant current drive circuit; Figure 8 A schematic diagram of the constant current feedback loop is shown; Figure 9 A functional diagram of the digital isolation and switch control section is shown.

[0067] In the picture, R 1 indicates the current sampling resistor, used to... LED The current is converted into a voltage signal, which serves as the input to the constant current feedback loop; the preferred value is 0.1. Ω ; Q 1 indicates constant current control MOSFET It is connected in series as a variable resistor in the main circuit, and its stability is achieved by adjusting the on-resistance.LED Current; Q 2 is a high-speed switch MOSFET , Q 2 and Q 1. Can be adopted Infineon BSC 018 N 04 LSG ; R 2 is Q 2 gate series resistors are used to limit MOSFET The gate charging current protects the output stage of the digital isolator, suppresses parasitic oscillations in the gate circuit, and improves switching stability; the preferred value is 1. kΩ ; Riso for Q 1. Gate isolation resistor, used to isolate the op-amp output from... MOSFET Gate capacitor, to prevent loop oscillation, limit gate charging current, and protect the op-amp output stage; preferred value is 22. Ω ; Ccomp This is a loop compensation capacitor used to offset... MOSFET The poles introduced by the gate capacitance expand the loop bandwidth, provide phase margin, and ensure that the loop is stable and oscillate-free throughout the entire current regulation range. The preferred value is 47. pF ; OPA The 656 is a high-speed operational amplifier with low input offset voltage; DAC The 8562 is a 16-bit digital-to-analog converter that will... FPGA The output 16-bit digital light intensity value is converted into an analog reference voltage. V ref ; ADUM The 1400 is a four-channel magnetic isolator used to achieve... FPGA Electrical isolation between digital logic and power circuits improves anti-interference capability and safety.

[0068] In the constant current regulation section, each LED The drive channel is configured based on an operational amplifier and power. MOSFET This is a feedback-type constant current circuit. The non-inverting input of the operational amplifier receives a reference voltage from the digital-to-analog converter, and the inverting input is connected to one end of a current sampling resistor located on the negative branch of the LED. The other end of the current sampling resistor is connected to a high-speed switch. MOSFET Q 2's drain, Q The source of pin 2 is grounded. The non-inverting input of the operational amplifier receives the reference voltage output from the digital-to-analog converter, and the inverting input receives the feedback voltage across the current sampling resistor. The difference between the two is amplified by the operational amplifier to drive the power. MOSFET The gate of the circuit forms a negative feedback loop that stabilizes the output current.

[0069] The working principle of this loop is as follows: when the current of the LED increases for some reason, the voltage across the sampling resistor rises, the voltage at the inverting input of the operational amplifier rises, causing the output to decrease. This, in turn, reduces the gate voltage of the MOSFET, increasing its on-resistance, and ultimately causing the current to drop back to the set value. The reverse is also true. Through this negative feedback mechanism, each... LED The output current of the drive channel can be stabilized at a value determined by the reference voltage and the resistance value of the sampling resistor.

[0070] For example, let the resistance of the sampling resistor be... R The unit is ohms, and the analog reference voltage output by the digital-to-analog converter is... V ref If the unit is volts, then the output current of the constant current source is... I = V ref / R .

[0071] In the high-speed switching section, a high-speed power supply is connected in series in each LED branch. MOSFET ,power MOSFET This is a switching element used to quickly turn on and off a light-emitting diode (LED). This power... MOSFET The gate is directly made of FPGA The logic level signal output by the main control unit 12 drives the circuit, and electrical isolation can be achieved through a high-speed digital isolator.

[0072] To ensure nanosecond-level rise and fall times, special attention must be paid to parasitic parameters in the gate drive circuit. Preferably, the drive circuit wiring uses wide copper foil traces close to the ground plane to control parasitic inductance to within 1 nanohenry. The switching MOSFET itself should be a device with a gate charge of less than 10 nanocoulombs to complete state switching under extremely short drive pulses.

[0073] Constant current control MOSFET ( Q 1) Always operates in the linear region, stabilized by adjusting the on-resistance. LED Current; high-speed switching MOSFET ( Q 2) Always operates in the saturation or cutoff region to achieve nanosecond-level performance. ​ On / off control. This architecture, which separates the constant current transistor from the switching transistor, avoids interference from switching action on the stability of the constant current loop, while ensuring extremely high switching speed.

[0074] Furthermore, each ​The drive channel also integrates overcurrent and overtemperature protection logic circuits. Current detection can be achieved by reusing the sampling resistor in the constant current feedback loop, simultaneously feeding its voltage signal into a comparator. When the sampled voltage exceeds a preset threshold, the comparator flips, directly blocking the current. ​ The drive signal of the switching MOSFET in the drive channel is simultaneously sent to... ​ The main control unit 12 sends an interrupt request. Over-temperature protection is provided by a temperature sensor arranged on the LED substrate, which also cuts off the drive when the temperature exceeds the limit.

[0075] This overcurrent protection is a hardware-level fast protection with a response time of less than 200 seconds. ​ No need to wait ​ Interruption handling can directly cut off the faulty channel, effectively preventing... ​ Chips and power devices were damaged due to overcurrent.

[0076] each ​ Electrical isolation between drive channels is achieved through optocouplers or magnetic couplers to prevent one of them from being electrically isolated during high-speed switching. ​ Noise from the drive channel is coupled to other sources via a common ground or power line. ​ Drive channel.

[0077] The camera triggering unit 14 adopts a composite triggering mechanism that combines hardware triggering and software pre-triggering.

[0078] In hardware trigger mode, the camera trigger unit 14, according to ​ The trigger timing generated by the main control unit 12 outputs... ​ Level or ​ The trigger signal, at a specific level, directly controls the camera's exposure start time. Preferably, the delay time of the trigger signal is less than 1 nanosecond, and the jitter is less than 100 picoseconds.

[0079] In software pre-trigger mode, the camera trigger unit 14 sends a pre-trigger signal to the camera in advance, causing the camera to enter the exposure preparation state, and then sends the main trigger signal at the set time point, reducing the camera's shutter lag time. Preferably, the camera trigger unit 14 supports multiple camera trigger modes, including edge trigger, level trigger, and pulse width trigger, and is compatible with most scientific and industrial cameras on the market.

[0080] The device synchronization expansion unit 15 is used to achieve synchronization between multiple monochromators and between a monochromator and other external devices. Non-limitingly, the device synchronization expansion unit 15 provides 8 synchronization input interfaces and 8 synchronization output interfaces, supporting daisy-chain connections. The device synchronization expansion unit 15 also integrates a timestamp generation module, capable of adding timestamps to each synchronization event.

[0081] The monochrome​ Array unit 2 includes narrowband ​ Chip array unit, thermal management unit, spectral calibration unit and ​ Array mounting and positioning unit.

[0082] The narrow band ​ The chip array units are arranged in a high-density matrix. Schematic, up to 128 narrowband chips of different wavelengths are integrated within a circular area with a diameter of 25 mm. ​ chip. ​ The chips are arranged in a spiral pattern according to wavelength order; this arrangement reduces the number of different wavelengths. ​ This reduces optical crosstalk between systems and facilitates the design of subsequent optical systems. Furthermore, ​ The light-emitting surface of each chip faces the incident surface of the integrated optical coupling and homogenizing unit, and the light-emitting surfaces of each chip are in the same plane. ​ The chip is surrounded by a 0.5 mm wide metal shielding wall to suppress electromagnetic coupling and light scattering.

[0083] The thermal management unit can employ a hybrid thermal management system combining liquid cooling and thermoelectric refrigeration. For example, ​ The array is mounted on a high thermal conductivity copper heat sink substrate, which has a microchannel liquid cooling structure inside, using circulating coolant to cool the surface. ​ The generated heat is carried away. Furthermore, each ​ Arrangement near the base ​ Thermistor ​ The output signal of the thermistor is converted into a digital signal by an analog-to-digital converter and then transmitted to... ​ Main control unit 12. ​ The main control unit 12 adjusts the corresponding temperature wavelength mapping table according to the preset temperature wavelength mapping table. ​ The drive current of the drive channel corrects for wavelength drift caused by temperature.

[0084] The spectral calibration unit incorporates a miniature fiber optic spectrometer for each... ​ corresponding to the drive channel ​ The output spectrum is calibrated.

[0085] ​ The array mounting and positioning unit employs a three-dimensional adjustment mechanism to achieve... ​ Array in X , Y , Z Translation and rotation in three directions X , Y , Z Rotation of three axes.

[0086] Integrated optical coupling and homogenizing unit 3 includes ​Collimation unit, spatial light modulation unit, fiber optic coupling unit, integrating sphere homogenizing unit, and optical switching unit.

[0087] ​ The collimation unit employs a composite collimation optical system combining an aspherical lens array and a freeform surface lens. Each ​ The chip corresponds to an aspherical collimating lens, used to... ​ The emitted Lambertian diverging light is collimated into parallel light with a half-divergence angle of less than 0.5 degrees. All aspherical collimating lenses are integrated on a single lens substrate to form a lens array, whose position is consistent with... ​ The array positions correspond. The collimated parallel light then undergoes secondary collimation through a freeform lens, further reducing the beam divergence angle.

[0088] The spatial light modulation unit employs a digital micromirror device (DMM) as a spatial light modulator to modulate the intensity distribution and spatial shape of the light beam. The DMM consists of millions of miniature mirrors, each capable of independently rotating ±12 degrees around its diagonal, corresponding to both on and off states. By controlling the on / off state and timing of each mirror, intensity modulation can be achieved in any region of the light beam. The spatial light modulation unit also integrates an imaging lens group to project the image of the DMM onto the input surface of the subsequent optical system. The function of the spatial light modulation unit is to compensate for the influence of light intensity distribution and spatial shape. ​ Uneven distribution of output light intensity caused by factors such as uneven array arrangement and optical system aberrations.

[0089] The fiber optic coupling unit employs a coupling optical system combining gradient refractive index lenses and multiple lens groups to achieve... ​ Coupling of light to optical fiber. The optical fiber coupling unit includes a front focusing lens, a gradient refractive index lens, and a rear coupling lens. The front focusing lens focuses the parallel light modulated by the spatial light modulation unit onto the input surface of the gradient refractive index lens. The refractive index of the gradient refractive index lens is parabolically distributed radially, enabling it to focus the incident light into a very small spot. The rear coupling lens further focuses the light output from the gradient refractive index lens and couples it into the fiber core.

[0090] Furthermore, the fiber optic coupling unit also includes an optical path delay compensation module. This module compensates for the time delay difference in the propagation of light of different wavelengths within the fiber. The speed of light in an optical fiber can be expressed as: v = c / n ( ​ ) in, v The speed of light in an optical fiber, measured in meters per second; c The speed of light in a vacuum is approximately 3 × 10⁻⁶.8 meters per second; n ( ​ ) is the optical fiber at wavelength ​ The refractive index at that point.

[0091] For wavelength ​ 1 and ​ 2 Two beams of light, with a length of L The time delay difference transmitted in the optical fiber can be expressed as: ​ = L ×(1 / v 1 -1 / v 2 )= L ×( n ( ​ 1 )- n ( ​ 2 )) / c .

[0092] in, Δt The time delay difference is expressed in seconds. v 1 represents the wavelength. λ The speed of light in an optical fiber, measured in meters per second; v 2 represents the wavelength. λ 2. The speed of light in an optical fiber, measured in meters per second; n ( λ 1 ) is the optical fiber at wavelength λ Refractive index at point 1; n ( λ 2 ) is the optical fiber at wavelength λ The refractive index at point 2.

[0093] To compensate for this time delay difference, the length of one of the optical fibers needs to be adjusted. ΔL , so that: ΔL × n ( λ ) / c = Δ t Thus we get: ΔL = c × Δt / n ( λ ).

[0094] The optical path delay compensation module includes multiple fiber optic reels, each corresponding to one fiber. The fiber optic reels are driven by stepper motors, allowing for adjustment of the fiber length. The system calculates the required fiber length adjustment based on the refractive index of different wavelengths of light, and then drives the stepper motors to rotate the fiber optic reels, adjusting the fiber length accordingly.

[0095] By compensating for optical path delay, it is possible to ensure that the time for light of all wavelengths to reach the target under test is consistent, thereby eliminating the influence of fiber dispersion on the time resolution of multispectral imaging and enabling the system to achieve microsecond-level multispectral sequence imaging.

[0096] Furthermore, the fiber optic coupling interface employs a spring alignment mechanism. The end face of each fiber is fixed by a fine-tuning seat with a built-in spring load.

[0097] The integrating sphere homogenizing unit employs a high-reflectivity integrating sphere to achieve high uniformity of output light. Light output from the fiber-coupled subunit enters the integrating sphere through the input port, undergoes multiple diffuse reflections on the inner wall of the integrating sphere, and is then output as uniform diffuse light from the output port.

[0098] The optical switching unit uses a combination of a high-speed motorized optical shutter and a mirror to enable rapid switching between different output modes.

[0099] The optical switching unit includes two high-speed motorized optical shutters and a rotatable plane mirror. The first optical shutter is located between the spatial light modulation unit and the fiber optic coupling unit, and the second optical shutter is located at the output port of the integrating sphere homogenizing unit.

[0100] The plane mirror is located between the fiber optic coupling unit and the integrating sphere homogenizing unit, and can rotate 90 degrees around its central axis.

[0101] When the system operates in direct imaging mode, the plane mirror rotates to a 45-degree position, reflecting the parallel light modulated by the spatial light modulation unit towards the camera, while simultaneously closing both optical shutters. When the system operates in fiber illumination mode, the plane mirror rotates to a 0-degree position, allowing light to enter the fiber through the fiber coupling unit, while simultaneously opening the first optical shutter and closing the second optical shutter. When the system operates in integrating sphere homogenization output mode, the plane mirror rotates to a 0-degree position, allowing light to enter the fiber through the fiber coupling unit, and then enter the integrating sphere homogenization unit from the fiber output end, while simultaneously opening both optical shutters. The switching time of the optical switching unit is less than 10 milliseconds, enabling rapid switching between different output modes.

[0102] The multi-mode output interface unit 4 includes a direct imaging output unit, an optical fiber output unit, an integrating sphere homogenizing output unit, and an extended output unit.

[0103] The direct imaging output unit is used to directly output the parallel light modulated by the spatial light modulation unit to the camera, so as to achieve imaging with one color per frame.

[0104] The direct imaging output unit includes an imaging lens group and a camera mounting interface. The imaging lens group focuses parallel light onto the camera's image sensor to form a sharp image. The camera mounting interface uses a standard... C Interface and CS The interface is compatible with the vast majority of scientific and industrial cameras on the market.

[0105] More preferably, the direct imaging output unit also integrates a filter wheel, which can be fitted with multiple different filters to further improve the spectral purity of the output light or filter out stray light.

[0106] The fiber optic output unit is used to output the light coupled by the fiber optic coupler through the fiber optic cable, enabling frame-by-frame color illumination in long-distance and complex scenarios. The fiber optic output unit has various standard fiber optic interfaces, including... FC interface, SC interface, ST Interface and LC The interface is compatible with different types of optical fibers. The optical fiber output end also integrates a collimator, which can collimate the divergent light output from the optical fiber into parallel light.

[0107] The integrating sphere homogenizing output unit is used to output uniform light after it has been homogenized by the integrating sphere homogenizing unit. It is suitable for applications that require high uniformity of light intensity, such as flat panel display testing and solar cell testing.

[0108] The extended output unit is used to connect to other external optical devices, such as microscopes, spectrometers, lidar, etc., to expand the application range of the monochromator.

[0109] In the above technical solution of the present invention, the timing synchronization control unit 1 serves as the control center, and is connected to the monochrome [color] ... LED The array unit 2, the integrated optical coupling and homogenizing unit 3, and the multi-mode output interface unit 4 are connected. Monochrome LED Array unit 2 serves as a light source unit, and its optical output is connected to the optical input of integrated optical coupling and homogenizing unit 3 via an optomechanical interface. The optical output of integrated optical coupling and homogenizing unit 3 is connected to the optical input of multi-mode output interface unit 4 via an optomechanical interface.

[0110] All units receive power from independent power supply and management units, which provide stable DC power at different voltage levels to each unit via shielded power cables. The grounding terminals of all units are connected to the system's single-point grounding point via independent grounding wires, forming a star grounding structure to avoid signal crosstalk caused by common ground impedance.

[0111] The timing synchronization control unit 1 includes a clock reference unit 11. FPGA Main control unit 12 LED Drive array unit 13, camera trigger unit 14, and device synchronization expansion unit 15.

[0112] Schematic, the first output of clock reference unit 11 is connected to a differential trace with 50 ohms impedance matching. FPGA The global clock input pin of the main control unit 12 is sent to... FPGA The main control unit 12 provides a frequency of 100 MHz The system's master clock signal. The second output of clock reference unit 11 is simultaneously connected to the system's master clock signal via a differential trace with 50 ohms impedance matching. FPGA The external interrupt input pin of the main control unit 12 and the synchronization clock input pin of the device synchronization expansion unit 15 provide a frequency of 1 to both. Hz The second pulse synchronization signal.

[0113] The control input terminal of the clock reference unit 11 is connected to the serial peripheral interface bus. FPGA The general purpose input / output pins of the main control unit 12, FPGA The main control unit 12 configures and reads the status of the clock reference unit 11 via this bus. The status output terminal of the clock reference unit 11 is connected to a general purpose input / output pin. FPGA The interrupt input pin of the main control unit 12 sends an interrupt signal to the clock reference unit 11 when the clock reference unit 11 malfunctions or loses lock. FPGA The main control unit 12 sends an interrupt request signal.

[0114] FPGA The first set of general purpose input / output pins of the main control unit 12 is connected to a high-speed parallel bus. LED The control input terminal of the drive array unit 13. FPGA The dedicated control pins of the main control unit 12 are connected to the serial bus. LED The shift register chain control input of drive array unit 13. The serial bus includes serial data lines ( SER ), shift clock line ( SRCLK ), latch clock line ( RCLK ) and output enable line ( OE (4 signal lines in total, connected to 8 cascaded 74 chips in the embodiment)HC 595 connection. Control commands are shifted into the shift register chain one by one in serial data form. After all 128 bits of data have been loaded, the latch clock simultaneously outputs the data to the drive isolation circuits of all channels, achieving simultaneous updates of all channels. The preferred shift clock frequency is 100 MHz. MHz Loading 128 bits of data requires 1.28 seconds. μs The latching operation completes the synchronous output of all channels within one clock cycle.

[0115] FPGA The second set of general purpose input / output pins of the main control unit 12 is connected to the serial peripheral interface bus. LED The parameter configuration input terminal for the drive array unit 13. FPGA The main control unit 12 transmits data to each device via a serial peripheral interface bus. LED The digital-to-analog converter of the drive channel writes the current setting value to achieve this for each channel. LED Independent adjustment of the light intensity of the drive channel.

[0116] FPGA The third set of general-purpose input / output pins of the main control unit 12 is connected to the trigger input terminal of the camera trigger unit 14 through differential signal lines, providing camera trigger timing signals to the camera trigger unit 14. FPGA The fourth set of general-purpose input / output pins of the main control unit 12 is connected to the configuration input terminal of the camera trigger unit 14 through the serial peripheral interface bus to configure parameters such as the trigger mode, delay time and pulse width of the camera trigger unit 14.

[0117] FPGA The fifth group of general-purpose input / output pins of the main control unit 12 is connected to the control input terminal of the device synchronization expansion unit 15 through differential signal lines, providing synchronization control signals to the device synchronization expansion unit 15. FPGA The sixth group of general-purpose input / output pins of the main control unit 12 is connected to the configuration input terminal of the device synchronization expansion unit 15 through the serial peripheral interface bus to configure parameters such as the synchronization mode and input / output direction of the device synchronization expansion unit 15.

[0118] FPGA The seventh group of general purpose input / output pins of the main control unit 12 is connected to the monochrome via a serial peripheral interface bus. LED The output terminals of the thermal management unit and the spectral calibration unit of array unit 2 receive temperature signals and spectral data. FPGA The eighth group of general-purpose input / output pins of the main control unit 12 is connected to the control input terminals of the spatial light modulation unit, fiber optic coupling unit, and optical switching unit of the integrated optical coupling and homogenizing unit 3 through a serial peripheral interface bus, and sends control commands to these units.

[0119] LED The input terminal of the digital-to-analog converter in the current setting section of the drive array unit 13 is connected to the serial peripheral interface bus. FPGA The general purpose input / output pins of the main control unit 12 receive signals from... FPGA The digital code value of the main control unit 12. The output of the digital-to-analog converter is connected to the non-inverting input of the operational amplifier in the constant current regulation section via an analog signal line, providing a reference voltage to the operational amplifier.

[0120] The inverting input of the operational amplifier in the constant current regulation section is connected to one end of the current sampling resistor via an analog signal line, and the other end of the current sampling resistor is connected to system ground. The output of the operational amplifier is connected to the power supply of the constant current regulation section via an analog signal line. MOSFET The gate. Power of the high-speed switching section. MOSFET The gate is connected to a high-speed digital isolator. FPGA The general purpose input / output pins of the main control unit 12 receive signals from... FPGA The switch control signal.

[0121] Power of constant current regulation section MOSFET The drain is connected to the monochromatic electrode via a wire. LED Corresponding array unit 2 LED The cathode and source of the chip are connected to the upper end of the current sampling resistor via wires. The power of the high-speed switching section... MOSFET The drain is connected to the lower end of the current sampling resistor, and the source is connected to system ground.

[0122] Each LED The input of the overcurrent protection comparator in the drive channel is connected to one end of the current sampling resistor via an analog signal line, and the output is connected to... FPGA The interrupt input pin of the main control unit 12 is also connected to MOSFET The enable terminal of the gate drive circuit.

[0123] Preferably, the camera trigger unit 14 includes a trigger signal generation circuit, a level conversion circuit, and an interface protection circuit.

[0124] The input terminal of the trigger signal generation circuit is connected to the differential signal line. FPGA The general purpose input / output pins of the main control unit 12 receive signals from... FPGA The trigger timing signal of the main control unit 12. The output of the trigger signal generation circuit is connected to the input of the level conversion circuit via an analog signal line.

[0125] The output of the level conversion circuit is connected to the input of the interface protection circuit via a wire. The output of the interface protection circuit is connected to the trigger input port of the external camera via an external connector. The feedback input of the camera trigger unit 14 is connected to the frame synchronization output port of the external camera via an external connector, and the feedback output is connected to the external camera via a general-purpose input / output pin. FPGA Interrupt input pin of main control unit 12.

[0126] Narrowband LED The chip array unit contains multiple narrowband chips of different wavelengths. LED Chips (e.g., 128), all LED The chip's anodes are connected together to the power supply and power management unit's 12... V DC power output terminal. Each LED The cathodes of the chip are connected to each other via independent shielded wires. LED Corresponding to drive array unit 13 LED Power of drive channel MOSFET The drain electrode. LED The chip array is mounted on a copper heat sink substrate, which is in close contact with the liquid cooling structure of the thermal management unit through thermal grease.

[0127] The thermal management unit includes a temperature sensor array, and the output of the temperature sensors is connected via... I 2 C Bus connected to FPGA The general purpose input / output pins of the main control unit 12 are used to... FPGA The main control unit 12 sends each LED Drive channel correspondence LED Chip operating temperature data.

[0128] The control input of the spectral calibration unit is connected to the serial peripheral interface bus. FPGA The general purpose input / output pins of the main control unit 12 receive signals from... FPGA Main control unit 12 LED Drive channel selection command.

[0129] ​ The aspherical lens array of the collimation unit is mounted in a narrow band. ​ In front of the light-emitting face of the chip array unit, each aspherical lens is aligned with a [missing information - likely a specific lens or element]. ​ The light-emitting surface of the chip. The light-emitting surface of the aspherical lens array faces the incident surface of the freeform lens. The light-emitting surface of the freeform lens faces the incident surface of the spatial light modulation unit. ​ The collimation unit is fixed by a mechanical bracket. ​ On the array mounting and positioning unit.

[0130] The incident surface orientation of the digital micromirror device in the spatial light modulation unit ​ The light-emitting surface of the freeform lens in the collimation unit. The control input terminal of the digital micromirror device is connected to a flexible flat cable. ​ The general purpose input / output pins of the main control unit 12 receive signals from... ​ Image data and control commands of the main control unit 12.

[0131] The light-emitting surface of the digital micromirror device faces the incident surface of the imaging lens group. The light-emitting surface of the imaging lens group faces the incident surface of the optical switching unit. The spatial light modulation unit is fixed to the optical platform by a mechanical support.

[0132] The first optical shutter of the optical switching unit is installed in the optical path between the light-emitting surface of the imaging lens group of the spatial light modulation unit and the incident surface of the fiber optic coupling unit. The second optical shutter is installed at the light-emitting port of the integrating sphere homogenizing unit.

[0133] A plane mirror is mounted on the optical path between the light-emitting surface of the first optical shutter and the incident surface of the fiber optic coupling unit, and can rotate 90 degrees around its central axis. When the plane mirror rotates to the 45-degree position, the parallel light from the spatial light modulation unit is reflected to the incident surface of the direct imaging output unit of the multi-mode output interface unit 4. When the plane mirror rotates to the 0-degree position, the parallel light from the spatial light modulation unit passes through the first optical shutter and enters the incident surface of the fiber optic coupling unit.

[0134] The incident surface of the front focusing lens of the fiber optic coupling unit faces the exit surface of the plane mirror of the optical switching unit. The exit surface of the front focusing lens faces the incident surface of the gradient refractive index lens. The exit surface of the gradient refractive index lens faces the incident surface of the rear coupling lens. The exit surface of the rear coupling lens faces the incident end face of the optical fiber.

[0135] The direct imaging output unit of the multi-mode output interface unit 4 includes an imaging lens group, a filter wheel, and a camera mounting interface. The incident surface of the imaging lens group faces the light-emitting surface of the plane mirror of the optical switching unit. The light-emitting surface of the imaging lens group faces the incident surface of the filter wheel. The light-emitting surface of the filter wheel faces the camera mounting interface.

[0136] The control input terminal of the filter wheel rotation mechanism is connected via a wire to... ​ The general purpose input / output pins of the main control unit 12 receive signals from... ​ Filter selection command from main control unit 12. Camera mounting interface adopts standard... C Interface and ​ The interface allows direct connection to external scientific and industrial cameras.

[0137] The input of the fiber optic output unit is connected to the output of the fiber optic coupling unit via a fiber optic connector. The output collimator of the fiber optic output unit is connected to the output of any standard fiber optic interface via a fiber optic connector.

[0138] After the system is powered on, the clock reference unit 11 first outputs 100. ​ System master clock and 1 ​ Second pulse synchronization signal to ​ Main control unit 12. ​ After the main control unit 12 completes initialization, it reads preset parameters such as wavelength switching sequence, exposure time and light intensity from non-volatile memory.

[0139] Upon receiving the start command ​ The main control unit 12 transmits data to the main control unit via a high-speed parallel bus. ​ Corresponding to drive array unit 13 ​ The drive channel sends a switch control signal and simultaneously sends a signal to the serial peripheral interface bus. ​ The digital-to-analog converter of the drive channel writes the current setting value. ​ Corresponding to drive array unit 13 ​ The drive channel outputs a constant current to drive narrowband. ​ Corresponding chip array unit ​ The chip emits light.

[0140] ​ The light emitted by the chip passes through ​ The collimation unit collimates the light into parallel light, which is then incident on the spatial light modulation unit. ​ The main control unit 12 sends control commands to the spatial light modulation unit to modulate the intensity distribution of the light beam. The modulated light beam is then incident on the optical switching unit.

[0141] If the system is operating in direct imaging mode ​ The main control unit 12 controls the plane mirror to rotate to a 45-degree position, simultaneously closing both optical shutters. The light beam is reflected by the plane mirror to the direct imaging output unit, focused by the imaging lens group and filtered by the filter wheel, before illuminating the target being measured. Meanwhile, ​ The main control unit 12 sends a trigger signal to the camera trigger unit 14, and the camera trigger unit 14 outputs a trigger signal to the external camera to control the camera to start exposure.

[0142] If the system is operating in fiber optic illumination mode ​ The main control unit 12 controls the plane mirror to rotate to the 0-degree position, simultaneously opening the first optical shutter and closing the second optical shutter. The light beam passes through the first optical shutter and enters the fiber optic coupling unit, where it is focused and coupled before entering the optical fiber. ​The main control unit 12 controls the optical path delay compensation module to adjust the length of the optical fiber according to the refractive index of different wavelengths of light, thus compensating for the transmission delay difference of different wavelengths of light. The light is transmitted through the optical fiber to the optical fiber output unit, where it is collimated by the output collimator and then illuminates the target being measured. Simultaneously, ​ The main control unit 12 sends a trigger signal to the camera trigger unit 14 to control the camera exposure.

[0143] If the system is operating in integrating sphere uniform light output mode ​ The main control unit 12 controls the plane mirror to rotate to the 0-degree position and simultaneously opens both optical shutters. After passing through the fiber optic coupling unit and fiber optic output unit, the light beam enters the integrating sphere homogenizing unit for homogenization. The homogenized beam then passes through the diffuser plate and beam adjustment mechanism of the integrating sphere homogenizing output unit before illuminating the target. Simultaneously... ​ The main control unit 12 sends a trigger signal to the camera trigger unit 14 to control the camera exposure.

[0144] Throughout the entire operation, the temperature sensors of the thermal management unit monitor each [unit / item / etc.] in real time. ​ Drive the channel's operating temperature and send the temperature data to ​ Main control unit 12. ​ The main control unit 12 adjusts the power of the thermoelectric cooler and the flow rate of the coolant based on the temperature data to maintain... ​ The chip operates at a stable temperature. The spectral calibration unit periodically collects data for each... ​ Drive the output spectrum of the channel and send the spectral data to ​ Main control unit 12. ​ The main control unit 12 adjusts according to the spectral data. ​ Drive current and operating temperature of the drive channel to compensate for spectral drift.

[0145] When the exposure time ends ​ Main control unit 12 directions ​ Drive array unit 13 sends a shutdown signal to shut down the current array. ​ Drive channel. Meanwhile. ​ Main control unit 12 is ready to light up the next one. ​ corresponding to the drive channel ​ The chip repeats the above process until the entire wavelength switching sequence is completed.

[0146] The following are non-limiting embodiments.

[0147] All the following embodiments are based on ​ -7 ​ 7 A 100 T -2 ​ 676 C chip(​ )design.

[0148] I. Clock Reference Unit: Main Implementing Devices Master clock generator: ​ 5341 A - D - ​ 4-channel arbitrary frequency synthesizer ​ jitter <100 ​ ; ​ Taming module: u - ​ - M 8 N -0-10, multi-system positioning, second pulse accuracy <10 ​ ; Spare crystal oscillator: ​ 8 G -100.000 ​ - B 2 Y - T 100 ​ Differential active crystal oscillator, ±25 ​ Pull-up resistor: ​ 0805 ​ -0710 ​ 10 ​ 1% accuracy; Connection logic as follows ​ As shown.

[0149] two, ​ The main implementation device of the drive array unit (128-channel distributed constant current drive) Serial shift register: ​ 74 ​ 595 ​ 8-bit serial-in parallel-out, propagation delay <10 ​ ; High-speed digital isolators: ​ 1400 ​ Four-channel magnetic isolation, 2500 ​ ; Digital-to-analog converter: ​ 8562 ​ 16-bit dual-channel voltage output ​ interface; power ​ : ​ 018 N 04 ​ , N Ditch, 40 V 180A , ​ ( ​ )=1.8 ​ ; Current sampling resistor: ​ 0805 ​ 070 R 1 L 0.1 ​ 0.1% accuracy, 25 ​ / ℃; Overcurrent comparator: ​ 311 ​ Response time 200 ​ .

[0150] The connection logic is as follows: 128-channel switch control (only 4 slots are occupied) ​ (pins), 8 chips 74 ​ 595 cascades form a 128-displacement chain: ​ 1 connection 74 ​ 595-1 ​ (Serial data); ​ 2 connections 74 ​ 595-1 ​ (Shift clock); ​ 3 connections 74 ​ 595-1 ​ (Latch clock); ​ 4 connections 74 ​ 595-1 ​ (Output enable, active low); 74 per piece ​ 595 output connected to 4 chips ​ 1400, driver after isolation ​ Gate; 4 independent groups ​ Bus (controls 128) ​ ): ​ 1 (Channels 1-32): B 1( ​ ), B 2( ​ ), B 3( ​ ); ​ 2 (Channels 33-64): C 1( ​ ), C 2( ​ ),C 3( ​ ); ​ 3 (Channels 65-96): D 1( ​ ), D 2( ​ ), D 3( ​ ); ​ 4 (Channels 97-128): E 1( ​ ), E 2( ​ ), E 3( ​ ); 32 per group ​ A daisy-chain connection is used, with the bus end connected to 100. ​ Terminating resistors; all ​ The bus clock frequency is set to 20. ​ .

[0151] Overcurrent protection: Each ​ The drive channel is equipped with an overcurrent comparator (e.g.) ​ ​ 311 ​ Response time 200 ​ There are a total of 128 comparators. All comparator outputs use open-collector OR logic (pull-up resistors to 3.3). V ), jointly connected to ​ of F Pin 1. Any overcurrent in any path will pull the corresponding comparator output low. F When pin 1 goes low, it triggers... ​ Interrupted. ​ Immediately after receiving an interrupt, the output enable line ( ​ The output is set to high level, and all outputs are cleared through the shift register chain, thereby instantly cutting off all 128 drive channels.

[0152] III. Main Components of the Camera Trigger Unit ​ Differential driver: ​ 75 ​ 83 ​ 8 channels, 1.4 ​ ; ​ Differential receiver: ​ 75 ​ 82 ​ 8 channels, 1.4 ​ ; ​ Protect: ​ 3003-04 ​ ±15 ​ Contact discharge.

[0153] Connection logic as follows ​ As shown (all) ​ The signal uses 100 ​ Differential impedance matching, trace length difference ≤ 1 ​ Spacing ≥ 3 times the line width.

[0154] IV. Main components of the equipment synchronous expansion unit Same as the camera trigger unit, using the same ​ Driver / receiver; Timestamp counter: ​ Internal logic implementation, 32-bit, 10 ​ Resolution; Connection logic as follows ​ As shown.

[0155] V. Main components of the thermal management unit: I 2 C Multiplexer: ​ 9548 ​ 8 channels, 1.65 V -5.5 V ; 16-bit ​ : ​ 1115 ​ 4 channels, 860 ​ ; ​ Thermistor: ​ 57861 S 0103 F 040, 10 ​ 1% accuracy; ​ Drive: ​ 4 A Continuous output, ​ control; Liquid cooling pump driver: ​ 7960 B 43 A Peak current; The connection logic is as follows: 8 independent I 2 C Main Interface I 2 C 1: A 33(​ ), A 34( ​ )connect ​ 9548 A -1 I 2 C 2: B 33( ​ ), B 34( ​ ) connect ​ 9548 A -2 I 2 C 3: C 33( ​ ), C 34( ​ ) connect ​ 9548 A -3 I 2 C 4: D 33( ​ ), D 34( ​ ) connect ​ 9548 A -4 I 2 C 5: E 33( ​ ), E 34( ​ ) connect ​ 9548 A -5 I 2 C 6: F 33( ​ ), F 34( ​ ) connect TCA 9548 A -6 I 2 C 7: G 33( SCL ), G 34( SDA ) connect TCA 9548 A -7 I 2 C 8: H 33( SCL ), H 34(SDA ) connect TCA 9548 A -8 Hierarchical architecture: Each TCA 9548 A The first four channels each connect to one piece ADS 1115; per piece ADS 1115 followed by 4 NTC Thermistors; Total: 8 × 4 × 4 = 128 temperature monitoring points.

[0156] TEC Liquid cooling control: Route 32 PWM Signal: J 1- J 16. K 1- K 16→ DRV 595; Liquid cooling pump control: L 1 connection BTS 7960; Liquid cooling status feedback: L 2 connections BTS 7960; Temperature alarm interrupted: M 1 (Line or logic).

[0157] VI. The main components of the spectral calibration unit are... Miniature fiber optic spectrometer: Ocean Insight FLAME - S - VIS - NIR 350-1000 nm 0.5 nm Resolution; 128 channels MEMS Optical switch: Thorlabs MEMS - FSW -128, switching time <1 ms ; Stepper motor driver: TI DRV 8825 PWPR 2.5 A Peak value, 1 / 32 of a microstep; Connection logic as follows Figure 13 As shown.

[0158] VII. Spatial Light Modulation Unit: Main Implementing Devices DMD chip: TI DLP 4500 FQE 0.45 inches WXGA 1280×800; DLPController: TI DLPC 350 ZFF Maximum 120 Hz Frame rate; Level converter: TI SN 74 LVCC 3245 APWR 8-bit bidirectional level conversion; Connection logic as follows Figure 14 As shown.

[0159] VIII. Main Implementing Devices of Optical Switching and Fiber Coupling Unit High-speed electric shutter: Thorlabs SH 05, Switching time < 10 ms ; Rotary table: Thorlabs PRM 1 Z 8. Rotational accuracy 0.001°; Fiber optic reel motor: Haydon Kerk E 43 H 4 A -2.33-019, step angle 1.8°; Stepper motor driver: TI DRV 8825 PWPR .

[0160] The connection logic is as follows: First shutter control connection F 49- F 52; Second shutter control connection G 49- G 52; Plane mirror control connection H 49- H 52; 64-channel fiber optic reel control: J 49- J 56. K 49- K 56. L 49- L 56. M 49- M 56. N 49- N 56. P 49- P 56. R 49- R 56. T 49- T 56; Position sensor feedback: U 49- U 56; Optical power monitoring:V 49- V 56.

[0161] IX. Main Implementation Devices of the Communication Interface Unit USB 3.0 PHY : TI TUSB1310A 5 Gbps ; Ethernet PHY : Marvell 88 E 1512- A 0- NNP 2 C 000, 10 / 100 / 1000 Mbps ; RS 485 transceiver: TI MAX 485 CPA Half-duplex, 10 Mbps ; Reference clock: Abracon ABM 8 G -125.000 MHz - B 2 Y - T ±25 ppm (Two independent crystal oscillators); Connection logic as follows Figure 15 As shown.

[0162] ten, DDR 3 SDRAM Memory main implementation device DDR 3 chips: Micron MT 41 K 256 M 16 HA -125 IT 4 Gb 16-bit, 800 MHz ; Terminating resistor: Yageo RC 0805 FR -0749 R 9 L 49.9 Ω 1% accuracy; Connection logic as follows Figure 16 As shown.

[0163] XI. Configuration and Debugging Interface Unit Main implementation devices SPI Flash : Winbond W 25 Q 256 JVFIQ256 Mb ,support x 1 / x 2 / x 4 SPI ; JTAG Connector: Standard 14-pin IDC Connector; Pull-up / pull-down resistors: Yageo RC 0805 FR -074 K 7 L (4.7) kΩ ), RC 0805 FR -07330 R (330) Ω ), RC 0805 FR -071 K 0 L (1) kΩ ) Configuration status LED : Kingbright KP -2012 SRC - PRV Red, 60 mcd .

[0164] Connection logic: JTAG Debugging interface such as Figure 17 As shown, SPI Flash Configuration interface (main) SPIx 4 modes) such as Figure 18 As shown, the configuration control and status pins are as follows: Figure 19 As shown, the voltage domain requirements are as follows: Figure 20 As shown.

[0165] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0166] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A monochromator with one frame and one color, characterized in that, include: The timing synchronization control unit (1), as the control center, is connected to the monochrome circuit via electrical connection lines. led The array unit (2), the integrated optical coupling and homogenizing unit (3), and the multi-mode output interface unit (4) are connected; monochrome led The array unit (2) is arranged in a matrix to provide multiple monochromatic lights of different wavelengths; An integrated optical coupling and homogenizing unit (3) is used to collimate, spatially modulate, fiber couple, and homogenize the monochromatic light; as well as The multi-mode output interface unit (4) is used to output processed monochromatic light in multiple modes such as direct imaging, fiber output or integrating sphere homogenization output. The timing synchronization control unit (1) includes: FPGA Main control unit (12) and led Drive array unit (13); The FPGA The main control unit (12) includes: The timing generation unit (121) is used to generate drive signals and trigger signals for nanosecond-level timing. A wavelength sequence storage unit (122) is used to store a wavelength switching sequence containing multiple wavelength points; and The light intensity modulation unit (123) uses digital-to-analog conversion technology to be used for each led The drive channel provides an independent reference voltage; The led The drive array unit (13) contains multiple independent led Drive channel, each led The drive channel is used to independently drive the monochrome. led One of the corresponding array units (2) led chip.

2. The monochromator with one frame and one color according to claim 1, characterized in that, The led The drive array unit (13) adopts a distributed constant current drive architecture, and each of the aforementioned... led The drive channel includes a current setting section, a constant current regulation section, and a high-speed switching section.

3. The monochromator with one frame and one color according to claim 2, characterized in that, The current setting section includes a digital-to-analog converter, which is connected to the [specific device / system] via a serial peripheral interface bus. FPGA The main control unit (12) is used to receive digital code values ​​and output the reference voltage.

4. The monochromator with one frame and one color according to claim 2, characterized in that, The constant current regulation section includes: Current sampling resistor; Constant current control MOSFET ;as well as Operational amplifier; The non-inverting input of the operational amplifier receives the reference voltage, the inverting input is connected to one end of the current sampling resistor, and the output is connected to the constant current control. MOSFET The gate; The constant current control MOSFET The drain is connected to the corresponding led The cathode and source of the chip are connected to the other end of the current sampling resistor.

5. The monochromator with one frame and one color according to claim 4, characterized in that, The high-speed switch section includes a high-speed switch. MOSFET The high-speed switch MOSFET The drain is connected to the current sampling resistor away from the constant current control. MOSFET One end has its source grounded, and its gate connected to the digital isolator. FPGA Main control unit (12).

6. The monochromator with one frame and one color according to claim 1, characterized in that, The led The drive array unit (13) is connected to the serial bus via the FPGA The main control unit (12) is connected. The serial bus includes a serial data line, a shift clock line, a latch clock line and an output enable line. Control instructions are shifted into the shift register chain in the form of serial data, and the latch clock line enables the synchronous output of all channels.

7. The monochromator with one frame and one color according to claim 1, characterized in that, The led The drive array unit (13) also includes an overcurrent protection circuit, each of which led The drive channel is equipped with an overcurrent comparator, and the outputs of all overcurrent comparators are connected to the aforementioned via wired-AND logic. FPGA Main control unit (12).

8. The monochromator with one frame and one color according to claim 1, characterized in that, The integrated optical coupling and homogenizing unit (3) includes an optical path delay compensation module, which includes multiple fiber optic reels driven by stepper motors to adjust the length of the corresponding fiber to compensate for the time delay difference of light of different wavelengths in the fiber.

9. The monochromator with one frame and one color according to claim 8, characterized in that, The integrated optical coupling and homogenizing unit (3) also includes led Collimation unit, spatial light modulation unit, fiber optic coupling unit, integrating sphere homogenizing unit, and optical switching unit; The optical switching unit includes two high-speed motorized optical shutters and a rotatable planar mirror, used to switch between different output modes.

10. The monochromator with one frame and one color according to claim 1, characterized in that, The multi-mode output interface unit (4) includes a direct imaging output unit, an optical fiber output unit, an integrating sphere homogenizing output unit, and an extended output unit; The direct imaging output unit integrates a filter wheel, and the fiber optic output unit has multiple standard fiber optic interfaces.

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