FPGA multi-channel weak signal parallel phase-locked amplification method and FPGA processing device

Abstract

A method and device for parallel phase-locked loop (PLL) amplification of weak signals using FPGA multi-channel parallel processing is disclosed, relating to the field of digital signal processing technology. This method aims to improve the parallel processing capability of FPGA processing devices in extracting useful signals from strong noise backgrounds with limited hardware costs. In this method, the FPGA processing device generates a shared phase reference for all channels by employing a globally unified sampling counter and modulo-N addressing, and distributes it using a broadcast bus. This saves the significant logic resources consumed by traditional schemes that require independent configuration of phase accumulators for each channel. Furthermore, by utilizing a general-purpose logic array to implement integer multiplication instead of relying on a limited number of dedicated DSP hard cores, the parallel processing capability of the FPGA processing device in extracting useful signals from strong noise backgrounds is improved with limited hardware costs.

Description

Technical Field

[0001] This application relates to the field of digital signal processing technology, and in particular to an FPGA multi-channel parallel lock-in amplification method for weak signals and an FPGA processing device. Background Technology

[0002] In fields such as weak signal detection, communication, and radar detection, lock-in amplification or quadrature demodulation techniques are typically used to extract useful signals of specific frequencies from strong noise backgrounds. Field-programmable gate arrays (FPGAs) have become the mainstream hardware platform for implementing these lock-in amplification and quadrature demodulation algorithms due to their programmability and parallel processing advantages.

[0003] The generation and subsequent processing of sine and cosine signals in FPGAs typically employs Direct Digital Synthesis (DDS) combined with hardware multipliers. In this approach, the FPGA first uses a high-bit-width phase accumulator to continuously accumulate the frequency control word under clock drive to generate a real-time phase address. Then, it queries the read-only memory storing waveform data based on this address to obtain the sine or cosine value. After acquiring the reference signal, it further utilizes a dedicated DSP hard core unit integrated within the FPGA chip (such as a DSP48 Slice) or a multiplication circuit constructed with numerous logic gates to multiply the reference signal and the input signal point-by-point, thereby completing the signal mixing process.

[0004] However, since each channel's DDS phase accumulation logic requires an independent adder chain, and the mixing operation is highly dependent on the limited number of DSP hard cores inside the FPGA, this high resource-consuming architecture may exhaust the FPGA's logic units and DSP resources when a large number of parallel signal channels need to be processed simultaneously. This reduces the FPGA's ability to extract useful signals from a strong noise background in parallel processing with limited hardware costs. Summary of the Invention

[0005] This application provides a method for parallel phase-locked amplification of weak signals using FPGA multi-channel parallel lock-in amplifier and an FPGA processing device, which improves the parallel processing capability of FPGA processing device to extract useful signals from strong noise background with limited hardware cost.

[0006] In a first aspect, a method for parallel phase-locked loop amplification of weak signals using an FPGA multi-channel is provided. The method is characterized by its application to an FPGA processing device, comprising: the FPGA processing device pre-programming an integerized sine reference sequence and a cosine reference sequence of length N into the block memory within the FPGA to obtain an orthogonal lookup table, where N is a fixed number of sampling points within a single signal cycle; the FPGA processing device starting a global sampling counter to continuously count the sampling clock synchronized with the real-time sampling data to obtain a global sampling index; the FPGA processing device performing a modulo-N operation on the global sampling index to obtain a loop read address; and in each clock cycle, the FPGA processing device utilizing the loop read address... The address reads the current integer sine reference value and integer cosine reference value from the quadrature lookup table; the FPGA processing device synchronously distributes the integer sine reference value and integer cosine reference value to each parallel signal channel to be processed via the broadcast bus; after each parallel signal channel independently receives the input real-time sampled data, the FPGA processing device uses the programmable logic units in the FPGA logic array to perform parallel integer multiplication operations on the real-time sampled data with the received integer sine reference value and integer cosine reference value respectively, to obtain the in-phase component data stream and the quadrature component data stream; the FPGA processing device outputs the phase-locked amplification result based on the in-phase component data stream and the quadrature component data stream.

[0007] By adopting the above technical solution, the FPGA processing device generates a phase reference shared by all channels using a globally unified sampling counter and modulo-N addressing, and distributes it using a broadcast bus. This saves the significant logic resources consumed by traditional solutions that require independent configuration of phase accumulators for each channel. Simultaneously, by utilizing a general-purpose logic array to implement integer multiplication instead of relying on a limited number of dedicated DSP hard cores, the parallel processing capability of the FPGA processing device to extract useful signals from strong noise backgrounds is improved within a limited hardware cost.

[0008] In conjunction with some embodiments of the first aspect, in some embodiments, the step of the FPGA processing device synchronously distributing integerized sine reference values ​​and integerized cosine reference values ​​to each parallel signal channel to be processed via a broadcast bus specifically includes: the FPGA processing device constructing a tree-structured multi-stage pipeline register as a broadcast bus; the FPGA processing device transmitting the integerized sine reference values ​​and integerized cosine reference values ​​read from the orthogonal lookup table through the broadcast bus in a step-by-step manner, distributing the driving load, and finally reaching each parallel signal channel.

[0009] By adopting the above technical solution, under massively parallel channels, the FPGA processing device decomposes a huge fan-out load into multiple controllable small fan-out loads by constructing a tree-structured multi-level pipeline register, and uses a step-by-step transmission method to reduce long-distance wiring delay.

[0010] In conjunction with some embodiments of the first aspect, in some embodiments, before the step of the FPGA processing device using programmable logic units in the FPGA logic array to perform parallel integer multiplication operations on the real-time sampled data with the received integerized sine reference value and integerized cosine reference value respectively to obtain the in-phase component data stream and the quadrature component data stream after each parallel signal channel independently receives the input real-time sampled data, the method further includes: the FPGA processing device performing delay alignment processing on the real-time sampled data, wherein the delay cycle number of the delay alignment processing is equal to the number of clock cycles consumed by the transmission of the integerized sine reference value and the integerized cosine reference value in the multi-stage pipeline register.

[0011] By adopting the above technical solution, the FPGA processing device ensures that the sampled data involved in the multiplication operation and the reference value are strictly corresponding in time when the input real-time sampled data are processed with a delay that is exactly equal to the pipeline delay, thereby reducing timing mismatch problems.

[0012] In conjunction with some embodiments of the first aspect, in some embodiments, the step of the FPGA processing device pre-hardening an integerized sine reference sequence and a cosine reference sequence of length N into the block memory inside the FPGA to obtain an orthogonal lookup table specifically includes: based on the quarter-cycle symmetry characteristic of the sine function, the FPGA processing device constructs a quarter-cycle integerized sample sequence of length N / 4; and hardens the quarter-cycle integerized sample sequence into the block memory as a compressed orthogonal lookup table.

[0013] By adopting the above technical solution, the FPGA processing device constructs a more efficient storage strategy based on the inherent symmetry of trigonometric functions, storing only a quarter-cycle of the sample sequence. This saves on-chip storage resources without changing the phase resolution, allowing the limited memory to serve higher resolution reference signals or more functional modules, thereby improving the resource utilization efficiency of the FPGA processing device.

[0014] In conjunction with some embodiments of the first aspect, in some embodiments, the step of the FPGA processing device reading the integerized sine reference value and integerized cosine reference value of the current moment from the orthogonal lookup table using a cyclic read address in each clock cycle specifically includes: the FPGA processing device determining the quadrant interval in the complete signal cycle based on the high-order bits of the cyclic read address; the FPGA processing device performing address mapping transformation on the low-order bits of the cyclic read address according to the quadrant interval to obtain the physical read address for the compressed orthogonal lookup table; and the FPGA processing device performing sign bit correction on the data read from the compressed orthogonal lookup table according to the quadrant interval to obtain the integerized sine reference value and integerized cosine reference value.

[0015] By adopting the above technical solution, the FPGA processing device resolves quadrants, transforms addresses, and corrects signs through bit operations and logical judgments, thereby enabling it to restore the complete orthogonal reference value from the compressed lookup table in real time within each clock cycle using fewer logic resources.

[0016] In conjunction with some embodiments of the first aspect, in some embodiments, before the step of the FPGA processing device pre-hardening an integerized sine reference sequence and a cosine reference sequence of length N into the block memory inside the FPGA to obtain an orthogonal lookup table, the method further includes: the FPGA processing device determining a fixed number of sampling points N based on a preset proportional relationship between the frequency of the target signal to be detected and the frequency of the sampling clock.

[0017] By adopting the above technical solution, the FPGA processing device ensures that a fixed number of sample points are collected within one signal cycle by setting the sampling frequency to an integer multiple of the signal frequency. This establishes a definite and stable phase relationship between the internally digitally generated reference sequence and the external physical signal, thereby reducing phase drift and measurement errors caused by frequency mismatch.

[0018] In conjunction with some embodiments of the first aspect, in some embodiments, the step of the FPGA processing device outputting phase-locked amplification results based on the in-phase component data stream and the quadrature component data stream specifically includes: performing accumulation filtering processing on the in-phase component data stream and the quadrature component data stream of each parallel signal channel respectively, and extracting the DC component when the accumulation length reaches a preset threshold; calculating the amplitude and phase information of the weak signal of each channel based on the DC component.

[0019] By adopting the above technical solution, the FPGA processing device can extract the DC component that reaches the preset threshold by accumulating and filtering the in-phase and quadrature components respectively, with a lower hardware resource cost.

[0020] In a second aspect, embodiments of this application provide an FPGA processing device, which includes: one or more processors and a memory; the memory is coupled to the one or more processors, and the memory is used to store computer program code, the computer program code including computer instructions, and the one or more processors call the computer instructions to cause the FPGA processing device to perform the method described in the first aspect and any possible implementation thereof.

[0021] Thirdly, embodiments of this application provide a computer program product containing instructions that, when the computer program product is run on an FPGA processing device, cause the FPGA processing device to perform the method described in the first aspect and any possible implementation thereof.

[0022] Fourthly, embodiments of this application provide a computer-readable storage medium including instructions that, when executed on an FPGA processing device, cause the FPGA processing device to perform the method described in the first aspect and any possible implementation thereof.

[0023] It is understood that the FPGA processing device provided in the second aspect, the computer program product provided in the third aspect, and the computer storage medium provided in the fourth aspect are all used to execute the methods provided in the embodiments of this application. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods, and will not be repeated here.

[0024] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0025] 1. FPGA processing devices generate a shared phase reference for all channels by employing a globally unified sampling counter and modulo-N addressing, and distribute it using a broadcast bus. This saves the significant logic resources required by traditional solutions that require independent configuration of phase accumulators for each channel. Furthermore, by utilizing a general-purpose logic array to implement integer multiplication instead of relying on a limited number of dedicated DSP hard cores, the parallel processing capability of FPGA devices to extract useful signals from strong noise backgrounds is improved within a limited hardware cost.

[0026] 2. In massively parallel channels, FPGA processing devices decompose a huge fan-out load into multiple controllable small fan-out loads by constructing a tree-structured multi-stage pipeline register, and reduce long-distance wiring delay by using a step-by-step transmission method.

[0027] 3. Based on the inherent symmetry of trigonometric functions, the FPGA processing device has constructed a more efficient storage strategy, storing only a quarter-cycle of the sample sequence. This saves on-chip storage resources without changing the phase resolution, allowing the limited memory to serve higher resolution reference signals or more functional modules, thereby improving the resource utilization efficiency of the FPGA processing device. Attached Figure Description

[0028] Figure 1 This is a flowchart illustrating an FPGA multi-channel parallel phase-locked amplification method for weak signals in an embodiment of this application.

[0029] Figure 2 This is another flowchart illustrating an FPGA multi-channel weak signal parallel lock-in amplification method in this application.

[0030] Figure 3 This is a schematic diagram of the physical device structure of an FPGA processing device in the embodiments of this application. Detailed Implementation

[0031] The terminology used in the following embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to include the plural expressions as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this application refers to and includes any or all possible combinations of one or more of the listed items.

[0032] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0033] This application provides a method for parallel phase-locked amplification of weak signals using FPGA multi-channel parallel lock-in amplifier and an FPGA processing device, which improves the parallel processing capability of FPGA processing device to extract useful signals from strong noise background with limited hardware cost.

[0034] Please see Figure 1 This is a flowchart illustrating a method for parallel phase-locked loop amplification of weak signals using an FPGA in an embodiment of this application.

[0035] S101. The FPGA processing device pre-fuses an integerized sine reference sequence and a cosine reference sequence of length N into the block memory inside the FPGA to obtain an orthogonal lookup table.

[0036] In this context, an FPGA processing device refers to a semiconductor device integrating a programmable logic array, block memory, clock management unit, and input / output unit, used to execute the FPGA multi-channel weak signal parallel phase-locked amplification method of this invention. The integerized sine and cosine reference sequences of length N refer to two integer arrays obtained by sampling a complete period (0 to 2π) of sine and cosine waves at N discrete phase points, and multiplying the floating-point amplitude of each sample point by a scaling factor and rounding. Block memory is a high-speed static random access memory resource provided within the FPGA chip. An orthogonal lookup table is a data structure formed by storing the above integer sequences in block memory, establishing a mapping relationship between discrete phase indices and orthogonal signal amplitudes. The fixed number of sampling points N represents the number of data points collected within an ideal period of the signal to be detected; the value of the fixed number of sampling points determines the phase resolution of the reference sequence.

[0037] Specifically, this step is typically performed during the FPGA hardware design phase or power-on initialization phase. Its purpose is to transform the computationally intensive real-time generation of trigonometric functions into a less resource-intensive memory retrieval process. Before performing the firmware installation, the FPGA processing device needs to determine the fixed number of sampling points N. The value of N is not arbitrarily chosen, but determined by a preset proportional relationship between the frequency of the target signal to be detected and the frequency of the sampling clock. For example, if the frequency of the target signal to be detected is... The sampling clock frequency is The fixed number of sampling points N is then set to This ensures that N data points are collected within one signal cycle.

[0038] After determining N, the FPGA processing device calculates the ideal sine and cosine values ​​of N sampling points within a complete cycle (0 to 2π) offline, based on the frequency of the target signal to be detected and the frequency of the sampling clock. Then, these floating-point numbers in the range [-1.0, 1.0] are multiplied by a scaling factor (e.g., ...). , (Data width) and rounded to the nearest integer. These are signed integers. Ultimately, these integer sequences are compiled into the FPGA's configuration file (bitstream file) and automatically written to the designated block memory when the FPGA is powered on and configured, forming a fixed-content orthogonal lookup table.

[0039] In some embodiments, the data solidification process in this step can be implemented in several ways: Optionally, the contents of the block memory can be directly defined using initialization statements in the design code of a hardware description language (such as Verilog or VHDL). In this way, the reference sequence data becomes part of the FPGA logic design, and the memory initialization file is automatically generated and solidified by the logic synthesis tool. Optionally, a standard memory initialization file (such as .coe or .mif format) can also be generated in the FPGA design project using an external script (such as MATLAB or Python script), and then the file can be associated with the specified block memory IP core in the FPGA synthesis tool, with the tool completing the data filling when generating the bitstream.

[0040] In some embodiments, to further optimize the utilization efficiency of the FPGA's internal block memory, especially in scenarios with high phase resolution requirements leading to very large N values ​​(e.g., tens of thousands of points), the quarter-cycle symmetry of the sine and cosine functions can be utilized. Specifically, the FPGA processing device only needs to construct and store an integer sample sequence of a quarter-cycle of length N / 4 (e.g., the interval from 0 to π / 2). Since the cosine waveform is a π / 2 phase shift of the sine waveform, only a quarter-cycle sequence of a sine wave needs to be stored, and the complete sine and cosine reference values ​​can be simultaneously reconstructed through address transformation and logical operations. In this way, the storage resource requirement can be reduced to 1 / 4 or even 1 / 8 of the original, thereby reserving storage resources for more parallel channels or other functional modules without sacrificing phase resolution. At this time, the orthogonal lookup table obtained in S101 is a compressed orthogonal lookup table.

[0041] S102, The FPGA processing device starts the global sampling counter to continuously count the sampling clock synchronized with the real-time sampling data to obtain the global sampling index.

[0042] In this context, the global sampling counter refers to a unified counter logic unit within the FPGA processing device, shared by all parallel channels. The sampling clock is the clock signal that drives the analog-to-digital converter (ADC) to sample data; each valid edge corresponds to the generation of a sampled data point. Synchronization with real-time sampling data means that the counter's counting behavior is strictly consistent with the input clock cycle of the sampled data. The global sampling index is the counter's count value at any given moment; it uniquely identifies the total number of clock cycles elapsed from the start of sampling to the current moment, serving as a globally unified timestamp.

[0043] Specifically, this step is initiated synchronously when the FPGA processing device begins receiving digital sampled data streams from external multi-channel analog signals converted by an ADC. A global sampling counter automatically increments by one on each valid edge of the sampling clock (e.g., the rising edge). Because this counter is unique and globally shared, its output global sampling index provides an unbiased, fully synchronized absolute time base for all parallel processing channels. This design avoids configuring independent phase accumulators for each channel, thus saving logic resources such as adders and registers within the FPGA.

[0044] In some embodiments, the counter startup and synchronization in this step can be implemented in several ways: Optionally, the counter can be designed in a free-running mode, where it starts counting from zero when the first sampling clock arrives after the FPGA processing device is reset and continues to accumulate, suitable for applications where the initial phase is not strictly required. Optionally, the counter can also be designed in a triggered startup mode, where the counter is normally in a hold state, and only starts counting on the effective edge of the next sampling clock after the FPGA processing device receives an external synchronization trigger signal (such as a synchronization pulse from a laser pulse or an external event). This method enables the phase of the internally generated reference signal to be more accurately locked with the external physical event.

[0045] S103, the FPGA processing device performs a modulo-N operation on the global sampling index to obtain the loop read address.

[0046] Modulo-N operation refers to dividing an integer by N and taking the remainder, with the result ranging from 0 to N-1. The cyclic read address refers to the address signal obtained after the modulo-N operation, used to address the orthogonal lookup table. This address cyclically changes between 0 and N-1 as the global sampling index increases.

[0047] Specifically, this step is performed within each sampling clock cycle to convert the linearly growing global sampling index generated in the previous stage into a periodically repeating address signal. Since the orthogonal lookup table only stores N sampling points for one cycle, while the global sampling index grows indefinitely, it is necessary to fold the index value back into the address space [0, N-1] using modulo N operations. In this way, regardless of how much time has passed globally, the generated loop read address can accurately point to the corresponding phase point within a complete waveform cycle.

[0048] In some embodiments, the modulo-N operation in this step can be implemented in several ways: Optionally, when N is an integer power of 2 (e.g., N=1024), the modulo-N operation can be greatly simplified to a bit truncation operation on the global sampling index, and the FPGA processing device only needs to extract the low-order bits of the global sampling index. Using bits as the loop read address eliminates the need for any arithmetic logic, reducing resource consumption and latency. Optionally, when N is not a power of 2, the FPGA processing device can employ a remainder counter circuit that counts synchronously with the global sampling index. When the remainder counter is less than N-1, the remainder counter is incremented by 1; otherwise, it is set to 0.

[0049] S104. In each clock cycle, the FPGA processing device uses the loop read address to read the integerized sine reference value and integerized cosine reference value of the current time from the quadrature lookup table.

[0050] Here, the current time refers to the point in time defined by the global sampling index corresponding to this clock cycle. The integerized sine reference value and the integerized cosine reference value are integer data representing the two quadrature components of the phase at this moment, read from the quadrature lookup table.

[0051] Specifically, in each sampling clock cycle, the loop read address generated in the previous step is sent to the address port of the quadrature lookup table (i.e., block memory). Based on this address, the block memory finds the entry corresponding to the address in its internally stored data within one clock cycle and outputs its content. In order to obtain both sine and cosine values ​​simultaneously, the data port width of the block memory is configured to be the sum of two integer bit widths, so that a pair of quadrature reference values ​​can be obtained simultaneously in a single read operation.

[0052] In some embodiments, data reading in this step can be implemented in several ways: Optionally, a single wide-port block memory can be used, which stores concatenated sine and cosine values ​​(e.g., a 32-bit data word, with the high 16 bits being the sine value and the low 16 bits being the cosine value) in one address unit, allowing all data to be obtained in a single read. Optionally, two independent block memories can also be used, one storing a sine table and the other storing a cosine table. The cyclic read address is simultaneously sent to the address ports of both memories, and the two memories output their respective reference values ​​in parallel. This approach may offer greater flexibility in physical layout.

[0053] In some embodiments, if step S101 employs a compressed orthogonal lookup table scheme that stores a quarter-cycle sample sequence, the data reading process in this step will be adjusted accordingly. Specifically, the FPGA processing device first determines the quadrant interval (first, second, third, or fourth quadrant) of the current moment within the complete signal period based on the high-order bits (usually the highest 2 bits) of the cyclic read address. Subsequently, according to the determined quadrant interval, the low-order bits of the cyclic read address are transformed by address mapping, for example, by inversion or invariance, to generate the physical read address for the compressed orthogonal lookup table. Finally, the FPGA processing device corrects the sign bit of the data read from the compressed orthogonal lookup table according to the quadrant interval (e.g., inversion or invariance), and uses trigonometric relationships such as sin(x+π / 2)=cos(x) to reconstruct the complete and correct integerized sine reference value and integerized cosine reference value for the current moment.

[0054] S105, the FPGA processing device synchronously distributes the integerized sine reference value and the integerized cosine reference value to each parallel signal channel to be processed via the broadcast bus.

[0055] In the context of FPGAs, a broadcast bus refers to a signal path structure that replicates and distributes data signals from a single source to multiple target logic units. Synchronous distribution means that the data signal arrives at all target units within the same clock cycle to meet the timing requirements of subsequent parallel operations. Parallel signal channels refer to a set of logic processing units within the FPGA that are independently partitioned to process each input signal.

[0056] Specifically, the unique integerized sine and cosine reference values ​​output from the orthogonal lookup table by the FPGA processing device need to be synchronously provided to hundreds or thousands of parallel signal channels for multiplication operations in the next stage. The FPGA processing device connects the integerized sine and cosine reference values ​​obtained from the lookup table to a signal network with high fan-out capability. This network replicates and routes these two reference values ​​to the input of each parallel signal channel. It should be noted that the synchronous distribution described here aims to ensure that the reference phase received by all channels has a uniform time base. In practical applications, depending on the system clock frequency and channel size, this distribution process can achieve low-skew transmission through the FPGA's global clock network, or employ a pipelined transmission structure that guarantees timing certainty, thereby ensuring the phase accuracy of the phase-locked amplification in subsequent multiplication steps.

[0057] In some embodiments, broadcast distribution in this step can be implemented in several ways to ensure timing convergence: Optionally, for cases with a small number of channels, the automatic fan-out optimization capability of the FPGA synthesis tool can be directly utilized, with the tool automatically copying registers and constructing a routing network to balance the delay of each path. Optionally, for massively parallel channels, the FPGA processing device can also explicitly instantiate one or more intermediate register layers in the code, manually constructing a data distribution network to decompose a high-fan-out node into multiple low-fan-out nodes, thereby reducing the driving load of a single signal and improving timing stability under high-speed clocks.

[0058] S106. After each parallel signal channel independently receives the input real-time sampled data, the FPGA processing device uses the programmable logic units in the FPGA logic array to perform parallel integer multiplication operations on the real-time sampled data with the received integerized sine reference value and integerized cosine reference value, respectively, to obtain the in-phase component data stream and the quadrature component data stream.

[0059] In this context, FPGA logic array refers to the array structure that constitutes the main body of an FPGA chip, consisting of a large number of programmable logic units. Programmable logic units typically refer to basic logic building blocks such as lookup tables and flip-flops. Parallel integer multiplication refers to all channels independently completing multiplication operations within the same clock cycle, utilizing the logic array resources. In-phase component data stream (I-component) refers to the result sequence obtained by multiplying real-time sampled data with a sine reference sequence. Quadrature component data stream (Q-component) refers to the result sequence obtained by multiplying real-time sampled data with a cosine reference sequence.

[0060] Specifically, within each parallel signal channel, the FPGA processing device instantiates two integer multipliers. One multiplier multiplies the real-time sampled data input to that channel with a broadcast global integerized sine reference value, while the other multiplier multiplies the same real-time sampled data with a broadcast global integerized cosine reference value. The key here is that the multipliers are implemented using the FPGA's general-purpose programmable logic units, rather than calling dedicated DSP hard cores. This makes the architecture independent of the limited number of DSP resources on the FPGA chip, thus enabling support for a larger scale of parallel processing channels. Multiplication operations for all channels are completed within the same clock cycle, producing multiple parallel in-phase and quadrature data streams.

[0061] S107, the FPGA processing device outputs phase-locked amplification results based on in-phase component data streams and quadrature component data streams.

[0062] The results of lock-in amplification typically include the amplitude and phase information of the measured signal.

[0063] Specifically, this step involves low-pass filtering and post-processing the mixed data to extract the final useful information. The in-phase and quadrature component data streams generated by mixing contain useful signal components near the DC frequency and high-frequency unwanted components near twice the reference frequency. The FPGA processing device performs low-pass filtering on each in-phase and quadrature data stream to remove high-frequency components and noise, extracting its DC component. Subsequently, based on the extracted in-phase DC component (… ) and orthogonal DC components ( ), through the amplitude calculation formula (e.g. ) and phase calculation formula (e.g. This allows the amplitude and phase of the original weak signal to be demodulated.

[0064] In the above embodiments, the FPGA processing device generates a phase reference shared by all channels by employing a globally unified sampling counter and modulo-N addressing, and distributes it using a broadcast bus. This saves the significant logic resources required by traditional solutions where each channel needs an independently configured phase accumulator. Simultaneously, by utilizing a general-purpose logic array to implement integer multiplication instead of relying on a limited number of dedicated DSP hard cores, the parallel processing capability of the FPGA processing device to extract useful signals from a noisy background is improved within a limited hardware cost.

[0065] However, directly connecting a single signal source to hundreds or thousands of target cells in the above embodiments results in high fan-out. At high-speed clocks, this massive drive load increases signal delay, makes routing more difficult, and may cause timing violations, making it difficult for the FPGA processing device to operate stably. Especially when the number of parallel channels is large or the FPGA operating frequency is high, the broadcast method in the above embodiments becomes a performance bottleneck for the entire design.

[0066] Please see Figure 2 This is another flowchart illustrating an FPGA multi-channel weak signal parallel phase-locked amplification method in this application.

[0067] S201. The FPGA processing device pre-fuses an integerized sine reference sequence and a cosine reference sequence of length N into the block memory inside the FPGA to obtain an orthogonal lookup table.

[0068] S202, The FPGA processing device starts the global sampling counter to continuously count the sampling clock synchronized with the real-time sampling data to obtain the global sampling index.

[0069] S203, the FPGA processing device performs a modulo-N operation on the global sampling index to obtain the loop read address.

[0070] S204. In each clock cycle, the FPGA processing device uses the cyclic read address to read the integerized sine reference value and integerized cosine reference value of the current time from the quadrature lookup table.

[0071] Step S201 is similar to step S101, step S202 is similar to step S102, step S203 is similar to step S103, and step S204 is similar to step S104, so they will not be repeated here.

[0072] The S205 FPGA processing device constructs a tree-structured multi-stage pipelined register as a broadcast bus.

[0073] In this context, a tree structure refers to a hierarchical data distribution network where signals originate from a root node and are distributed level by level to multiple nodes in the next level, eventually reaching the leaf nodes at the end. A multi-stage pipelined register refers to a register (flip-flop) inserted at each level or key node of this tree structure to temporarily store and pause the transmitted signals.

[0074] Specifically, this step is a high-performance physical implementation of a broadcast bus. To address the issue of significant capacitance and routing delays caused by a single signal source driving a large load (high fan-out), leading to timing non-convergence, FPGA processing devices do not use straight connections but instead construct a hierarchical distribution tree. Integerized sine and cosine reference values ​​obtained from an orthogonal lookup table serve as the root of the tree, initially driving a few registers in the first level. Each first-level register then drives several registers in the next level, and so on, expanding level by level until the leaf registers of the final level directly drive the multipliers of each parallel signal channel. This structure decomposes a large fan-out load into multiple smaller fan-out loads, ensuring that the driving pressure on each level's registers remains within a controllable range.

[0075] In some embodiments, the tree structure construction in this step can be implemented in several ways: Optionally, a symmetrical binary tree or quadtree structure can be constructed, with a fixed fan-out number for each level node, resulting in a regular structure that is easy to design and timing analysis. Optionally, an asymmetrical tree structure related to physical layout can also be constructed. FPGA synthesis and placement / routing tools can intelligently group channels with similar physical locations into a group, driven by a single branch, based on the physical location of each parallel channel on the chip, thereby optimizing the overall routing length and power consumption.

[0076] S206 The FPGA processing device reads the integerized sine reference value and integerized cosine reference value from the orthogonal lookup table, transmits them step by step through the broadcast bus, distributes the driving load, and finally reaches each parallel signal channel.

[0077] In this context, step-by-step transmission refers to the process where data signals are transmitted from one register to the next in a tree-like structure, requiring one clock cycle. The signal propagates forward step by step, much like in an assembly line. Distributed load control is a key advantage of this architecture, as each register only needs to drive a few registers in the next level, thus avoiding timing bottlenecks.

[0078] Specifically, this step describes the dynamic data transfer process within the tree structure constructed by S205. When an integerized sine or cosine reference value is read from the lookup table, it is first latched by the root node's register. In the next clock cycle, the value is passed to all registers in the first level and latched. In the following clock cycle, it is passed to all registers in the second level. This process continues until, after D clock cycles (D being the depth of the tree), the reference value finally reaches all leaf node registers and is provided to the multiplier. Although a fixed delay of D clock cycles is introduced, once this pipeline structure is filled, a new set of reference values ​​arrives at all channels every subsequent clock cycle, thus achieving high-throughput data distribution and improving timing convergence issues under high-speed clocks.

[0079] In some embodiments, the timing transmission control in this step can be implemented in several ways: Optionally, uncontrolled free transmission can be used, where all pipeline registers unconditionally latch the data from the previous stage in each clock cycle, suitable for scenarios with continuous data flow. Optionally, a valid bit and backpressure handshake mechanism can be added to the pipeline, where each stage register only latches data when the data from the previous stage is valid and the next stage is ready to receive it. This allows for finer-grained flow rate control of the data flow to accommodate potential pauses in the back-end processing units.

[0080] S207. After each parallel signal channel independently receives the input real-time sampled data, the FPGA processing device uses the programmable logic units in the FPGA logic array to perform parallel integer multiplication operations on the real-time sampled data with the received integerized sine reference value and integerized cosine reference value, respectively, to obtain the in-phase component data stream and the quadrature component data stream.

[0081] The S208 FPGA processing device outputs phase-locked amplification results based on in-phase component data streams and quadrature component data streams.

[0082] Steps S207 and S106 are similar, and steps S208 and S107 are similar, so they will not be described again here. However, it is important to note that before performing the multiplication operation in S207, the FPGA processing device needs to perform delay alignment processing on the input real-time sampled data. Specifically, to compensate for the D clock cycle delay introduced by the reference value transmission in the tree-like pipeline, the real-time sampled data of each parallel signal channel cannot be directly fed into the multiplier, but needs to first pass through a delay unit of depth D (such as a shift register or a small FIFO). This ensures that at the multiplier input, the real-time sampled data and its corresponding reference value are strictly aligned in time, thereby guaranteeing the correct phase relationship of the lock-in amplification.

[0083] In the above embodiments, a higher-performance solution is proposed to address the timing bottlenecks that the basic architecture may encounter during large-scale parallel implementation. In a large-scale parallel channel, the FPGA processing device decomposes a large fan-out load into multiple controllable small fan-out loads by constructing a tree-structured multi-stage pipeline register, and reduces long-distance routing latency by using a step-by-step transmission method. Furthermore, a data delay alignment mechanism is employed to perform delay alignment processing on the input real-time sampled data, ensuring that the delay is exactly equal to the pipeline delay. This ensures that during multiplication operations, the sampled data participating in the operation and the reference value are strictly time-corresponding, thereby reducing timing mismatch problems.

[0084] The above describes a method for parallel phase-locked loop amplification of weak signals using an FPGA in an embodiment of this application. The following describes an exemplary FPGA processing device 300 provided in an embodiment of this application.

[0085] Figure 3 This is an exemplary hardware structure diagram of the FPGA processing device 300 provided in an embodiment of this application. In some embodiments, the FPGA processing device 300 is a computer device. The computer device includes a processor, a memory, and a network interface connected via a system bus. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database of the computer device stores data. The network interface of the computer device is used to communicate with other external terminals or servers via a network connection. In some embodiments, the network interface can be a wired network interface; in some embodiments, the network interface can also be a wireless network interface. When the computer program is executed by the processor, it implements an FPGA multi-channel weak signal parallel phase-locked amplification method according to an embodiment of this application.

[0086] Those skilled in the art will understand that Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0087] In some embodiments of this application, a computer-readable storage medium is also provided, including instructions that, when executed on the FPGA processing device 300, cause the FPGA processing device 300 to perform an FPGA multi-channel weak signal parallel phase-locked amplification method according to an embodiment of this application.

[0088] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

[0089] As used in the above embodiments, depending on the context, the term "when..." can be interpreted as meaning "if...", "after...", "in response to determining...", or "in response to detecting...". Similarly, depending on the context, the phrase "when determining..." or "if (the stated condition or event) is interpreted as meaning "if determining...", "in response to determining...", "when (the stated condition or event) is detected", or "in response to detecting (the stated condition or event)".

[0090] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0091] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A method for parallel lock-in amplification of weak signals using FPGA multi-channel circuits, characterized in that, Applied to FPGA processing devices, the method includes: The FPGA processing device pre-stores an integerized sine reference sequence and a cosine reference sequence of length N into the block memory inside the FPGA to obtain an orthogonal lookup table, where N is the fixed number of sampling points in a single signal period; The FPGA processing device starts a global sampling counter to continuously count the sampling clock synchronized with the real-time sampling data, thereby obtaining a global sampling index; The FPGA processing device performs a modulo-N operation on the global sampling index to obtain the loop read address; In each clock cycle, the FPGA processing device uses the loop read address to read the integerized sine reference value and integerized cosine reference value of the current time from the orthogonal lookup table; The FPGA processing device synchronously distributes the integerized sine reference value and the integerized cosine reference value to each parallel signal channel to be processed via a broadcast bus; After each of the parallel signal channels independently receives the input real-time sampled data, the FPGA processing device uses the programmable logic units in the FPGA logic array to perform parallel integer multiplication operations on the real-time sampled data with the received integerized sine reference value and the integerized cosine reference value, respectively, to obtain in-phase component data stream and quadrature component data stream; The FPGA processing device outputs phase-locked amplification results based on the in-phase component data stream and the quadrature component data stream.

2. The method according to claim 1, characterized in that, The step of the FPGA processing device synchronously distributing the integerized sine reference value and the integerized cosine reference value to each parallel signal channel to be processed via a broadcast bus specifically includes: The FPGA processing device constructs a tree-structured multi-stage pipelined register as the broadcast bus; The FPGA processing device reads the integerized sine reference value and the integerized cosine reference value from the orthogonal lookup table, transmits them step by step through the broadcast bus, distributes the driving load, and finally reaches each of the parallel signal channels.

3. The method according to claim 2, characterized in that, Before the step of the FPGA processing device using programmable logic units in the FPGA logic array to perform parallel integer multiplication operations on the real-time sampled data with the received integerized sine reference value and the integerized cosine reference value respectively after each of the parallel signal channels independently receives the input real-time sampled data, and before obtaining the in-phase component data stream and the quadrature component data stream, the method further includes: The FPGA processing device performs delay alignment processing on the real-time sampled data. The number of delay cycles for the delay alignment processing is equal to the number of clock cycles consumed by the transmission of the integerized sine reference value and the integerized cosine reference value in the multi-stage pipeline register.

4. The method according to claim 1, characterized in that, The step of the FPGA processing device pre-programming an integerized sine reference sequence and a cosine reference sequence of length N into the block memory inside the FPGA to obtain an orthogonal lookup table specifically includes: Based on the quarter-period symmetry property of the sine function, the FPGA processing device constructs a quarter-period integer sample sequence with a length of N / 4; The quarter-cycle integerized sample sequence is stored in the block memory as a compressed orthogonal lookup table.

5. The method according to claim 4, characterized in that, The step of the FPGA processing device reading the integerized sine reference value and integerized cosine reference value at the current time from the orthogonal lookup table using the cyclic read address in each clock cycle specifically includes: The FPGA processing device determines the quadrant interval in the complete signal cycle at the current moment based on the high-order bits of the cyclic read address. The FPGA processing device performs address mapping transformation on the low-order bits of the cyclic read address according to the quadrant interval to obtain the physical read address for the compressed orthogonal lookup table. The FPGA processing device performs sign bit correction on the data read from the compressed orthogonal lookup table according to the quadrant interval to obtain the integerized sine reference value and the integerized cosine reference value.

6. The method according to claim 1, characterized in that, Before the step of pre-writing the integerized sine reference sequence and cosine reference sequence of length N into the block memory inside the FPGA to obtain an orthogonal lookup table, the method further includes: The FPGA processing device determines the fixed number of sampling points N based on a preset ratio between the frequency of the target signal to be detected and the frequency of the sampling clock.

7. The method according to claim 1, characterized in that, The step of the FPGA processing device outputting the phase-locked amplification result based on the in-phase component data stream and the quadrature component data stream specifically includes: The in-phase component data stream and the quadrature component data stream of each of the parallel signal channels are respectively subjected to accumulation and filtering processing, and the DC component is extracted when the accumulation length reaches a preset threshold. The amplitude and phase information of the weak signals in each channel are calculated based on the DC component.

8. An FPGA processing device, characterized in that, The FPGA processing device includes: one or more processors and a memory; the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code including computer instructions, and the one or more processors call the computer instructions to cause the FPGA processing device to perform the method as described in any one of claims 1-7.

9. A computer program product containing instructions, characterized in that, When the computer program product is run on the FPGA processing device, the FPGA processing device performs the method as described in any one of claims 1-7.

10. A computer-readable storage medium comprising instructions, characterized in that, When the instructions are executed on the FPGA processing device, the FPGA processing device performs the method as described in any one of claims 1-7.

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