Method for manufacturing a circuit board and circuit board

Abstract

The embodiment of the application provides a manufacturing method of a circuit board, which comprises the following steps: setting a glue guide groove in communication with an independent via pad on a grounding layer, so that the independent via pad is connected with a peripheral empty area to a certain extent. In the process of laminating, glue flow and exhaust are promoted, and the phenomenon of bubbles appearing at the negative pad position of the independent via pad in the grounding layer area is effectively avoided. The elimination of bubbles significantly improves the mechanical strength of the pad. When the product is subjected to external forces such as vibration and impact, the probability of problems such as pad falling off and loose connection is reduced, the risk of electrical connection interruption is reduced, and the product can work normally and stably. At the same time, the elimination of bubbles also avoids the problem of increased contact resistance caused by the destruction of the electrical performance of the pad by the bubbles, reduces the attenuation and distortion phenomenon in the signal transmission process, improves the signal quality and stability of the product, and thus comprehensively improves the reliability of the product.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and in particular to a method for manufacturing a circuit board and a circuit board. Background Technology

[0002] In the design of printed circuit boards (PCBs) for battery and power products, copper thickness is a critical parameter. Currently, the copper thickness of PCBs for these products is generally set at 70µm or higher. Higher copper thickness can, to some extent, meet the product's requirements for high current carrying capacity, effectively reduce circuit resistance losses, and decrease heat generation, thereby improving the overall performance and efficiency of the product. However, higher copper thickness also brings a series of process challenges, among which the issue of independent via pads in the ground plane area is particularly prominent.

[0003] In PCB manufacturing, independent via pads are crucial structures for achieving electrical connections between different layers. The ground plane, as a critical reference potential and signal return path in the circuit, directly impacts the electrical performance and reliability of its independent via pads. When the copper thickness reaches 70µm or more, the independent via pads in the ground plane area are susceptible to the effects of excessive copper thickness during soldering and other processes, resulting in air bubbles at negative pad locations. The presence of these air bubbles severely affects product reliability. Firstly, air bubbles reduce the mechanical strength of the pads, making them prone to detachment and loosening when subjected to vibration, impact, or other external forces, leading to electrical connection interruptions and product malfunction. Secondly, air bubbles also damage the electrical properties of the pads, increasing contact resistance and causing signal attenuation and distortion during transmission, affecting signal quality and stability.

[0004] Therefore, there is an urgent need to design a circuit board manufacturing method that can solve the problem of air bubbles at the negative pad position of the independent via pad in the grounding layer area caused by the large copper thickness in current battery and power supply products, and improve the reliability of the products. Summary of the Invention

[0005] This application provides a method for manufacturing a circuit board and a circuit board that can solve the problem of air bubbles at the negative pad position of the independent via pad in the grounding layer area caused by the large copper thickness in current battery and power products, thereby improving product reliability.

[0006] This application provides a method for manufacturing a circuit board, including: Obtain circuit design data, which includes a ground plane and has independent via pads; The circuit design data is modified to include a conductive groove on the ground layer, which is connected to the independent via pad. An exposure film is made according to the revised circuit design data, and the exposure film forms a window at the position corresponding to the adhesive guide groove and the independent via pad; The exposure film is pressed onto the copper layer to be processed and etched to create independent via pads and adhesive guide grooves corresponding to the opening on the copper layer. The bottom of the adhesive guide groove has a copper layer.

[0007] In some embodiments, the copper layer has a minimum etch pitch, and the width of the adhesive groove is half of the minimum etch pitch.

[0008] In some embodiments, the thickness of the copper layer to be processed is 100 μm, the minimum etching spacing is 150 μm, and the width of the adhesive guide groove is 75 μm.

[0009] In some embodiments, the copper layer to be processed is the copper layer of the core board, and after pressing the exposure film onto the copper layer to be processed and etching it, the process further includes: A dielectric layer and copper foil are sequentially disposed on both sides of the core board; The core board and the dielectric layers and copper foils on both sides of the core board are bonded together, and the dielectric layers partially fill the independent via pads and adhesive grooves of the copper layer.

[0010] In some embodiments, during the lamination process, air in the individual via pads of the copper layer is discharged through the adhesive guide groove.

[0011] In some embodiments, there are multiple independent via pads in the grounding layer, and the multiple independent via pads are interconnected through the adhesive guide groove.

[0012] This application embodiment also provides a circuit board including a copper layer, on which independent via pads and adhesive guide grooves are provided. The adhesive guide grooves are connected to the independent via pads, and the bottom of the adhesive guide grooves has a copper layer.

[0013] In some embodiments, the copper layer has a minimum etch pitch, and the width of the adhesive groove is half of the minimum etch pitch.

[0014] In some embodiments, the copper layer thickness is 100µm, the minimum etch spacing is 150µm, and the width of the adhesive channel is 75µm.

[0015] In some embodiments, the copper layer is the copper layer of the core board, and the circuit board further includes a dielectric layer and copper foil disposed sequentially on both sides of the core board, wherein the dielectric layer partially fills the independent via pads and adhesive grooves.

[0016] The circuit board manufacturing method provided in this application provides a method for connecting independent via pads to a ground plane by setting adhesive guide grooves that communicate with the independent via pads to a certain extent. During lamination and other processes, this promotes adhesive flow and venting, effectively preventing air bubbles from forming at the negative pad positions of the independent via pads in the ground plane area. Eliminating air bubbles significantly improves the mechanical strength of the pads, reducing the probability of pad detachment and loosening when the product is subjected to external forces such as vibration and impact, lowering the risk of electrical connection interruption, and ensuring the product's normal and stable operation. Simultaneously, eliminating air bubbles also avoids increased contact resistance caused by air bubbles damaging the electrical performance of the pads, reducing attenuation and distortion during signal transmission, improving signal quality and stability, and thus comprehensively enhancing the product's reliability. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a first process diagram illustrating a method for manufacturing a circuit board according to an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of the second process of a circuit board manufacturing method according to an embodiment of this application.

[0020] Figure 3 This is a first structural schematic diagram of a circuit board according to an embodiment of this application.

[0021] Figure 4 This is a schematic diagram of the second structure of the circuit board according to an embodiment of this application.

[0022] Figure 5 This is a schematic diagram of the third structure of the circuit board according to an embodiment of this application.

[0023] Figure 6 This is a schematic diagram of the fourth structure of the circuit board according to an embodiment of this application.

[0024] Figure 7 This is a fifth structural schematic diagram of the circuit board according to an embodiment of this application.

[0025] Among them, 100 is the circuit board; 10 is the circuit design data; 11 is the ground layer; 20 is the independent via pad; 30 is the adhesive guide groove; 40 is the exposure film; 50 is the copper layer; 60 is the dielectric layer; and 70 is the copper foil. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0027] This application provides a method for manufacturing a circuit board 100, referring to... Figure 1 , Figure 1 This is a first flowchart illustrating a method for manufacturing a circuit board 100 according to an embodiment of this application. The manufacturing method includes the following steps: S101, Obtain circuit design data 10, the circuit design data 10 includes a ground plane 11, the ground plane 11 has independent via pads 20; S102, Modify the circuit design data 10, and set a guide groove 30 on the ground layer 11. The guide groove 30 is connected to the independent via pad 20. S103, based on the modified circuit design data 10, an exposure film 40 is made, and the exposure film 40 forms a window at the position corresponding to the adhesive guide groove 30 and the independent via pad 20. S104, the exposure film 40 is pressed onto the copper layer 50 to be processed and etched to make independent via pads 20 and adhesive guide grooves 30 corresponding to the opening on the copper layer 50. The bottom of the adhesive guide groove 30 has the copper layer 50.

[0028] Please refer to the above. Figures 3 to 7 , Figure 3 This is a first structural schematic diagram of the circuit board 100 according to an embodiment of this application. Figure 4 This is a schematic diagram of the second structure of the circuit board 100 according to an embodiment of this application. Figure 5 This is a schematic diagram of the third structure of the circuit board 100 according to an embodiment of this application. Figure 6 This is a schematic diagram of the fourth structure of the circuit board 100 according to an embodiment of this application. Figure 7 This is a fifth structural schematic diagram of the circuit board 100 according to an embodiment of this application.

[0029] As an example, in the fabrication of the circuit board, firstly, in step S101, the customer's original circuit design data 10 is obtained. This circuit design data 10 includes a ground layer 11, on which independent via pads 20 are distributed. This original circuit design data 10 is the basis for subsequent modifications and fabrication, defining the basic electrical connections and layout structure of the circuit board 100. Subsequently, in step S102, the circuit design data 10 is modified by adding a tree-branch-like adhesive channel 30 to the obtained ground layer 11. The adhesive channel 30 is connected to the independent via pads 20. The purpose of the adhesive channel 30 is to connect the independent via pads 20 surrounded by the ground layer 11 in series, forming a tree-branch and fruit-like structure. Subsequently, in step S103, based on the modified circuit design data 10, an exposure film 40 for the current layer of the circuit board 100 is fabricated. The exposure film 40 forms windows at positions corresponding to the adhesive channel 30 and the independent via pads 20. These openings are key areas for forming the corresponding structures of the copper layer in subsequent etching processes. The precision and positional accuracy of the openings directly affect the forming quality of the adhesive guide grooves 30 and independent via pads 20 on the final circuit board 100. Finally, in step S104, the prepared exposure film 40 is pressed onto the copper layer 50 to be processed (thick copper surface), and then the film is exposed, so that the opening positions of the exposure film 40 form specific exposure areas. Then, an etching / film stripping scheme is used for etching. During the etching process, the shapes of the independent via pads 20 and adhesive guide grooves 30 gradually take shape. Due to the reasonable width design of the adhesive guide groove 30, a certain thickness of copper layer 50 is still retained at the bottom of the adhesive guide groove 30 after etching, and it is not completely etched away. In this way, a circuit with adhesive guide grooves 30 is formed, and the independent via pads 20 on the circuit are interconnected with the adhesive guide grooves 30.

[0030] The method for manufacturing the circuit board 100 provided in this application embodiment involves setting a guide groove 30 on the ground layer 11 that communicates with the independent via pad 20, thereby connecting the independent via pad 20 to a certain extent with the surrounding open area. During lamination and other processes, this promotes adhesive flow and venting, effectively preventing air bubbles from forming at the negative pad positions of the independent via pads in the ground layer area. The elimination of air bubbles significantly improves the mechanical strength of the pads, reducing the probability of pad detachment and loosening when the product is subjected to external forces such as vibration and impact, lowering the risk of electrical connection interruption, and ensuring the product can operate normally and stably. Simultaneously, the elimination of air bubbles also avoids the problem of increased contact resistance caused by air bubbles damaging the electrical performance of the pads, reducing attenuation and distortion during signal transmission, improving the signal quality and stability of the product, and thus comprehensively enhancing the reliability of the product.

[0031] Furthermore, this example employs a partial copper reduction scheme. During the design of the adhesive guide groove 30, parameters such as its width are carefully designed to ensure that the copper layer 50 at the bottom of the groove is not completely etched away. This ensures that the overall copper thickness of the power layer meets the product's high current carrying capacity requirements while also allowing for the design of fine lines / hole spacing within the thick copper plate of the circuit board. This satisfies the product's electrical performance requirements while providing more space for customer circuit design, making the design of the circuit board 100 more flexible and adaptable to the needs of different customers and application scenarios.

[0032] In some examples, the copper layer 50 has a minimum etch pitch, and the width of the adhesive trench 30 is half of the minimum etch pitch.

[0033] As an example, the width of the adhesive channel 30 is set to half the minimum etching pitch of the copper layer 50. This precise dimensional design is based on a deep understanding and accurate control of the etching process. During etching, the forming accuracy of the adhesive channel 30 is ensured, so that its width is neither too large, wasting copper and affecting circuit layout, nor too small, causing poor gas and adhesive conduction. The precisely sized adhesive channel 30 can form a stable and effective gas and adhesive conduction channel. During processes such as lamination, gas and adhesive can flow and be discharged smoothly through the adhesive channel, greatly improving the efficiency of gas and adhesive conduction and effectively solving the problem of air bubbles at the negative pad position of the independent via pad in the ground layer area caused by the large copper thickness.

[0034] In some examples, the copper layer 50 to be processed is 100um thick, the minimum etch pitch is 150um, and the width of the adhesive groove 30 is 75um.

[0035] As an example, the width of the adhesive guide groove 30 needs to be determined based on the copper thickness and the etching capability of the PCB manufacturer's etching lines. If the copper layer 50 to be processed is 100µm thick with a minimum etching pitch of 150µm, the width of the adhesive guide groove 30 should be 75µm. For instance, if it is known that the minimum etching pitch for a 100µm thick copper layer in factory A is 150µm, then the width of the adhesive guide groove 30 should be designed to be 75µm. This design ensures that the copper at the location of the adhesive guide groove 30 is not completely etched away, avoiding impact on the original trace layout, while also achieving the intended function of the adhesive guide groove 30. On the ground layer 11, the path of the adhesive guide groove 30 is carefully planned according to its 75µm width. The adhesive guide groove 30 adopts a meandering shape, orderly connecting the individual via pads 20 surrounded by the ground copper layer to form a complete air and adhesive guiding network. During the planning process, the overall circuit layout and signal transmission requirements are fully considered to ensure that the addition of the adhesive guide groove 30 will not negatively impact circuit performance.

[0036] The width of the adhesive guide groove 30 is set to half the minimum etching pitch of the copper layer 50, i.e., 75µm. This precise dimensional design fully considers the characteristics and requirements of the etching process. During etching, it ensures the forming accuracy of the adhesive guide groove 30, making its width uniform and preventing inconsistencies. The precisely sized adhesive guide groove 30 forms a stable and efficient gas and adhesive guiding channel. During processes such as lamination, gas and adhesive can flow and exit smoothly through the adhesive guide groove, effectively avoiding problems caused by improper groove dimensions and reducing various defects caused by issues with the adhesive guide groove 30, such as bubbles and short circuits, thus ensuring the smooth progress of the circuit board 100 manufacturing process.

[0037] In some examples, reference Figure 2 , Figure 2 This is a schematic diagram of the second process of manufacturing a circuit board 100 according to an embodiment of this application. The copper layer 50 to be processed is the copper layer 50 of the core board. After pressing the exposure film 40 onto the copper layer 50 to be processed and etching it, the process further includes: S105, a dielectric layer 60 and a copper foil 70 are sequentially disposed on both sides of the core board; S106, perform pressing to bond the core board and the dielectric layer 60 and copper foil 70 on both sides of the core board together. The dielectric layer 60 partially fills the independent via pads 20 and adhesive grooves 30 of the copper layer 50.

[0038] As an example, the copper layer 50 to be processed is the copper layer 50 of the core board. The prepared dielectric layer 60 and copper foil 70 are cut according to requirements to ensure that their dimensions match the core board. The surface flatness and cleanliness of the dielectric layer 60 and copper foil 70 are checked, and any impurities or scratches need to be treated. When fabricating the circuit board 100, firstly, the exposure film 40 is pressed onto the copper layer 50 of the core board and etched. Then, the dielectric layer 60 and copper foil 70 are placed sequentially on both sides of the core board, with the dielectric layer 60 covering the etched copper layer 50 and partially filling the independent via pads 20 and adhesive channels 30. Subsequently, the core board with the dielectric layer 60 and copper foil 70 set is pressed together, so that the core board and the dielectric layer 60 and copper foil 70 on both sides of the core board are bonded together, with the dielectric layer 60 partially filling the independent via pads 20 and adhesive channels 30 of the copper layer 50. For example, a core board with the dielectric layer 60 and copper foil 70 set is placed in a laminator. Suitable cushioning material is placed between the upper and lower plates of the laminator to ensure uniform pressure distribution during lamination. The laminator's temperature, pressure, and time parameters are controlled. First, a preheating stage is performed to gradually soften the dielectric layer 60 material. Then, the pressure is gradually increased to ensure tight adhesion between the core board, dielectric layer 60, and copper foil 70. During lamination, gas in the independent via pads 20 and adhesive channels 30 can be smoothly discharged along the adhesive channels 30, and the dielectric layer 60 material can fully fill the spaces of the independent via pads 20 and adhesive channels 30, forming a good electrical connection and mechanical structure. After lamination, the temperature and pressure are slowly reduced, and the fabricated circuit board 100 is removed.

[0039] In this example, after etching the core board, a dielectric layer 60 is applied and then laminated, causing the dielectric layer 60 to partially fill the independent via pads 20 and adhesive guide grooves 30 of the copper layer 50. The well-designed adhesive guide grooves 30 provide a smooth flow channel for gas and dielectric layer 60 material. During lamination, gas can be discharged promptly, and dielectric layer 60 material can be fully filled, avoiding defects such as bubbles and voids caused by gas residue and insufficient filling, greatly improving the manufacturing quality of the circuit board 100. The lamination process forms a tightly bonded whole between the core board, dielectric layer 60, and copper foil 70, enhancing the mechanical strength of the circuit board 100. The filling effect of the dielectric layer 60 can disperse stress, reducing circuit board deformation and damage caused by external forces or thermal expansion and contraction, thereby extending the service life of the circuit board 100 and improving product stability and reliability.

[0040] In some examples, reference Figure 6 and Figure 7 , Figure 6 This is a schematic diagram of the fourth structure of the circuit board 100 according to an embodiment of this application. Figure 7 This is a fifth structural schematic diagram of the circuit board 100 in an embodiment of this application. During the lamination process, air in the independent via pads 20 of the copper layer 50 is discharged through the adhesive guide groove 30.

[0041] As an example, during the lamination process, air in the independent via pads 20 of the copper layer 50 is discharged through the adhesive channel 30, thus avoiding defects such as bubbles and voids caused by residual air. This improves the insulation performance and mechanical strength of the circuit board 100, ensures the reliability and stability of the circuit, greatly improves the manufacturing quality of the circuit board 100, and reduces the defect rate.

[0042] In some examples, reference Figure 3 , Figure 3 This is a first structural schematic diagram of the circuit board 100 in an embodiment of this application. There are multiple independent via pads 20 on the ground layer 11, and the multiple independent via pads 20 are interconnected through the adhesive guide groove 30.

[0043] As an example, there are multiple independent via pads 20 on the ground layer 11, which are interconnected by adhesive guide grooves 30. This arrangement provides a unified venting channel for air. During lamination, air can be smoothly discharged along the adhesive guide grooves 30, avoiding accumulation within individual via pads 20. This significantly reduces lamination defects caused by residual air and improves the yield rate of the circuit board 100. Furthermore, since the adhesive guide grooves 30 connect multiple independent via pads 20, the dielectric material can flow and fill more evenly under pressure. This makes the distribution of dielectric material around each individual via pad 20 more consistent, reducing local stress concentration problems caused by uneven filling, and improving the structural stability and reliability of the circuit board 100.

[0044] This application provides a circuit board 100. The circuit board 100 is prepared by the above-described method for manufacturing circuit board 100. The circuit board 100 can be applied to equipment or systems such as power supplies, control systems, and frequency converters.

[0045] refer to Figures 3 to 5 , Figure 3 This is a first structural schematic diagram of the circuit board 100 according to an embodiment of this application. Figure 4 This is a schematic diagram of the second structure of the circuit board 100 according to an embodiment of this application. Figure 5 This is a schematic diagram of the third structure of the circuit board 100 according to an embodiment of this application.

[0046] The circuit board 100 includes a copper layer 50, on which independent via pads 20 and adhesive guide grooves 30 are provided. The adhesive guide grooves 30 are connected to the independent via pads 20, and the bottom of the adhesive guide grooves 30 has the copper layer 50.

[0047] As an example, the circuit board 100 includes a copper layer 50. On the copper layer 50, independent via pads 20 and adhesive guide grooves 30 are rationally arranged according to the circuit connection requirements. The adhesive guide grooves 30 are connected to the independent via pads 20. The independent via pads 20 are used to achieve electrical connections between different signal layers and the bottom layer. Their shape is circular, and their diameter is determined according to the width of the connected signal lines and the current carrying capacity. For example, in areas where high-speed signal lines need to be connected, the diameter of the independent via pads 20 is appropriately increased to ensure good electrical connection performance. The adhesive guide grooves 30 adopt a layout combining straight lines and broken lines, connecting adjacent independent via pads 20 in series to form a complete air and adhesive guiding network. The bottom of the adhesive guide grooves 30 is ensured to retain the complete copper layer 50 to guarantee the electrical continuity and mechanical strength of the circuit board 100.

[0048] In this example, the circuit board 100, by setting the adhesive guide groove 30 to connect with the independent via pad 20, provides a smooth air venting channel. Air can be smoothly discharged along the adhesive guide groove 30, avoiding accumulation within individual independent via pads 20, greatly reducing lamination defects caused by residual air, and improving the yield rate of the circuit board 100. The design of the adhesive guide groove 30 allows the dielectric material to flow and fill more evenly during the lamination process. The dielectric material can fill around the independent via pad 20 along the adhesive guide groove 30, avoiding local accumulation or absence of dielectric material. This helps improve the electrical and mechanical performance of the circuit board 100 and reduces problems such as signal interference and insufficient structural strength caused by uneven dielectric filling.

[0049] In some examples, reference Figure 6 and Figure 7 , Figure 6 This is a schematic diagram of the fourth structure of the circuit board 100 according to an embodiment of this application. Figure 7 This is a fifth structural schematic diagram of the circuit board 100 according to an embodiment of this application. The copper layer 50 is the copper layer 50 of the core board. The circuit board 100 also includes a dielectric layer 60 and a copper foil 70 sequentially disposed on both sides of the core board. The dielectric layer 60 partially fills the independent via pads 20 and the adhesive guide grooves 30.

[0050] As an example, copper layer 50 is the copper layer 50 of the core board. The prepared dielectric layer 60 and copper foil 70 are cut according to requirements to ensure that their dimensions match the core board. The surface flatness and cleanliness of dielectric layer 60 and copper foil 70 are checked, and any impurities or scratches need to be treated. When fabricating circuit board 100, firstly, the exposure film 40 is pressed onto the copper layer 50 of the core board and etched. Then, dielectric layer 60 and copper foil 70 are placed sequentially on both sides of the core board, with dielectric layer 60 covering the etched copper layer 50 and partially filling the independent via pads 20 and adhesive channels 30. Subsequently, the core board with dielectric layer 60 and copper foil 70 set is pressed together, so that the core board and the dielectric layer 60 and copper foil 70 on both sides of the core board are bonded together, with dielectric layer 60 partially filling the independent via pads 20 and adhesive channels 30 of copper layer 50. For example, a core board with the dielectric layer 60 and copper foil 70 set is placed in a laminator. Suitable cushioning material is placed between the upper and lower plates of the laminator to ensure uniform pressure distribution during lamination. The laminator's temperature, pressure, and time parameters are controlled. First, a preheating stage is performed to gradually soften the dielectric layer 60 material. Then, the pressure is gradually increased to ensure tight adhesion between the core board, dielectric layer 60, and copper foil 70. During lamination, gas in the independent via pads 20 and adhesive channels 30 can be smoothly discharged along the adhesive channels 30, and the dielectric layer 60 material can fully fill the spaces of the independent via pads 20 and adhesive channels 30, forming a good electrical connection and mechanical structure. After lamination, the temperature and pressure are slowly reduced, and the fabricated circuit board 100 is removed.

[0051] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0052] The manufacturing method of the circuit board 100 and the circuit board 100 provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for manufacturing a circuit board, characterized in that, include: Obtain circuit design data, which includes a ground plane and has independent via pads; The circuit design data is modified to include a conductive groove on the ground layer, which is connected to the independent via pad. An exposure film is made according to the revised circuit design data, and the exposure film forms a window at the position corresponding to the adhesive guide groove and the independent via pad; The exposure film is pressed onto the copper layer to be processed and etched to create independent via pads and adhesive guide grooves corresponding to the opening on the copper layer. The bottom of the adhesive guide groove has a copper layer.

2. The manufacturing method according to claim 1, characterized in that, The copper layer has a minimum etch spacing, and the width of the adhesive guide groove is half of the minimum etch spacing.

3. The manufacturing method according to claim 2, characterized in that, The thickness of the copper layer to be processed is 100µm, the minimum etching spacing is 150µm, and the width of the adhesive guide groove is 75µm.

4. The manufacturing method according to any one of claims 1 to 3, characterized in that, The copper layer to be processed is the copper layer of the core board. After pressing the exposure film onto the copper layer to be processed and etching it, the process further includes: A dielectric layer and copper foil are sequentially disposed on both sides of the core board; The core board and the dielectric layers and copper foils on both sides of the core board are bonded together, and the dielectric layers partially fill the independent via pads and adhesive grooves of the copper layer.

5. The manufacturing method according to claim 4, characterized in that, During the lamination process, air in the independent via pads of the copper layer is discharged through the adhesive guide groove.

6. The manufacturing method according to any one of claims 1 to 3, characterized in that, The grounding layer has multiple independent via pads, and these multiple independent via pads are interconnected through the adhesive guide groove.

7. A circuit board, characterized in that, It includes a copper layer, on which independent via pads and adhesive guide grooves are provided. The adhesive guide grooves are connected to the independent via pads, and the bottom of the adhesive guide grooves has a copper layer.

8. The circuit board according to claim 7, characterized in that, The copper layer has a minimum etch spacing, and the width of the adhesive guide groove is half of the minimum etch spacing.

9. The circuit board according to claim 8, characterized in that, The copper layer thickness is 100µm, the minimum etching spacing is 150µm, and the width of the adhesive guide groove is 75µm.

10. The circuit board according to any one of claims 7 to 9, characterized in that, The copper layer is the copper layer of the core board. The circuit board also includes a dielectric layer and copper foil disposed sequentially on both sides of the core board. The dielectric layer partially fills the independent via pads and adhesive grooves.

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