Semiconductor device and method of forming the same

Abstract

Embodiments of the present application provide a semiconductor device and a method of forming the same. The semiconductor device can include, in a cross-sectional view, a first epitaxial source / drain region, a first nanostmcture on a sidewall of the first epitaxial source / drain region, and a first gate structure surrounding the first nanostmcture. The first gate structure can include, in the cross-sectional view, a first dielectric layer surrounding the first nanostmcture and a first gate electrode surrounding the first dielectric layer. A first portion of the first dielectric layer can be on a top surface of the first nanostmcture, and in the cross-sectional view, the first portion of the first dielectric layer can include a substantially planar top surface. A second portion of the first dielectric layer can be on a bottom surface of the first nanostmcture, and in the cross-sectional view, the second portion of the first dielectric layer can include a protruding bottom surface.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum part size, allowing more components to be integrated into a given area. As the semiconductor industry further moves towards increasing device density, improving performance, and reducing costs, manufacturing and design challenges have led to stacked device configurations, such as stacked transistor devices including complementary field-effect transistors (CFETs). However, with the reduction in minimum part size, additional features are introduced. Summary of the Invention

[0004] According to one aspect of the embodiments of this application, a semiconductor device is provided, comprising: a first epitaxial source / drain region, wherein the first epitaxial source / drain region is doped with a dopant, wherein the first epitaxial source / drain region includes a first portion and a second portion, wherein the first portion has a first dopant concentration, and wherein the second portion has a second dopant concentration different from the first dopant concentration; a first nanostructure located on a sidewall of the first epitaxial source / drain region and in contact with the first portion of the first epitaxial source / drain region, wherein the second portion of the first epitaxial source / drain region is spaced apart from the first nanostructure by the first portion of the first epitaxial source / drain region; and a first gate structure surrounding the first nanostructure in a cross-sectional view, the first gate structure including a first dielectric layer surrounding the first nanostructure in a cross-sectional view, wherein a first portion of the first dielectric layer is located on a top surface of the first nanostructure, wherein the first portion of the first dielectric layer in a cross-sectional view includes a substantially flat top surface, and a second portion of the first dielectric layer is located on a bottom surface of the first nanostructure, wherein the second portion of the first dielectric layer in a cross-sectional view includes a protruding bottom surface; and the first gate structure including a first gate electrode surrounding the first dielectric layer in a cross-sectional view.

[0005] According to another aspect of the embodiments of this application, a method for forming a semiconductor device is provided, the method comprising: forming a first nanostructure over a semiconductor fin and forming a second nanostructure over the first nanostructure; growing a first epitaxial structure, wherein the first nanostructure and the second nanostructure are in contact with the first epitaxial structure, wherein the first epitaxial structure is doped with a dopant, wherein the first epitaxial structure includes a first portion adjacent to the first nanostructure and a second portion distant from the first nanostructure, wherein the first portion has a first dopant concentration and wherein the second portion has a second dopant concentration different from the first dopant concentration; forming a first etch stop layer over the first epitaxial structure; forming a first dielectric layer over the first etch stop layer; depositing a first gate dielectric layer surrounding the first nanostructure and a second gate dielectric layer surrounding the second nanostructure in a cross-sectional view, wherein the first gate dielectric layer and the second gate dielectric layer comprise a first material; forming a first protective layer between the first gate dielectric layer and the second gate dielectric layer, wherein the first protective layer comprises a second material; removing the first protective layer by an etching process, wherein during the etching process, a second etch rate of the second material is higher than a first etch rate of the first material; and forming a first gate electrode surrounding the first gate dielectric layer and the second gate dielectric layer in a cross-sectional view.

[0006] According to another aspect of the embodiments of this application, a method for forming a semiconductor device is provided, the method comprising: forming a first nanostructure and a second nanostructure over a semiconductor fin, wherein the first nanostructure is located between the second nanostructure and the semiconductor fin; depositing a first gate dielectric layer surrounding the first nanostructure and a second gate dielectric layer surrounding the second nanostructure in a cross-sectional view, wherein the first gate dielectric layer and the second gate dielectric layer comprise a first material; forming a first protective layer on the bottom surface of the first gate dielectric layer and forming a second protective layer on the bottom surface of the second gate dielectric layer, wherein the first protective layer and the second protective layer comprise a second material different from the first material; removing the first protective layer; forming a first gate electrode surrounding the first gate dielectric layer in a cross-sectional view; removing the second protective layer; and forming a second gate electrode surrounding the second gate dielectric layer in a cross-sectional view. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A perspective view of a stacked transistor device according to some embodiments is shown.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 17A and Figure 17B These are various views of intermediate stages in the fabrication of stacked transistor devices according to some embodiments. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0012] Various embodiments provide a semiconductor device and a method of forming the same. The semiconductor device may be a stacked transistor device comprising a vertically stacked upper transistor and a lower transistor. The upper transistor may include an upper gate structure surrounding an upper semiconductor nanostructure and an upper source / drain region located on the sidewalls of the upper semiconductor nanostructure. The upper gate structure may include an upper gate electrode and an upper gate dielectric layer. The lower transistor may include a lower gate structure surrounding a lower semiconductor nanostructure and a lower source / drain region located on the sidewalls of the lower semiconductor nanostructure. The lower gate structure may include a lower gate electrode and a lower gate dielectric layer. A sacrificial dielectric layer may be formed between adjacent upper semiconductor nanostructures. The sacrificial dielectric layer can reduce the risk of damage to the gate dielectric layer and the risk of residual lower gate electrode material between adjacent upper semiconductor nanostructures during the etching process of recessing the lower gate electrode. As a result, the performance and reliability of the stacked transistor device can be improved.

[0013] Figure 1 An example of a stacked transistor device 10 according to some embodiments is shown. Figure 1 This is a perspective view; for clarity, some features of the stacked transistor device are omitted. The stacked transistor device comprises multiple vertically stacked FETs. For example, the stacked transistor device may include a lower nanostructure FET 10L of a first device type (e.g., n-type or p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type or n-type). When the stacked transistor device is a complementary field-effect transistor (CFET), the second device type of the upper nanostructure FET 10U is opposite to the first device type of the lower nanostructure FET 10L. Both the upper nanostructure FET 10U and the lower nanostructure FET 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 serves as the channel region of the nanostructure FET. The lower semiconductor nanostructure 26L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is used for the upper nanostructure FET 10U. In other embodiments, the stacked transistor device can be applied to other types of transistors, such as nano-FETs and finFETs.

[0014] A gate dielectric layer 78 surrounds the corresponding semiconductor nanostructure 26. Gate electrodes 80 (including a lower gate electrode layer 80L and an upper gate electrode layer 80U) are located above the gate dielectric layer 78. Source / drain regions 62 (including a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U) are disposed on opposite sides of the gate dielectric layer 78 and the corresponding gate electrode 80. Depending on the context, each source / drain region 62 may individually or collectively refer to a source or drain. Isolation components (not shown) may be formed to separate selected regions within the source / drain regions 62 and / or selected gate electrodes 80.

[0015] Figure 1 Reference sections A-A' and B-B' are further illustrated. Reference section A-A' can be a vertical section parallel to the longitudinal axis of the semiconductor nanostructure 26 of the stacked transistor device 10 and along, for example, the current direction between the source / drain regions 62 of the stacked transistor device. Reference section B-B' can be a vertical section perpendicular to reference section A-A' and extending through the gate electrode 80. Figure 1 The reference sections A-A' and B-B' in the figures may correspond to the reference sections A-A' and B-B' shown in some subsequent figures.

[0016] Figures 2 to 12B It is a stacked transistor device according to some embodiments (including a lower nanostructure FET and an upper nanostructure FET, which may be similar to...) Figure 1 Various views of intermediate stages in the manufacturing process of the stacked transistor device 10 shown. Figure 2 It is a perspective view. Figures 3 to 17B yes Figure 2 A cross-sectional view of a portion of the structure shown. Figure 2 The invention provides a wafer including a substrate 20. The substrate 20 may be a semiconductor substrate formed of a crystalline semiconductor material. The substrate 20 may be doped (e.g., with p-type or n-type dopants) or undoped. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, or combinations thereof.

[0017] Semiconductor strips 28 are formed extending upward from substrate 20. Each semiconductor strip 28 includes a semiconductor fin 20' (a patterned portion of substrate 20) and a multilayer stack 22. The stacked components of the multilayer stack 22 are referred to hereinafter as nanostructures. Specifically, the multilayer stack 22 includes pseudo-nanostructures 24A and 24B, a lower semiconductor nanostructure 26L, a lower semiconductor nanostructure 26L', an upper semiconductor nanostructure 26U, and an upper semiconductor nanostructure 26U'. Pseudo-nanostructures 24A and 24B can also be collectively referred to as pseudo-nanostructure 24. The lower semiconductor nanostructures 26L, 26L', 26U, and 26U' can also be collectively referred to as semiconductor nanostructure 26.

[0018] The pseudo-nanostructure 24A is formed of a first semiconductor material, and the pseudo-nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials on the substrate 20. The first and second semiconductor materials have high etch selectivity towards each other. Therefore, in subsequent processes, the pseudo-nanostructure 24B can be removed at a faster rate than the pseudo-nanostructure 24A.

[0019] Semiconductor nanostructure 26 is formed of one or more third semiconductor materials. The third semiconductor material can be selected from candidate semiconductor materials of substrate 20. The lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U can be formed of the same semiconductor material or can be formed of different semiconductor materials. Furthermore, the first and second semiconductor materials of pseudo-nanostructure 24 have high etch selectivity relative to the third semiconductor material of semiconductor nanostructure 26. Therefore, pseudo-nanostructure 24 can be selectively removed in subsequent processes without significantly removing semiconductor nanostructure 26. In some embodiments, semiconductor nanostructure 26 is formed of silicon, pseudo-nanostructure 24A is formed of silicon-germanium, and pseudo-nanostructure 24B is formed of germanium or silicon-germanium with a higher percentage of germanium atoms than pseudo-nanostructure 24A.

[0020] The lower semiconductor nanostructure 26L can be used as the channel region of the lower nanostructure FET in a stacked transistor device. The upper semiconductor nanostructure 26U can be used as the channel region of the upper nanostructure FET in a stacked transistor device. The lower semiconductor nanostructure 26L' and the upper semiconductor nanostructure 26U', which are adjacent to (e.g., in contact with) the pseudo-nanostructure 24B, can be used for isolation and may or may not serve as the channel region of the stacked transistor device. Figure 2An upper nanostructure FET comprising two channel regions and a lower nanostructure FET comprising two channel regions are shown as examples. The upper nanostructure FET may include one channel region, three channel regions, or other numbers of channel regions. The lower nanostructure FET may include one channel region, three channel regions, or other numbers of channel regions. The pseudo-nanostructure 24B can then be replaced with an isolation structure defining the boundary between the lower and upper nanostructure FETs.

[0021] To form the semiconductor strip 28, first, second, and third semiconductor material layers (as shown and arranged above) can be deposited on the substrate 20. The first, second, and third semiconductor material layers can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Patterning processes can then be applied to the first, second, and third semiconductor material layers and the substrate 20 to define the semiconductor strip 28, which includes semiconductor fins 20', pseudo-nanostructures 24, and semiconductor nanostructures 26.

[0022] For example, the patterning process may include one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers are used as an etch mask for the patterning process to etch the first, second, and third semiconductor material layers and the substrate 20. Etching can be performed using any acceptable etch process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic.

[0023] STI region 34 is formed above substrate 20 and between adjacent semiconductor strips 28. STI region 34 may be located on the sidewalls of semiconductor fin 20'. STI region 34 may include dielectric pads and dielectric material on the dielectric pads. Each of the dielectric pads and dielectric material may include oxides (such as silicon oxide), nitrides (such as silicon nitride), etc., or combinations thereof. Formation of STI region 34 may include depositing a dielectric layer and performing planarization processes, such as chemical mechanical polishing (CMP), mechanical polishing, etc., to remove excess dielectric material. Deposition processes may include ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or combinations thereof. In some embodiments, STI region 34 includes silicon oxide formed by an FCVD process, followed by an annealing process. The dielectric pads and dielectric material are then recessed to define STI region 34 such that the upper portion of semiconductor strip 28 (including multilayer stack 22) protrudes higher than the remaining STI region 34.

[0024] After forming the STI region 34, a dummy gate stack 42 can be formed above and along the sidewall of the upper portion of the semiconductor strip 28 (the portion protruding above the STI region 34). Forming the dummy gate stack 42 may include forming a dummy dielectric layer 36 on the semiconductor strip 28 and forming a dummy gate layer 38 above the dummy dielectric layer 36. The dummy dielectric layer 36 may be formed of, for example, silicon oxide, silicon nitride, combinations thereof, and may be deposited or thermally grown according to acceptable techniques. The dummy gate layer 38 may be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, for example, by a CMP process. The material of the dummy gate layer 38 may be selected from the group including amorphous silicon, polysilicon, poly-SiGe, etc.

[0025] A mask layer 40' is formed over the planarized dummy gate layer 38. The mask layer 40' may include silicon nitride, silicon oxynitride, etc. The mask layer 40' can then be patterned using appropriate photolithography and etching processes to form the mask 40 (e.g., ...). Figure 3 (As shown), the dummy gate layer 38 and dummy dielectric layer 36 can then be patterned using mask 40. Mask 40, the remainder of dummy gate layer 38, and dummy dielectric layer 36 can be referred to as dummy gate stack 42.

[0026] exist Figure 3In this process, a gate spacer 44 and a source / drain recess 46 are formed. First, the gate spacer 44 is formed over the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and subsequently anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as CVD and ALD. The mask 40 and the gate spacer 44 can be used to protect the dummy gate layer 38 during subsequent etching processes.

[0027] Subsequently, source / drain recesses 46 are formed in semiconductor strip 28. The source / drain recesses 46 are formed by etching and can extend through the multilayer stack 22 and into semiconductor fin 20'. The bottom surface of the source / drain recesses 46 can be above, below, or flush with the top surface of the STI region 34 (not shown). During the etching process, gate spacers 44 and dummy gate stacks 42 mask portions of semiconductor strip 28. Etching can include a single etching process or multiple etching processes. A timed etching process can be used to stop etching the source / drain recesses 46 when a selected depth is reached.

[0028] exist Figure 4 In the process, pseudo-nanostructure 24A is partially removed, and pseudo-nanostructure 24B is completely removed. Then, internal spacers 54 and dielectric isolation layers 56 are formed. After the partial removal of pseudo-nanostructure 24A, the sidewalls of pseudo-nanostructure 24A can be recessed. Pseudo-nanostructures 24A and 24B can be removed by an appropriate etching process. The etching process can selectively remove material from pseudo-nanostructures 24A and 24B without significantly removing material from the upper semiconductor nanostructures 26U and 26U', the lower semiconductor nanostructures 26L and 26L', or the semiconductor fin 20'. The etching process can remove pseudo-nanostructure 24A at a slower rate than that removing pseudo-nanostructure 24B.

[0029] In embodiments where pseudo-nanostructure 24B is formed of germanium or silicon-germanium with a high percentage of germanium atoms, pseudo-nanostructure 24A is made of silicon-germanium with a low percentage of germanium atoms, and semiconductor nanostructure 26 is formed of germanium-free silicon, the etching process can be a dry etching process using an etchant (e.g., chlorine). Because the pseudo-gate stack 42 surrounds the sidewalls of semiconductor nanostructure 26 (see...), Figure 2 The dummy gate stack 41 can support the upper semiconductor nanostructures 26U and 26U', so that the upper semiconductor nanostructures 26U and 26' will not collapse when the dummy nanostructure 24B is completely removed.

[0030] Internal spacers 54 can be formed on the recessed sidewalls of the pseudo-nanostructure 24A. A dielectric isolation layer 56 can be formed in the space occupied by the pseudo-nanostructure 24B before it is removed. Subsequently, source / drain regions can be formed in the source / drain recess 46, and the pseudo-nanostructure 24A can be replaced with a corresponding gate structure. Internal spacers 54 can be used to isolate the subsequently formed source / drain regions from the subsequently formed gate structure. The dielectric isolation layer 56 can be used to isolate the upper semiconductor nanostructures 26U and 26U' from the lower semiconductor nanostructures 26L and 26L'.

[0031] The internal spacer 54 and dielectric isolation layer 56 can be formed by conformally depositing a suitable dielectric material within the source / drain trench 46, on the sidewalls of the pseudo-nanostructure 24A, and between the upper semiconductor nanostructure 26U' and the lower semiconductor nanostructure 26L'. The dielectric material can then be etched to remove excess portions. The dielectric material can be a hard dielectric material, such as a carbon-containing dielectric material like silicon carbonitride, silicon oxycarbonate, silicon carbonitride, etc. Other low dielectric constant (low-k) materials with a k-value less than about 3.5 can be used. The dielectric material can be formed using a suitable deposition process, such as ALD, CVD, etc. The etching of the dielectric material can be anisotropic or isotropic etching.

[0032] exist Figure 5A and Figure 5B In the middle, the lower source / drain region 62L, the upper epitaxial source / drain region 62U, the first contact etch stop layer (CESL) 66, the first interlayer dielectric (ILD) 68, the second CESL 70 and the second ILD 72 are formed in the source / source groove 46. Figure 5A Can be along with Figure 1 The reference section corresponding to the reference section A-A' shown is obtained. Figure 5B Can follow along with, as Figure 1 The reference section corresponding to the reference section B-B' shown is obtained.

[0033] A lower epitaxial source / drain region 62L is formed at the lower part of the source / source recess 46. The lower epitaxial source / drain region 62L contacts the lower semiconductor nanostructure 26L but not the upper semiconductor nanostructure 26U. The upper epitaxial source / drain region 62U contacts the upper semiconductor nanostructure 26U but not the lower semiconductor nanostructure 26L. The lower epitaxial source / drain region 62L contacts an internal spacer 54, which electrically insulates the lower epitaxial source / drain region 62L from the pseudo-nanostructure 24A. The upper epitaxial source / drain region 62U contacts an internal spacer 54, which electrically insulates the upper epitaxial source / drain region 62U from the pseudo-nanostructure 24A. In subsequent processes, the pseudo-nanostructure 24A will be replaced by a replacement gate.

[0034] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material can include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus or arsenic. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material can include silicon or silicon-germanium doped with p-type dopants such as boron or indium. The lower epitaxial source / drain region 62L can be in-situ doped and can be implanted or not implanted with the corresponding p-type or n-type dopants. During the epitaxial process of the lower epitaxial source / drain region 62L, the exposed surfaces (e.g., sidewalls) of the upper semiconductor nanostructures 26U and 26U' can be masked to prevent undesirable epitaxial growth on the upper semiconductor nanostructures 26U and 26'. After growing the lower epitaxial source / drain region 62L, the mask on the upper semiconductor nanostructures 26U and 26U' can be removed.

[0035] As a result of the epitaxial process used to form the lower epitaxial source / drain region 62L, the upper surface of the lower epitaxial source / drain region 62L has facets that extend laterally outward beyond the sidewalls of the multilayer stack 22 (not shown). In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these facets cause adjacent lower epitaxial source / drain regions 62L to merge. The lower epitaxial source / drain region 62L may include one or more layers of semiconductor material. In some embodiments, the lower epitaxial source / drain region 62L includes a first layer 63A in contact (e.g., on, adjacent to) the sidewalls of the lower semiconductor nanostructure 26L and a second layer 63B on the first layer 63A. The second layer 63B may be spaced apart (e.g., separated, away) from the lower semiconductor nanostructure 26L by the first layer 63A. The first layer 63A and the second layer 63B may be doped with the same dopant to different dopant concentrations.

[0036] The first CESL 66 and the first ILD 68 are formed above the lower epitaxial source / drain region 62L. The first CESL 66 can be formed from a dielectric material with high etch selectivity for etching the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 can be formed from a dielectric material that can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0037] The formation process may include depositing a conformal CESL layer, depositing material for the first ILD 68, followed by a planarization process and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the unetched conformal CESL layer. An anisotropic etching process is then performed to remove portions of the conformal CESL layer above the recessed first ILD 68. After the recess, the sidewalls of the upper semiconductor nanostructures 26U and 26U' are exposed.

[0038] Then, an upper epitaxial source / drain region 62U is formed on the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U can be epitaxially grown from the exposed surfaces of the upper semiconductor nanostructures 26U and 26U'. The material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials used to form the lower epitaxial source region 62L, depending on the selected conductivity type of the upper epitaxial source / drain region 62U. In embodiments where the stacked transistor device is a CFET, the conductivity type of the upper epitaxial source / drain region 62U can be opposite to that of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U can be doped in opposite directions to the lower epitaxial source / drain region 62L. Alternatively, the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L can have the same conductivity type. The upper epitaxial source / drain region 62U can be doped in situ and / or implanted with n-type or p-type dopants.

[0039] As a result of the epitaxial process used to form the upper epitaxial source / drain region 62U, the upper surface of the upper epitaxial source / drain region 62U has facets that extend laterally outward beyond the sidewalls of the multilayer stack 22 (not shown). In some embodiments, adjacent upper epitaxial source / drain regions 62U remain separated after the epitaxial process is completed. In other embodiments, these facets cause adjacent upper epitaxial source / drain regions 62U to merge. The upper epitaxial source / drain region 62U may include one or more layers of semiconductor material. In some embodiments, the upper epitaxial source / drain region 62U includes a first layer 65A in contact (e.g., on, adjacent to) the sidewalls of the upper semiconductor nanostructure 26U and a second layer 65B on the first layer 65A. The second layer 65B may be spaced apart (e.g., separated, far away) from the upper semiconductor nanostructure 26U by the first layer 65A. The first layer 65A and the second layer 65B may be doped with the same dopant to different dopant concentrations.

[0040] After forming the upper epitaxial source / drain region 62U, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods can be similar to those of the first CESL 66 and the first ILD 68, respectively. The formation process may include depositing a conformal CESL layer and the second ILD 72, and performing a planarization process to remove excess portions of the respective layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the mask 40 are substantially coplanar (within the range of process variations). In the illustrated embodiment, the mask 40 is retained after the removal process. In other embodiments, the mask 40 is removed, exposing the top surface of the dummy gate layer 38.

[0041] exist Figure 6A and Figure 6B In this process, mask 40 and dummy gate stack 42 are removed. Figure 6A The cross-sectional diagram in the middle can be compared with Figure 5A Corresponding to the cross-sectional view shown, Figure 6B The cross-sectional diagram in the middle can be compared with Figure 5B The cross-sectional view shown corresponds to this. Mask 40 can be removed by a suitable etching process. Dummy gate stack 42 can be removed by one or more suitable etching processes. In some embodiments, dummy gate layer 38 and dummy dielectric layer 36 are removed by one or more anisotropic dry etching processes. The etching process can use an etchant that selectively etches the dummy gate layer 38 and dummy dielectric layer 36, while gate spacer 44, second CESL 70 and second ILD 72 can remain substantially intact during the etching process.

[0042] exist Figure 7A and Figure 7B In the process, the pseudo-nanostructure 24A was removed. Figure 7A The cross-sectional diagram in the middle can be compared with Figure 6ACorresponding to the cross-sectional view shown, Figure 7B The cross-sectional diagram in the middle can be compared with Figure 6B The cross-sectional view shown corresponds to this. The pseudo-nanostructure 24A can be removed by a suitable etching process. The etching process can selectively remove the pseudo-nanostructure 24A, while the semiconductor fin 20' and semiconductor nanostructure 26 can remain substantially intact during the etching process. Figure 7B The exposure angles of the semiconductor fin 20' and semiconductor nanostructure 26 shown can be rounded after the etching process. In embodiments where the pseudo-nanostructure 24A comprises silicon-germanium and the semiconductor nanostructure 26 comprises silicon, the etching process can be a wet isotropic etching process, and an etchant such as tetramethylammonium hydroxide, ammonium hydroxide, etc. can be used.

[0043] exist Figure 8A and Figure 8B In this process, a gate dielectric layer 78 is formed on the exposed surface of the semiconductor nanostructure 26, and a protective layer 77 is formed on the gate dielectric layer 78. The protective layer 77 can then be partially removed, and the remaining portion of the protective layer 77 can reduce the risk of damaging the gate dielectric layer 78 in subsequent etching processes, as described in more detail below. Figure 8A The cross-sectional diagram in the middle can be compared with Figure 7A Corresponding to the cross-sectional view shown, Figure 8B The cross-sectional diagram in the middle can be compared with Figure 7B The cross-sectional view shown corresponds to that.

[0044] The gate dielectric layer 78 can be formed on the exposed surfaces of the semiconductor nanostructure 26, the semiconductor fin 20', the STI region 34, the internal spacer 54, and the gate spacer 44. The gate dielectric layer 78 can surround the semiconductor nanostructure 26, such as... Figure 8B As shown. The gate dielectric layer 78 can be located on the exposed top, bottom, and sidewalls of the semiconductor nanostructure 26. Figure 8B As shown, the protective layer 77 can enclose the gate dielectric layer 78 that contacts the semiconductor nanostructure 26. The protective layer 77 can be located on the top surface, bottom surface, and sidewalls of the gate dielectric layer 78 that contacts the semiconductor nanostructure 26. The protective layer 77 can fill the space between adjacent semiconductor nanostructures 26 above the same semiconductor fin 20'.

[0045] The gate dielectric layer 78 may include a material with a dielectric constant (k value) greater than about 7.0, which may be referred to as a high-k material. High-k materials may be oxides, such as silicon oxide, metal oxides, etc.; silicates, such as metal silicates, etc.; combinations thereof, etc. Metal oxides may be oxides of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, combinations thereof, etc. Metal silicates may be silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, combinations thereof, etc. The gate dielectric layer 78 may be formed by a suitable deposition process, such as molecular beam deposition (MBD), ALD, PECVD, etc. Then, a suitable etching process may be performed to remove a portion of the gate dielectric layer 78 above the second ILD 72. As an example, a single-layer gate dielectric layer 78 may be... Figure 8A and Figure 8B As shown, the gate dielectric layer 78 may include multiple layers.

[0046] The protective layer 77 may include a dielectric material with high etch selectivity relative to the material of the gate dielectric layer 78, such as silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, etc. The protective layer 77 may be formed by a suitable deposition process, such as ALD, PECVD, etc. The protective layer 77 may cover the surfaces of the gate dielectric layer 78, the gate spacer 44, the second CESL 70, and the second ILD 72.

[0047] exist Figure 9A and Figure 9B In the middle, the sacrificial layer 79 is formed in the lower part of the protective layer 77. Figure 9A The cross-sectional diagram in the middle can be compared with Figure 8A Corresponding to the cross-sectional view shown, Figure 9B The cross-sectional diagram in the middle can be compared with Figure 8B The cross-sectional view shown corresponds to that illustrated. The sacrificial layer 79 can protect the portion of the protective layer 77 in contact with the sacrificial layer 79 during subsequent etching processes. The top surface of the sacrificial layer 79 can be located below the top surface of the dielectric isolation layer 56 and above the bottom surface of the dielectric insulating layer 56. The sacrificial layer 79 can include a silicon-containing dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide, silicon carbonitride, etc. The sacrificial layer 79 can be formed by a suitable deposition process, such as ALD, PECVD, etc. Then, a suitable etching process can be performed to remove the portion of the sacrificial layer 79 above the protective layer 77.

[0048] exist Figure 10A and Figure 10B In the middle, the protective layer 77 was partially removed. Figure 10A The cross-sectional diagram in the middle can be compared with Figure 9A Corresponding to the cross-sectional view shown, Figure 10B The cross-sectional diagram in the middle can be compared with Figure 9BCorresponding to the cross-sectional view shown. After partial removal, the protective layer 77 can remain between the adjacent upper semiconductor nanostructures 26U and 26U', and on the top and bottom surfaces of the gate dielectric layer 78 in contact with the upper semiconductor nanostructures 26U and 26U'. A recess 81 can be formed between the sidewalls of the protective layer 77 and the sidewalls of the upper semiconductor nanostructures 26U and 26U'. The recess 81 can expose the portions of the top and bottom surfaces of the gate dielectric layer 78 in contact with the upper semiconductor nanostructures 26U and 26U'. The portion of the protective layer 77 covered by the sacrificial layer 79 can also be partially removed, and after partial removal, the top surface of the lower part of the protective layer 77 can be lower than the top surface of the sacrificial layer 79. Figure 10B An example is shown where the top surface of the lower portion of the protective layer 77 is substantially flat. In other embodiments, the lower portion of the protective layer 77 is convex.

[0049] The protective layer 77 can be partially removed by an appropriate etching process (such as dry etching). In the etching process, the material of the protective layer 77 is removed at a rate significantly higher than that of the gate dielectric layer 78. During the etching process, portions of the gate dielectric layer 78 exposed to the etchant may be slightly etched, while some portions of the gate dielectric layer 78 still covered by the protective layer 77 may remain substantially intact.

[0050] exist Figure 10C In the middle, sacrificial layer 79 was removed. Figure 10C The cross-sectional diagram in the middle can correspond to Figure 10A The cross-sectional view shown is illustrated. The sacrificial layer 79 can be removed by a suitable etching process, such as a wet etching process using a solution containing a strong oxidant and acidic or alkaline chemicals as the etchant. During the etching process, portions of the gate dielectric layer 78 exposed to the etchant may be slightly etched, while portions of the gate dielectric layer 78 covered by the protective layer 77 may remain substantially intact. The etch selectivity between the protective layer 77 and the gate dielectric layer 78 can be higher than the etch selectivity between the sacrificial layer 79 and the gate dielectric layer 78.

[0051] exist Figure 10D In the middle, material layer 83' is formed in Figure 10C Above the structure shown. Figure 10D The cross-sectional diagram in the middle can correspond to Figure 10A The cross-sectional view shown is illustrated. Material layer 83' may fill recess 81. Material layer 83' may include the same conductive material as the subsequently formed lower gate electrode layer 80L, such as titanium nitride. Material layer 83' may be formed by a suitable deposition process, such as ALD, PECVD, etc.

[0052] exist Figure 11A and Figure 11B In the middle, by removing material layer 83' (e.g. Figure 10DThe protective layer 83 is formed from the portion shown in the figure. Figure 11A The cross-sectional diagram in the middle can correspond to Figure 10A The cross-sectional view shown, Figure 11B The cross-sectional diagram in the middle can correspond to Figure 10B The cross-sectional view shown is illustrated. Protective layer 83 can protect protective layer 77 and the gate dielectric layer 78 in contact with protective layer 77 during subsequent etching processes. A portion of material layer 83' can be removed by a suitable etching process. During the etching process, portions of the gate dielectric layer 78 exposed to the etchant may be slightly etched, while portions of the gate dielectric layer 78 covered by protective layer 77 and protective layer 83 may remain substantially intact.

[0053] Protective layers 77 and 83 can occupy the space between adjacent upper semiconductor nanostructures 26U and 26U', which prevents lower gate electrode material from forming between adjacent upper semiconductor nanostructures 26U and 26U' in subsequent processes. Therefore, the length of subsequent processes for recessing the lower gate electrode can be shortened, and the risk of residual lower gate electrode material between adjacent upper semiconductor nanostructures 26U and 26U' after recessing the lower gate electrode can be reduced.

[0054] exist Figure 12A and Figure 12B In the process, the protective layer 77 below the dielectric isolation layer 56 is removed, and a lower gate electrode layer 80L is formed on the exposed surface of the gate dielectric layer 78. Figure 12A The cross-sectional diagram in the middle can correspond to Figure 11A The cross-sectional view shown, Figure 12B The cross-sectional diagram in the middle can correspond to Figure 11B The cross-sectional view shown. The protective layer 77 beneath the dielectric isolation layer 56 can be removed by a suitable etching process, such as similar to... Figure 10A and Figure 10B The etching process described herein. In the etching process, the material of the protective layer 77 is removed at a rate significantly higher than that of the gate dielectric layer 78. In the etching process, portions of the gate dielectric layer 78 exposed to the etchant may be slightly etched, while portions of the gate dielectric layer 78 covered by the protective layer 77 and the protective layer 83 may remain substantially intact.

[0055] Then, a lower gate electrode layer 80L can be formed on the exposed surface of the gate dielectric layer 78 and the sidewalls of the protective layer 83. The lower gate electrode layer 80L can enclose the lower semiconductor nanostructures 26L and 26L', and fill the spaces between adjacent lower semiconductor nanostructures 26L and 26', as well as between the lower semiconductor nanostructure 26L and the semiconductor fin 20'. As an example, a monolayer lower gate electrode layer 80L is as follows... Figure 12A and Figure 12BAs shown, the lower gate electrode layer 80L may comprise multiple layers. The lower gate electrode layer 80L can be formed by one or more suitable deposition processes, such as PVD, CVD, etc.

[0056] The lower gate electrode layer 80L can be formed of a material suitable for the device type of a lower nanostructure FET. For example, the lower gate electrode layer 80L may include one or more work function tuning layers formed of a material suitable for the device type of a lower nanostructure FET. In some embodiments, the lower gate electrode layer 80L includes an n-type work function tuning layer, which may be formed of aluminum titanium, aluminum titanium nitride, aluminum titanium carbide, aluminum tantalum, tantalum carbide, or combinations thereof. In some embodiments, the lower gate electrode layer 80L includes a p-type work function tuning layer, which may be formed of titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, or combinations thereof.

[0057] exist Figure 13A and Figure 13B In the middle, the lower gate electrode layer 80L is recessed, and the protective layer 83 is removed. The lower gate electrode layer 80L and the gate dielectric layer 78 in contact with the lower gate electrode layer 80L can be collectively referred to as the lower gate structure 90L, and the lower semiconductor nanostructure 26L can be referred to as the lower channel region. Figure 13A The cross-sectional diagram in the middle can be compared with Figure 12A Corresponding to the cross-sectional view shown, Figure 13B The cross-sectional diagram in the middle can be compared with Figure 12B Corresponding to the cross-sectional view shown. The top surface of the recessed lower gate electrode layer 80L can be located below the top surface of the dielectric isolation layer 56. After recessing the lower gate electrode layer 80L, the surface of the gate dielectric layer 78 on the upper semiconductor nanostructures 26U and 26U' that is not covered by the protective layer 77 may be exposed. After removing the protective layer 83, the sidewalls of the protective layer 77 can be exposed. The lower gate electrode layer 80L can be recessed by a suitable etching process, such as a wet etching process using a solution containing a strong oxidant and acidic or alkaline chemicals as the etchant. The protective layer 83 can be removed by the same etching process. The etch selectivity between the protective layer 77 and the gate dielectric layer 78 can be higher than the etch selectivity between the lower gate electrode layer 80L and the gate dielectric layer 78.

[0058] During the etching process, portions of the gate dielectric layer 78 exposed to the etchant may be slightly etched, while portions covered by the protective layer 77 may remain largely intact. Due to the protective layer 77, the gate dielectric layer 78 between adjacent upper semiconductor nanostructures 26U and 26U' is protected during the etching process, and the etching process length can be shortened because the protective layer 77 prevents material of the lower gate electrode layer 80L from forming between adjacent upper semiconductor nanostructures 26U and 26U', which reduces the risk of damaging other portions of the gate dielectric layer 78. Therefore, the risk of damaging the gate dielectric layer 78 during the etching process can be reduced. Furthermore, because the protective layer 77 prevents material of the lower gate electrode layer 80L from forming between adjacent upper semiconductor nanostructures 26U and 26U', the risk of residual material of the lower gate electrode layer 80L remaining between adjacent lower semiconductor nanostructures 26U and 26U' after the etching process can be reduced. As a result, the performance and reliability of the subsequently formed stacked transistor devices can be improved.

[0059] In some embodiments, an isolation layer (not shown) is formed on the lower gate electrode layer 80L. The isolation layer can serve as an isolation component between the lower gate electrode layer 80L and the upper gate electrode subsequently formed over the lower gate electrode layer 80L. The isolation layer can be formed by depositing a dielectric layer (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, combinations thereof, etc.) and subsequently recessing the dielectric layer to expose the gate dielectric layer 78 on the upper semiconductor nanostructures 26U and 26U'.

[0060] exist Figures 14A to 14B In the process, the protective layer 77 between the adjacent upper semiconductor nanostructures 26U and 26U' is removed. Figure 14A The cross-sectional diagram in the middle can be compared with Figure 13A Corresponding to the cross-sectional view shown, Figure 14B The cross-sectional diagram in the middle can be compared with Figure 13B The cross-sectional view shown corresponds to this. The protective layer 77 between the adjacent upper semiconductor nanostructures 26U and 26U' can be removed by a suitable etching process, such as similar to... Figure 10A and Figure 10B The etching process described herein involves the removal of the protective layer 77 at a rate significantly higher than that of the gate dielectric layer 78. Following the etching process, portions of the gate dielectric layer 78 between adjacent upper semiconductor nanostructures 26U and 26U' are exposed.

[0061] Figure 14C Showing Figure 14BDetailed views of regions 84U and 84L are shown. In region 84U, upper semiconductor nanostructures 26U and 26U' are shown, along with a gate dielectric layer 78 on the upper semiconductor nanostructures 26U and 26'U. (Refer to...) Figures 11A to 14B In the described etching process, the portion of the gate dielectric layer 78 protected (e.g., contacted) by the protective layers 77 and 83 can be referred to as the protected portion. The protected portion may include a portion of the gate dielectric layer 78 between adjacent upper semiconductor nanostructures 26U and 26U'. The protected portion may have protrusions and uneven surfaces (e.g., protruding surfaces). (Refer to...) Figures 11A to 14B In the described etching process, the portion of the gate dielectric layer 78 that is not protected by the protective layer 77 or the protective layer 83 (e.g., not in contact) can be referred to as the unprotected portion. The unprotected portion may include portions of the gate dielectric layer 78 located on the sidewalls of the upper semiconductor nanostructures 26U and 26U', and portions of the gate dielectric layer 78 located on the top surface of the upper semiconductor nanostructure 26U on top of the multilayer stack 22 (e.g., ...). Figure 5B (As shown). Unprotected portions may have a uniform surface (e.g., a substantially flat surface).

[0062] The protected portion near the centerline of the upper semiconductor nanostructures 26U and 26U' may have a thickness T1. Thickness T1 can range from about 1 nm to about 2 nm. The protected portion adjacent to the sidewalls of the upper semiconductor nanostructures 26U and 26U' may have a thickness T2. Thickness T2 can range from about 1 nm to about 2 nm. Thickness T1 may be greater than thickness T2. The unprotected portion on the top surface of the upper semiconductor nanostructure 26U may have a thickness T3 adjacent to the centerline of the upper semiconductor nanostructure 26U. Thickness T3 can range from about 1 nm to about 2 nm. The unprotected portion on the top surface of the upper semiconductor nanostructure 26U may have a thickness T4 adjacent to the sidewalls of the upper semiconductor nanostructure 26U. Thickness T4 can range from about 1 nm to about 2 nm. Thickness T3 may be equal to thickness T4. The unprotected portion on the sidewalls of the upper semiconductor nanostructures 26U and 26U' may have a thickness T5. Thickness T5 can range from about 1 nm to about 2 nm. Thicknesses T1 and T2 can be greater than thicknesses T3, T4, and T5.

[0063] In region 84L, lower semiconductor nanostructures 26L and 26L' and gate dielectric layers 78 on the lower semiconductor nanostructures 26L and 26L' are shown. Portions of the gate dielectric layers 78 between adjacent lower semiconductor nanostructures 26L and on the bottom surface of the lower semiconductor nanostructure 26L can have uniform surfaces. Portions of the gate dielectric layers 78 on the sidewalls of the lower semiconductor nanostructures 26L and 26L' can have uniform surfaces. Portions of the gate dielectric layers 78 between adjacent lower semiconductor nanostructures 26L and 26L' can have a thickness T6 in the range of about 1 nm to about 2 nm. Portions of the gate dielectric layers 78 on the bottom surface of the lower semiconductor nanostructure 26L can have a thickness T7 in the range of about 1 nm to about 2 nm. Thicknesses T6 and T7 can be equal to thickness T1. Portions of the gate dielectric layers 78 on the sidewalls of the lower semiconductor nanostructures 26L and 26L' can have a thickness T8 in the range of about 1 nm to about 2 nm. Thickness T8 can be greater than thickness T5.

[0064] exist Figures 15A to 15B In this structure, an upper gate electrode layer 80U is formed on the exposed surfaces of the lower gate electrode layer 80L and the gate dielectric layer 78, and a fill layer 85 is formed above the upper gate electrode layer 80U. The upper gate electrode layer 80U, the gate dielectric layer 78 in contact with the upper gate electrode layer 80U, and the fill layer 85 can be collectively referred to as the upper gate structure 90U, and the upper semiconductor nanostructure 26U can be referred to as the upper channel region. The lower gate structure 90L and the upper gate structure 90U can be collectively referred to as the gate structure 90. Figure 15A The cross-sectional diagram in the middle can be compared with Figure 14A Corresponding to the cross-sectional view shown, Figure 15B The cross-sectional diagram in the middle can be compared with Figure 14B The cross-sectional view shown corresponds to that.

[0065] The upper gate electrode layer 80U can enclose the upper semiconductor nanostructures 26U and 26U' and fill the space between adjacent upper semiconductor nanostructures 26U and 26'. The filling layer 85 can be located on the top surface and sidewalls of the upper gate electrode layer 80U, and on the top surface of the lower gate electrode layer 80L. As an example, a single upper gate electrode layer 80U is as follows: Figure 15A and Figure 15B As shown, the upper gate electrode layer 80U may comprise multiple layers. The upper gate electrode layer 80U can be formed by one or more suitable deposition processes, such as PVD, CVD, etc. Then, the fill layer 85 can be formed by a suitable deposition process (such as PVD, CVD, etc.) or a suitable plating process.

[0066] The upper gate electrode layer 80U can be formed of a material suitable for the device type of an upper nanostructure FET. For example, the lower gate electrode layer 80L can include one or more work function tuning layers formed of a material suitable for the device type of a lower nanostructure FET for stacked transistor devices. In some embodiments, the upper gate electrode layer 80U includes an n-type work function tuning layer, which can be formed of aluminum titanium, aluminum titanium nitride, aluminum titanium carbide, aluminum tantalum, tantalum carbide, or combinations thereof. In some embodiments, the upper gate electrode layer 80U includes a p-type work function tuning layer, which can be formed of titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, or combinations thereof. The filler layer 136 can be formed of a conductive material, such as aluminum, tungsten, cobalt, copper, etc.

[0067] Figure 15C Showing Figure 15B Detailed views of regions 84U and 84L are shown. In region 84U, upper semiconductor nanostructures 26U and 26U', a gate dielectric layer 78 on the upper semiconductor nanostructures 26U and 26U', and an upper gate electrode layer 80U are shown. A portion of the upper gate electrode layer 80U between adjacent protected portions of the gate dielectric layer 78 may have a width W1 adjacent to the centerline of the upper semiconductor nanostructures 26U and 26U'. The width W1 may be in the range of about 4 nm to about 8 nm. A portion of the upper gate electrode layer 80U between adjacent protected portions of the gate dielectric layer 78 may have a width W2 adjacent to the sidewalls of the upper semiconductor nanostructures 26U and 26U'. The width W2 may be in the range of about 4 nm to about 8 nm. The width W2 may be greater than the width W1. In region 84L, lower semiconductor nanostructures 26L and 26L', a gate dielectric layer 78 on the lower semiconductor nanostructures 26L and 26', and a lower gate electrode layer 80L are shown. A portion of the upper gate electrode layer 80L between adjacent gate dielectric layers 78 may have a width W3. The width W3 may be in the range of approximately 4 nm to approximately 8 nm. The width W3 may be equal to the width W1.

[0068] exist Figures 16A to 16B In this process, the gate mask 92 can be formed on the upper gate structure 90U. Figure 16A The cross-sectional diagram in the middle can be compared with Figure 15A Corresponding to the cross-sectional view shown, Figure 16B The cross-sectional diagram in the middle can be compared with Figure 15BThe cross-sectional view shown corresponds to this. The gate mask 92 can be formed by recessing the upper gate structure 90U, filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, or silicon carbonitride, and performing a planarization process such as CMP to remove excess dielectric material above the second ILD 72. After the planarization process, the top surfaces of the gate mask 92, the gate dielectric layer 78, the second ILD 72, and the gate spacer 44 can be substantially coplanar (within the range of process variations).

[0069] exist Figures 17A to 17B In the middle, the metal-semiconductor alloy region 94 and the source / drain contact 96 are formed by the second ILD 72 to be electrically coupled to the upper epitaxial source / drain region 62U and / or the lower epitaxial source / drain region 62L. Figure 17A The cross-sectional diagram in the middle can correspond to Figure 16A The cross-sectional view shown, Figure 17B The cross-sectional view in the middle can correspond to Figure 16B The cross-sectional view shown. Figure 17A and Figure 17B This is a cross-sectional view of the same structure, which can be called a stacked transistor device 150.

[0070] As an example of forming the source / drain contact 96, an opening through the second ILD 72 and the second CESL 70 is formed using acceptable photolithography and etching techniques. A pad (not shown separately), such as a diffusion barrier layer, an adhesive layer, etc., and a conductive material are formed within the opening. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A removal process may be performed to remove excess material from the top surfaces of the gate spacer 44 and the second ILD 72. The remaining pad and conductive material form the source / drain contact 96 within the opening. In some embodiments, a planarization process, such as CMP, etch-back process, or a combination thereof, is utilized. After the planarization process, the top surfaces of the gate spacer 44, the second ILD 72, and the source / drain contact 96 are substantially coplanar (within the range of process variations).

[0071] Optionally, a metal-semiconductor alloy region 94 is formed at the interface between the source / drain region 62 and the source / drain contact 96. The metal-semiconductor alloy region 94 can be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed from metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a germanium silicide region formed from both metal silicides and metal germanides. The metal-semiconductor alloy region 94 can be formed before the material of the source / drain contact 96 by depositing metal in the opening of the source / drain contact 96 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material of the source / drain region 62 (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited using deposition processes such as ALD, CVD, PVD, etc. Following the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the openings in the source / drain contact 96 (e.g., from the surface of the metal-semiconductor alloy region 94). The material for the source / drain contact 96 can then be formed on the metal-semiconductor alloy region 94.

[0072] Then, a third CESL 104 and a third ILD 106 are formed. In some embodiments, the third CESL 104 may include a dielectric material with high etch selectivity relative to the etching of the third ILD 106, such as alumina, aluminum nitride, silicon carbide, etc. The third ILD 106 may be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., which may be deposited by any suitable method, such as CVD, PECVD, etc.

[0073] Subsequently, a gate contact 108 and a source / drain via 110 are formed to contact the upper gate electrode layer 80U and the source / drain contact 96, respectively. As an example of forming the gate contact 108 and the source / drain via 110, openings for the gate contact 108 and the source / drain via 110 are formed through the third ILD 106 and the third CESL 104. The openings can be formed using acceptable photolithography and etching techniques. Pads (not shown separately), such as diffusion barrier layers, adhesive layers, etc., and conductive material are formed in the openings. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the top surface of the third ILD 106. The remaining pads and conductive material form the gate contact 108 and the source / drain via 110 in the openings. The gate contact 108 and the source / drain via 110 can be formed in different processes or in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 108 and the source / drain via 110 can be formed in a different cross section, which can prevent short circuits of the contacts.

[0074] A front interconnect structure 114 is formed on the third ILD 106. The front interconnect structure 114 includes a dielectric layer 116 and a conductive component layer 118 within the dielectric layer 116. The dielectric layer 116 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 116 may also include a passivation layer formed of a non-low-k and dense dielectric material above the low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, etc., or combinations thereof. The dielectric layer 116 may also include a polymer layer.

[0075] The conductive component 118 may include wires and vias that can be formed using an damascene process. The conductive component 118 may include metal wires and metal vias, which include a diffusion barrier layer and copper-containing material on the diffusion barrier layer. Aluminum pads may also be present above and electrically connected to the metal wires and vias. In some embodiments, the lower gate structure 90L and the lower epitaxial source / drain region 62L may be contacted via the back side of the substrate 20 (e.g., the side opposite the front interconnect structure 114).

[0076] The embodiments disclosed herein have several advantageous features. Due to the protective layer 77, the risk of damage to portions of the gate dielectric layer 78 during the recessing of the lower gate electrode layer 80L is reduced, as is the risk of residual material of the lower gate electrode layer 80L between adjacent upper semiconductor nanostructures 26U and 26U' after the recessing of the lower gate electrode layer 80L. As a result, the performance and reliability of the stacked transistor device 150 can be improved.

[0077] In one embodiment, the semiconductor device includes: a first epitaxial source / drain region, wherein the first epitaxial source / drain region is doped with a dopant, wherein the first epitaxial source / drain region includes a first portion and a second portion, wherein the first portion has a first dopant concentration, and wherein the second portion has a second dopant concentration different from the first dopant concentration; a first nanostructure located on a sidewall of the first epitaxial source / drain region and in contact with the first portion of the first epitaxial source / drain region, wherein the second portion of the first epitaxial source / drain region is spaced apart from the first nanostructure by the first portion of the first epitaxial source / drain region; and a first gate structure surrounding the first nanostructure in a cross-sectional view, the first gate structure including: a first dielectric layer surrounding the first nanostructure in a cross-sectional view, wherein a first portion of the first dielectric layer is located on a top surface of the first nanostructure, wherein the first portion of the first dielectric layer includes a substantially flat top surface in a cross-sectional view, wherein a second portion of the first dielectric layer is located on a bottom surface of the first nanostructure, and wherein the second portion of the first dielectric layer includes a protruding bottom surface in a cross-sectional view; and a first gate electrode surrounding the first dielectric layer in a cross-sectional view. In one embodiment, a second portion of the first dielectric layer has a first thickness adjacent to the centerline of the first nanostructure in a cross-sectional view, wherein the second portion of the first dielectric layer has a second thickness adjacent to the first sidewall of the first nanostructure in a cross-sectional view, and wherein the first thickness is greater than the second thickness. In one embodiment, a first portion of the first dielectric layer has a third thickness adjacent to the centerline of the first nanostructure in a cross-sectional view, and wherein the first thickness is greater than the third thickness. In one embodiment, a first portion of the first dielectric layer has a third thickness adjacent to the first sidewall of the first nanostructure in a cross-sectional view, and wherein the second thickness is greater than the third thickness. In one embodiment, a third portion of the first dielectric layer is located on the first sidewall of the first nanostructure, wherein the third portion has a third thickness in a cross-sectional view, and wherein the second thickness is greater than the third thickness. In one embodiment, the semiconductor device further includes a second nanostructure located on the sidewall of the first epitaxial source / drain region, wherein the second nanojunction is located below the first nanostructure, wherein the first gate structure surrounds the second nanostructure in a cross-sectional view, wherein the first gate structure further includes a second dielectric layer surrounding the second nanostructure in a cross-sectional view, wherein a first portion of the second dielectric layer is located on the top surface of the second epitaxial source / drain region, wherein the first portion of the second dielectric layer includes a protruding top surface in a cross-sectional view, wherein a second portion of the second dielectric layer is located on the bottom surface of the second nanostructure, and wherein the second portion of the second dielectric layer includes a protruding bottom surface in a cross-sectional view.In one embodiment, the semiconductor device includes a second nanostructure located below a first nanostructure; and a second gate structure surrounding the second nanostructure in a cross-sectional view, the second gate structure including: a second dielectric layer surrounding the second nanostructure in a cross-sectional view, wherein a first portion of the second dielectric layer is located on a top surface of the second nanostructure, wherein the first portion of the second dielectric layer includes a substantially flat top surface in the cross-sectional view, wherein a second portion of the second dielectric layer is located on a bottom surface of the second nanostructure, and wherein the second portion of the second dielectric layer includes a substantially flat bottom surface in the cross-sectional view; and a second gate electrode surrounding a second gate electrode of the second dielectric layer in a cross-sectional view.

[0078] In one embodiment, a method of forming a semiconductor device includes: forming a first nanostructure over a semiconductor fin and forming a second nanostructure over the first nanostructure; growing a first epitaxial structure, wherein the first nanostructure and the second nanostructure are in contact with the first epitaxial structure, wherein the first epitaxial structure is doped with a dopant, wherein the first epitaxial structure includes a first portion adjacent to the first nanostructure and a second portion distant from the first nanostructure, wherein the first portion has a first dopant concentration and wherein the second portion has a second dopant concentration different from the first dopant concentration; forming a first etch stop layer over the first epitaxial structure; forming a first dielectric layer over the first etch stop layer; depositing a first gate dielectric layer surrounding the first nanostructure and a second gate dielectric layer surrounding the second nanostructure in a cross-sectional view, wherein the first gate dielectric layer and the second gate dielectric layer comprise a first material; forming a first protective layer between the first gate dielectric layer and the second gate dielectric layer, wherein the first protective layer comprises a second material; removing the first protective layer by an etching process, wherein during the etching process, a second etch rate of the second material is higher than a first etch rate of the first material; and forming a first gate electrode surrounding the first gate dielectric layer and the second gate dielectric layer in a cross-sectional view. In one embodiment, the second gate dielectric layer includes a first portion located on the top surface of the second nanostructure and a second portion located on the bottom surface of the second nanostructure, wherein after the first protective layer is removed, the first portion includes a flat top surface in a cross-sectional view, and wherein after the first protective layer is removed, the second portion includes an uneven bottom surface in a cross-sectional view. In one embodiment, a first thickness of the first portion is less than a second thickness of the second portion. In one embodiment, the second material is silicon oxide, aluminum oxide, titanium oxide, or tantalum oxide. In one embodiment, the method further includes: forming a second gate electrode over a semiconductor fin after forming the first protective layer, wherein a first portion of the second gate electrode is located on the sidewalls of the first and second gate dielectric layers; and removing the first portion of the second gate electrode to expose the sidewalls of the first and second gate dielectric layers before removing the first protective layer. In one embodiment, the first gate electrode is located over the remaining portion of the second gate electrode, and wherein the first and second gate electrodes comprise different materials. In one embodiment, the method further includes: forming a second protective layer on the sidewalls of the first protective layer before forming the second gate electrode, wherein the second protective layer and the second gate electrode comprise the same material; and removing the second protective layer during the removal of the first portion of the second gate electrode.

[0079] In one embodiment, a method of forming a semiconductor device includes: forming a first nanostructure and a second nanostructure over a semiconductor fin, wherein the first nanostructure is located between the second nanostructure and the semiconductor fin; depositing a first gate dielectric layer surrounding the first nanostructure and a second gate dielectric layer surrounding the second nanostructure in a cross-sectional view, wherein the first gate dielectric layer and the second gate dielectric layer comprise a first material; forming a first protective layer on the bottom surface of the first gate dielectric layer and forming a second protective layer on the bottom surface of the second gate dielectric layer, wherein the first protective layer and the second protective layer comprise a second material different from the first material; removing the first protective layer; forming a first gate electrode surrounding the first gate dielectric layer in a cross-sectional view; removing the second protective layer; and forming a second gate electrode surrounding the second gate dielectric layer in a cross-sectional view. In one embodiment, after removing the first protective layer, the first gate dielectric layer has a flat bottom surface in the cross-sectional view, and wherein after removing the second protective layer, the second gate dielectric layer has an uneven bottom surface in the cross-sectional view. In one embodiment, in the cross-sectional view, the first protective layer surrounds the first gate dielectric layer, and wherein the sidewalls of the second protective layer are recessed from the sidewalls of the second gate dielectric layer. In one embodiment, the method further includes forming a third protective layer on the sidewall of the second protective layer before removing the first protective layer. In one embodiment, the method further includes simultaneously removing portions of the first gate electrode on the sidewalls of the second gate dielectric layer and the third protective layer before removing the second protective layer. In one embodiment, the method further includes: forming an isolation structure between the first nanostructure and the second nanostructure; and forming a third gate dielectric layer on the sidewall of the isolation structure in a cross-sectional view.

[0080] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A semiconductor device, comprising: A first epitaxial source / drain region, wherein the first epitaxial source / drain region is doped with a dopant, wherein the first epitaxial source / drain region includes a first portion and a second portion, wherein the first portion has a first dopant concentration, and wherein the second portion has a second dopant concentration different from the first dopant concentration; A first nanostructure is located on the sidewall of the first epitaxial source / drain region and is in contact with the first portion of the first epitaxial source / drain region, wherein the second portion of the first epitaxial source / drain region is spaced apart from the first nanostructure through the first portion of the first epitaxial source / drain region; as well as The first gate structure, as shown in the cross-sectional view, surrounds the first nanostructure. The first gate structure includes a first dielectric layer surrounding the first nanostructure in the cross-sectional view, wherein a first portion of the first dielectric layer is located on the top surface of the first nanostructure, wherein the first portion of the first dielectric layer in the cross-sectional view includes a substantially flat top surface, wherein a second portion of the first dielectric layer is located on the bottom surface of the first nanostructure, and wherein the second portion of the first dielectric layer in the cross-sectional view includes a protruding bottom surface; and The first gate structure includes a first gate electrode surrounding the first dielectric layer in the cross-sectional view.

2. The semiconductor device according to claim 1, wherein, The second portion of the first dielectric layer has a first thickness adjacent to the centerline of the first nanostructure in the cross-sectional view, wherein the second portion of the first dielectric layer has a second thickness adjacent to the first sidewall of the first nanostructure in the cross-sectional view, and wherein the first thickness is greater than the second thickness.

3. The semiconductor device according to claim 2, wherein, The first portion of the first dielectric layer has a third thickness adjacent to the center line of the first nanostructure in the cross-sectional view, and wherein the first thickness is greater than the third thickness.

4. The semiconductor device according to claim 2, wherein, The first portion of the first dielectric layer has a third thickness adjacent to the first sidewall of the first nanostructure in the cross-sectional view, and wherein the second thickness is greater than the third thickness.

5. The semiconductor device according to claim 2, wherein, The third portion of the first dielectric layer is located on the first sidewall of the first nanostructure, wherein the third portion has a third thickness in the cross-sectional view, and wherein the second thickness is greater than the third thickness.

6. The semiconductor device of claim 1, further comprising a second nanostructure located on the sidewall of the first epitaxial source / drain region, wherein the second nanojunction is located below the first nanostructure, wherein the first gate structure surrounds the second nanostructure in the cross-sectional view, wherein the first gate structure further includes a second dielectric layer surrounding the second nanostructure in the cross-sectional view, wherein a first portion of the second dielectric layer is located on the top surface of the second epitaxial source / drain region, wherein the first portion of the second dielectric layer includes a protruding top surface in the cross-sectional view, wherein a second portion of the second dielectric layer is located on the bottom surface of the second nanostructure, and wherein... The second portion of the second dielectric layer includes a protruding bottom surface in the cross-sectional view.

7. The semiconductor device according to claim 1, further comprising: The second nanostructure is located below the first nanostructure; as well as A second gate structure, surrounding the second nanostructure in the cross-sectional view. The second gate structure includes a second dielectric layer surrounding the second nanostructure in the cross-sectional view, wherein a first portion of the second dielectric layer is located on the top surface of the second nanostructure, wherein the first portion of the second dielectric layer includes a substantially flat top surface in the cross-sectional view, wherein a second portion of the second dielectric layer is located on the bottom surface of the second nanostructure, and wherein the second portion of the second dielectric layer includes a substantially flat bottom surface in the cross-sectional view; and The second gate structure includes a second gate electrode surrounding the second dielectric layer in the cross-sectional view.

8. A method of forming a semiconductor device, the method comprising: A first nanostructure is formed above the semiconductor fin, and a second nanostructure is formed above the first nanostructure; A first epitaxial structure is grown, wherein the first nanostructure and the second nanostructure are in contact with the first epitaxial structure, wherein the first epitaxial structure is doped with a dopant, wherein the first epitaxial structure includes a first portion adjacent to the first nanostructure and a second portion away from the first nanostructure, wherein the first portion has a first dopant concentration, and wherein the second portion has a second dopant concentration different from the first dopant concentration; A first etch stop layer is formed above the first epitaxial structure; A first dielectric layer is formed above the first etch stop layer; A first gate dielectric layer and a second gate dielectric layer are deposited around the first nanostructure and the second nanostructure in the cross-sectional view, wherein the first gate dielectric layer and the second gate dielectric layer comprise a first material; A first protective layer is formed between the first gate dielectric layer and the second gate dielectric layer, wherein the first protective layer comprises a second material; The first protective layer is removed by an etching process, wherein during the etching process, the second etching rate of the second material is higher than the first etching rate of the first material; as well as A first gate electrode is formed around the first gate dielectric layer and the second gate dielectric layer in the cross-sectional view.

9. The method according to claim 8, further comprising: After forming the first protective layer, a second gate electrode is formed over the semiconductor fin, wherein a first portion of the second gate electrode is located on the sidewalls of the first gate dielectric layer and the second gate dielectric layer; and Before removing the first protective layer, the first portion of the second gate electrode is removed to expose the sidewalls of the first gate dielectric layer and the second gate dielectric layer.

10. A method of forming a semiconductor device, the method comprising: A first nanostructure and a second nanostructure are formed above a semiconductor fin, wherein the first nanostructure is located between the second nanostructure and the semiconductor fin; A first gate dielectric layer and a second gate dielectric layer are deposited around the first nanostructure and the second nanostructure in the cross-sectional view, wherein the first gate dielectric layer and the second gate dielectric layer comprise a first material; A first protective layer is formed on the bottom surface of the first gate dielectric layer, and a second protective layer is formed on the bottom surface of the second gate dielectric layer, wherein the first protective layer and the second protective layer comprise a second material different from the first material; Remove the first protective layer; A first gate electrode is formed around the first gate dielectric layer in the cross-sectional view; Remove the second protective layer; as well as A second gate electrode is formed around the second gate dielectric layer in the cross-sectional view.

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