Array substrate and display device

Abstract

Embodiments of the present disclosure provide an array substrate and a display device, and relate to the technical field of display, and are used for improving the image display quality. The array substrate comprises a substrate and a plurality of pixel driving circuits arranged on the substrate, a first electrode region of a driving transistor, a second electrode region of a data writing transistor and a second electrode region of a first light emitting control transistor are connected as a conductive connection pattern. The array substrate further comprises a conductive pattern, the conductive pattern comprises a pattern in the pixel driving circuit which is located at a different layer from the conductive connection pattern. The overlapping area of the conductive connection pattern of at least one pixel driving circuit in the odd row circuit group and the orthographic projection of the conductive pattern on the substrate is less than the overlapping area of the conductive connection pattern of at least one pixel driving circuit in the even row circuit group and the orthographic projection of the conductive pattern on the substrate. The array substrate is used for driving the display device to display an image.

Description

[0001] This application is a divisional application. The original application has the application number 202211378086.2 and the application date is November 4, 2022. The entire contents of the original application can be incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Technology

[0003] With the maturation of AMOLED (Active-Matrix Organic Light Emitting Diode) technology, more and more devices are using AMOLED as their display panel. For gaming products, the market demand for high refresh rate (90Hz, 120Hz) AMOLED screens is becoming increasingly urgent. Summary of the Invention

[0004] The purpose of the embodiments of this disclosure is to provide an array substrate and a display device to solve the problem of brightness difference between odd and even rows caused by inconsistent compensation time of compensation transistors in the odd and even row pixel driving circuits of the array substrate, thereby improving the image quality of the display.

[0005] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions: On one hand, an array substrate is provided, comprising: a substrate and a plurality of pixel driving circuits disposed on the substrate, each of the plurality of pixel driving circuits comprising: a transistor, the transistor comprising: a driving transistor, a data writing transistor, and a first light-emitting control transistor. The array substrate further comprises: a first electrode region and a second electrode region of the transistor, wherein the first electrode region of the driving transistor, the second electrode region of the data writing transistor, and the second electrode region of the first light-emitting control transistor are connected in a conductive connection pattern, and the conductive connection pattern is a continuous pattern.

[0006] The plurality of pixel driving circuits are configured as: an odd-numbered circuit group and an even-numbered circuit group, wherein the odd-numbered circuit group and the even-numbered circuit group include a plurality of pixel driving circuits arranged along a first direction, and the odd-numbered circuit group and the even-numbered circuit group are alternately arranged along a second direction, wherein the first direction and the second direction intersect.

[0007] The array substrate further includes a conductive pattern, which includes a pattern in the pixel driving circuit located on a different layer than the conductive connection pattern. The overlap area of ​​the conductive connection pattern of at least one pixel driving circuit in the odd-numbered circuit group and the orthographic projection of the conductive pattern on the substrate is smaller than the overlap area of ​​the conductive connection pattern of at least one pixel driving circuit in the even-numbered circuit group and the orthographic projection of the conductive pattern on the substrate.

[0008] In the aforementioned array substrate, the overlapping area of ​​the conductive connection patterns in the odd-numbered circuit groups and their orthogonal projections onto the substrate is differentiated from that in the even-numbered circuit groups. This difference in overlapping area leads to a different design of parasitic capacitance at the conductive connection patterns in the odd-numbered and even-numbered circuit groups. This resolves the issue of brightness differences between odd and even rows, improving the image display quality.

[0009] In some embodiments, the transistor further includes a compensation transistor, and the array substrate further includes a gate pattern of the compensation transistor and a second scan signal line, wherein the gate pattern of the compensation transistor is electrically connected to the second scan signal line; and the second electrode region of the compensation transistor is connected to the second electrode region of the driving transistor. The plurality of pixel driving circuits are further configured as: a plurality of pixel group units sequentially arranged along the second direction, each pixel group unit including: the odd-numbered circuit group and the even-numbered circuit group adjacent to the odd-numbered circuit group. Each pixel group unit shares one second scan signal line.

[0010] In some embodiments, the array substrate further includes a first semiconductor layer disposed on the substrate, wherein the conductive connection pattern is located on the first semiconductor layer.

[0011] In some embodiments, the array substrate further includes: a shielding layer disposed on the substrate, and a first semiconductor layer disposed on the side of the shielding layer away from the substrate. The conductive pattern is located on the shielding layer.

[0012] In some embodiments, the array substrate further includes: a first gate conductive layer disposed on the side of the first semiconductor layer away from the substrate, and a second gate conductive layer disposed on the side of the first gate conductive layer away from the substrate. The pixel driving circuit further includes: a capacitor and a compensation transistor. The capacitor includes: a first electrode and a second electrode, the first electrode being located on the first gate conductive layer, and the second electrode being located on the second gate conductive layer. The first electrode is electrically connected to a first electrode region of the compensation transistor, and the second electrode is electrically connected to a power signal line. The conductive pattern includes: a first portion located on the shielding layer and a second portion electrically connected to the second electrode.

[0013] In some embodiments, the array substrate further includes: a first gate conductive layer disposed on the side of the first semiconductor layer away from the substrate, and a second gate conductive layer disposed on the side of the first gate conductive layer away from the substrate. The conductive pattern is located in the second gate conductive layer.

[0014] In some embodiments, the area of ​​the orthographic projection of the conductive pattern in the odd-numbered circuit group onto the substrate is equal to the area of ​​the orthographic projection of the conductive pattern in the even-numbered circuit group onto the substrate. In the even-numbered circuit group, a first extended pattern located on the first semiconductor layer is connected to the conductive connection pattern, and the orthographic projection of the conductive pattern onto the substrate covers the orthographic projection of the first extended pattern onto the substrate.

[0015] In some embodiments, the array substrate further includes a second gate conductive layer disposed on the side of the first semiconductor layer away from the substrate. The array substrate also includes a second scan signal line located in the second gate conductive layer. The conductive pattern and the second scan signal line are integrally formed.

[0016] In some embodiments, the array substrate further includes: a first source / drain metal layer disposed on the side of the first semiconductor layer away from the substrate, the first source / drain metal layer including a third extended pattern, the third extended pattern being connected to the conductive connection pattern via vias. The array substrate further includes: a second source / drain metal layer disposed on the side of the first source / drain metal layer away from the substrate, the second source / drain metal layer including power signal lines. The conductive pattern and the power signal lines are integrally formed, and the overlap area of ​​the orthographic projection of the third extended pattern on the substrate and the orthographic projection of the conductive pattern on the substrate in the odd-numbered circuit groups is smaller than the overlap area of ​​the orthographic projection of the third extended pattern on the substrate and the orthographic projection of the conductive pattern on the substrate in the even-numbered circuit groups.

[0017] In some embodiments, in the odd-numbered circuit group, the orthographic projection of the data signal line onto the substrate does not overlap with the orthographic projection of the third extended pattern onto the substrate.

[0018] In some embodiments, the orthographic projection of the third extended pattern onto the substrate overlaps with the orthographic projection of the conductive connection pattern onto the substrate.

[0019] In some embodiments, the transistor includes: a first reset transistor, a compensation transistor, a second light-emitting control transistor, and a second reset transistor. The array substrate further includes: a first initial signal line, a second initial signal line, a data signal line, and a power signal line. A first electrode region of the first reset transistor is electrically connected to the first initial signal line; a second electrode region of the first reset transistor is electrically connected to the first electrode region of the compensation transistor; and a second electrode region of the compensation transistor is electrically connected to the second electrode region of the driving transistor. A first electrode region of the second light-emitting control transistor is electrically connected to the second electrode region of the driving transistor; a second electrode region of the second light-emitting control transistor is electrically connected to the second electrode region of the second reset transistor; and a first electrode region of the second reset transistor is electrically connected to the second initial signal line. A first electrode region of the data writing transistor is electrically connected to the data signal line, and a first electrode region of the first light-emitting control transistor is electrically connected to the power signal line.

[0020] In some embodiments, the array substrate further includes: a gate pattern of the first reset transistor, a reset signal line, a gate pattern of the second reset transistor, a first scan signal line, a gate pattern of the first light-emitting control transistor, a gate pattern of the second light-emitting control transistor, and a light-emitting control signal line. The gate pattern of the first reset transistor is electrically connected to the reset signal line, the gate pattern of the second reset transistor is electrically connected to the first scan signal line, and the gate patterns of the first and second light-emitting control transistors are electrically connected to the light-emitting control signal line.

[0021] In some embodiments, the array substrate further includes: a first semiconductor layer disposed on one side of the substrate, wherein the conductive connection pattern is located on the first semiconductor layer; a first gate conductive layer disposed on the side of the first semiconductor layer away from the substrate, wherein the first scan signal line and the light emission control signal line are located on the first gate conductive layer; a second gate conductive layer disposed on the side of the first gate conductive layer away from the substrate, wherein the first initial signal line and the reset signal line are located on the second gate conductive layer; a first source / drain metal layer disposed on the side of the second gate conductive layer away from the substrate, wherein the second initial signal line is located on the first source / drain metal layer; and a second source / drain metal layer disposed on the side of the first source / drain metal layer away from the substrate, wherein the data signal line and the power signal line are located on the second source / drain metal layer.

[0022] In some embodiments, the compensation transistor and the first reset transistor comprise oxide thin-film transistors. The array substrate further comprises a second semiconductor layer and a third gate conductive layer disposed between the second gate conductive layer and the first source / drain metal layer, the third gate conductive layer being disposed on the side of the second semiconductor layer away from the substrate.

[0023] On the other hand, an array substrate is provided, comprising: a substrate and a plurality of pixel driving circuits disposed on the substrate. Each pixel driving circuit includes: a transistor, the transistor comprising: a driving transistor, a data writing transistor, and a first light-emitting control transistor. The array substrate further includes: a first electrode region and a second electrode region of the transistor; the first electrode region of the driving transistor, the second electrode region of the data writing transistor, and the second electrode region of the first light-emitting control transistor are connected in a conductive connection pattern, and the conductive connection pattern is a continuous pattern.

[0024] The plurality of pixel driving circuits are configured as: an odd-numbered circuit group and an even-numbered circuit group, each comprising a plurality of pixel driving circuits arranged along a first direction. Along a second direction, the odd-numbered circuit group and the even-numbered circuit group are alternately arranged; the first direction and the second direction intersect. The array substrate further comprises: a conductive pattern, the conductive pattern including patterns in the pixel driving circuits located on a different layer than the conductive connection pattern. The capacitance value formed between the conductive connection pattern and the conductive pattern of at least one pixel driving circuit in the odd-numbered circuit group is less than the capacitance value formed between the conductive connection pattern and the conductive pattern of at least one pixel driving circuit in the even-numbered circuit group.

[0025] In the aforementioned array substrate, the problem of brightness difference between odd and even rows is solved by differentiating the capacitance values ​​of the conductive connection patterns and the capacitors formed by the conductive patterns in the odd-numbered circuit groups and the capacitance Ce formed by the conductive connection patterns and the conductive patterns in the even-numbered circuit groups, thereby improving the image display quality.

[0026] In some embodiments, the insulating layer between the conductive connection pattern and the conductive pattern of at least one pixel driving circuit in the odd-numbered circuit group is made of the same material as the insulating layer between the conductive connection pattern and the conductive pattern of at least one pixel driving circuit in the even-numbered circuit group.

[0027] In some embodiments, the insulating layer between the conductive connection pattern and the conductive pattern of at least one pixel driving circuit in the odd-numbered circuit group, and the insulating layer between the conductive connection pattern and the conductive pattern of at least one pixel driving circuit in the even-numbered circuit group, comprises at least one insulating layer of the same material.

[0028] In another aspect, a display device is provided, comprising an array substrate as described in any of the above embodiments.

[0029] The above-described display device has the same structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0031] Figure 1 This is a structural diagram of a display panel provided according to some embodiments; Figure 2 This is an equivalent circuit diagram of a pixel driving circuit provided according to some embodiments; Figure 3 Based on some embodiments Figure 2 Timing diagram of the provided pixel driving circuit; Figure 4 This is a structural diagram of an array substrate provided according to some embodiments of the present disclosure; Figure 5 This is an equivalent circuit diagram of a pixel driving circuit provided according to some embodiments of the present disclosure; Figure 6This is a structural diagram of the superimposed shielding layer, first semiconductor layer, and first gate conductive layer according to some embodiments of the present disclosure; Figure 7 This is another equivalent circuit diagram of a pixel driving circuit provided according to some embodiments of the present disclosure; Figure 8 Based on some embodiments of this disclosure Figure 7 Timing diagram of the provided pixel driving circuit; Figure 9 This is a structural diagram of a first semiconductor layer, a first gate conductive layer, a second gate conductive layer, a second semiconductor layer, and a third gate conductive layer stacked according to some embodiments of this disclosure; Figure 10 This is a structural diagram of a display panel provided according to some embodiments of the present disclosure; Figure 11 This is a structural diagram of the superimposed shielding layer, first semiconductor layer, first gate conductive layer and second gate conductive layer according to some embodiments of the present disclosure; Figure 12 This is a partial structural diagram of the superimposed shielding layer, first semiconductor layer, and second gate conductive layer provided according to some embodiments of the present disclosure; Figure 13 This is a structural diagram of the stacked first semiconductor layer, first gate conductive layer and second gate conductive layer according to some embodiments of the present disclosure; Figure 14 This is another structural diagram of the superimposed shielding layer, first semiconductor layer, first gate conductive layer and second gate conductive layer according to some embodiments of the present disclosure; Figure 15 This is another structural diagram of a shielding layer, a first semiconductor layer, a first gate conductive layer and a second gate conductive layer stacked according to some embodiments of the present disclosure; Figure 16 This is a structural diagram of the superimposed shielding layer, first semiconductor layer, first gate conductive layer, second gate conductive layer and first source / drain metal layer according to some embodiments of the present disclosure; Figure 17 This is a structural diagram of the superimposed shielding layer, first semiconductor layer, first gate conductive layer, second gate conductive layer, first source / drain metal layer and second source / drain metal layer according to some embodiments of this disclosure; Figure 18 This is another structural diagram of the superimposed shielding layer, first semiconductor layer, first gate conductive layer, second gate conductive layer, first source / drain metal layer and second source / drain metal layer according to some embodiments of this disclosure; Figure 19This is a structural diagram of a shielding layer, a first semiconductor layer, a first gate conductive layer, a second gate conductive layer, a second semiconductor layer, a third gate conductive layer, a first source / drain metal layer, and a second source / drain metal layer stacked together according to some embodiments of this disclosure; Figure 20 This is another structural diagram of a first semiconductor layer, a first gate conductive layer, and a second gate conductive layer stacked according to some embodiments of the present disclosure; Figure 21 This is yet another equivalent circuit diagram of a pixel driving circuit provided according to some embodiments of the present disclosure; Figure 22 This is another structural diagram of a first semiconductor layer, a first gate conductive layer, and a second gate conductive layer stacked according to some embodiments of the present disclosure; Figure 23 This is another structural diagram of a first semiconductor layer, a first gate conductive layer, and a second gate conductive layer stacked according to some embodiments of the present disclosure; Figure 24 This is a structural diagram of a display device provided according to some embodiments of the present disclosure. Detailed Implementation

[0032] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0033] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0034] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0035] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0036] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0037] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0038] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0039] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0040] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0041] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0042] With the development of Organic Light Emitting Diode (OLED) display technology, such as Active-Matrix Organic Light Emitting Diode (AMOLED) display technology, people have increasingly higher requirements for the display effect of display products. The design of the pixel driving circuit in display products is crucial to the display characteristics of AMOLED products.

[0043] In the existing pixel driving circuit 10', the pixel driving circuit 10' includes: a light emission control signal line EM, a first scan signal line Gate1, and a second scan signal line Gate2. For example... Figure 1 As shown, the GOA (Gate on Array, array substrate row drive) circuit of the first scan signal line Gate1 drives one row at a time. The GOA circuit of the first scan signal line Gate1 includes: odd-numbered row GOA circuits (Gate1-odd GOA) and even-numbered row GOA circuits (Gate1-even GOA). However, in order to reduce the occupation of the GOA circuit on the bezel area BB of the display panel 100' to achieve a narrower bezel, the GOA circuit of the light emission control signal line EM and the GOA circuit of the second scan signal line Gate2 adopt a driving architecture of one GOA circuit driving two rows (i.e., one-to-two). That is, one light emission control signal line EM GOA circuit and the second scan signal line Gate2 GOA circuit drive the two rows of pixel driving circuits 10' located in the display area AA.

[0044] For example, such as Figure 2As shown, the compensation transistors T2 in adjacent pixel driving circuits 10' are driven by the same second scan signal line, Gate2. For example, the first reset transistor T1 and the compensation transistor T2 are LTPO (Low Temperature Polycrystalline Oxide) transistors, which are enabled by a high level, while the remaining transistors are LTPS (Low Temperature Poly-silicon) P-type transistors, which are enabled by a low level. A detailed description of the transistors and their connections in the pixel driving circuit 10' can be found in subsequent sections and will not be repeated here.

[0045] For example, such as Figure 3 As shown, this is the corresponding Figure 2 The driving timing diagram of the pixel driving circuit 10' shown is mainly divided into 6 stages: ① The light emission control signal line EM and the reset signal line Reset are both high, and the first node N1 is reset by the first initial signal line Vinit1 signal; ② The second scan signal line Gate2 jumps to a high level, and the compensation transistor T2 of the odd row and even row pixel driving circuit 10' is turned on simultaneously; ③ The scan signal Gate1-odd of the first scan signal line Gate1 of the odd row is low, and the data signal of the odd row is written to the driving transistor T2. 3. Threshold compensation is performed simultaneously; ④ The scan signal Gate1-even of the first scan signal line Gate1 of even row even is at a low level, and the data signal writing and threshold compensation of the driving transistor T3 of even row even are performed simultaneously; ⑤ The data signal writing and threshold compensation of the driving transistor T3 of odd row even row even row even row continue to be performed simultaneously using the parasitic capacitance of the second node N2, until the compensation transistor T2 of odd row even row even row even row is turned off simultaneously; ⑥ The light emission control signal line EM is at a low level, and the light emission of odd row even row even row even row even row is performed simultaneously.

[0046] The inventors discovered that in the aforementioned pixel driving circuit 10', through Figure 3 As can be seen from the driving timing diagram, the duration from the cutoff of the odd-numbered row's self-scanning signal Gate1-odd to the cutoff of the second scan signal line Gate2 is 'a', and the duration from the cutoff of the even-numbered row's self-scanning signal Gate1-even to the cutoff of the second scan signal line Gate2 is 'b', with duration 'a' being longer than duration 'b'.

[0047] After the first scan signal line Gate1 is cut off, regardless of whether it is an odd row (odd) or an even row (even), the pixel driving circuit 10' will continue to write data signals and perform threshold compensation to the first node N1 through the parasitic capacitance Ct of the second node N2 and the driving transistor T3. Since the parasitic capacitance Ct of the second node N2 of the pixel driving circuit 10' for odd rows (odd) and even rows (even) is exactly the same, the duration 'a' and duration 'b' of continuing to write data signals for odd rows (odd) and even rows (even) are different, with duration 'a' being longer than duration 'b'. Therefore, under the same data signal voltage, the compensation results for odd rows (odd) and even rows (even) will differ. This will ultimately be reflected in the display panel 100' as odd rows (odd) being dark and even rows (even) being bright, resulting in poor display quality.

[0048] Based on this, the present disclosure provides an array substrate 1, such as Figure 4 As shown, the array substrate 1 includes a substrate 101 and a plurality of pixel driving circuits 10 disposed on the substrate 101. Figure 5 As shown, each pixel driving circuit 10 in the plurality of pixel driving circuits 10 includes a transistor, the transistor including a driving transistor T3, a data writing transistor T4 and a first light-emitting control transistor T5.

[0049] like Figure 6 As shown, the array substrate 1 further includes: a first pole region and a second pole region of a transistor, the first pole region S3 of the driving transistor T3, the second pole region D4 of the data writing transistor T4 and the second pole region D5 of the first light-emitting control transistor T5 are connected to form a conductive connection pattern M1, and the conductive connection pattern M1 is a continuous pattern.

[0050] In the pixel driving circuit 10, such as Figure 5 As shown, the electrical connection point of the driving transistor T3, the data writing transistor T4, and the first light-emitting control transistor T5 is node N2. Therefore, in the layout design of the array substrate 1, the conductive connection pattern M1 region corresponds to the second node N2 in the pixel driving circuit 10.

[0051] It is understood that in the pixel driving circuit 10, the transistor includes a first electrode and a second electrode. The first electrode of the transistor in the pixel driving circuit 10 corresponds to the first electrode region of the transistor in the layout design of the array substrate 1, and the second electrode of the transistor in the pixel driving circuit 10 corresponds to the second electrode region of the transistor in the layout design of the array substrate 1. For example, Figure 6 The first pole S3 of the driving transistor T3 corresponds to Figure 5 The first electrode s3 of the driving transistor T3. Figure 6 Data is written to the second pole region D4 of transistor T4, corresponding to Figure 5Data is written to the second electrode d4 of transistor T4. Figure 6 The second electrode region D5 of the first light-emitting control transistor T5 corresponds to Figure 5 The second electrode d5 of the first light-emitting control transistor T5.

[0052] therefore, Figure 6 The conductive connection pattern M1, which connects the first electrode region S3 of the driving transistor T3, the second electrode region D4 of the data writing transistor T4, and the second electrode region D5 of the first light-emitting control transistor T5, corresponds to the junction point of the electrical connections of the first electrode S3 of the driving transistor T3, the second electrode D4 of the data writing transistor T4, and the second electrode D5 of the first light-emitting control transistor T5, i.e., node N2. Therefore, it can be understood that the conductive connection pattern M1 region, corresponding to the second node N2 in the pixel driving circuit 10, refers to the parasitic capacitance present at the second node N2, which is due to the parasitic capacitance generated in the conductive connection pattern M1 region during the layout design of the array substrate 1.

[0053] The term "parasitic" refers to a capacitor that was not originally designed for this location, but due to the mutual capacitance between wirings, this mutual capacitance can be considered as parasitic between wirings, hence the name parasitic capacitance, also known as stray capacitance.

[0054] It should be noted that in the circuits provided in the embodiments of this disclosure, nodes do not represent actual existing components, but rather represent the junctions of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junctions of related electrical connections in the circuit diagram.

[0055] like Figure 4 As shown, the plurality of pixel driving circuits 10 are configured as: an odd-numbered circuit group O1 and an even-numbered circuit group E1, each comprising a plurality of pixel driving circuits 10 arranged along a first direction X. Along a second direction Y, the odd-numbered circuit group O1 and the even-numbered circuit group E1 are alternately arranged. The first direction X and the second direction Y intersect.

[0056] For example, the first direction X is the row direction in which the multiple pixel driving circuits 10 are arranged, and each row of pixel driving circuits 10 is called a circuit group. The second direction Y is the column direction in which the multiple pixel driving circuits 10 are arranged. The multiple circuit groups are arranged along the second direction Y, namely the first row, the second row, the third row, ... the nth row. The first row, the third row, the fifth row, ... are all located in odd-numbered rows and can all be called odd-numbered circuit groups O1. The second row, the fourth row, the sixth row, ... are all located in even-numbered rows and can all be called even-numbered circuit groups E1. Therefore, the odd-numbered circuit groups O1 and the even-numbered circuit groups E1 are arranged alternately.

[0057] For example, the first direction X and the second direction Y are perpendicular.

[0058] like Figure 6 , Figure 11 , Figures 13-17 As shown, the array substrate 1 further includes a conductive pattern Q, which comprises a pattern in the pixel driving circuit 10 located on a different layer from the conductive connection pattern M1. The overlap area of ​​the orthographic projection of the conductive connection pattern M1 of at least one pixel driving circuit 10 in the odd-numbered circuit group O1 and the conductive pattern Q onto the substrate 101 is smaller than the overlap area of ​​the orthographic projection of the conductive connection pattern M1 of at least one pixel driving circuit 10 in the even-numbered circuit group E1 and the conductive pattern Q onto the substrate 101.

[0059] It should be noted that, in this disclosure, "orthographic projection" refers to a projection produced by projection lines that are perpendicular to the projection plane and are parallel to each other.

[0060] It is understandable that, such as Figure 4 As shown, the pixel driving circuit 10 is disposed on the substrate 101. Figures 5-17 The base 101 is not shown in the diagram. The location of the base 101 can be referenced. Figure 4 As shown.

[0061] To facilitate understanding of the conductive pattern Q of odd-numbered circuit group O1 and even-numbered circuit group E1, as follows: Figure 6 , Figure 11 , Figures 13-17 As shown, the conductive pattern Q of the odd-numbered circuit group O1 is represented as the first conductive pattern Q1, and the conductive pattern Q of the even-numbered circuit group E1 is represented as the second conductive pattern Q2.

[0062] When the orthographic projections of the conductive pattern Q and the conductive connection pattern M1 onto the substrate 101 overlap, a parasitic capacitance is generated between them. The magnitude of this parasitic capacitance is related to the size of the overlap area between their orthographic projections on the substrate 101. The larger the overlap area, the larger the parasitic capacitance.

[0063] For example, such as Figure 6 As shown, the overlap area between the orthographic projection of the conductive connection pattern M1 on the substrate 101 in the odd-numbered circuit group O1 and the orthographic projection of the first conductive pattern Q1 on the substrate 101 is smaller than the overlap area between the orthographic projection of the conductive connection pattern M1 on the substrate 101 and the orthographic projection of the second conductive pattern Q2 on the substrate 101 in the even-numbered circuit group E1. Therefore, the parasitic capacitance Ce generated by the even-numbered circuit group E1 at the second node N2 is greater than the parasitic capacitance Ce generated by the odd-numbered circuit group O1 at the second node N2.

[0064] As mentioned earlier, the durations 'a' and 'b' for continuing data signal writing in odd-numbered rows (odd) and even-numbered rows (even) are different, with duration 'a' being longer than duration 'b'. Please refer to the above for details, which will not be repeated here. This disclosure differentiates the parasitic capacitance Ce of the second node N2 of the odd-numbered circuit group O1 from that of the second node N2 of the even-numbered circuit group E1. The parasitic capacitance Ce of the second node N2 of the odd-numbered circuit group O1 is designed to be smaller, while the parasitic capacitance Ce of the second node N2 of the even-numbered circuit group E1 is designed to be larger.

[0065] Based on this design, under the existing one-to-two driving architecture of the compensation transistor T2, although the compensation time 'a' of the compensation transistor T2 in the odd-numbered circuit group O1 is greater than the compensation time 'b' of the compensation transistor T2 in the even-numbered circuit group E1 after the first scan signal line Gate1 is cut off, the parasitic capacitance Ce of the second node N2 in the even-numbered circuit group E1 is greater than the parasitic capacitance Co of the second node N2 in the odd-numbered circuit group O1.

[0066] Therefore, after the Gate1 signal of the first scan signal line is cut off, the potential of the second node N2 in the even-numbered circuit group E1 drops slowly, while the potential of the second node N2 in the odd-numbered circuit group O1 drops quickly. Although the compensation duration b in the even-numbered circuit group E1 is shorter than the compensation duration a in the odd-numbered circuit group O1, the amount of charge written in the same duration is greater due to the slower potential drop of the second node N2 in the even-numbered circuit group E1, ultimately resulting in the same compensation effect for the odd-numbered circuit group O1 and the even-numbered circuit group E1.

[0067] Under the same data voltage, the light-emitting devices L driven by the pixel driving circuit 10 of the odd row circuit group O1 and the pixel driving circuit 10 of the even row circuit group E1 have no difference in light emission brightness, thereby solving the problem of odd and even row brightness difference caused by the inconsistent compensation time of the compensation transistor T2 of the odd and even row pixel driving circuit 10, and improving the image quality of the display panel 100.

[0068] For example, the conductive pattern Q is located in a different layer from the conductive connection pattern M1 in the pixel driving circuit 10. The conductive pattern Q and the conductive connection pattern M1 are not connected, and the conductive pattern Q and the conductive connection pattern M1 are located in different film layers.

[0069] It should be noted that, as Figure 6As shown, to more clearly illustrate the structural design of the parasitic capacitance forming in the conductive connection pattern M1 region of the odd-numbered circuit group O1 and the even-numbered circuit group E1, other film layers that do not affect the differentiated design of parasitic capacitance are not shown in the figure. The design of other film layers on the array substrate 1 is not limited, and the same applies below. Furthermore, this disclosure focuses on the layout design of the conductive connection pattern M1 region as an example, and the design of other regions outside the conductive connection pattern M1 region is not limited.

[0070] In some embodiments, such as Figure 5 and Figure 7 As shown, the transistor also includes a compensation transistor T2. (As...) Figure 9 As shown, the array substrate 1 further includes: a gate pattern G2 of a compensation transistor T2 and a second scan signal line Gate2, wherein the gate pattern G4 of the compensation transistor T2 and the second scan signal line Gate2 are electrically connected. The second pole region D2 of the compensation transistor T2 is connected to the second pole region D3 of the driving transistor T3.

[0071] like Figure 4 and Figure 5 As shown, the multiple pixel driving circuits 10 are further configured as: multiple pixel group units 70 arranged sequentially along the second direction Y, each pixel group unit 70 including: an odd-numbered row circuit group O1 and an even-numbered row circuit group E1 arranged adjacent to the odd-numbered row circuit group O1, and each pixel group unit 70 shares a second scan signal line Gate2.

[0072] For example, the second direction Y is the column direction in which multiple pixel driving circuits 10 are arranged. Multiple circuit groups are arranged along the second direction Y, namely the first row, the second row, the third row... the nth row. The first row and the second row are a pixel group unit 70, the third row and the fourth row are a pixel group unit 70, the fifth row and the sixth row are a pixel group unit 70... and each pixel group unit 70 shares a second scan signal line Gate2.

[0073] Each pixel group unit 70 shares a second scan signal line Gate2, which is the Gate2-driven-two-pixel architecture. Under the Gate2-driven-two-pixel architecture, the design of this disclosure, namely the overlap area of ​​the orthographic projection of the conductive connection pattern M1 on the substrate 101 in the odd-numbered circuit group O1 and the orthographic projection of the conductive pattern Q on the substrate 101, is smaller than the overlap area of ​​the orthographic projection of the conductive connection pattern M1 on the substrate 101 and the orthographic projection of the conductive pattern Q on the substrate 101 in the even-numbered circuit group E1, can solve the problem of brightness difference between the light-emitting devices L driven by the odd-numbered circuit group O1 and the even-numbered circuit group E1.

[0074] To facilitate understanding of the design of the conductive pattern Q, the following will first introduce an example structure of the pixel driving circuit 10 and an example structure of the layout design of the array substrate 1. It should be understood that the following content is only an example of the structure of the pixel driving circuit 10 and the layout design of the array substrate 1, and is not a limitation on the structure of the pixel driving circuit 10 and the layout design of the array substrate 1.

[0075] In some embodiments, the pixel driving circuit 10 in this disclosure may be a circuit including 7T1C, 8T1C or 9T1C, where T represents a transistor, the number before T indicates the number of transistors, C represents a capacitor, and the number before C indicates the number of capacitors. For example, 7T1C represents 7 transistors and 1 capacitor.

[0076] In some embodiments, a description based on Figure 5 The pixel driving circuit 10 shown includes: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a second reset transistor T7.

[0077] For example, such as Figure 5 As shown, the first reset transistor T1 includes a gate g1, a first terminal s1, and a second terminal d1. The gate g1 of the first reset transistor T1 is electrically connected to the reset signal line terminal, the first terminal s1 of the first reset transistor T1 is electrically connected to the first initial signal terminal, and the second terminal d1 of the first reset transistor T1 is electrically connected to the first node N1. The reset signal terminal is used to receive the reset signal transmitted by the reset signal line Reset. The first initial signal terminal is used to receive the initial signal transmitted by the first initial signal line Vinit1. The first reset transistor T1 is configured to: in response to the reset signal received at the reset signal line Reset, transmit the initial signal received at the first initial signal line Vinit1 to the first node N1 to reset the gate g3 of the driving transistor T3.

[0078] It should be noted that the first electrode of the transistor in this disclosure is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first electrode and the second electrode of the transistor in the embodiments of this disclosure can be structurally indistinguishable. For example, in the case of a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, in the case of an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0079] For example, such as Figure 5As shown, the compensation transistor T2 includes a gate g2, a first electrode s2, and a second electrode d2. The gate g2 of the compensation transistor T2 is electrically connected to the second scan signal terminal, the first electrode s2 of the compensation transistor T2 is electrically connected to the first node N1, and the second electrode d2 of the compensation transistor T2 is electrically connected to the third node N3. The second scan signal terminal is used to receive the scan signal transmitted at the second scan signal line Gate2. The compensation transistor T2 is configured to perform threshold compensation on the driving transistor T3 in response to the scan signal received at the second scan signal line Gate2.

[0080] For example, such as Figure 5 As shown, the driving transistor T3 includes a gate g3, a first terminal s3, and a second terminal d3. The gate g3 of the driving transistor T3 is electrically connected to the first node N1, the first terminal s3 of the driving transistor T3 is electrically connected to the second node N2, and the second terminal d3 of the driving transistor T3 is electrically connected to the third node N3. The driving transistor T3 is configured to generate a driving current signal.

[0081] For example, such as Figure 5 As shown, the data writing transistor T4 includes a gate g4, a first terminal s4, and a second terminal d4. The gate g4 of the data writing transistor T4 is electrically connected to the first scan signal terminal, the first terminal s4 of the data writing transistor T4 is electrically connected to the data signal terminal, and the second terminal d4 of the data writing transistor T4 is electrically connected to the second node N2. The data signal terminal is used to receive the data signal transmitted by the data signal line Vdata. The data writing transistor T4 is configured to transmit the data signal received at the data signal line Vdata to the driving transistor T3 in response to the scan signal received at the first scan signal line Gate1.

[0082] For example, such as Figure 5 As shown, the first light-emitting control transistor T5 includes a gate g5, a first electrode g5, and a second electrode d5. The gate g5 of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal terminal, the first electrode g5 of the first light-emitting control transistor T5 is electrically connected to the power supply signal terminal, and the second electrode d5 of the first light-emitting control transistor T5 is electrically connected to the second node N2. The light-emitting control signal terminal is used to receive the light-emitting control signal transmitted by the light-emitting control signal line EM. The power supply signal terminal is used to receive the power supply signal transmitted by the power supply signal line ELVDD. The first light-emitting control transistor T5 is configured to transmit the power supply signal received at the power supply signal line ELVDD to the driving transistor T3 in response to the light-emitting control signal received at the light-emitting control signal line EM.

[0083] For example, such as Figure 5As shown, the second light-emitting control transistor T6 includes a gate g6, a first electrode s6, and a second electrode d6. The gate g6 of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal terminal, the first electrode s6 of the second light-emitting control transistor T6 is electrically connected to the third node N3, and the second electrode d6 of the second light-emitting control transistor T6 is electrically connected to the fourth node N4. The second light-emitting control transistor T6 is configured to transmit a drive current signal to the light-emitting device L in response to the light-emitting control signal received at the light-emitting control signal line EM, for driving the light-emitting device L to emit light.

[0084] For example, such as Figure 5 As shown, the second reset transistor T7 includes a gate g7, a first terminal s7, and a second terminal d7. The gate g7 of the second reset transistor T7 is electrically connected to the first scan signal terminal, the first terminal s7 of the second reset transistor T7 is electrically connected to the second initial signal terminal, and the second terminal d7 of the second reset transistor T7 is electrically connected to the fourth node N4. The second reset transistor T7 is configured to transmit the initial signal received at the second initial signal line Vinit2 to the light-emitting device L in response to the scan signal received at the first scan signal line Gate1, so as to reset the light-emitting device L.

[0085] For example, the anode of the light-emitting device L is electrically connected to the fourth node N4, and the cathode of the light-emitting device L is electrically connected to the reference voltage line ELVSS.

[0086] For example, such as Figure 5 As shown, the pixel driving circuit 10 further includes a capacitor Cst, which includes a first plate Cst1 and a second plate Cst2. The first plate Cst1 of the capacitor Cst is electrically connected to the first node N1, and the second plate Cst2 of the capacitor Cst is electrically connected to the power signal terminal.

[0087] For example, the first reset transistor T1 and the compensation transistor T2 can be oxide thin-film transistors, i.e., LTPO (Low Temperature Polycrystalline Oxide) transistors, which are turned on at a high level. The driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 are all P-type transistors of low temperature polysilicon thin film transistors, which are turned on at a low level.

[0088] The driving timing diagram of the pixel driving circuit 10 described above can be found in [reference]. Figure 3 This will not be elaborated upon here.

[0089] It should be noted that the examples of the first reset transistor T1, compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, and second reset transistor T7 are not intended to limit the types of transistors.

[0090] In some embodiments, a description based on Figure 7 The pixel driving circuit 10 shown includes: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, a third reset transistor T8, and a capacitor Cst.

[0091] Among them, the compensation transistor T2 can be an N-type transistor, and the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8 can be P-type transistors.

[0092] For example, such as Figure 7 As shown, the first terminal s2 of the compensation transistor T2 is connected to the gate g3 of the driving transistor T3, and the second terminal d2 is connected to the second terminal d3 of the driving transistor T3. The gate g2 is connected to the second scan signal terminal. The first terminal s1 of the first reset transistor T1 is connected to the first initial signal terminal, and the second terminal d1 is connected to the second terminal d2 of the compensation transistor T2. The gate g1 is connected to the first reset signal terminal. The first terminal s4 of the data writing transistor T4 is connected to the data signal terminal, and the second terminal d4 is connected to the first terminal s3 of the driving transistor T3. The gate g4 is connected to the first scan signal terminal. The first terminal s5 of the first light-emitting control transistor T5 is connected to the power supply signal terminal, and the second terminal d5 is connected to the first terminal s3 of the driving transistor T3. Gate g5 is connected to the light-emitting control signal terminal; the first terminal s6 of the second light-emitting control transistor T6 is connected to the second terminal d3 of the driving transistor T3, and gate g6 is connected to the light-emitting control signal terminal; the first terminal s7 of the second reset transistor T7 is connected to the second initial signal terminal, the second terminal d7 is connected to the second terminal d6 of the second light-emitting control transistor T6, and gate g7 is connected to the second reset signal terminal; the first terminal s8 of the third reset transistor T8 is connected to the third initial signal terminal, the second terminal d8 is connected to the first terminal s3 of the driving transistor T3, and gate g8 is connected to the second reset signal terminal; the first plate Cst1 of capacitor Cst is connected to the gate g3 of the driving transistor T3, and the second plate Cst2 is connected to the power supply signal terminal. This pixel driving circuit 10 can be used to drive the light-emitting device L to emit light.

[0093] The second scan signal terminal is used to receive the second scan signal transmitted by the second scan signal line Gate2. The first initial signal terminal is used to receive the first initial signal transmitted by the first initial signal line Vinit1. The first reset signal terminal is used to receive the first reset signal transmitted by the first reset signal line Reset1. The data signal terminal is used to receive the data signal transmitted by the data signal line Vdata. The first scan signal terminal is used to receive the first scan signal transmitted by the first scan signal line Gate1. The power signal terminal is used to receive the power signal transmitted by the power signal line ELVDD. The light emission control signal terminal is used to receive the light emission control signal transmitted by the light emission control signal line EM. The second initial signal terminal is used to receive the second initial signal transmitted by the second initial signal line Vinit2. The second reset signal terminal is used to receive the second reset signal transmitted by the second reset signal line Reset2. The third initial signal terminal is used to receive the third initial signal transmitted by the third initial signal line Vinit3.

[0094] For example, such as Figure 7 The timing diagram of the pixel driving circuit 10 shown is as follows: Figure 8 As shown, EM represents the timing diagram of the light emission control signal transmitted by the light emission control signal line EM; Gate1 represents the timing diagram of the first scan signal transmitted by the first scan signal line Gate1; Gate2 represents the timing diagram of the second scan signal transmitted by the second scan signal line Gate2; Reset1 represents the timing diagram of the first reset signal transmitted by the first reset signal line Reset1; and Reset2 represents the timing diagram of the second reset signal transmitted by the second reset signal line Reset2.

[0095] The driving method of the pixel driving circuit 10 in this disclosure may include a scan frame Ft. The scan frame Ft may include: a first reset stage t1, a second reset stage t2, a third reset stage t3, a data writing stage t4, and a light emission stage t5. In the first reset stage t1: the second scan signal terminal outputs a high-level signal, the second reset signal line Reset2 outputs a low-level signal, the compensation transistor T2, the second reset transistor T7, and the third reset transistor T8 are turned on, the second initial signal terminal inputs a second initial signal to the first electrode of the light-emitting device L, the third initial signal terminal inputs a third initial signal to the first electrode s3 of the driving transistor T3, and simultaneously, the driving transistor T3 can be turned on, and the third initial signal terminal writes a reset signal to the gate g3 of the driving transistor T3; In the second reset stage t2: the second scan signal terminal outputs a high-level signal, the first reset signal terminal outputs a low-level signal, the first reset transistor T1 and the compensation transistor T2 are turned on, and the first initial signal terminal inputs a first initial signal to the gate g3 of the driving transistor T3. In the third reset phase t3: the second scan signal terminal outputs a high-level signal, the first reset signal terminal outputs a low-level signal, the first reset transistor T1 and the compensation transistor T2 are turned on, and the first initial signal terminal inputs the first initial signal to the gate g3 of the driving transistor T3; in the data writing phase t4: the first scan signal terminal outputs a low-level signal, the second scan signal terminal outputs a high-level signal, the compensation transistor T2 and the data writing transistor T4 are turned on, and the data signal terminal outputs a data signal to write the compensation voltage to the gate g3 of the driving transistor T3; in the light emission phase t5: the light emission control signal terminal outputs a low-level signal, the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the driving transistor T3 drives the light emission device L to emit light under the voltage of its gate g3.

[0096] In this exemplary embodiment, the gate g3 of the driving transistor T3 is connected to the first initial signal terminal via the compensation transistor T2 and the first reset transistor T1, thereby reducing the leakage current of the driving transistor T3 to the first initial signal terminal during the light-emitting phase. Furthermore, during the first reset phase t1, the third initial signal terminal inputs a reset signal to the gate g3 of the driving transistor T3 and inputs a third initial signal to the first terminal g3 of the driving transistor T3. This configuration can restore the hysteresis of the driving transistor T3 caused by the bias voltage of the previous frame and resolve issues such as the first frame being too dark.

[0097] It should be noted that in other exemplary embodiments, the pixel driving circuit 10 may have other driving methods, and this disclosure does not limit the driving method of the pixel driving circuit 10.

[0098] The following is an exemplary description of a film layer design structure for an array substrate 1. It should be noted that the following example is not intended to limit the design of the film layer structure of the array substrate 1.

[0099] like Figure 10 As shown, the display panel 100 includes an array substrate 1 and a light-emitting device L. The pixel driving circuit 10 on the array substrate 1 is used to drive the light-emitting device L to emit light. The array substrate 1 includes a first semiconductor layer 13, a first gate conductive layer 15, a second gate conductive layer 17, a second semiconductor layer 61, a third gate conductive layer 62, a first source / drain metal layer 19, and a second source / drain metal layer 21, which are sequentially stacked on a substrate 101.

[0100] It should be noted that an insulating layer is also disposed between the functional film layers of the array substrate 1. The functional film layers include: a first semiconductor layer 13, a first gate conductive layer 15, a second gate conductive layer 17, a second semiconductor layer 61, a third gate conductive layer 62, a first source / drain metal layer 19, and a second source / drain metal layer 21. In the example diagram of the layout design, the insulating layer between the functional film layers is not shown to more clearly illustrate the stacking relationship between the functional film layers.

[0101] For example, such as Figure 10 As shown, the insulating layer includes: a first gate insulating layer 103, a second gate insulating layer 104, a first inorganic insulating layer 105, a third gate insulating layer 106, a second inorganic insulating layer 107, a passivation layer 108, a first planarization layer 109, and a second planarization layer 110.

[0102] For example, the pixel driving circuit 10 includes a first semiconductor layer 13, a first gate insulating layer 103, a first gate conductive layer 15, a second gate insulating layer 104, a second gate conductive layer 17, a first inorganic insulating layer 105, a second semiconductor layer 61, a third gate insulating layer 106, a third gate conductive layer 62, a second inorganic insulating layer 107, a first source / drain metal layer 19, a passivation layer 108, a first planarization layer 109, a second source / drain metal layer 21, and a second planarization layer 110, which are stacked sequentially.

[0103] For example, the materials of the first planarization layer 109 and the second planarization layer 110 include polyimide, and the materials of the first inorganic insulating layer 105 and the second inorganic insulating layer 107 include either silicon nitride or silicon oxide.

[0104] The following is a description of the conductive connection pattern M1 and the conductive pattern Q in this disclosure. The following embodiments can be understood based on the description of the pixel driving circuit 10 and the film layer design of the array substrate 1 in the above example.

[0105] In some embodiments, such as Figure 6 , Figure 11 , Figures 13-17 As shown, the array substrate 1 further includes a first semiconductor layer 13 disposed on the substrate 101, and a conductive connection pattern M1 is located on the first semiconductor layer 13.

[0106] For example, the material of the first semiconductor layer 13 includes P-Si (polycrystalline silicon).

[0107] For example, the conductive connection pattern M1 is located in the first semiconductor layer 13, and the parasitic capacitance of the second node N2 includes the parasitic capacitance between the conductive connection pattern M1 and the first gate conductive layer 15, the parasitic capacitance between the conductive connection pattern M1 and the second gate conductive layer 17, or the parasitic capacitance between the conductive connection pattern M1 and the first source / drain metal layer 19.

[0108] In some embodiments, such as Figure 6 As shown, the array substrate 1 further includes: a shielding layer 11 disposed on the substrate 101, and a first semiconductor layer 13 disposed on the side of the shielding layer 11 away from the substrate 101, with the conductive pattern Q located on the shielding layer 11.

[0109] For example, such as Figure 6 As shown, the overlapping area of ​​the orthographic projection of the conductive connection pattern M1 in the odd-numbered circuit group O1 onto the substrate 101 and the orthographic projection of the shielding layer 11 onto the substrate 101 is smaller than the overlapping area of ​​the orthographic projection of the conductive connection pattern M1 in the even-numbered circuit group E1 onto the substrate 101 and the orthographic projection of the shielding layer 11 onto the substrate 101.

[0110] In other words, such as Figure 6 As shown, in the layout design of the first semiconductor layer 13, the conductive connection pattern M1 in the odd-numbered circuit group O1 can have the same design shape and the same area as the conductive connection pattern M1 in the even-numbered circuit group E1. In the layout design of the shielding layer 11, the area of ​​the second conductive pattern Q2 is larger than the area of ​​the first conductive pattern Q1, such that the overlapping area of ​​the orthographic projection of the first conductive pattern Q1 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101 is smaller than the overlapping area of ​​the orthographic projection of the second conductive pattern Q2 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101. This achieves the goal that, in a pixel group unit 70, the parasitic capacitance of the pixel driving circuit 10 of the even-numbered circuit group E1 at the second node N2 is greater than the parasitic capacitance of the pixel driving circuit 10 of the odd-numbered circuit group O1 at the second node N2.

[0111] It is understandable that, in a pixel group unit 70, the overlapping area of ​​the orthographic projection of the first conductive pattern Q1 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101 can be smaller than the overlapping area of ​​the orthographic projection of the second conductive pattern Q2 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101.

[0112] Alternatively, in the entire layout design of the array substrate 1, the overlapping area of ​​the orthographic projection of all the first conductive patterns Q1 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101 can be smaller than the overlapping area of ​​the orthographic projection of all the second conductive patterns Q2 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101.

[0113] That is, in a pixel group unit 70, the goal is to achieve that the parasitic capacitance Ce of the pixel driving circuit 10 of the even-numbered circuit group E1 at the second node N2 is greater than the parasitic capacitance Co of the pixel driving circuit 10 of the odd-numbered circuit group O1 at the second node N2, and no limitation is set here.

[0114] For example, the shielding layer 11 can be connected to a fixed potential to shield the influence of surrounding stray charges on the driving transistor T3.

[0115] In some embodiments, such as Figure 11 As shown, the array substrate 1 further includes a first gate conductive layer 15 disposed on the side of the first semiconductor layer 13 away from the substrate 101, and a second gate conductive layer 17 disposed on the side of the first gate conductive layer 15 away from the substrate 101.

[0116] like Figure 5 and Figure 9 As shown, the pixel driving circuit 10 further includes a capacitor Cst and a compensation transistor T2. The capacitor Cst includes a first plate Cst1 and a second plate Cst2. The first plate Cst1 is located in the first gate conductive layer 15, and the second plate Cst2 is located in the second gate conductive layer 17. The first plate Cst1 is electrically connected to the first electrode region S2 of the compensation transistor T2, and the second plate Cst2 is electrically connected to the power signal line ELVDD.

[0117] It should be noted that the first plate Cst1 is connected to the first electrode region S2 of the compensation transistor T2 through a via, the second plate Cst2 is connected to the power signal line ELVDD through a via, and the first electrode region S5 of the first light-emitting control transistor T5 is connected to the power signal line ELVDD through a via. To more clearly show the position of each transistor, the connection pattern between the first plate Cst1 and the first electrode region S2 of the compensation transistor T2, and the connection pattern between the second plate Cst2 and the power signal line ELVDD are not shown.

[0118] like Figure 11 and Figure 12 As shown, the conductive pattern Q includes a first portion Qa located in the shielding layer 11 and a second portion Qb electrically connected to the second electrode Cst2.

[0119] For example, such as Figure 12As shown, a shielding layer 11, a first semiconductor layer 13, and a second gate conductive layer 17 are sequentially disposed on one side of the substrate 101. F represents the incident direction of the projection ray, which can be perpendicular to the plane of the substrate 101. Viewed from the incident direction of the projection ray, the area overlapping the second electrode Cst2 and the conductive connection pattern M1 is equal to the area overlapping the orthographic projection of the second electrode Cst2 onto the substrate 101 and the orthographic projection of the conductive connection pattern M1 onto the substrate 101.

[0120] from Figure 12 It can be seen that the overlapping area of ​​the orthographic projections of the conductive pattern Q and the conductive connection pattern M1 onto the substrate 101 comprises two parts: the overlapping area of ​​the second part Qb of the second electrode plate Cst2 and the conductive connection pattern M1 in the projection ray direction, and the overlapping area of ​​the first part Qa of the shielding layer 11 and the conductive connection pattern M1 in the projection ray direction. Therefore, in this embodiment, the conductive connection pattern M1 is located between the second electrode plate Cst2 and the shielding layer 11, forming a sandwich parasitic capacitance on the conductive connection pattern M1. The magnitude of this sandwich parasitic capacitance is proportional to the sum of the overlapping areas of the second part Qb of the second electrode plate Cst2 and the conductive connection pattern M1 in the projection ray direction, and the overlapping areas of the first part Qa of the shielding layer 11 and the conductive connection pattern M1 in the projection ray direction.

[0121] For example, such as Figure 12 As shown, the sum of the overlap areas of the second portion Qb of the second electrode Cst2 in the odd-numbered circuit group O1 and the conductive connection pattern M1 in the projection ray direction, and the sum of the overlap areas of the first portion Qa of the shielding layer 11 and the conductive connection pattern M1 in the projection ray direction, is smaller than that of the sum of the overlap areas of the second portion Qb of the second electrode Cst2 in the even-numbered circuit group E1 and the conductive connection pattern M1 in the projection ray direction. This allows for a larger design of the parasitic capacitance Ce of the second node N2 in the even-numbered circuit group E1, thus resolving the brightness difference between the light-emitting devices L driven by the odd-numbered circuit group O1 and the even-numbered circuit group E1.

[0122] In some embodiments, such as Figure 13 As shown, the array substrate 1 includes a first gate conductive layer 15 disposed on the side of the first semiconductor layer 13 away from the substrate 101, and a second gate conductive layer 17 disposed on the side of the first gate conductive layer 15 away from the substrate 101. The conductive pattern Q is located in the second gate conductive layer 17.

[0123] For example, such as Figure 13As shown, the pixel driving circuit 10 further includes a capacitor Cst, which includes a first electrode Cst1 and a second electrode Cst2. The first electrode Cst1 is located on the first gate conductive layer 15, and the second electrode Cst2 is located on the second gate conductive layer 17. The conductive pattern Q located on the second gate conductive layer 17 is electrically connected to the second electrode Cst2, which can also be understood as the conductive pattern Q being located on the second electrode Cst2.

[0124] For example, such as Figure 13 As shown, the second electrode Cst2 in the odd-numbered circuit group O1 is provided with a first conductive pattern Q1, and the second electrode Cst2 in the even-numbered circuit group E1 is provided with a second conductive pattern Q2. The overlapping area of ​​the orthographic projection of the first conductive pattern Q1 on the substrate 101 in the odd-numbered circuit group O1 and the orthographic projection of the conductive connection pattern M1 on the substrate 101 is smaller than the overlapping area of ​​the orthographic projection of the second conductive pattern Q2 on the substrate 101 and the orthographic projection of the conductive connection pattern M1 on the substrate 101 in the even-numbered circuit group E1. This achieves the goal of making the parasitic capacitance Ce generated by the even-numbered circuit group E1 at the second node N2 greater than the parasitic capacitance Ce generated by the odd-numbered circuit group O1 at the second node N2, thus solving the problem of brightness difference between the light-emitting devices L driven by the odd-numbered circuit group O1 and the even-numbered circuit group E1.

[0125] In some embodiments, such as Figure 14 As shown, the area of ​​the conductive pattern Q in the odd-numbered circuit group O1 projected onto the substrate 101 is equal to the area of ​​the conductive pattern Q in the even-numbered circuit group E1 projected onto the substrate.

[0126] For example, the conductive pattern Q is located on the second plate Cst2, and the design area of ​​the second plate Cst2 is the same in both the odd-numbered circuit group O1 and the even-numbered circuit group E1. In other words, in the layout design, the second plate Cst2 in the odd-numbered circuit group O1 and the even-numbered circuit group E1 can have the same shape and equal area.

[0127] like Figure 14 As shown, in the even-numbered circuit group E1, the conductive connection pattern M1 is connected to the first extended pattern U1 located on the first semiconductor layer 13, and the orthographic projection of the conductive pattern Q on the substrate 101 covers the orthographic projection of the first extended pattern U1 on the substrate 101.

[0128] For example, such as Figure 14 As shown, in the even-numbered circuit group E1, the first extended pattern U1 is connected to the conductive connection pattern M1 and both are located in the first semiconductor layer 13. The first extended pattern U1 and the conductive connection pattern M1 can be integrally molded. That is to say, the design area of ​​the conductive connection pattern M1 in the even-numbered circuit group E1 is larger than the design area of ​​the conductive connection pattern M1 in the odd-numbered circuit group O1.

[0129] In the even-numbered circuit group E1, the orthographic projection of the second conductive pattern Q2 onto the substrate 101 covers the orthographic projection of the first extended pattern U1 onto the substrate 101. Therefore, in the even-numbered circuit group E1, the parasitic capacitance Ce of the second node N2 is related to the overlapping area of ​​the orthographic projections of the second conductive pattern Q2 onto the substrate 101, the conductive connection pattern M1, and the first extended pattern U1 onto the substrate 101. This overlapping area is larger than the overlapping area of ​​the orthographic projections of the first conductive pattern Q1 and the conductive connection pattern M1 onto the substrate 101 in the odd-numbered circuit group O1. This design, where the parasitic capacitance Ce of the second node N2 in the even-numbered circuit group E1 is larger than the parasitic capacitance Co of the second node N2 in the odd-numbered circuit group O1, solves the problem of brightness difference between the light-emitting devices L driven by the odd-numbered circuit group O1 and the even-numbered circuit group E1.

[0130] It should be noted that, as Figure 14 As shown, in the even-numbered circuit group E1 and the odd-numbered circuit group O1, the orthographic projection of the shielding layer 11 onto the substrate 101 overlaps with the orthographic projection of the conductive connection pattern M1 onto the substrate 101, and the overlapping area is the same. Therefore, in the even-numbered circuit group E1 and the odd-numbered circuit group O1, the presence of the shielding layer 11 causes the second node N2 to generate equal parasitic capacitance. Thus, it does not affect the differentiated design of the parasitic capacitance of the second node N2 in the even-numbered circuit group E1 and the odd-numbered circuit group O1.

[0131] Therefore, it can be understood that the conductive pattern Q is the definition of a pattern that compares the even-numbered circuit group E1 and the odd-numbered circuit group O1, resulting in a differential design of the parasitic capacitance of the second node N2.

[0132] In some embodiments, such as Figure 15 As shown, the array substrate 1 further includes a second gate conductive layer 17 disposed on the side of the first semiconductor layer 13 away from the substrate 101. The array substrate 1 also includes a second scan signal line Gate2, which is located on the second gate conductive layer 17. The conductive pattern Q and the second scan signal line Gate2 are integrally formed.

[0133] For example, such as Figure 15As shown, in both the even-numbered circuit group E1 and the odd-numbered circuit group O1, the conductive connection pattern M1 has the same design shape and area. The orthographic projection of the second scanning signal line Gate2 on the substrate 101 overlaps with the orthographic projection of the conductive connection pattern M1 on the substrate 101. The area of ​​the first conductive pattern Q1 located on the second scanning signal line Gate2 in the odd-numbered circuit group O1 is smaller than the area of ​​the second conductive pattern Q2 on the second scanning signal line Gate2 in the even-numbered circuit group E1. This design ensures that the parasitic capacitance Ce of the second node N2 in the even-numbered circuit group E1 is greater than the parasitic capacitance Co of the second node N2 in the odd-numbered circuit group O1, thus solving the problem of brightness difference between the light-emitting devices L driven by the odd-numbered circuit group O1 and the even-numbered circuit group E1.

[0134] It should be noted that, as Figure 15 As shown, in the even-numbered circuit group E1 and the odd-numbered circuit group O1, the orthographic projection of the shielding layer 11 onto the substrate 101 overlaps with the orthographic projection of the conductive connection pattern M1 onto the substrate 101, and the overlapping area is the same. The orthographic projection of the second electrode plate Cst2 located on the second gate conductive layer 17 onto the substrate 101 overlaps with the orthographic projection of the conductive connection pattern M1 onto the substrate 101, and the overlapping area is the same.

[0135] Therefore, in both even-numbered circuit group E1 and odd-numbered circuit group O1, the presence of the shielding layer 11 results in equal parasitic capacitance at the second node N2, and the presence of the second electrode Cst2 also results in equal parasitic capacitance at the second node N2. Neither of these factors affects the differentiated design of the parasitic capacitance at the second node N2 in both even-numbered circuit group E1 and odd-numbered circuit group O1. Therefore, in both even-numbered circuit group E1 and odd-numbered circuit group O1, the portion where the orthographic projection of the shielding layer 11 and the second electrode Cst2 onto the substrate 101 overlaps with the orthographic projection of the conductive connection pattern M1 onto the substrate 101 is not referred to as the aforementioned conductive pattern Q.

[0136] In some embodiments, such as Figure 16 As shown, the array substrate 1 further includes: a second gate conductive layer 17 disposed on the side of the first semiconductor layer 13 away from the substrate 101, and a first source / drain metal layer 19 disposed on the side of the second gate conductive layer 17 away from the substrate 101. The first source / drain metal layer 19 includes a second extended pattern U2. The conductive pattern Q is located on the second gate conductive layer 17. In the even-numbered circuit group E1, the second extended pattern U2 and the conductive connection pattern M1 are connected through a via H1.

[0137] For example, such as Figure 16As shown, in the even-numbered circuit group E1, the second extended pattern U2 located in the first source-drain metal layer 19 is connected to the conductive connection pattern M1 located in the first semiconductor layer 13 through a via H1, which is equivalent to increasing the area of ​​the conductive connection pattern M1. The second extended pattern U2 and the conductive connection pattern M1 have the same function, that is, they can form a parasitic capacitance with the conductive pattern Q.

[0138] Therefore, as Figure 16 As shown, in the even-numbered circuit group E1, the second conductive pattern Q2 is located on the second electrode Cst2, which is located on the second gate conductive layer 17. The second extended pattern U2 is connected to the conductive connection pattern M1. The second electrode Cst2 is located between the second extended pattern U2 and the conductive connection pattern M1. A parasitic capacitance is formed between the conductive connection pattern M1 and the second conductive pattern Q2. At the same time, a parasitic capacitance is also formed between the second extended pattern U2 and the second conductive pattern Q2, thereby increasing the parasitic capacitance Ce of the second node N2 in the even-numbered circuit group E1.

[0139] For example, the overlapping area of ​​the orthographic projection of the second extended pattern U2 on the substrate 101 in the odd-numbered circuit group O1 and the orthographic projection of the second electrode Cst2 on the substrate 101 can be set to be smaller than the overlapping area of ​​the orthographic projection of the second extended pattern U2 on the substrate 101 and the orthographic projection of the second electrode Cst2 on the substrate 101 in the even-numbered circuit group E1, thereby realizing the differentiated design of the parasitic capacitance of the second node N2 of the even-numbered circuit group E1 and the odd-numbered circuit group O1.

[0140] For example, such as Figure 16 As shown, in the odd-numbered circuit group O1, the second extended pattern U2 can be omitted. In this case, it can be considered that the difference in parasitic capacitance of the second node N2 of the even-numbered circuit group E1 and the odd-numbered circuit group O1 is caused by the setting of the second extended pattern U2 in the even-numbered circuit group E1.

[0141] In some embodiments, such as Figure 17 As shown, the array substrate 1 further includes a first source / drain metal layer 19 disposed on the side of the first semiconductor layer 13 away from the substrate 101. The first source / drain metal layer 19 includes a third extended pattern U3, and the third extended pattern U3 is connected to the conductive connection pattern M1 through a via H1.

[0142] For example, a third extended pattern U3 is provided in both the even-numbered circuit group E1 and the odd-numbered circuit group O1, and the shape and area of ​​the third extended pattern U3 in the even-numbered circuit group E1 and the odd-numbered circuit group O1 are the same. The third extended pattern U3 is connected to the conductive connection pattern M1 through the via H1, thereby increasing the area of ​​the conductive connection pattern M1. The third extended pattern U3 and the conductive connection pattern M1 have the same function, that is, they can form a parasitic capacitance with the conductive pattern Q.

[0143] like Figure 17 As shown, the array substrate 1 further includes a second source / drain metal layer 21 disposed on the side of the first source / drain metal layer 19 away from the substrate 101, the second source / drain metal layer 21 including a power signal line ELVDD. The conductive pattern Q and the power signal line ELVDD are integrally formed. The overlapping area of ​​the orthographic projection of the third extended pattern U3 on the substrate 101 in the odd-numbered circuit group O1 and the orthographic projection of the conductive pattern Q on the substrate 101 is smaller than the overlapping area of ​​the orthographic projection of the third extended pattern U3 on the substrate 101 and the orthographic projection of the conductive pattern Q on the substrate 101 in the even-numbered circuit group E1.

[0144] For example, such as Figure 17 As shown, in the even-numbered circuit group E1, the second conductive pattern Q2 and the power signal line ELVDD are integrated into one structure. The orthographic projection of the second conductive pattern Q2 on the substrate 101 overlaps with the orthographic projection of the third extended pattern U3 on the substrate 101. Therefore, a parasitic capacitance is formed between the second conductive pattern Q2 and the third extended pattern U3. This achieves the purpose of increasing the parasitic capacitance Ce of the second node N2 in the even-numbered circuit group E1.

[0145] And, as Figure 17 As shown, in the even-numbered circuit group E1, a second gate conductive layer 17 is disposed between the third extended pattern U3 and the first semiconductor layer 13. The orthographic projection of the pattern on the second gate conductive layer 17 connected to the second electrode Cst2 onto the substrate 101 overlaps with the orthographic projections of the third extended pattern U3 and the first semiconductor layer 13 onto the substrate 101. Therefore, parasitic capacitances are formed between the first semiconductor layer 13 and the second electrode Cst2, between the second electrode Cst2 and the third extended pattern U3, and between the third extended pattern U3 and the second conductive pattern Q2, thus forming a multilayer capacitor.

[0146] In some embodiments, such as Figure 17 As shown, in the odd-numbered circuit group O1, the orthographic projection of the power signal line ELVDD on the substrate 101 does not overlap with the orthographic projection of the third extended pattern U3 on the substrate 101.

[0147] For example, such as Figure 17As shown, compared to the power signal line ELVDD in the odd-numbered circuit group O1, the orthographic projection of the power signal line ELVDD in the even-numbered circuit group E1 onto the substrate 101 overlaps with the orthographic projection of the third extended pattern U3 onto the substrate 101, while the orthographic projection of the power signal line ELVDD in the odd-numbered circuit group O1 onto the substrate 101 does not overlap with the orthographic projection of the third extended pattern U3 onto the substrate 101. This achieves the purpose of increasing the parasitic capacitance Ce of the second node N2 in the even-numbered circuit group E1.

[0148] For example, such as Figure 17 As shown, the orthographic projection of the third extended pattern U3 on the substrate 101 overlaps with the orthographic projection of the conductive connection pattern M1 on the substrate 101. The third extended pattern U3 and the conductive connection pattern M1 are connected through a via H1, such that the second electrode Cst2 disposed between the third extended pattern U3 and the conductive connection pattern M1 forms parasitic capacitances with both the third extended pattern U3 and the conductive connection pattern M1, which is beneficial to increasing the parasitic capacitance of the second node N2 in the pixel driving circuit 10.

[0149] In some embodiments, such as Figure 18 As shown, the array substrate 1 further includes: a first source / drain metal layer 19 disposed on the side of the first semiconductor layer 13 away from the substrate 101, and a second source / drain metal layer 21 disposed on the side of the first source / drain metal layer 19 away from the substrate 101. The second source / drain metal layer 21 includes a data signal line Vdata and a power signal line ELVDD. The conductive pattern Q and the power signal line ELVDD are integrally structured.

[0150] In the odd-numbered circuit group O1, the overlapping area of ​​the orthographic projections of the first conductive pattern and the conductive connection pattern M1 onto the substrate 101 is smaller than the overlapping area of ​​the orthographic projections of the second conductive pattern Q2 and the conductive pattern Q onto the substrate 101 in the even-numbered circuit group E1. To avoid the influence of the data signal line Vdata, the data signal line Vdata is designed to avoid overlap with the orthographic projection of the conductive connection pattern M1 onto the substrate 101.

[0151] In some examples, the conductive pattern Q is located in a different layer from the conductive connection pattern M1 in the pixel driving circuit 10. For example, the conductive pattern Q may be electrically connected to the reference voltage line ELVSS, electrically connected to the first initial signal line Vinit1, electrically connected to the second initial signal line Vinit2, or electrically connected to other constant voltage lines, etc., without limitation.

[0152] Based on the above introduction of conductive connection pattern M1 and conductive pattern Q, the following example illustrates another film layer design of array substrate 1.

[0153] In some embodiments, such as Figure 19 As shown, the transistors include: a first reset transistor T1, a compensation transistor T2, a second light-emitting control transistor T6, and a second reset transistor T7. The array substrate 1 also includes: a first initial signal line Vinit1, a second initial signal line Vinit2, a data signal line Vdata, and a power signal line ELVDD.

[0154] The first electrode region S1 of the first reset transistor T1 is electrically connected to the first initial signal line Vinit1. The second electrode region D1 of the first reset transistor T1 is electrically connected to the first electrode region S2 of the compensation transistor T2. The second electrode region D2 of the compensation transistor T2 is electrically connected to the second electrode region D3 of the driving transistor T3. The first electrode region S6 of the second light-emitting control transistor T6 is electrically connected to the second electrode region D3 of the driving transistor T3. The second electrode region D6 of the second light-emitting control transistor T6 is electrically connected to the second electrode region D7 of the second reset transistor T7. The first electrode region S7 of the second reset transistor T7 is electrically connected to the second initial signal line Vinit2. The first electrode region S4 of the data writing transistor T4 is electrically connected to the data signal line Vdata. The first electrode region S5 of the first light-emitting control transistor T5 is electrically connected to the power signal line ELVDD.

[0155] For example, such as Figure 9 As shown, the array substrate 1 further includes: a gate pattern G1 of a first reset transistor T1, a reset signal line Reset, a gate pattern G7 of a second reset transistor T7, a first scan signal line Gate1, a gate pattern G5 of a first light-emitting control transistor T5, a gate pattern G6 of a second light-emitting control transistor T6, and a light-emitting control signal line EM. The gate pattern G1 of the first reset transistor T1 is electrically connected to the reset signal line Reset, the gate pattern G7 of the second reset transistor T7 is electrically connected to the first scan signal line Gate1, and the gate patterns G5 of the first light-emitting control transistor T5 and G6 of the second light-emitting control transistor T6 are electrically connected to the light-emitting control signal line EM.

[0156] For example, such as Figure 19As shown, the array substrate 1 includes: a first semiconductor layer 13 disposed on one side of the substrate 101, with a conductive connection pattern M1 located on the first semiconductor layer 13. The array substrate 1 includes: a first gate conductive layer 15 disposed on the side of the first semiconductor layer 13 away from the substrate 101, with a first scan signal line Gate1 and a light emission control signal line EM located on the first gate conductive layer 15. The array substrate 1 includes: a second gate conductive layer 17 disposed on the side of the first gate conductive layer 15 away from the substrate 101, with a first initial signal line Vinit1 and a reset signal line Reset located on the second gate conductive layer 17. The array substrate 1 includes: a first source / drain metal layer 19 disposed on the side of the second gate conductive layer 17 away from the substrate 101, with a second initial signal line Vinit2 located on the first source / drain metal layer 19. The array substrate 1 includes: a second source / drain metal layer 21 disposed on the side of the first source / drain metal layer 19 away from the substrate, with a data signal line Vdata and a power signal line ELVDD located on the second source / drain metal layer 21.

[0157] In some embodiments, such as Figure 9 and Figure 19 As shown, the compensation transistor T2 and the first reset transistor T1 are oxide thin-film transistors. For example, the compensation transistor T2 and the first reset transistor T1 are N-type oxide thin-film transistors. The array substrate 1 also includes a second semiconductor layer 61 and a third gate conductive layer 62 disposed between the second gate conductive layer 17 and the first source / drain metal layer 19, wherein the third gate conductive layer 62 is disposed on the side of the second semiconductor layer 61 away from the substrate 101.

[0158] For example, the material of the second semiconductor layer 61 includes indium gallium zinc oxide, but is not limited thereto. The channel portions of the compensation transistor T2 and the first reset transistor T1 are located in the second semiconductor layer 61, and the gate patterns of the compensation transistor T2 and the first reset transistor T1 are located in the third gate conductive layer 62.

[0159] Some embodiments of this disclosure also provide an array substrate 1, such as Figure 4 As shown, the array substrate 1 includes a substrate 101 and a plurality of pixel driving circuits 10 disposed on the substrate 101. Figure 5 As shown, each pixel driving circuit 10 in the plurality of pixel driving circuits 10 includes a transistor, the transistor including a driving transistor T3, a data writing transistor T4 and a first light-emitting control transistor T5.

[0160] The array substrate 1 further includes: a first pole region and a second pole region of a transistor, the first pole region S3 of the driving transistor T3, the second pole region D4 of the data writing transistor T4 and the second pole region D5 of the first light-emitting control transistor T5 are connected to form a conductive connection pattern M1, and the conductive connection pattern M1 is a continuous pattern.

[0161] like Figure 4 As shown, the plurality of pixel driving circuits 10 are configured as: an odd-numbered circuit group O1 and an even-numbered circuit group E1, each comprising a plurality of pixel driving circuits 10 arranged along a first direction X. Along a second direction Y, the odd-numbered circuit group O1 and the even-numbered circuit group E1 are alternately arranged. The first direction X and the second direction Y intersect.

[0162] like Figure 6 , Figure 11 , Figures 13-17 As shown, the array substrate 1 further includes a conductive pattern Q, which comprises a pattern in the pixel driving circuit 10 located on a different layer from the conductive connection pattern M1. The capacitance Co formed by the conductive connection pattern M1 and the conductive pattern Q of at least one pixel driving circuit 10 in the odd-numbered circuit group O1 is less than the capacitance Ce formed by the conductive connection pattern M1 and the conductive pattern Q of at least one pixel driving circuit 10 in the even-numbered circuit group E1.

[0163] For example, an insulating layer is provided between each functional film layer of the array substrate 1. By adjusting the different insulating layers, the capacitance value of the capacitor Co formed by the conductive connection pattern M1 and the conductive pattern Q in the odd-numbered circuit group O1 and the capacitance value Ce formed by the conductive connection pattern M1 and the conductive pattern Q in the even-numbered circuit group E1 can be differentiated (i.e., capacitance value).

[0164] In some embodiments, the insulating layer between the conductive connection pattern M1 and the conductive pattern Q of at least one pixel driving circuit 10 in the odd-numbered circuit group O1 is made of the same material as the insulating layer between the conductive connection pattern M1 and the conductive pattern Q of at least one pixel driving circuit 10 in the even-numbered circuit group E1.

[0165] For example, the insulation layer thickness between conductive connection pattern M1 and conductive pattern Q in odd-numbered circuit group O1 can be set to be greater than that between conductive connection pattern M1 and conductive pattern Q in even-numbered circuit group E1. This results in the capacitance Co formed by conductive connection pattern M1 and conductive pattern Q in odd-numbered circuit group O1 being less than the capacitance Ce formed by conductive connection pattern M1 and conductive pattern Q in even-numbered circuit group E1.

[0166] In some embodiments, the insulating layer between the conductive connection pattern M1 and the conductive pattern Q of at least one pixel driving circuit 10 in the odd-numbered circuit group O1, and the insulating layer between the conductive connection pattern M1 and the conductive pattern Q of at least one pixel driving circuit 10 in the even-numbered circuit group E1, comprises at least one insulating layer of the same material.

[0167] For example, by adjusting the material difference between the insulating layer between the conductive connection pattern M1 and the conductive pattern Q in the odd-numbered circuit group O1 and the insulating layer between the conductive connection pattern M1 and the conductive pattern Q in the even-numbered circuit group E1, a differentiated design can be achieved for the capacitance value Co formed by the conductive connection pattern M1 and the conductive pattern Q in the odd-numbered circuit group O1 and the capacitance value Ce formed by the conductive connection pattern M1 and the conductive pattern Q in the even-numbered circuit group E1. Furthermore, by using at least one insulating layer of the same material in both the odd-numbered circuit group O1 and the even-numbered circuit group E1, the number of process steps for forming the film layer on the array substrate 1 can be reduced.

[0168] In some embodiments, such as Figure 11 As shown, the array substrate 1 further includes a first gate conductive layer 15 disposed on the side of the first semiconductor layer 13 away from the substrate 101, and a second gate conductive layer 17 disposed on the side of the first gate conductive layer 15 away from the substrate 101. Figure 9 As shown, the pixel driving circuit 10 further includes a capacitor Cst, which includes a first electrode Cst1 and a second electrode Cst2. The first electrode Cst1 is located in the first gate conductive layer 15, and the second electrode Cst2 is located in the second gate conductive layer 17. Figure 20 As shown, the capacitance value of capacitor Cst in odd-numbered circuit group O1 is greater than the capacitance value of capacitor Cst in even-numbered circuit group E1.

[0169] In other words, the storage capacitance of capacitor Cst in odd-numbered circuit group O1 is greater than that in even-numbered circuit group E1. This is beneficial for the rapid input of data signals from even-numbered circuit group E1 to the first node N1, thus compensating for the insufficient time b for writing data signals and threshold compensation to the first node N1 in even-numbered circuit group E1.

[0170] For example, such as Figure 20 As shown, the projected area of ​​the first plate Cst1 of capacitor Cst in odd-numbered circuit group O1 on substrate 101 is larger than the projected area of ​​the first plate Cst1 of capacitor Cst in even-numbered circuit group E1 on substrate 101. This achieves the goal of making the capacitance value of capacitor Cst in odd-numbered circuit group O1 greater than the capacitance value of capacitor Cst in even-numbered circuit group E1.

[0171] In some embodiments, such as Figure 21As shown, a pixel driving circuit 10 disposed on the array substrate 1 is used to drive light-emitting devices L that emit different colors of light. The pixel driving circuit 10 includes a first pixel driving circuit 10a, a second pixel driving circuit 10b, and a third pixel driving circuit 10c. For example, the first pixel driving circuit 10a is used to drive the light-emitting device L that emits green light, the second pixel driving circuit 10b is used to drive the light-emitting device L that emits red light, and the third pixel driving circuit 10c is used to drive the light-emitting device L that emits blue light.

[0172] like Figure 21 As shown, since the green light emitted by the light-emitting device L is brighter, the parasitic capacitance Ct of the second node N2 of the odd and even rows of the first pixel driving circuit 10a can be designed differently. For example, the capacitance value Co of the parasitic capacitance Co of the second node N2 of the first pixel driving circuit 10a in the odd row circuit group O1 is smaller than the capacitance value Ce of the parasitic capacitance Ce of the second node N2 of the first pixel driving circuit 10a in the even row circuit group E1.

[0173] The parasitic capacitance Ct of the second node N2 of the second pixel driving circuit 10b and the third pixel driving circuit 10c is not differentiated. For example, in the odd-numbered circuit group O1 and the even-numbered circuit group E1, the parasitic capacitance Ct of the second node N2 of the second pixel driving circuit 10b and the third pixel driving circuit 10c is equal. Alternatively, the parasitic capacitance Ct of the second node N2 of the second pixel driving circuit 10b and the third pixel driving circuit 10c is differentiated according to the chromaticity of the light-emitting device L emitting red light and the light-emitting device L emitting blue light.

[0174] For the differentiated design scheme of the parasitic capacitance Ct of the second node N2, please refer to the above content, and it will not be repeated here.

[0175] In some embodiments, since the light-emitting device L that emits green light has a high turn-on voltage, the following two examples are provided to eliminate the problem of uneven display brightness caused by brightness differences.

[0176] For example, such as Figure 22 As shown, in the same row of circuit groups, the capacitance value of capacitor Cst of the first pixel driving circuit 10a is smaller than the capacitance value of capacitor Cst of the second pixel driving circuit 10b and the third pixel driving circuit 10c. For example, the projected area of ​​the first plate Cst1 of capacitor Cst of the first pixel driving circuit 10a on the substrate 101 is smaller than the projected area of ​​the first plate Cst1 of capacitor Cst of the second pixel driving circuit 10b on the substrate 101, and smaller than the projected area of ​​the first plate Cst1 of capacitor Cst of the third pixel driving circuit 10c on the substrate 101.

[0177] For example, such as Figure 23 As shown, in the same row of circuit groups, the parasitic capacitance Ct of the second node N2 of the first pixel driving circuit 10a is greater than the parasitic capacitance Ct of the second node N2 of the second pixel driving circuit 10b, and greater than the parasitic capacitance Ct of the second node N2 of the third pixel driving circuit 10c. For example, the overlapping area of ​​the orthographic projections of the conductive pattern Q and the conductive connection pattern M1 of the first pixel driving circuit 10a onto the substrate 101 is greater than the overlapping area of ​​the orthographic projections of the conductive pattern Q and the conductive connection pattern M1 of the second pixel driving circuit 10b onto the substrate 101, and greater than the overlapping area of ​​the orthographic projections of the conductive pattern Q and the conductive connection pattern M1 of the third pixel driving circuit 10c onto the substrate 101.

[0178] Some embodiments of this disclosure also provide a display device 1000, such as Figure 24 As shown, the display device 1000 includes the array substrate 1 provided in any of the above embodiments.

[0179] The display device provided in this disclosure can be any device that displays text or images, whether in motion (e.g., video) or stationary (e.g., still images). More specifically, the embodiments are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0180] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, include: A substrate and a plurality of pixel driving circuits disposed on the substrate; Each pixel driving circuit in the plurality of pixel driving circuits includes a transistor, the transistor including a driving transistor, a data writing transistor and a first light-emitting control transistor; the transistor includes a first pole region and a second pole region; the first pole region of the driving transistor, the second pole region of the data writing transistor and the second pole region of the first light-emitting control transistor are connected to a second node; The plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit arranged along a first direction, wherein the first pixel driving circuit and the second pixel driving circuit are used to drive light-emitting devices of different colors to emit light. The array substrate further includes: a conductive pattern, the conductive pattern including a pattern in the pixel driving circuit that is located on a different layer from the second node; The overlapping area of ​​the second node in the first pixel driving circuit and the orthographic projection of the conductive pattern in the first pixel driving circuit onto the substrate is different from the overlapping area of ​​the second node in the second pixel driving circuit and the orthographic projection of the conductive pattern in the second pixel driving circuit onto the substrate.

2. The array substrate according to claim 1, characterized in that, The plurality of pixel driving circuits further include: a third pixel driving circuit, wherein the first pixel driving circuit, the second pixel driving circuit and the third pixel driving circuit are used to drive light-emitting devices of different colors to emit light; Wherein, the overlapping area of ​​the second node in the first pixel driving circuit and the orthographic projection of the conductive pattern in the first pixel driving circuit on the substrate is greater than the overlapping area of ​​the second node in the second pixel driving circuit and the orthographic projection of the conductive pattern in the second pixel driving circuit on the substrate, and the overlapping area of ​​the second node in the first pixel driving circuit and the orthographic projection of the conductive pattern in the first pixel driving circuit on the substrate is greater than the overlapping area of ​​the second node in the third pixel driving circuit and the orthographic projection of the conductive pattern in the third pixel driving circuit on the substrate.

3. The array substrate according to claim 1, characterized in that, The plurality of pixel driving circuits further include: a third pixel driving circuit, wherein the first pixel driving circuit, the second pixel driving circuit and the third pixel driving circuit are used to drive light-emitting devices of different colors to emit light; Wherein, the capacitance value between the second node in the first pixel driving circuit and the conductive pattern in the first pixel driving circuit is greater than the capacitance value between the second node in the second pixel driving circuit and the conductive pattern in the second pixel driving circuit, and the capacitance value between the second node in the first pixel driving circuit and the conductive pattern in the first pixel driving circuit is greater than the capacitance value between the second node in the third pixel driving circuit and the conductive pattern in the third pixel driving circuit.

4. The array substrate according to claim 1, characterized in that, Also includes: A second source / drain metal layer is disposed on the side of the second node away from the substrate. The second source / drain metal layer includes a constant voltage line, and the conductive pattern is electrically connected to the constant voltage line.

5. The array substrate according to claim 4, characterized in that, Also includes: A first source / drain metal layer is disposed between the second node and the second source / drain metal layer, the first source / drain metal layer including a third extended pattern, the third extended pattern being electrically connected to the second node.

6. The array substrate according to claim 5, characterized in that, In the second pixel driving circuit, the orthographic projection of the power signal line on the substrate does not overlap with the orthographic projection of the third extended pattern on the substrate.

7. The array substrate according to claim 5, characterized in that, The orthographic projection of the third extended pattern onto the substrate overlaps with the orthographic projection of the second node onto the substrate.

8. The array substrate according to claim 1, characterized in that, Also includes: A second source / drain metal layer is disposed on the side of the second node away from the substrate. The second source / drain metal layer includes a power signal line. The first electrode region of the first light-emitting control transistor is electrically connected to the power signal line. The conductive pattern and the power signal line are an integral structure.

9. The array substrate according to claim 8, characterized in that, Also includes: A data signal line, wherein the first pole region of the data writing transistor is electrically connected to the data signal line; The data signal line is located in the second source / drain metal layer.

10. The array substrate according to claim 1, characterized in that, Also includes: A shielding layer is disposed between the substrate and the second node; The conductive pattern is located in the shielding layer.

11. The array substrate according to claim 10, characterized in that, Also includes: A first gate conductive layer is disposed on the side of the second node away from the substrate, and a second gate conductive layer is disposed on the side of the first gate conductive layer away from the substrate; The pixel driving circuit further includes a capacitor, which includes a first electrode plate and a second electrode plate, wherein the first electrode plate is located in the first gate conductive layer and the second electrode plate is located in the second gate conductive layer. The conductive pattern includes a first portion located in the shielding layer and a second portion electrically connected to the second electrode plate.

12. The array substrate according to claim 1, characterized in that, Also includes: A first gate conductive layer is disposed on the side of the second node away from the substrate, and a second gate conductive layer is disposed on the side of the first gate conductive layer away from the substrate; The pixel driving circuit further includes a capacitor, which includes a first electrode plate and a second electrode plate, wherein the first electrode plate is located in the first gate conductive layer and the second electrode plate is located in the second gate conductive layer. The conductive pattern is located in the second gate conductive layer and is connected to the second electrode plate.

13. The array substrate according to claim 12, characterized in that, Also includes: A first semiconductor layer disposed between the substrate and the first gate conductive layer; The area of ​​the orthographic projection of the conductive pattern in the first pixel driving circuit onto the substrate is equal to the area of ​​the orthographic projection of the conductive pattern in the second pixel driving circuit onto the substrate. In the first pixel driving circuit, a first extended pattern located on the first semiconductor layer is connected to the second node, and the orthogonal projection of the conductive pattern on the substrate covers the orthogonal projection of the first extended pattern on the substrate.

14. The array substrate according to claim 1, characterized in that, The transistor further includes: a compensation transistor; The array substrate further includes: the gate pattern of the compensation transistor and the second scan signal line; the gate pattern of the compensation transistor and the second scan signal line are electrically connected; the second pole region of the compensation transistor is connected to the second pole region of the driving transistor; The array substrate further includes: a second gate conductive layer disposed on the side of the second node away from the substrate, and the second scan signal line is located in the second gate conductive layer; The conductive pattern and the second scanning signal line are an integral structure.

15. The array substrate according to claim 1, characterized in that, The transistor further includes: a compensation transistor; The array substrate further includes: the gate pattern of the compensation transistor and the second scan signal line; the gate pattern of the compensation transistor and the second scan signal line are electrically connected; the second pole region of the compensation transistor is connected to the second pole region of the driving transistor; The plurality of pixel driving circuits are further configured as: a plurality of pixel group units arranged sequentially along the second direction, each of the plurality of pixel group units including: two rows of pixel driving circuits arranged adjacent to each other along the second direction; each of the pixel group units sharing a second scan signal line; the first direction and the second direction intersect.

16. A display device, characterized in that, Includes the array substrate as described in any one of claims 1 to 15.

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