Instruction package constraint solving and generation method, electronic device, and computer program product
By decomposing the instruction packet constraint solving process into local operation parameter solving and slot-by-slot allocation, the efficiency and completeness issues of instruction packet verification in multi-slot concurrent environments in the prior art are solved, and efficient instruction packet generation is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI CHAOWEI WUJI ELECTRONIC TECHNOLOGY CO LTD
- Filing Date
- 2026-06-23
- Publication Date
- 2026-07-21
AI Technical Summary
Existing technologies struggle to balance complex semantic and structural solutions in multi-slot concurrent environments when validating instruction packages for AI inference accelerators. The solution completeness falls far short of the ideal state, and the solution efficiency is low.
The hybrid constraint solution of the instruction package is divided into three processes: solving the first operation parameter, allocating slots for instruction instances, and solving the constraint solver. By solving the first operation parameter with local action and allocating physical slots one by one, the complexity of the global slot uniqueness constraint is reduced, and the overall semantic validity of the instruction package is preserved during the constraint solution time.
It significantly improves the efficiency and completeness of instruction packet constraint solving, ensures the generation of legal instruction sequences within an acceptable time, and reduces computational complexity and time consumption.
Smart Images
Figure CN122431737A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip verification technology, specifically to a method for solving and generating instruction packet constraints, electronic devices, and computer program products. Background Technology
[0002] AI inference accelerators, such as Tensor Processing Units (TPUs) and Neural Processing Units (NPUs), commonly employ Very Long Instruction Word (VLIW) architectures. Compared to general-purpose CPUs, this architecture can issue multiple instructions in parallel to multiple physical execution slots within a single clock cycle. Furthermore, general-purpose TPUs have massive instruction sets with hundreds of instruction operation types, exhibiting both local independent constraints and global coupling constraints within and between instruction packets. Functional verification of such ultra-wide VLIW instruction packets requires a hybrid constraint-solving approach adapted to the hierarchical constraint characteristics. This approach separately addresses local independent constraints within instruction packets and global coupling constraints between instruction packets, thereby generating a valid random instruction sequence.
[0003] Currently, constraint solving for instruction packets mainly falls into three categories, all of which suffer from insurmountable technical defects: First, there are RISC-V DV-type general-purpose random instruction generation tools. These tools are designed for scalar single-issue pipelines, generating instructions sequentially in a serial manner. They are not adapted to the concurrent execution characteristics of VLIW multi-slots, and cannot constrain cross-slot instruction allocation rules within the same instruction packet. They also cannot cover concurrent semantic constraints such as instruction pairing and bit field borrowing, as well as hardware resource conflicts such as register preemption, memory conflicts, and FIFO queue read / write dependencies. This results in a large number of legal instruction scenarios not being covered, leading to insufficient solution completeness. Second, there are global joint solution schemes based on SystemVerilog constraint solvers. This scheme can achieve overall constraint verification of instruction packets, ensuring instruction legality, but it has a significant performance bottleneck: the uniqueness constraint of a single instruction in a single slot in VLIW needs to be implemented through pairwise inequalities with O(N²) complexity. The solver needs to simultaneously complete instruction selection, slot mapping, and field configuration joint solving in a high-dimensional space, resulting in a huge computational load and extremely low instruction generation efficiency. Thirdly, there are script-pre-allocation or random retry schemes. The former is prone to losing the ability of the SV constraint solver to handle complex semantic constraints, such as memory block bitmap, register dependency, first-in-first-out queue state, and instruction packet resource occupation. The latter checks the uniqueness after randomly generating slot combinations, which not only has a high failure probability and requires repeated retries, but also has the problem of extremely low efficiency and possible timeout.
[0004] It is evident that the existing technology has the following drawbacks: 1) When constrained solving is performed using instruction packets as the whole unit, it is difficult to simultaneously address complex semantic and structural solutions, resulting in a solution completeness that is far from the ideal state; 2) It is impossible to complete the solution within an acceptable time. Summary of the Invention
[0005] The technical problem solved by this application is to provide a method for solving and generating instruction packet constraints, an electronic device and a computer program product, which can ensure that the results of solving instruction packet constraints are valid in both structure and semantics in a multi-slot concurrent environment, making the completeness of the solution closer to the ideal state, and ensuring the efficiency of the solution.
[0006] According to a first aspect of the embodiments of this application, a method for generating an instruction packet is provided, comprising: The first operation parameter of the current instruction packet is constrained and solved using a random object to obtain the value of the first operation parameter; the first operation parameter includes the identification information of at least one first operation type that should be activated in the current instruction packet and the number of instructions for each first operation type; A first queue is constructed based on the value of the first operation parameter. The first queue includes at least one first instruction instance. Each first instruction instance includes identification information of a first operation type and the corresponding number of instructions. A second queue is constructed based on the value of a second operation parameter, the second operation parameter including a second operation type specified by the test scenario, and the second queue includes at least one second instruction instance, each second instruction instance including identification information of a second operation type; In accordance with the order of the second queue first and then the first queue, physical slots are allocated to each instruction instance, and each physical slot can accommodate at most one instruction instance, thus obtaining the slot allocation result; The acquired set of test semantic constraints, the slot allocation result, and the value of the first operation parameter are input into the constraint solver for solving, to obtain the register address, memory instruction address, storage map, first-in-first-out queue management scheme, predicate field value, and operand field value; the operand field is the operation parameter other than the first operation type and the second operation type in the current instruction packet.
[0007] Compared with existing technologies, this application divides the hybrid constraint solution of instruction packets into three processes: solving the first operation parameter, allocating slots for instruction instances, and solving the constraint solver. Specifically, in solving the first operation parameter, this application limits the solution to first operation parameters with a dimension lower than a preset value, local effects, and sparse coupling. This type of operation parameter does not introduce slot uniqueness during the solution process. The algorithm complexity is O(n). The application avoids pairwise mutual exclusion constraints and does not introduce complex cross-field semantic constraints such as memory banks, address modulo operations, and register dependencies. Therefore, the solution complexity for this type of operation parameter is significantly lower than that of global joint solution. Furthermore, once the first and second instruction instances are known, this application allocates physical slots to all instruction instances to be allocated sequentially according to the queue sequence, and limits each physical slot to at most one instruction instance. This achieves the goal of ensuring that slots within the same instruction packet are not repeatedly occupied without constructing pairwise inequalities between all instruction instances, thereby ensuring that slots are not repeatedly occupied. The global slot mutual exclusion constraint is transformed into The sequential allocation operation significantly improves processing efficiency. By determining the legal structure for the constraint solving stage in the first two stages, and using the semantic constraint set as input to the constraint solver, only complex parameters such as semantic constraints are solved, thereby resolving instruction dependencies and resource conflicts within and between instruction packets. In other words, this application does not remove complex semantic constraints from the constraint solving process, but rather decouples them from other solving content. By providing a structural foundation for semantic solving through the pre-process, it maintains the overall semantic and structural legality at the instruction packet level while keeping the constraint solving time within an acceptable range, further approaching the ideal state of solution completeness.
[0008] In one implementation, the following rules are satisfied when allocating physical slots: Physical slot allocation is performed on only one instruction instance at a time; the instruction instance is either the second instruction instance or the first instruction instance. For any physical slot, when it is occupied, it is stored in the occupied slot set; For any of the instruction instances, when it is allocated, only the physical slots of the non-occupied slot set are opened, and the slot selection variable corresponding to the instruction instance is locked only when the allocation is successful; the value of the slot selection variable is the identification information of the physical slot to which the current instruction instance is allocated.
[0009] In one implementation, if any of the second instruction instances fails to be assigned, the constraint solving process is terminated.
[0010] In one implementation, if the allocation of the first instruction instance fails, the following operations are performed: If there are available physical slots, but none of the available physical slots match the first instruction instance to be allocated, then the first operation parameter corresponding to the first instruction instance to be allocated is set to zero, and the constraint solution process continues. When all physical slots are occupied, the first operation parameter of the first instruction instance to be allocated and all subsequent first instruction instances in the first queue is set to zero, and the constraint solving process continues.
[0011] By adopting differentiated allocation failure handling strategies for the first and second queues, the above-described implementation can ensure the mandatory execution of necessary operations in the test scenario and avoid the generation of invalid test sequences. At the same time, it can flexibly disable optional random operations without interrupting the overall solution process, thereby improving the fault tolerance, solution efficiency and stability of the constraint solution method.
[0012] In one implementation, when each instruction instance in the first queue and the second queue has completed its physical slots and is in a verification scenario of extreme stress test, slot utilization stress test or full release test, the remaining unoccupied physical slots are filled according to a preset rule.
[0013] In one implementation, the set of test semantic constraints includes at least register dependencies, first-in-first-out (FIFO) read / write rules, memory address and storage bank rules, predicate emission rules, and special instruction field rules. This implementation uses these semantic constraints as input to a constraint solver to resolve instruction dependencies and resource occupancy conflicts within the same instruction packet, thereby ensuring that the solution satisfies the following conditions: multiple instructions cannot illegally contend for the same register write-back resource; illegal read / write conflicts cannot occur in the same storage bank; and FIFO read / write rules cannot violate capacity and data validity constraints.
[0014] In one implementation, the input to the constraint solver further includes: historical states injected by the resource manager, and fixed constraints of test cases or configuration files.
[0015] The above implementation introduces fixed constraints from use cases or configuration files and historical states injected by the resource manager as solver inputs. Data such as register busy / idle status, FIFO queue depth, memory state, and pipeline latency generated by adjacent or historical instruction packets are used as prerequisite states for solving the current instruction packet constraints. This fully restores the context of continuous hardware operation, effectively avoids instruction dependencies and resource conflicts between instruction packets, and improves the accuracy of solving the semantic fields of instruction packets.
[0016] According to a second aspect of the embodiments of this application, a method for generating an instruction packet is provided, the method comprising: The first operation parameter of the current instruction packet is constrained and solved using a random object to obtain the value of the first operation parameter; the first operation parameter includes the identification information of at least one first operation type that should be activated in the current instruction packet and the number of instructions for each first operation type; A first queue is constructed based on the value of the first operation parameter. The first queue includes at least one first instruction instance. Each first instruction instance includes identification information of a first operation type and the corresponding number of instructions. A second queue is constructed based on the value of a second operation parameter, the second operation parameter including a second operation type specified by the test scenario, and the second queue includes at least one second instruction instance, each second instruction instance including identification information of a second operation type; Following the order of the second queue first and then the first queue, physical slots are allocated to each instruction instance, and each physical slot can accommodate at most one instruction instance, thus obtaining the slot allocation result; the slot allocation result and the value of the first operation parameter are structural parameters. The acquired set of test semantic constraints and structural parameters are input into the constraint solver for solving to obtain semantic parameters; the semantic parameters include: register address, memory instruction address, storage block map, first-in-first-out queue management scheme, predicate field value, and operand field value; the operand field consists of operation parameters other than the first and second operation types in the current instruction packet; Instruction packets are generated based on the aforementioned structural and semantic parameters.
[0017] According to a third aspect of the embodiments of this application, an electronic device is provided, including a memory and a processor, wherein the memory is used to store a computer program executable by the processor; and the processor is used to execute the computer program in the memory to implement the above-described instruction packet constraint solving method or instruction packet generation method.
[0018] According to a fourth aspect of the embodiments of this application, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described instruction packet constraint solving method or instruction packet generation method. Attached Figure Description
[0019] Figure 1 This is a flowchart illustrating a method for solving instruction packet constraints according to an exemplary embodiment; Figure 2 This is a flowchart illustrating an instruction packet generation method according to an exemplary embodiment; Figure 3 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation
[0020] Unless otherwise defined, the technical or scientific terms used in this specification and claims shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. Specific embodiments of this application will be described below in conjunction with the accompanying drawings. It should be noted that, in order to provide a concise description, this specification cannot exhaustively describe all features of the actual embodiments. Without departing from the spirit and scope of this application, those skilled in the art can modify and substitute the embodiments of this application, and the resulting embodiments are also within the protection scope of this application.
[0021] As mentioned earlier, when solving instruction packet constraints, the following problems exist: most solutions are difficult to adapt to the concurrent operation logic of the VLIW architecture, the generated results cannot simultaneously take into account complex semantic and structural solutions, and the completeness of the solution is far from the ideal state, making it difficult to meet the needs of practical applications. On the other hand, the solution method that can guarantee instruction compliance has a high computational load and runs slowly; while the mode of relying on pre-allocation or repeated trial and error either has a greatly reduced ability to handle complex constraints or has high trial and error costs and poor operational stability, making it difficult to complete the solution within an acceptable time.
[0022] To address the aforementioned technical problems, this application proposes a method for solving and generating instruction packet constraints, an electronic device, and a computer program product. By decoupling the operational structure from the instruction semantics, the constraint solver no longer needs to solve semantic constraints, but does not need to simultaneously handle pairwise mutual exclusion relationships of a large number of slots. While maintaining the instruction packet as the overall solution unit and preserving the ability to solve complex semantic constraints, it eliminates the constraints caused by the uniqueness of VLIW slots. This addresses the issues of constraint explosion and timeout, significantly reducing constraint solution time and enabling rapid generation of individual instruction packets.
[0023] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0024] One embodiment of this application provides a method for solving instruction packet constraints. This method can be applied to an instruction packet generation method and related products. Please refer to... Figure 1 The method for generating an instruction packet includes: Step 101: Use a random object to solve for the constraints of the first operation parameter of the current instruction packet to obtain the value of the first operation parameter.
[0025] It should be noted that in step 101, the first operation parameter is a parameter with a dimension lower than the preset value, which only has local effect and coefficient coupling. It includes at least one first operation type that should be activated in the current instruction package and the number of instructions for each first operation type. In addition, parameters such as the upper and lower bounds of the total number of instructions and probability distribution constraints can be solved according to the test requirements.
[0026] If this step fails, it indicates that the test constraints or fixed configurations conflict with each other. You can choose to reduce the number of target instructions, re-randomize, or report an error directly.
[0027] Through this step, this application can only determine the types of optional operations that should be activated in the current instruction package and the corresponding number of instructions by using the first operation parameter. Such parameters are not related to cross-instruction semantic constraints such as physical slot uniqueness, register dependency, and memory conflict. Therefore, its solution complexity is significantly lower than that of global joint solution.
[0028] Step 102: Construct the first queue based on the value of the first operation parameter.
[0029] It should be emphasized that the first queue includes at least one first instruction instance, and each first instruction instance includes identification information of a first operation type and the corresponding number of instructions.
[0030] Step 103: Construct a second queue based on the value of the second operation parameter.
[0031] It should be emphasized that the second operation parameter includes the second operation type specified by the test scenario, and the second queue includes at least one second instruction instance, each second instruction instance including identification information of a second operation type.
[0032] Step 104: Allocate physical slots for each instruction instance in the order of the second queue first and then the first queue, and each physical slot can hold at most one instruction instance, to obtain the slot allocation result.
[0033] It should be noted that there is no clear sequential relationship between the aforementioned steps 103 and 104.
[0034] After determining the optional operation types and their corresponding instruction instances in the previous step, unlike traditional methods, this application does not delegate the physical slot selection and semantic constraints of all instruction instances to the constraint solver all at once. Instead, this step assigns physical operations to each instruction instance to be allocated in the first and second queues, prioritizing the allocation of instruction instances in the second queue. This not only eliminates... The large-scale computation caused by global slot mutual exclusion constraints can ensure that the instructions required for the test scenario are executed. In addition, shuffling can be performed in the first and second queues to maximize the randomness of the operation arrangement while satisfying the scenario constraints.
[0035] In some embodiments, the following rules must be met when allocating physical slots: 1) Only one instruction instance is allocated a physical slot at a time, where the instruction instance here is either the second instruction instance or the first instruction instance mentioned above.
[0036] 2) For any physical slot, when it is occupied, it is stored in the occupied slot set.
[0037] 3) For any instruction instance, when it is allocated, only the physical slots of the non-occupied slot set are opened, and a valid slot is selected according to the available slot range of the operation type corresponding to the instruction. The slot selection variable corresponding to the instruction instance is locked only when the allocation is successful. The value of this slot selection variable is the identifier information of the physical slot to which the current instruction instance is assigned.
[0038] It should be noted that the slot allocation result must include the slot selection variable for each instruction instance. In addition to the internally maintained set of occupied slots, optionally, it may also include the status of idle slots and their corresponding launch readiness status.
[0039] By allocating slots one instruction instance at a time and locking them immediately after allocation, it is possible to ensure that slots within the same instruction packet are not occupied repeatedly without constructing pairwise inequalities between instruction instances, thereby reducing algorithm complexity.
[0040] In some embodiments, if any second instruction instance fails to be assigned, the constraint solving process is terminated.
[0041] In some embodiments, if the allocation of a first instruction instance fails, the following operations are performed: if there are available physical slots, but none of the available physical slots match the first instruction instance to be allocated, the first operation parameter corresponding to the first instruction instance to be allocated is set to zero, and the constraint solving process continues; if all physical slots are occupied, the first operation parameter of the first instruction instance to be allocated and all subsequent first instruction instances in the first queue are set to zero, and the constraint solving process continues.
[0042] The reason is that if the allocation of the second instruction instance fails, it means that the current scenario it represents cannot execute the operation that must occur in the test scenario under the existing fixed conditions, and does not meet the test requirements. Therefore, the solution process needs to be interrupted. The first instruction instance represents the optional random operation generated in step 101, which is not necessary to execute. Therefore, the instruction instance can be discarded by setting its corresponding operation enable op_enable and its instruction count instr_num to 0, without affecting the global constraint solution process.
[0043] In some embodiments, when each instruction instance in the first queue and the second queue has completed its physical slots and is in a verification scenario of extreme stress test, slot utilization stress test or full release test, the remaining unoccupied physical slots are filled according to a preset rule.
[0044] For example, the filling process can be as follows: after all instruction instances in all queues have been allocated, unoccupied physical slots are filtered out, and instruction instances corresponding to legally pursuable operations are selected for filling based on the known mapping relationship between physical operations and operation types.
[0045] In special cases, this operation may be omitted during formal random regression or general functional verification, reserving some empty slots to maintain the natural distribution of random scenarios.
[0046] Step 105: Input the obtained test semantic constraint set, slot allocation result and the value of the first operation parameter into the constraint solver for solving.
[0047] In this application, the structural parameters are fixed through steps 101 to 104. In this step, the complex semantic parameters that still need to be randomized, such as register address, memory instruction address, memory mapping diagram, first-in-first-out queue management scheme, predicate field value, and operand field value, are solved.
[0048] The first-in-first-out (FIFO) queue management scheme includes FIFO queue depth, storable data types, and available space management; the operand field contains the operation parameters that are required by instruction packets other than the first and second operation types in the current instruction packet.
[0049] In some embodiments, the set of test semantic constraints includes at least register dependencies, first-in-first-out read / write rules, memory address and storage rules, predicate emission rules, and special instruction field rules.
[0050] Through the above operations, it is ensured that the constraint solver can resolve instruction dependencies and resource conflicts within the same instruction package when solving. For example, multiple instructions within the same instruction package cannot illegally contend for the same register write-back resource, illegal read-write conflicts cannot occur in the same memory bank, and the first-in-first-out read-write rule cannot violate capacity and data validity constraints.
[0051] In some embodiments, the input to the constraint solver may also include: historical states injected by the resource manager, and fixed constraints of test cases or configuration files.
[0052] The above operations ensure that the constraint solver can resolve instruction dependencies and resource conflicts between instruction packets during the solution process, such as register busy / idle conditions, FIFO queue depth, memory state, and pipeline delays caused by adjacent or historical instruction packets. It should be noted that the constraint solver mentioned in this application can be selected according to the requirements of the test environment.
[0053] It should also be noted that if step 105 fails to solve, it means that the structural parameters obtained from the first two steps conflict with the current resource state or semantic constraints. In this case, the current instruction packet can be discarded and re-randomized, or diagnostic information can be output for the test cases to adjust.
[0054] In summary, the technical solution provided in this application has the following advantages: 1) By decoupling the structural and semantic solutions, specifically, the structural parameter solution process... The global slot mutual exclusion constraint is transformed into The sequential allocation operation eliminates the need for the constraint solver to handle the complete slot uniqueness constraint; it only needs to solve the semantic constraint. This significantly reduces the solution time while still preserving the overall semantic validity at the instruction package level and cross-instruction coverage.
[0055] 2) This application distinguishes instruction instances into first instruction instances and second instruction instances, differentiates between mandatory operations and optional random operations, and provides different error reporting and fault tolerance mechanisms for different types of operation instances, which can prevent the overall generation of instruction packages from failing.
[0056] 3) This application prioritizes slot uniqueness allocation instead of rewriting all semantic constraints, which is beneficial for reusing existing verification assets and reducing engineering migration costs.
[0057] To verify the feasibility and superiority of the instruction package constraint solving method provided in this application, an embodiment is also provided to apply the above method in a UVM-based AI chip verification environment, and the constraint solver is selected as the SV constraint solver. The detailed process is described above and will not be repeated here. The scenario is set as follows: A) Full slot pressure scenario.
[0058] In this scenario, the test configuration requires that the physical slots of the entire instruction packet be filled with instructions as much as possible; the solution is performed using the method provided in this application and by using only the SV constraint solver. When using the method provided in this application, a higher target instruction quantity is selected in step 101. In step 104, the sequential slot allocation of the first and second queues is completed first, and the slot filling channel can be opened to fill the remaining empty slots. Subsequently, in step 105, the SV constraint solver is used to solve for the semantic parameter values only based on the already determined slot mapping.
[0059] B) A scenario where most physical slots are assigned commands, but a small number of physical slots are not assigned commands.
[0060] In this scenario, most physical slots within the instruction packet have been assigned instructions, but a small number of physical slots are still allowed to remain in a non-issue state; the solution is performed using the method provided in this application and by using only the SV constraint solver.
[0061] In this scenario, when using a single SV joint solution, the solver still needs to simultaneously determine whether a large number of instruction instances are enabled, issued, and whether there are slot and resource conflicts with other instances, which will inevitably lead to a still high solution time. When using the instruction package constraint solution method provided in this application, step 101 first determines candidate operations, step 104 eliminates slot uniqueness conflicts, and step 105 only processes the remaining semantic constraints.
[0062] C) A scenario where a small portion of physical slots are allocated commands, while most physical slots do not issue commands.
[0063] In this scenario, only a small portion of the physical slots were assigned instructions; the solution was obtained using the method provided in this application and by using only the SV constraint solver.
[0064] Although the instruction size is relatively small in this scenario, the SV constraint solver still needs to derive a large number of inactive or unissued branches in the global constraint system and handle conditional slot uniqueness, resource conflicts, and semantic field constraints. Therefore, the time consumption does not decrease linearly with the final number of issued instructions. However, when using the instruction packet constraint solving method provided in this application, steps 101 to 104 first converge the structural range actually involved in the solution in step 105. In step 105, the SV constraint solver no longer handles complete slot uniqueness constraints.
[0065] After solving the above three scenarios, the time consumed by the two methods was statistically analyzed, and the results are shown in Table 1.
[0066] Table 1. Solving time parameters for different scenarios
[0067] As can be seen, this application changes the organization of constraint solving in the constraint solving process: firstly, the structural selection and slot uniqueness, which are prone to combinatorial explosion, are separated from the global SV joint solution, and then the SV constraint solver completes the solution of complex semantic legality. This not only retains the ability of the SV constraint solver to handle complex resource correlations, but also avoids the long solution time problem caused by the strong coupling between slot uniqueness and semantic constraints when using the SV constraint solver alone.
[0068] Another embodiment of this application provides a method for generating instruction packets, the process of which is as follows: Figure 2 As shown, it includes: Step 201: Use a random object to solve for the constraints of the first operation parameter of the current instruction packet to obtain the value of the first operation parameter.
[0069] In this step, the first operation parameter includes identification information of at least one first operation type that should be activated by the current instruction package and the number of instructions for each first operation type. Step 201 is similar to step 101 described above, and will not be repeated here.
[0070] Step 202: Construct a first queue based on the value of the first operation parameter. The first queue includes at least one first instruction instance. Each first instruction instance includes identification information of a first operation type and the corresponding number of instructions.
[0071] Step 202 is similar to step 102 above, and will not be repeated here.
[0072] Step 203: Construct a second queue based on the value of the second operation parameter. The second operation parameter includes the second operation type specified by the test scenario. The second queue includes at least one second instruction instance, and each second instruction instance includes identification information of a second operation type.
[0073] Step 203 is similar to step 103 above, and will not be repeated here.
[0074] Step 204: Allocate physical slots for each instruction instance in the order of the second queue first and then the first queue, and each physical slot can accommodate at most one instruction instance, to obtain the slot allocation result.
[0075] It should be noted that the slot allocation result and the value of the first operation parameter in this step are structural parameters, and step 204 is similar to step 104 above, so it will not be repeated here.
[0076] Step 205: Input the obtained test semantic constraint set and structural parameters into the constraint solver for solving to obtain semantic parameters. It should be noted that semantic parameters include: register address, memory instruction address, memory block map, first-in-first-out queue management scheme, predicate field value, and operand field value; the operand field consists of operation parameters other than the first and second operation types in the current instruction packet.
[0077] Step 205 is similar to step 105 above, and will not be repeated here.
[0078] Step 206: Generate instruction packets based on structural and semantic parameters.
[0079] The method embodiments of this application and the related product embodiments can complement each other.
[0080] Embodiments of this application also provide an electronic device 600, such as... Figure 3 As shown, the electronic device 600 includes a memory 601 and a processor 602. The memory 601 is used to store computer programs in a computer program product executable by the processor 602. The processor 602 is used to execute the computer programs in the memory 601 to implement the instruction packet constraint solving method and instruction packet generation method provided in any of the above embodiments.
[0081] The electronic device 600 also includes a communication interface 603. The processor 602, memory 601, and communication interface 603 are connected via a communication bus and communicate with each other.
[0082] Processor 602 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of programs in the above scheme.
[0083] Communication interface 603 is used to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Networks (WLAN), etc.
[0084] The memory 601 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory may exist independently and be connected to the processor via a bus. The memory may also be integrated with the processor.
[0085] Embodiments of this application also propose a computer program product, including a computer program that, when executed by a processor, implements the instruction packet constraint solving method or instruction packet generation method of any of the above embodiments.
[0086] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.
[0087] The above description of the embodiments is intended to enable those skilled in the art to understand and apply this application. It will be apparent to those skilled in the art that various modifications can be easily made to these embodiments, and the general principles described herein can be applied to other embodiments without creative effort. Therefore, this application is not limited to the embodiments described herein, and any improvements and modifications made by those skilled in the art based on the disclosure of this application without departing from the scope and spirit of this application are within the scope of this application.
Claims
1. A method for solving instruction packet constraints, characterized in that, include: The first operation parameter of the current instruction packet is constrained and solved using a random object to obtain the value of the first operation parameter; The first operation parameters include identification information of at least one first operation type that should be activated in the current instruction package and the number of instructions for each first operation type; A first queue is constructed based on the value of the first operation parameter. The first queue includes at least one first instruction instance. Each first instruction instance includes identification information of a first operation type and the corresponding number of instructions. A second queue is constructed based on the value of a second operation parameter, the second operation parameter including a second operation type specified by the test scenario, and the second queue includes at least one second instruction instance, each second instruction instance including identification information of a second operation type; In accordance with the order of the second queue first and then the first queue, physical slots are allocated to each instruction instance, and each physical slot can accommodate at most one instruction instance, thus obtaining the slot allocation result; The obtained set of test semantic constraints, the slot allocation result, and the value of the first operation parameter are input into the constraint solver for solving, to obtain the register address, memory instruction address, storage map, first-in-first-out queue management scheme, the value of the predicate field, and the value of the operand field. The operand field is an operation parameter other than the first operation type and the second operation type in the current instruction package.
2. The instruction packet constraint solving method as described in claim 1, characterized in that, The following rules must be met when allocating physical slots: Physical slot allocation is performed on only one instruction instance at a time; the instruction instance is either the first instruction instance or the second instruction instance. For any physical slot, when it is occupied, it is stored in the occupied slot set; For any of the aforementioned instruction instances, when it is allocated, only the physical slots of the non-occupied slot set are opened, and the slot selection variable corresponding to the instruction instance is locked only when the allocation is successful; the value of the slot selection variable is the identification information of the physical slot allocated to the current instruction instance.
3. The method for solving instruction packet constraints as described in claim 1, characterized in that, If any of the second instruction instances fails to be assigned, the constraint solving process is terminated.
4. The method for solving instruction packet constraints as described in claim 1, characterized in that, If the allocation of the first instruction instance fails, the following operations are performed: If there are available physical slots, but none of the available physical slots match the first instruction instance to be allocated, then the first operation parameter corresponding to the first instruction instance to be allocated is set to zero, and the constraint solution process continues. When all physical slots are occupied, the first operation parameter of the first instruction instance to be allocated and all subsequent first instruction instances in the first queue is set to zero, and the constraint solving process continues.
5. The method for solving instruction packet constraints as described in claim 1, characterized in that, After the physical slot allocation of instruction instances in the first and second queues is completed, and the system is in a verification scenario such as extreme stress test, slot utilization stress test, or full release test, the remaining unoccupied physical slots are filled according to preset rules.
6. The method for solving instruction packet constraints as described in claim 1, characterized in that, The set of test semantic constraints includes at least register dependencies, first-in-first-out read / write rules, memory address and storage rules, predicate emission rules, and special instruction field rules.
7. The method for solving instruction packet constraints as described in claim 1, characterized in that, The inputs to the constraint solver also include: historical states injected by the resource manager, and fixed constraints of test cases or configuration files.
8. A method for generating instruction packets, characterized in that, The method includes: The first operation parameter of the current instruction packet is constrained and solved using a random object to obtain the value of the first operation parameter; the first operation parameter includes the identification information of at least one first operation type that should be activated in the current instruction packet and the number of instructions for each first operation type; A first queue is constructed based on the value of the first operation parameter. The first queue includes at least one first instruction instance. Each first instruction instance includes identification information of a first operation type and the corresponding number of instructions. A second queue is constructed based on the value of a second operation parameter, the second operation parameter including a second operation type specified by the test scenario, and the second queue includes at least one second instruction instance, each second instruction instance including identification information of a second operation type; Following the order of the second queue first and then the first queue, physical slots are allocated to each instruction instance, and each physical slot can accommodate at most one instruction instance, thus obtaining the slot allocation result; the slot allocation result and the value of the first operation parameter are structural parameters. The acquired set of test semantic constraints and structural parameters are input into the constraint solver for solving to obtain semantic parameters; the semantic parameters include: register address, memory instruction address, storage block map, first-in-first-out queue management scheme, predicate field value, and operand field value; the operand field consists of operation parameters other than the first and second operation types in the current instruction packet; Instruction packets are generated based on the aforementioned structural and semantic parameters.
9. An electronic device, characterized in that, The system includes a memory and a processor, wherein the memory stores a computer program executable by the processor; and the processor executes the computer program in the memory to implement the instruction packet constraint solving method as described in any one of claims 1 to 7 or the instruction packet generation method as described in claim 8.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the instruction packet constraint solving method as described in any one of claims 1 to 7 or the instruction packet generation method as described in claim 8.