Recovery computer system for reusable launch vehicle

Abstract

The application provides a reusable launch vehicle return computer system, comprising at least one return calculation module, a power module and a general backboard module; wherein the power module is inserted into the power slot of the general backboard module, and the at least one return calculation module is inserted into the general module slot of the general backboard module to realize at least one redundancy. The optional embodiment adopts a high-performance heterogeneous computing platform, a high-bandwidth real-time bus network and a modular reconfigurable software architecture, can significantly improve the solving efficiency and instruction response speed of a complex guidance algorithm, ensures the accurate control and safe recovery of the rocket in the return section, and simultaneously realizes the flexible configuration and rapid technical iteration of the system functions.

Description

Technical Field

[0001] This invention relates to the field of space launch vehicle control technology, and in particular to a return computer system for a reusable launch vehicle. Background Technology

[0002] With the rapid development of commercial spaceflight and reusable launch vehicle technology, the precise guidance, navigation, and control of the first-stage reentry phase of a rocket have become crucial for achieving reusability. The reentry phase requires complex algorithms such as convex optimization, placing extremely high demands on the computing power, communication bandwidth, and real-time performance of industrial control computers and systems. Traditional rocket flight control computers lack sufficient computing power, and the limited bandwidth of buses such as CAN and 1553B makes it difficult to meet the requirements of high-speed data exchange and rapid response. Furthermore, existing systems are mostly designed with fixed modules, closed hardware interfaces and software architectures, resulting in poor configuration flexibility and hindering technological iteration and mission expansion. Therefore, there is an urgent need to develop a highly reliable, high-real-time, and easily expandable reentry computer system to meet the control requirements of reusable launch vehicles. Summary of the Invention

[0003] In view of this, the present invention provides a return computer system for a reusable launch vehicle, which at least solves the problems of limited computing performance of flight control computers and limited communication bandwidth of traditional bus architecture used in existing conventional rocket control systems.

[0004] To address the aforementioned technical problems, embodiments of the present invention provide a reusable launch vehicle return computer system, comprising at least one return computing module, a power module, and a universal backplane module; The power module is inserted into the power slot of the general backplane module, and the at least one return calculation module is inserted into the general module slot of the general backplane module to achieve at least one redundancy. The return calculation module includes an external communication group, an internal communication group, an FPGA communication controller, and a processor unit; The FPGA communication controller controls the external communication group to receive data and send the data to the processor unit, wherein the data includes at least onboard bus data or other external device data. The processor unit receives the data and processes it to obtain a calculation result. It then sends the calculation result and control instructions to the FPGA communication controller. The FPGA communication controller controls the external communication group to send the calculation result and control instructions to the onboard bus and / or other external devices. When the return computing module performs internal communication with the computer, for low-speed communication, the processor unit controls the low-speed communication part in the internal communication group through the FPGA communication controller, and communicates with other return computing modules via the general backplane module; for high-speed communication, the processor unit directly controls the high-speed communication part in the internal communication group, and communicates with other return computing modules via the general backplane module.

[0005] Optionally, the external communication group includes at least one of the following interfaces: a powerlink bus interface, a CAN FD bus interface, an RS422 communication interface, and a switch control interface; or, the external communication group includes at least one of the following interfaces: a TSN bus interface, a TTE bus interface, an RS422 communication interface, and a switch control interface.

[0006] Optionally, the internal communication group includes at least one of the following interfaces: MLVDS bus interface, LVDS communication interface, heartbeat synchronization interface, and PCIe switch component; the processor unit directly controls the PCIe switch component in the internal communication group to achieve high-speed communication between the return computing modules; or, the internal communication group includes at least one of the following interfaces: heartbeat synchronization interface, SRIO interface, or Aurora interface.

[0007] Optionally, the FPGA communication controller includes at least one of the following modules: a PCIe bus communication module, a PCIe-Local bus conversion module, a UART module, a CCDL module, a Powerlink module, a heartbeat synchronization control module, and an interrupt control and channel fault logic module; The Powerlink module drives the Powerlink bus interface in the external communication group to receive or send data from the onboard Powerlink bus and convert the protocol to the Local bus. The UART module drives the RS422 communication interface in the external communication group to communicate with the RS422 interfaces of other onboard devices and then convert the protocol to the Local bus. The UART module also drives the MLVDS bus interface circuit in the internal communication group to convert received and transmitted data to the Local bus. The CCDL drives the LVDS communication interface in the internal communication group to convert received and transmitted data to the Local bus. The PCIe-Local bus conversion module converts data on the Local bus to PCIe endpoints and interacts with the processor unit through the PCIe interface protocol. The heartbeat synchronization control module is controlled by the processor unit through the Local-PCIe link. Each return calculation module periodically toggles the heartbeat synchronization signal to complete synchronization confirmation with the other return calculation modules. When an interrupt signal is generated after each interface module has finished receiving or sending data, the interrupt control and channel fault logic module transmits the interrupt signal and fault signal to the processor unit.

[0008] Optionally, the processor unit includes at least a high-performance CPU, DDR memory, eMMC memory, and Flash memory.

[0009] Optionally, the processor unit adopts the S32G processor chip, which has 8 Cortex-A53 cores, a single-core instruction processing capability of 4000 DMIPS, and a maximum frequency of 1.4 GHz.

[0010] Optionally, the power module includes an input connector, at least two voltage regulation conversion units, and a backplane connector, wherein the input connector connects to at least two of the voltage regulation conversion units, and the voltage regulation conversion units are connected to the general-purpose backplane module through the backplane connector to provide at least two independent redundant power supplies to the general-purpose backplane module; the voltage regulation conversion unit includes at least a filter module, a surge protection device, an overvoltage protection device, an overcurrent protection device, a reverse connection protection device, and a DC-DC isolation conversion circuit; After the external power supply is input through the input connector, it passes through at least one of the voltage regulation units' filtering module, surge protection device, overvoltage protection device, overcurrent protection device, reverse connection protection device, and DC / DC isolation conversion circuit to generate secondary power, which is then supplied to the return calculation module through the backplane connector.

[0011] Optionally, the input connector connection includes three of the voltage regulation conversion units, thereby the power module provides three independent redundant power supplies to the general backplane module.

[0012] Optionally, the universal backplane module includes a power supply slot and multiple universal module slots with consistent point definitions; wherein the number of the multiple universal module slots is greater than or equal to 3.

[0013] Optionally, the return computer includes three return computing modules connected to three independent rocket-borne buses.

[0014] This invention provides a reentry computer system for a reusable launch vehicle, including at least one reentry computing module, a power supply module, and a universal backplane module. The power supply module is inserted into a power supply slot on the universal backplane module, and the at least one reentry computing module is inserted into a universal module slot on the universal backplane module to achieve at least one redundancy. The reentry computing module includes an external communication group, an internal communication group, an FPGA communication controller, and a processor unit. The FPGA communication controller controls the external communication group to receive data, including at least onboard bus data or data from other external devices, and sends the data to the processor unit. The processor unit receives the data, processes it to obtain a calculation result, and sends the calculation result and control commands to the FPGA communication controller. The FPGA communication controller then controls the external communication group to send the calculation result and control commands to the onboard bus and / or other external devices.

[0015] When the return computing module implements internal communication within the return computer, for low-speed communication, the processor unit controls the low-speed communication part in the internal communication group through the FPGA communication controller, and communicates with other return computing modules via the general-purpose backplane module; for high-speed communication, the processor unit directly controls the high-speed communication part in the internal communication group, and communicates with other return computing modules via the general-purpose backplane module. This solves the problem of insufficient computing performance of existing traditional launch vehicle flight control computers and limited bandwidth of traditional bus communication, which cannot meet the requirements of high-precision convex optimization guidance algorithms and high-speed data exchange in the return segment.

[0016] Furthermore, existing systems employ fixed functional modules, have closed hardware and software architectures, and lack flexibility, making them difficult to adapt to the technological iterations and mission expansions of reusable rockets. This optional embodiment utilizes a high-performance heterogeneous computing platform, a high-bandwidth real-time bus network, and a modular, reconfigurable software architecture, which can significantly improve the solution efficiency and command response speed of complex guidance algorithms, ensuring precise control and safe recovery of the rocket's reentry stage, while also enabling flexible configuration of system functions and rapid technological iteration.

[0017] It should be understood that the above general description and the following specific embodiments are merely exemplary and illustrative, and do not limit the scope of the invention. Attached Figure Description

[0018] The accompanying drawings, which are part of the specification of this invention, illustrate exemplary embodiments of the invention. The drawings, together with the description in the specification, serve to illustrate the principles of the invention.

[0019] Figure 1 This is a hardware structure diagram of the return computer system for a reusable launch vehicle provided in a specific embodiment of the present invention.

[0020] Figure 2 The diagram shows the hardware structure of the return calculation module provided in a specific embodiment of the present invention.

[0021] Figure 3 A logic block diagram of an FPGA communication controller provided for an example of the present invention.

[0022] Figure 4 A hardware structure diagram of a power module provided as an example of the present invention; Figure 5 A hardware structure diagram of a general backplane module provided for an example of the present invention; Figure 6 This is a hardware block diagram of a processor unit provided as an example of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the spirit of the contents disclosed in the present invention will be clearly explained below with reference to the accompanying drawings and detailed description. After understanding the embodiments of the present invention, any person skilled in the art can make changes and modifications based on the technology taught in the present invention without departing from the spirit and scope of the present invention.

[0024] The illustrative embodiments and descriptions of the present invention are used to explain the invention, but are not intended to limit the invention. Furthermore, elements / components using the same or similar reference numerals in the drawings and embodiments are used to represent the same or similar parts.

[0025] The terms "first," "second," etc., used in this document are not intended to specifically refer to order or sequence, nor are they intended to limit the invention. They are merely used to distinguish elements or operations described using the same technical terms.

[0026] The directional terms used in this article, such as up, down, left, right, front, or back, are for reference only when referring to the accompanying drawings. Therefore, the use of directional terms is for illustrative purposes and not to limit this work.

[0027] The terms “include,” “including,” “have,” “contain,” etc., used in this article are all open-ended terms, meaning that they include but are not limited to.

[0028] The term "and / or" as used herein includes any or all of the things mentioned.

[0029] The term "multiple" in this article includes "two" and "more than two"; the term "multiple groups" in this article includes "two groups" and "more than two groups".

[0030] The terms "approximately," "about," etc., used herein are intended to modify any quantity or error that may vary slightly, but these slight variations or errors do not change the essence of the quantity or error. Generally, the range of slight variations or errors modified by such terms may be 20% in some embodiments, 10% in others, 5% in still others, or other values. Those skilled in the art should understand that the aforementioned values ​​can be adjusted according to actual needs and are not limited thereto.

[0031] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0032] When expressions such as "at least one of A, B, and C" are used, they should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). When expressions such as "at least one of A, B, or C" are used, they should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). A person skilled in the art should also understand that any conjunction and / or phrase that substantially arbitrarily indicates two or more optional items, whether in the specification, claims, or drawings, should be understood to indicate the possibility of including one of these items, either of these items, or both items. For example, the phrase “A or B” should be understood as including the possibility of “A” or “B”, or “A and B”.

[0033] With the rapid development of commercial spaceflight and reusable launch vehicle technology, precise control of the rocket's reentry stage has become a key technological aspect for achieving rocket reusability. The reentry computer, as a crucial component of the rocket control system, undertakes the guidance, navigation, and control tasks of the first-stage reentry phase, and its performance directly affects the rocket's safe return and reusability efficiency. The various convex optimization algorithms required for the guidance, navigation, and control algorithms of the first-stage reentry phase often necessitate high-performance computers for computation. However, the flight control computers used in traditional rocket control systems currently have limited computing power. The rocket reentry phase demands extremely fast response times for control commands, and the limited communication bandwidth of traditional bus architectures (such as CAN and 1553B) makes it difficult to meet the high-speed data exchange requirements of complex guidance algorithms. Furthermore, existing systems often employ fixed functional module designs with closed hardware interfaces and software architectures, making it difficult to flexibly adjust system configurations according to mission requirements, thus limiting technological iteration and application expansion. To address these technical challenges, there is an urgent need to develop a highly reliable, high-real-time, and easily upgradeable and expandable reentry computer system to meet the stringent requirements of reusable launch vehicles for their control systems.

[0034] To address the limitations of traditional launch vehicle flight control computers in terms of computational performance and bandwidth, which cannot meet the demands of high-precision convex optimization guidance algorithms and high-speed data exchange during the reentry phase, and the fact that existing systems employ fixed functional modules with closed hardware and software architectures, resulting in poor flexibility and difficulty in adapting to the technological iterations and mission expansions of reusable rockets, this invention provides a reentry computer system for reusable launch vehicles. Figure 1 This is a hardware structure diagram of the return computer system for a reusable launch vehicle provided as a specific embodiment of the present invention. (See diagram below.) Figure 1 As shown, the system includes at least one return computing module, a power supply module, and a universal backplane module. The power supply module is inserted into a power supply slot on the universal backplane module, and the at least one return computing module is inserted into a universal module slot on the universal backplane module to provide at least one redundancy. In a specific optional embodiment, the return computer includes three return computing modules connected to three independent onboard buses.

[0035] Specifically, in this optional embodiment, the return computer for a reusable launch vehicle serves as the carrier of the first-stage return guidance and control algorithm. The return computer includes three sets of return computing modules, a power supply module, and a universal backplane module. Each set of return computing modules has independent communication and computation functions, capable of independently receiving external computation requests and outputting computation results. The three sets of return computing modules are identical, and inter-module communication and redundancy synchronization mechanisms are achieved through the universal backplane module. The power supply module supplies power to the return computing modules through the universal backplane module.

[0036] In this embodiment, the system can ensure the continuous correctness of control commands in the event of a failure of any module through a triple-redundant processor module, significantly improving reliability. In use, the return computer is installed on the first stage of the launch vehicle and connected to three sets of onboard buses; each return computing module is connected to one set of onboard buses, and the three sets of onboard buses are independent and redundant. During the return phase of the first stage of the launch vehicle, the return computer receives the flight control mission requirements and calculates the necessary parameters through the onboard buses, runs the return guidance algorithm in the processor unit, and undertakes flight control and other tasks.

[0037] Figure 2 This is a hardware structure diagram of the return calculation module provided for a specific embodiment of the present invention. (See diagram below.) Figure 2 As shown, the return calculation module includes an external communication group, an internal communication group, an FPGA communication controller, and a processor unit. The external communication group is used to access the onboard bus system, receive external calculation data, and transmit calculation results back. The internal communication group is used to realize communication, redundancy management, and synchronization between various modules within the return computer. The FPGA communication controller has communication management and protocol conversion functions, and controls the external communication group and some internal communications according to the instructions of the processor unit. Specifically, the FPGA communication controller controls the external communication group to receive data, which includes at least onboard bus data or data from other external devices, and sends the data to the processor unit. The processor unit receives the data, processes it to obtain calculation results, and sends the calculation results and control instructions to the FPGA communication controller. The FPGA communication controller then controls the external communication group to send the calculation results and control instructions to the onboard bus and / or other external devices. When the return calculation module performs internal communication back to the computer, for low-speed communication, the processor unit controls the low-speed communication portion of the internal communication group through the FPGA communication controller, communicating with other return calculation modules via the general-purpose backplane module. For high-speed communication, the processor unit directly controls the high-speed communication portion of the internal communication group, communicating with other return calculation modules via the general-purpose backplane module. During internal communication, differentiated control methods are used for low-speed and high-speed communication. Low-speed communication is uniformly managed by the FPGA communication controller, improving system versatility and reliability; high-speed communication is directly controlled by the processor unit, reducing data relay links, lowering communication latency, and improving data transmission rate and bandwidth utilization. The overall scheme has a clear structure and distinct layers, which helps to improve the integration, reliability and maintainability of the reusable launch vehicle's return computer, and meets the high real-time and high reliability communication and computing requirements during the return control process.

[0038] In one optional embodiment, the external communication group may include at least one of the following interfaces: a powerlink bus interface, a CAN FD bus interface, an RS422 communication interface, and a switch control interface; or, the external communication group may include at least one of the following interfaces: a TSN bus interface, a TTE bus interface, an RS422 communication interface, and a switch control interface. In one optional embodiment, the internal communication group may include at least one of the following interfaces: an MLVDS bus interface, an LVDS communication interface, a heartbeat synchronization interface, and a PCIe switch component; the processor unit directly controls the PCIe switch component in the internal communication group to achieve high-speed communication between the return computing modules; or, the internal communication group may include at least one of the following interfaces: a heartbeat synchronization interface, an SRIO interface, or an Aurora interface.

[0039] Figure 3 A logic block diagram of an FPGA communication controller provided as an example of the present invention. Figure 3 As shown, in one optional embodiment, the FPGA communication controller includes at least one of the following modules: a PCIe bus communication module, a PCIe-Local bus conversion module, a UART module, a CCDL module, a Powerlink module, a heartbeat synchronization control module, and an interrupt control and channel fault logic module.

[0040] The Powerlink module drives the Powerlink bus interface in the external communication group, receiving or sending data from the onboard Powerlink bus and converting the protocol to the Local bus. The PCIe-Local bus conversion module converts data on the Local bus to PCIe endpoints, enabling interaction with the processor unit via PCIe. PCIe-Local bus conversion refers to the conversion between the PCIe protocol and the Local bus protocol. The Local bus protocol is an on-chip bus. For modules on the FPGA to communicate with the CPU (equivalent to the aforementioned processor unit), they first send data to the Local bus, then convert it to the PCIe protocol via the PCIe-Local bus conversion module, and finally send it to the CPU via the PCIe interface. Receiving data follows the same process.

[0041] The aforementioned UART module drives the RS422 communication interface in the external communication group, communicates with the RS422 interfaces of other onboard equipment, and then converts the protocol to the Local bus. This UART module is multiplexed to simultaneously drive the MLVDS bus interface circuit in the internal communication group, converting received and transmitted data to the Local bus. The CCDL module is also multiplexed to drive the LVDS communication interface in the internal communication group, converting received and transmitted data to the Local bus. The heartbeat synchronization control module is controlled by the processor unit via a Local-PCIe link. Each return calculation module periodically toggles the heartbeat synchronization signal to complete synchronization confirmation with the other return calculation modules. When an interrupt signal is generated after each interface module has finished receiving or transmitting, the interrupt control and channel fault logic module transmits the interrupt signal and fault signal to the processor unit.

[0042] The return computing module uses a processor unit as its computing and control core. The processor unit is connected to the FPGA communication controller via a PCIe bus. The FPGA communication controller acts as the communication switching hub, controlling the Powerlink bus interface, CAN FD bus interface, RS422 communication interface, and discrete quantity interface in the external communication group, and the MLVDS bus interface, LVDS communication interface, and heartbeat synchronization interface in the internal communication group. The processor unit can directly control the PCIe switch components in the internal communication group to achieve high-speed communication between modules. The external communication group connects to external connectors to achieve connection with the onboard bus or peripherals, while the internal communication group connects to the backplane via backplane connectors.

[0043] This optional embodiment significantly improves the scenario adaptability, communication reliability, and data transmission performance of the return computing module by differentiating the interface types of the external and internal communication groups: The external communication group provides multiple industrial / aerospace-grade bus interface options, among which the Powerlink bus interface can adapt to the onboard real-time communication scenario, while the TSN and TTE bus interfaces meet the high time determinism requirements of the next generation of aerospace communication. Combined with the universal CAN FD, RS422 communication interfaces and discrete interfaces, it can be compatible with different types of onboard peripherals and bus architectures, greatly improving the module's versatility and environmental adaptability; The internal communication group matches the internal communication requirements of different rates through a hierarchical interface design. The MLVDS and LVDS interfaces can meet the low-speed, high-reliability internal data interaction, while the PCIe switch components, SRIO, or Aurora high-speed serial interfaces support high-bandwidth, low-latency high-speed data transmission between modules. During high-speed communication, the processor unit can directly control the high-speed communication components, reducing relay overhead. Combined with the heartbeat synchronization interface, it ensures the clock and state coordination of multiple return computing modules, further enhancing the real-time performance and reliability of communication within the return computer. The overall solution can flexibly adapt to the return control requirements of different types of reusable launch vehicles, providing more flexible communication support for the stable operation of the system.

[0044] Figure 4 This is a hardware structure diagram of a power module provided as an example of the present invention. For example... Figure 4 As shown, the power module includes an input connector, at least two voltage regulation conversion units, and a backplane connector. The input connector connects to at least two voltage regulation conversion units, and the voltage regulation conversion units connect to a general-purpose backplane module via the backplane connector to provide at least two independent redundant power supplies to the general-purpose backplane module. Each voltage regulation conversion unit may include at least a filter module, surge protection device, overvoltage protection device, overcurrent protection device, reverse connection protection device, and a DC-DC (Direct Current to Direct Current) isolation conversion circuit. After external power is input through the input connector, it passes through at least one of the voltage regulation units' filter module, surge protection device, overvoltage protection device, overcurrent protection device, reverse connection protection device, and DC-DC isolation conversion circuit to generate secondary power, which is then supplied to the return calculation module via the backplane connector.

[0045] In one optional embodiment, the aforementioned input connector connection includes three of the aforementioned voltage regulation conversion units, thereby providing three independent redundant power supplies to the general-purpose backplane module. Optionally, after the three redundant power supplies are input to the return computing module, they are combined using a conventional diode to provide power to the return computing module.

[0046] This optional embodiment provides three redundant power supplies to the general-purpose backplane module via a power module, effectively preventing system shutdown due to single-channel power supply failure and significantly improving the reliability and continuity of power supply to the return computing module. The external power supply sequentially passes through filtering, surge suppression, overvoltage protection, overcurrent protection, reverse connection protection, and DC / DC isolation conversion circuits, effectively filtering out electromagnetic interference, resisting external surge impacts, and preventing damage to downstream circuits from abnormal operating conditions such as overvoltage, overcurrent, and reverse connection. DC / DC isolation conversion achieves electrical isolation, reduces loop interference, and improves system safety and anti-interference capabilities. The three redundant power supplies, combined using ideal diodes, power the return computing module, achieving lossless, reverse-current-free automatic switching, ensuring stable power supply and rapid response. The overall solution achieves modular power supply through a general-purpose backplane, with a simple structure, strong versatility, and easy system maintenance and expansion, meeting the requirements for long-term stable and reliable operation of the return computing module.

[0047] Figure 5 This is a hardware structure diagram of a general backplane module provided as an example of the present invention. For example... Figure 5 As shown, the universal backplane module includes a power supply slot and multiple universal module slots; these multiple universal module slots are identical, constraining the slot location definition. When replacing or upgrading the return computing module, as long as the slot location definition is met, it can be installed in the return computer for use, facilitating the replacement and upgrade of the return computing module. The number of these multiple universal module slots can be greater than 3.

[0048] In one optional embodiment, the processor unit includes at least a high-performance CPU, DDR memory, eMMC memory, and Flash memory. Optionally, the CPU in the processor unit can be replaced with other high-performance processor solutions, such as the LX2160 processor solution.

[0049] Figure 6 This is a hardware block diagram of a processor unit provided as an example of the present invention. For example... Figure 6 As shown, the processor unit adopts the S32G processor chip solution. The S32G processor has 8 Cortex-A53 cores, a single-core instruction processing capability of 4000 DMIPS, and a maximum frequency of 1.4 GHz, which is a significant improvement in computing power compared to the SM320C6713 commonly used in flight control computers.

[0050] This optional embodiment, by configuring a high-performance CPU with DDR memory, eMMC memory, and Flash memory, ensures the needs of program execution, temporary data storage, and persistent storage of key parameters during the return control process, laying a solid foundation of hardware support for the stable operation of the return computing module. The provided processor replacement solution can flexibly adapt to different models of high-performance processors according to the return control requirements of different launch vehicles, significantly improving the module's versatility and scalability. The solution using the S32G processor chip, with its multi-core architecture of eight Cortex-A53 cores, supports multi-task parallel processing. Its single-core instruction processing capability of 4000 DMIPS and a maximum frequency of 1.4 GHz can efficiently handle the high computing power requirements of large-scale real-time data processing, complex algorithm calculations, and multi-communication link scheduling during the return control process, effectively improving the real-time performance and reliability of the return computing and ensuring precise control of the return process of reusable launch vehicles.

[0051] In summary, this invention provides a launch vehicle reentry computer system based on a triple-redundant architecture. Compared to existing technologies, this system significantly improves reliability by ensuring the continuous correctness of control commands in the event of a failure of any module through triple-redundant processor modules; it optimizes computational performance and real-time performance by employing the S32G high-performance processor, a real-time system, and the Powerlink bus, meeting the millisecond-level response requirements of the launch vehicle reentry phase (computing power increased to 32000 DMIPS, Powerlink communication bandwidth reaching 100 Mbps); it enhances scalability and maintainability by using a modular, pluggable design that supports flexible functional configuration and rapid maintenance; and the optional embodiments of this invention provide key technical support for reusable launch vehicles, possessing significant engineering application value.

[0052] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A return computer system for a reusable launch vehicle, characterized in that, It includes at least one return calculation module, a power supply module, and a general-purpose backplane module; The power module is inserted into the power slot of the general backplane module, and the at least one return calculation module is inserted into the general module slot of the general backplane module to achieve at least one redundancy. The return calculation module includes an external communication group, an internal communication group, an FPGA communication controller, and a processor unit; The FPGA communication controller controls the external communication group to receive data and send the data to the processor unit, wherein the data includes at least onboard bus data or other external device data; The processor unit receives the data and processes it to obtain a calculation result. It then sends the calculation result and control instructions to the FPGA communication controller. The FPGA communication controller controls the external communication group to send the calculation result and control instructions to the onboard bus and / or other external devices. When the return computing module performs internal communication with the computer, for low-speed communication, the processor unit controls the low-speed communication part in the internal communication group through the FPGA communication controller, and communicates with other return computing modules via the general backplane module; for high-speed communication, the processor unit directly controls the high-speed communication part in the internal communication group, and communicates with other return computing modules via the general backplane module.

2. The return computer system for a reusable launch vehicle according to claim 1, characterized in that, The external communication group includes at least one of the following interfaces: powerlink bus interface, CAN FD bus interface, RS422 communication interface, and switch control interface; or, the external communication group includes at least one of the following interfaces: TSN bus interface, TTE bus interface, RS422 communication interface, and switch control interface.

3. The return computer system for a reusable launch vehicle according to claim 2, characterized in that, The internal communication group includes at least one of the following interfaces: MLVDS bus interface, LVDS communication interface, heartbeat synchronization interface, and PCIe switch component; the processor unit directly controls the PCIe switch component in the internal communication group to achieve high-speed communication between the return computing modules; or, the internal communication group includes at least one of the following interfaces: heartbeat synchronization interface, SRIO interface, or Aurora interface.

4. The return computer system for a reusable launch vehicle according to claim 3, characterized in that, The FPGA communication controller includes at least one of the following modules: PCIe bus communication module, PCIe-Local bus conversion module, UART module, CCDL module, Powerlink module, heartbeat synchronization control module, interrupt control and channel fault logic module; The Powerlink module drives the Powerlink bus interface in the external communication group to receive or send data from the onboard Powerlink bus and convert the protocol to the Local bus. The UART module drives the RS422 communication interface in the external communication group to communicate with the RS422 interfaces of other onboard devices and convert the protocol to the Local bus. The UART module also drives the MLVDS bus interface in the internal communication group to convert received and transmitted data to the Local bus. The CCDL module drives the L... The VDS communication interface converts received and transmitted data to the Local bus; the PCIe-Local bus conversion module converts data on the Local bus to the PCIe endpoint and interacts with the processor unit through the PCIe interface protocol; the heartbeat synchronization control module is controlled by the processor unit through the Local-PCIe link, and each return calculation module periodically toggles the heartbeat synchronization signal to complete synchronization confirmation with the other return calculation modules; when an interrupt signal is generated after each interface module has finished receiving or sending, the interrupt control and channel fault logic module is used to transmit the interrupt signal and fault signal to the processor unit.

5. The return computer system for a reusable launch vehicle according to claim 1, characterized in that, The processor unit includes at least a high-performance CPU, DDR memory, eMMC memory, and Flash memory.

6. The return computer system for a reusable launch vehicle according to claim 1, characterized in that, The processor unit adopts the S32G processor chip solution. The S32G processor has 8 Cortex-A53 cores, a single-core instruction processing capability of 4000 DMIPS, and a maximum frequency of 1.4 GHz.

7. The return computer system for a reusable launch vehicle according to claim 1, characterized in that, The power module includes an input connector, at least two voltage regulation conversion units, and a backplane connector. The input connector connects to at least two of the voltage regulation conversion units, and the voltage regulation conversion units connect to the general-purpose backplane module via the backplane connector to provide at least two independent redundant power supplies to the general-purpose backplane module. The voltage regulation conversion unit includes at least a filter module, a surge protection device, an overvoltage protection device, an overcurrent protection device, a reverse connection protection device, and a DC / DC isolation conversion circuit. After the external power supply is input through the input connector, it passes through at least one of the voltage regulation and conversion units, including the filter module, surge protection device, overvoltage protection device, overcurrent protection device, reverse connection protection device, and DC / DC isolation conversion circuit, to generate a secondary power supply, which is then provided to the return calculation module through the backplane connector.

8. The return computer system for a reusable launch vehicle according to claim 7, characterized in that, The input connector connects to three voltage regulation conversion units, thereby providing three independent redundant power supplies to the general-purpose backplane module.

9. The return computer system for a reusable launch vehicle according to claim 1, characterized in that, The universal backplane module includes a power supply slot and multiple universal module slots with consistent point definitions; wherein the number of the multiple universal module slots is greater than or equal to 3.

10. The return computer system for a reusable launch vehicle according to any one of claims 1 to 9, characterized in that, The return computer includes three return computing modules, which are connected to three independent rocket-borne buses.

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