Data processing apparatus for layered decoding of LDPC codes

Abstract

The application discloses a data processing device for LDPC code layered decoding, which comprises a configurable computing unit capable of switching between row update mode and column update mode, a storage system physically divided into multiple independent storage banks, an address generation unit and a control unit. The address generation unit is configured to map access addresses of parallel data requests to different independent storage banks, and the control unit is configured to schedule column update tasks to be performed first and then closely related row update tasks in a decoding layer, wherein the row update tasks directly read the latest variable node messages generated by the column update tasks. The application guarantees the immediate reuse requirement of the layered decoding algorithm for the latest messages by constructing a high-bandwidth parallel data access path, eliminates the memory access bottleneck, and thus can fully exert the performance advantage of the layered decoding algorithm to realize high-throughput decoding processing.

Description

Technical Field

[0001] This application relates to the field of digital communication technology, and in particular to a data processing apparatus for layered decoding of LDPC codes. Background Technology

[0002] Low-density parity-check codes (LDPC codes), as a type of forward error-correcting code, have been widely used in current mainstream communication standards, such as 5G and Wi-Fi, due to their excellent error-correcting performance approaching the Shannon limit. To meet the ever-increasing demands for high throughput and low latency in communication systems, designing efficient LDPC code hardware decoders has become a key technology.

[0003] In the hardware decoding implementation of LDPC codes, various decoding algorithms exist. Among them, the hierarchical decoding algorithm has gained widespread attention and application in the industry due to its faster convergence speed and better error correction performance compared to the traditional flooding decoding algorithm. The core feature of the hierarchical decoding algorithm is that it does not wait for all node information to be updated before starting the next iteration. Instead, during the decoding iteration process, the parity check matrix is ​​divided into multiple layers, and the variable nodes and parity check nodes are updated sequentially according to the layer order. This mechanism allows the latest decoded information to be immediately used in subsequent update processes, thereby accelerating the convergence process.

[0004] However, the aforementioned advantages of hierarchical decoding algorithms also present significant challenges in hardware implementation. Specifically, whether updating variable nodes or check nodes, hierarchical decoding algorithms require parallel reading of messages from multiple other nodes associated with that node from the storage system at each computational step. For example, updating a node with degree d requires simultaneously retrieving d message values ​​from the storage system. As LDPC codes evolve towards longer code lengths and higher node degrees, this demand for parallel data access becomes increasingly significant. In traditional hardware designs, decoders typically use static random access memory (SRAM) with a limited number of individual units or ports to store node messages. When high-performance hierarchical decoding algorithms are combined with this traditional memory architecture, large-scale parallel read requests concentrate on the limited memory ports, leading to severe memory access conflicts and preventing the storage system from supplying data to the computational units in a timely manner.

[0005] Therefore, there is a contradiction between the high performance requirements of hierarchical decoding algorithms and the insufficient data supply capacity of traditional memory architectures in the existing technology. The storage system has become a bottleneck restricting the performance improvement of the entire decoder. Summary of the Invention

[0006] To ensure the timely reuse of the latest messages by the hierarchical decoding algorithm and eliminate memory access bottlenecks, thereby fully leveraging the performance advantages of the hierarchical decoding algorithm, this application provides a data processing device for hierarchical decoding of LDPC codes.

[0007] This application provides a data processing device for layered decoding of LDPC codes, which adopts the following technical solution:

[0008] A data processing apparatus for layered decoding of LDPC codes, comprising:

[0009] A configurable computing unit is configured to switch between a row update mode for updating check node messages and a column update mode for updating variable node messages;

[0010] A storage system, connected to the configurable computing unit, is physically divided into multiple independent storage units, each with an independent access port, and logically divided into:

[0011] The variable node message area is used to store variable node messages; and

[0012] The verification node message area is used to store verification node messages;

[0013] An address generation unit, the address generation unit being configured to:

[0014] When responding to multiple data read requests in parallel, a set of parallel access addresses is generated, wherein within the same access cycle, each of the set of parallel access addresses points to a different independent memory bank; and

[0015] A control unit, the control unit being configured to:

[0016] The parity-check matrix of the LDPC code is grouped to obtain a decoding layer, and the configurable computing unit is controlled to perform a column update task first and then a row update task associated with the column update task within a decoding layer.

[0017] The column update task includes: reading the verification node messages in the verification node message area to generate updated variable node messages, and writing the updated variable node messages into the variable node message area;

[0018] The row update task includes: reading the updated variable node message written to the variable node message area by the column update task, generating an updated check node message, and writing the updated check node message to the check node message area.

[0019] By adopting the above technical solution, the storage system of this data processing device is divided into multiple independent storage blocks. The address generation unit generates a set of parallel access addresses, each pointing to a different independent storage block. This address generation method enables the configurable computing unit to obtain multiple message data required for node update operations through a single concurrent access to the multiple independent storage blocks, thereby achieving high-speed data supply to the computing unit.

[0020] Furthermore, the control unit of this data processing device schedules the hierarchical decoding process and controls the configurable computing unit to complete the column update task, thereby generating and writing back the updated variable node messages. After the column update task is completed, the control unit drives the row update task to read the updated variable node messages generated by the aforementioned column update task. The concurrent access capability of this scheme ensures the row update task's need for immediate reading of large-scale, up-to-date variable node messages, avoiding performance degradation of the computing unit due to data waiting.

[0021] Optionally, the control unit is further configured to:

[0022] When the number of parallel read requests required to perform a node update operation is greater than the number of independent storage units, the multiple data requests are divided into at least two batches, and the storage system is controlled to process the at least two batches of data requests sequentially in multiple consecutive access cycles; wherein, the node update operation is a row update or a column update;

[0023] The configurable computing unit further includes: an accumulation buffer module, used to temporarily store and accumulate part of the data or its intermediate calculation results obtained in the previous access cycle, and to complete the node update operation together with the data obtained in the final access cycle.

[0024] By adopting the above technical solution, and by limiting the control unit to have the ability to process in batches, and by adding an accumulation buffer module inside the configurable computing unit, a multi-cycle access processing mechanism is defined. This mechanism enables the device to correctly complete the processing of high node degrees by trading time for space when the physical parallelism of the hardware is insufficient, thus solving the problem of mismatch between hardware resources and algorithm requirements.

[0025] Optionally, when the configurable computing unit is in the column update mode, the accumulation buffer module is configured to perform an accumulation summation operation on a portion of the data acquired in the multiple consecutive access cycles;

[0026] When the configurable computing unit is in the row update mode, the accumulation buffer module includes at least two minimum value registers and is configured to compare the absolute value of a portion of the data acquired in an access cycle with the values ​​already stored in the at least two minimum value registers to update and store the global minimum and second smallest values.

[0027] By adopting the above technical solution, and by limiting the module to perform algebraic addition in column update mode and to maintain the global minimum / second smallest value (non-algebraic accumulation) through comparison-update in row update mode, the problem of how to effectively accumulate intermediate results under different operation modes in multi-cycle access is solved.

[0028] Optionally, the LDPC code is a quasi-cyclic LDPC code, and its parity check matrix is ​​composed of multiple cyclically shifted permutation submatrices;

[0029] The address generation unit includes:

[0030] Multiple base address registers are used to store the base addresses corresponding to the permutation submatrix;

[0031] Multiple shift value registers are used to store the shift values ​​corresponding to the cyclic shift; and

[0032] An address calculation circuit is configured to perform arithmetic operations on a base address read from the base address register and a shift value read from the shift value register to generate the set of parallel access addresses.

[0033] By adopting the above technical solution, and limiting the internal structure of the address generation unit to consist of a base address register, a shift value register, and an address calculation circuit, a low-complexity, high-efficiency hardware implementation scheme for address generation is clearly defined. This scheme utilizes the algebraic structure of QC-LDPC codes to simplify the complex address mapping problem into simple arithmetic operations, thereby reducing hardware overhead.

[0034] Optionally, the arithmetic operation performed by the address calculation circuit is a modular addition operation;

[0035] The data processing device includes a configuration interface configured to load the base address and the shift value into the plurality of base address registers and the plurality of shift value registers according to the code pattern parameters of the quasi-cyclic LDPC code before the decoding task begins.

[0036] By adopting the above technical solution, AGU is limited to arithmetic operations, and further specified as modular addition, which corresponds to the algebraic construction of QC-LDPC codes. The configuration interface is used to program the base address and shift value registers before decoding, solving the problem of how the device can adapt to different QC-LDPC codes.

[0037] Optionally, the data processing device further includes a decoding termination decision unit, which is configured to perform checksum calculation on the updated variable node message after at least one round of complete column update and row update tasks to generate a decision result;

[0038] The control unit is further configured to terminate the decoding process in advance, based on the decision result, when the decoding converges or before reaching a preset maximum number of iterations.

[0039] By adopting the above technical solution, adding a decoding termination decision unit and limiting its function to perform checksum calculations, while simultaneously granting the control unit the ability to terminate early based on the decision result, a complete dynamic decoding exit mechanism is defined. This mechanism avoids continuing unnecessary iterations after successful decoding, reducing the device's average power consumption and processing latency.

[0040] Optionally, the configurable computing unit includes:

[0041] A minimum sum calculation module is configured to be activated in the row update mode to perform a minimum sum operation on the input message data;

[0042] An adder module is configured to be activated in the column update mode to perform an accumulation operation on the input message data; and

[0043] A data selection network, controlled by the control unit, is configured to route message data read from the storage system to the minimum sum calculation module or the adder module based on the current mode.

[0044] By adopting the above technical solution, the two computing modes can each have their own optimized hardware paths, while resource reuse can be achieved through data selection networks.

[0045] Optionally, each of the plurality of base address registers and the plurality of shift value registers includes:

[0046] A working register set is used to store the base address and shift value used by the current decoding task; and

[0047] A spare register set is used to store the base address and shift value for the next decoding task;

[0048] The configuration interface is configured to load the parameters of the next decoding task into the spare register group while the configurable computing unit is executing the current decoding task.

[0049] By adopting the above technical solution, when switching tasks, only one almost instantaneous pointer switch is needed to enable new parameters, which greatly shortens the downtime caused by switching code types and significantly improves the effective data throughput of the device in multi-task and multi-standard application scenarios. Attached Figure Description

[0050] Figure 1 A schematic diagram of a data processing apparatus for layered decoding of LDPC codes is shown in one embodiment of the present invention. Detailed Implementation

[0051] The present application will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the application and are not intended to limit the scope of the application.

[0052] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the inventive concept. As part of this specification, some of the accompanying drawings of this disclosure are block diagrams illustrating structures and devices to avoid complicating the disclosed principles. For clarity, not all features of the actual embodiment need to be described. Furthermore, the language used in this disclosure has been primarily chosen for readability and instructional purposes and may not have been chosen to define or limit the subject matter of the invention, thus requiring the necessary claims to determine such inventive subject matter. References to “an embodiment” or “an embodiment” in this disclosure mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment, and multiple references to “an embodiment” or “an embodiment” should not be construed as necessarily referring to the same embodiment.

[0053] Unless explicitly defined, the terms “a,” “an,” and “the” are not intended to refer to a singular entity, but rather to include a general category whose specific examples can be used for illustration. Therefore, the use of the terms “a” or “an” can mean any number of at least one, including “a,” “one or more,” “at least one,” and “one or more.” The term “or” means any of the options and any combination of the options, including all options unless explicitly indicated that the options are mutually exclusive. The phrase “at least one of” when combined with a list of items refers to a single item in the list or any combination of items in the list. The phrase does not require all items listed unless explicitly defined as such.

[0054] This application relates to the technical field of channel coding and decoding in digital communication. In modern digital communication systems, forward error correction technology is indispensable to combat channel noise and interference and ensure the reliability of data transmission. Low-density parity-check codes (LDPC codes), as a linear block code with performance approaching the Shannon limit, have been adopted as the core channel coding scheme of mainstream communication standards such as 5G and wireless LANs due to their excellent error correction capabilities. The decoding process of LDPC codes is usually based on their bipartite graph representation, and is accomplished through iterative message passing between variable nodes representing data bits and check nodes representing check equations. This iterative process gradually corrects the confidence of each data bit until decoding converges or reaches a preset upper limit of iterations.

[0055] With the ever-increasing demands for data transmission rates and real-time performance in communication services, LDPC decoders must achieve the highest possible throughput and the lowest possible processing latency within limited hardware resources and power budgets. Compared to traditional flooding decoding scheduling, hierarchical decoding scheduling algorithms can significantly improve decoding efficiency. The core of hierarchical decoding lies in dividing the parity-check matrix into multiple layers and processing them sequentially during decoding iterations. Its advantage is that within a decoding layer, the latest message generated after an update by one node can be immediately utilized by the update process of the next adjacent node, without waiting for the entire iteration round to end. This instantaneous information reuse mechanism within layers gives hierarchical decoding algorithms faster convergence speeds and better error correction performance, making it the preferred technical path for achieving high-throughput LDPC decoders.

[0056] However, the high performance advantage of hierarchical decoding algorithms places high demands on its hardware, and traditional hardware architectures struggle to balance cost and performance. One direct approach is to configure separate, parallel processing hardware for row and column update operations, but this results in a large chip area and high static power consumption, leading to high costs. Another problem is that hierarchical decoding requires parallel reading of messages from multiple connected nodes in the memory system when processing each node. When the decoder uses a traditional monolithic static random access memory or a memory system with a limited number of ports, this large-scale parallel read request leads to a severe memory access bottleneck. Specifically, within the same access cycle, multiple parallel data read addresses have a high probability of hitting the same physical memory or its access port, forming hotspot conflicts. The memory controller must arbitrate such conflicts and queue some requests, which directly causes the computing unit to be unable to obtain all the required data within multiple cycles and is forced to pause its work, i.e., operator idling. Therefore, insufficient memory access bandwidth becomes the decisive factor restricting the actual performance of traditional hierarchical decoders, preventing them from achieving the theoretically high throughput.

[0057] Therefore, this application discloses a data processing apparatus for layered decoding of LDPC codes, referring to... Figure 1 The data processing device for LDPC code layered decoding includes a configurable computing unit, a storage system, an address generation unit, and a control unit. The configurable computing unit, as the core computing module, performs the specific decoding operations; the storage system, as a data warehouse, provides high-bandwidth data access for the decoding process; the address generation unit acts as a bridge for data access, ensuring that the computing unit can efficiently retrieve data from the storage system; and the control unit, as the scheduling center of the entire device, coordinates the orderly operation of other units. These four units work together to form a closed loop with tightly coupled computing power, bandwidth, and scheduling, aiming to maximize effective data throughput with equivalent hardware resources.

[0058] Specifically, the configurable computing unit is a reusable hardware arithmetic logic unit capable of switching between different operating modes to perform different decoding operations, thereby reducing chip costs. In one embodiment, the configurable computing unit includes a min-sum calculation module for performing row update operations and an adder or accumulator module for performing column update operations. When the device performs a row update task, the control unit configures it to row update mode. In this mode, the data path within the computing unit is configured to activate the min-sum calculation module to complete the check node message update based on the min-sum decoding algorithm or its variants. When the device performs a column update task, the control unit configures it to column update mode, and the data path accordingly switches to activate the adder or accumulator module to complete the variable node message update mainly involving summation operations.

[0059] The storage system is configured as the physical carrier of various message data during the decoding process. In one implementation, the storage system physically consists of multiple independently addressable and accessible memory banks. Each independent memory bank has its own access port, enabling concurrent access to different memory banks within the same clock cycle. Logically, the address space of the storage system is divided into two main regions: a variable node message area for storing messages passed from the variable node to the check node during the decoding iteration process; and a check node message area for storing messages passed from the check node to the variable node.

[0060] The address generation unit is responsible for translating upper-layer logical addresses into physical addresses in the storage system. In one implementation, when a configurable computing unit needs to read multiple data items in parallel to perform a node update operation, the address generation unit responds to this parallel read request and generates a set of parallel access addresses. A key feature of this address generation unit is that it ensures that within the same memory access cycle, each address in the generated set of parallel access addresses points to a physically different and independent memory bank. This address-to-memory mapping mechanism structurally avoids multiple read requests competing for access to the same memory bank at the same time.

[0061] The control unit is typically implemented using a finite state machine (FSM). In one implementation, the control unit is responsible for the overall scheduling of the decoding process. It first divides the decoding task into several decoding layers based on the parity-check matrix structure of the LDPC code, such as by row or by row group. Within a decoding layer, the control unit strictly follows a specific order of operations: first, it drives the configurable computing units and storage system to execute column update tasks; after these tasks are completed, it then drives them to execute the row update tasks associated with the aforementioned column update tasks. Furthermore, the control unit is also responsible for coordinating the underlying work cycles of various modules, including memory access timing, batch management of data requests, and mode switching control of the configurable computing units.

[0062] Specifically, in the processing flow of a decoding layer, the data flow is as follows: First, when executing a column update task, the configurable computing unit obtains the initial channel log-likelihood ratio (LLR) from an external or storage system and reads the relevant check node messages from the check node message area of ​​the storage system. In column update mode, the configurable computing unit performs incremental accumulation on the read data to generate updated variable messages and writes these updated variable messages back to the variable node message area through the storage system's access port. After this, the control unit switches the configurable computing unit to row update mode to execute row update tasks. In row update tasks, the configurable computing unit reads the latest updated variable messages written in the aforementioned column update task from the variable node message area and performs minimum or second-smallest value calculations on them to generate updated check node messages. These messages are ultimately written back to the check node message area for use in the next decoding layer or the next iteration.

[0063] To support the aforementioned data flow, the key connections and coordination mechanisms between modules are as follows. The read / write ports of the storage system are configured specifically to serve data requests from the configurable computing unit. Inside the configurable computing unit, a data selection network, controlled by the control unit, precisely routes data read from the storage system to the internal minimum sum computation module or adder module, depending on whether a row update task or a column update task is currently being executed. For node update operations that require multiple access cycles to complete, such as when the node degree exceeds the storage capacity (described later), the configurable computing unit may also include an accumulation buffer module to maintain intermediate computation states. Although column update tasks and row update tasks are executed sequentially within a decoding layer to ensure data dependency, at a higher system scheduling level, the processing of the current layer can be executed in parallel with the data prefetching or related configuration processes of the next decoding layer, forming a coarse-grained pipeline structure. This overlapping execution mechanism further reduces processing latency and improves the overall data throughput of the device.

[0064] This application also provides a preferred embodiment for handling scenarios where the data parallelism required for node update operations exceeds the physical parallelism capability of the storage system under certain conditions. This is because, in the application of LDPC codes, the degree of some nodes, i.e., the number of edges connected to that node, may be greater than the number of independent storage units possessed by the storage system. Under such conditions, without a special processing mechanism, it is impossible to complete the reading of all required data in a single cycle, leading to a performance bottleneck in the computing unit.

[0065] Therefore, in this preferred embodiment, the control unit is further configured to: when the number of parallel read requests required to perform a node update operation is greater than the number of independent storage units, divide the multiple data requests into at least two batches, and control the storage system to process the at least two batches of data requests sequentially in multiple consecutive access cycles. This batching strategy decomposes a single broadband parallel access request into multiple serial batch accesses with lower bandwidth requirements in the time dimension.

[0066] To coordinate with the batch access strategy of the control unit and correctly process the partial data arriving successively over multiple cycles, the configurable computing unit further includes: an accumulation buffer module, used to temporarily store and accumulate partial data or intermediate calculation results acquired in previous access cycles, and to jointly complete the node update operation with the data acquired in the final access cycle. The function of this accumulation buffer module is adaptively adjusted according to the mode in which the configurable computing unit is located. Specifically, when the configurable computing unit is in column update mode, the accumulation buffer module is configured to perform an accumulation sum operation on the partial data acquired in the multiple consecutive access cycles; when the configurable computing unit is in row update mode, the accumulation buffer module includes at least two minimum value registers and is configured to compare the absolute value of the partial data acquired in one access cycle with the values ​​already stored in the at least two minimum value registers to update and store the global minimum and second smallest values. This means that during column updates, this module acts as a multi-cycle adder; during row updates, it acts as a multi-cycle minimum / second smallest value comparator, and internally it also maintains the state of the global sign register and the minimum value position index.

[0067] For example, suppose a node to be updated has a degree *d* of 18, and the storage system has 8 independent memory banks *B*. The control unit detects that *d* > *B*, and therefore automatically divides the 18 data read requests into K = ⌈18 / 8⌉ = 3 batches. In the first access cycle, the address generation unit generates the access addresses for the first 8 data entries, which are then read by the storage system. The configurable computing unit processes these 8 data entries and stores the intermediate results in the accumulation buffer module. In the second access cycle, the next 8 data entries are read and merged with the existing intermediate results in the accumulation buffer module. In the third access cycle, the last 2 data entries are read and the final calculation is performed with the accumulated results from the previous two cycles to generate the final update message for the node. This combination of batching strategy and accumulation buffering mechanism ensures that the configurable computing unit's computing resources are not idle due to waiting for memory access when facing computational tasks with extremely high node degrees. Simultaneously, it smooths peak bandwidth demands over multiple consecutive cycles.

[0068] In a further embodiment, the LDPC code is a quasi-cyclic LDPC code, and its parity check matrix is ​​composed of multiple cyclically shifted permutation submatrices; the address generation unit includes: multiple base address registers for storing base addresses corresponding to the permutation submatrices; multiple shift value registers for storing shift values ​​corresponding to the cyclic shifts; and an address calculation circuit configured to perform arithmetic operations on the base addresses read from the base address registers and the shift values ​​read from the shift value registers to generate the set of parallel access addresses.

[0069] In this embodiment, the arithmetic operation performed by the address calculation circuit is modulo-Z addition, where Z is the order of the permutation submatrix in the QC-LDPC code parity check matrix. By performing a modulo addition operation between the base address of a submatrix and a shift value determined by the code structure, the accurate location of each data in the parallel access group within the logical address space of the storage system can be quickly calculated. However, simply generating logical addresses cannot completely avoid access conflicts. Therefore, the address generation unit may further include a bank mapping logic unit. The responsibility of this bank mapping logic unit is to calculate a corresponding physical memory bank number, i.e., a bank number, for each logical address based on the generated logical address or its input parameters, such as row index, column index, and shift value, using a preset permutation function or lookup table. The design goal of this bank mapping logic is to ensure that the mapped bank numbers of a group of parallel access addresses generated within the same access cycle are mutually exclusive, thereby avoiding access at the hardware level.

[0070] To enable this device to flexibly support different standards or different code pattern parameters under the same standard, in a more specific embodiment, the data processing device includes a configuration interface. This configuration interface is configured to load the base address and the shift value into the plurality of base address registers and the plurality of shift value registers according to the code pattern parameters of the quasi-cyclic LDPC code before the decoding task begins. Through this configuration interface, the upper-level controller or processor can pre-write the structure parameters of the LDPC code corresponding to a new decoding task into the internal registers of the address generation unit before starting the new decoding task, allowing the device to dynamically adapt to different decoding requirements.

[0071] This application also discloses a preferred embodiment. To implement the aforementioned dual-mode switching function, the configurable computing unit includes: a minimum sum calculation module configured to be activated in the row update mode to perform a minimum sum operation on the input message data; an adder module configured to be activated in the column update mode to perform an accumulation operation on the input message data; and a data selection network controlled by the control unit, configured to route message data read from the storage system to the minimum sum calculation module or the adder module according to the current mode.

[0072] The minimum sum calculation module is responsible for performing row update tasks. Its input interface receives one or more batches of variable node messages from the same check node. Internally, it first performs absolute value calculation on the input message data and obtains the global minimum value min1, the second smallest value min2, and the position index of the minimum value min1 through a comparator network. These intermediate results can be stored in dedicated explicit registers. Simultaneously, a sign accumulation logic performs an XOR operation on the sign bits of all input messages to obtain a global sign. When generating the output check node message, for each edge connected to the check node, if the edge corresponds to the position of the minimum value min1, the magnitude of its output message is min2; otherwise, the magnitude is min1. The sign of its output message is the XOR result of the global sign and the sign of the input message corresponding to that edge. Furthermore, to support improved algorithms such as normalized minimum sums, this module may also include a multiplier to multiply the calculated magnitude by a configurable scaling factor α. In the fixed-point implementation, the message data can be represented using sign-magnitude or two's complement, and saturation logic is provided to handle numerical overflow during the calculation process.

[0073] The adder module is responsible for performing column update tasks. This module supports incremental accumulation updates based on the current variable node's posterior probability (APP) value. Its input interface receives the new check node message and its corresponding old value. The module's internal calculation logic performs the operation of subtracting the old check node message and adding the new check node message, thereby efficiently generating the updated variable node message or posterior probability, avoiding the power consumption and latency of completely recalculating all inputs each time. This module's design, in conjunction with the aforementioned accumulation buffer module, enables cross-batch accumulation operations.

[0074] To further improve decoding efficiency and reduce average power consumption, in a preferred embodiment, the data processing device further includes a decoding termination decision unit. This unit is configured to perform a checksum calculation on the updated variable node message after at least one complete round of column and row update tasks to generate a decision result. The control unit is also configured to terminate the decoding process prematurely, based on the decision result, before decoding convergence or before reaching a preset maximum number of iterations. Specifically, the checksum calculation may include hard-determining the sign bits of the updated variable node message to obtain a decoded bit sequence, and then multiplying it by the checksum matrix. If the result is an all-zero vector, the decision result is decoding convergence. The control unit's interface accepts code pattern configurations such as the maximum number of iterations and outputs a decoding completion signal and status. In one embodiment, the control unit may be configured to trigger the decision unit after each decoding layer processing or after each complete iteration to balance decoding latency and decision overhead.

[0075] In the specific hardware implementation, to balance performance and resource consumption, this device uses fixed-point quantization to represent all message data in the decoding process, including channel LLR, variable node messages, and check node messages. A typical bit width configuration is 6 to 8 bits of amplitude value plus 1 sign bit. The choice of bit width is a key trade-off in decoder design: a higher bit width can provide better quantization accuracy, thereby achieving better bit error rate (FER / BER) performance, but it will also increase the capacity requirements of the storage system and the data path width of the computing unit, leading to an increase in hardware area and power consumption. Those skilled in the art can choose an appropriate bit width configuration according to the performance and cost requirements of the specific application scenario. Saturation logic is used inside the arithmetic unit to handle overflows that may occur in fixed-point number arithmetic.

[0076] To support multi-code pattern and multi-task processing, this device includes a configuration interface for loading parameters such as the base address and shift value of the QC-LDPC code before decoding. To support seamless hot-switching between different decoding tasks, in a preferred embodiment, each of the multiple base address registers and multiple shift value registers includes: a working register group for storing the base address and shift value used by the current decoding task; and a spare register group for storing the base address and shift value of the next decoding task. The configuration interface is configured to load the parameters of the next decoding task into the spare register group while the configurable computing unit is executing the current decoding task. Through this double-buffered register structure, the system can preload the code pattern parameters of the next data block into the spare register group in the background while processing the current data block. When switching tasks, the control unit only needs one clock cycle to complete the pointer switching between the working and spare register groups, thereby achieving zero-downtime task switching and significantly adapting to the needs of communication scenarios requiring frequent changes in code pattern parameters.

[0077] For example, in an embodiment for high-throughput applications, this device is configured to process quasi-cyclic LDPC codes with a submatrix order Z=384. Its storage system is physically divided into B=16 independent memory banks. Decoded message data is quantized using a 7+1 bit fixed-point format, i.e., 7 bits for amplitude and 1 bit for symbol. The scaling factor α can be configured to 0.75 using a normalized minimum sum algorithm. With this configuration, the device can achieve a peak decoding throughput exceeding 1 Gb / s. For typical LDPC codes with node degrees d ranging from 6 to 20, since the number of memory banks B=16, the node updates of most decoding layers satisfy the condition d≤B, thus enabling single-cycle data reading, i.e., K=1. Only for a few decoding layers with extremely high node degrees, the device enables a two-cycle data reading mode, i.e., K=2, thereby maintaining extremely high overall processing efficiency.

[0078] As another example, in Embodiment B, which targets low-power applications, the device is configured to process quasi-cyclic LDPC codes with a submatrix order Z=192, and its storage system is divided into B=8 independent memory banks. The fixed-point quantization width of the message data is 6+1 bits, and the scaling factor α can be configured to 0.8. The peak throughput under this configuration is approximately 500 Mb / s. Compared to Embodiment A, this configuration reduces overall power consumption by approximately 30% due to the use of fewer memory banks, narrower data path widths, and potentially lower operating clock frequencies. For LDPC codes with a node degree d≤8, this configuration ensures that all decoding layers complete data reading within a single cycle, i.e., K=1, achieving excellent energy efficiency in its target application scenario.

[0079] As can be seen from the above embodiments, the processing latency of a decoding layer largely depends on the number of memory access cycles required to complete the update of all nodes in that layer. This number of cycles, K, can be approximately estimated using the formula K = ⌈d / B⌉, where d is the node degree and B is the number of independent memory banks. The bank mapping logic included in the address generation unit of this application aims to proactively reduce the frequency of K > 1 in practical applications through intelligent address allocation.

[0080] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0081] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A data processing apparatus for layered decoding of LDPC codes, characterized in that, include: A configurable computing unit is configured to switch between a row update mode for updating check node messages and a column update mode for updating variable node messages; A storage system is connected to the configurable computing unit. The storage system is physically divided into multiple independent storage units, each storage unit having an independent access port, and logically divided into: a variable node message area for storing variable node messages and a verification node message area for storing verification node messages. An address generation unit is configured to: generate a set of parallel access addresses in response to multiple data read requests in parallel, wherein, within the same access cycle, each of the set of parallel access addresses points to a different independent memory bank; and A control unit is configured to: group the parity check matrix of the LDPC code to obtain a decoding layer, and control the configurable computing unit to first execute a column update task and then execute a row update task associated with the column update task within one of the decoding layers; The column update task includes: reading the verification node messages in the verification node message area to generate updated variable node messages, and writing the updated variable node messages into the variable node message area; The row update task includes: reading the updated variable node message written to the variable node message area by the column update task, generating an updated check node message, and writing the updated check node message to the check node message area.

2. The data processing apparatus for layered decoding of LDPC codes according to claim 1, characterized in that, The control unit is further configured to: When the number of parallel read requests required to perform a node update operation is greater than the number of independent storage units, the multiple data requests are divided into at least two batches, and the storage system is controlled to process the at least two batches of data requests sequentially in multiple consecutive access cycles; wherein, the node update operation is a row update or a column update; The configurable computing unit further includes: an accumulation buffer module, used to temporarily store and accumulate part of the data or its intermediate calculation results obtained in the previous access cycle, and to complete the node update operation together with the data obtained in the final access cycle.

3. The data processing apparatus for layered decoding of LDPC codes according to claim 2, characterized in that, When the configurable computing unit is in the column update mode, the accumulation buffer module is configured to perform an accumulation and sum operation on a portion of the data acquired in the multiple consecutive access cycles. When the configurable computing unit is in the row update mode, the accumulation buffer module includes at least two minimum value registers and is configured to compare the absolute value of a portion of the data acquired in an access cycle with the values ​​already stored in the at least two minimum value registers to update and store the global minimum and second smallest values.

4. The data processing apparatus for layered decoding of LDPC codes according to claim 1, characterized in that, The LDPC code is a quasi-cyclic LDPC code, and its parity check matrix is ​​composed of multiple cyclically shifted permutation submatrices. The address generation unit includes: Multiple base address registers are used to store the base addresses corresponding to the permutation submatrix; Multiple shift value registers are used to store the shift values ​​corresponding to the cyclic shift; and An address calculation circuit is configured to perform arithmetic operations on a base address read from the base address register and a shift value read from the shift value register to generate the set of parallel access addresses.

5. The data processing apparatus for layered decoding of LDPC codes according to claim 4, characterized in that, The arithmetic operation performed by the address calculation circuit is a modular addition operation; The data processing device further includes a configuration interface configured to load the base address and the shift value into the plurality of base address registers and the plurality of shift value registers according to the code pattern parameters of the quasi-cyclic LDPC code before the decoding task begins.

6. The data processing apparatus for layered decoding of LDPC codes according to claim 5, characterized in that, The data processing device further includes a decoding termination decision unit, which is configured to perform checksum calculation on the updated variable node message after at least one round of complete column update and row update tasks to generate a decision result; The control unit is further configured to terminate the decoding process in advance, based on the decision result, when the decoding converges or before reaching a preset maximum number of iterations.

7. The data processing apparatus for layered decoding of LDPC codes according to claim 1, characterized in that, The configurable computing unit includes: A minimum sum calculation module is configured to be activated in the row update mode to perform a minimum sum operation on the input message data; An adder module is configured to be activated in the column update mode to perform an accumulation operation on the input message data; and A data selection network, controlled by the control unit, is configured to route message data read from the storage system to the minimum sum calculation module or the adder module based on the current mode.

8. The data processing apparatus for layered decoding of LDPC codes according to claim 5, characterized in that, Each of the plurality of base address registers and the plurality of shift value registers includes: A working register set is used to store the base address and shift value used by the current decoding task; and A spare register set is used to store the base address and shift value for the next decoding task; The configuration interface is configured to load the parameters of the next decoding task into the spare register group while the configurable computing unit is executing the current decoding task.

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