Latching detection method and device based on branch current and latching protection circuit

Abstract

The application discloses a kind of based on branch current's latch detection method, device and latch protection circuit.The method includes obtaining the branch current from a protection branch;Branch current is converted into time-frequency domain signal;Time-frequency domain signal is structured as gray scale image;Extract the texture feature of gray scale image, whether the corresponding branch occurs latch and micro-latch is judged using pre-trained machine learning model.The method of this embodiment, directly for branch current detection, detection point quantity is exponentially decreased, improve the utilization of PCB board, also reduce the single board power consumption.In addition, the branch current of the application is structured as gray scale image, extracts the current texture feature in image, and is judged by pre-set machine learning model, the accuracy of identifying latch and micro-latch is high, supports the detection of various types of devices, so as to effectively protect the single board circuit in orbit operation, prevent it from being damaged due to latch or micro-latch.

Description

Technical Field

[0001] This invention relates to the field of circuit testing technology, and in particular to a latch-up detection method, apparatus, and latch-up protection circuit based on branch current. Background Technology

[0002] With the development of the low-Earth orbit (LEO) commercial satellite industry, high integration, high performance, and low cost are among the main challenges for commercial satellites. To alleviate cost pressures, most suppliers have begun using COTS (Commercial Off-the-Shelf) devices for satellite platform and payload development. COTS devices often cost only 1 / 10 or even less than aerospace devices, but their radiation resistance is inferior to traditional aerospace devices. In LEO environments, single-event latch-up (SEL) has the greatest impact on circuits, potentially causing device or board burnout, requiring prevention. The industry standard is to protect the device using a "current sensor detection + software-controlled power-down" approach. However, with the increasing functionality, performance, and integration of LEO satellites, the number of current signals to be detected is increasing, reaching hundreds, leading to a significant increase in the number of sensors and consuming substantial PCB area and MCU controller resources. Furthermore, this detection method often requires setting a latch-up current threshold for the current sensor (e.g., 1.5 times the rated current); exceeding this threshold is considered an SEL.

[0003] On the other hand, when a satellite is in orbit, devices in the circuitry may experience localized micro-latch-ups when struck by heavy ions. The current increase may not reach 1.5 times the rated current; for example, in SRAM (Static Random Access Memory) devices, the current increase during micro-latch-ups is only a few mA, less than the 1.5-fold threshold, making effective detection impossible. Prolonged micro-latch-ups can still shorten device lifespan or even damage the device. Current techniques for detecting micro-latch suffer from high false positive rates and long detection times, and are only applicable to specific types of devices (such as SRAM devices), not other types.

[0004] Given that latch-up and micro-latch-up of single-board circuit devices have a profound impact on the normal operation of satellites, there is an urgent need for methods that can detect them efficiently and accurately. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a latch-up detection scheme based on branch current, which can achieve high-performance latch-up and micro-latch-up detection at low cost.

[0006] The present invention solves the above-mentioned technical problems through the following aspects: A first aspect of the present invention provides a latch-up detection method based on branch current, the method comprising: Obtain the branch current from a protection branch; Convert the branch current into a time-frequency domain signal; Construct a grayscale image from the time-frequency domain signal; Extract texture features from grayscale images and use a pre-trained machine learning model to determine whether latch-up or micro-latch-up occurs in the corresponding protection branch.

[0007] A second aspect of the present invention provides a latch-up protection circuit based on branch current, the circuit comprising multiple protection branches, each protection branch having a protection switch and a protected power supply module, the protection circuit further comprising: In each protection branch, a current sampling unit is connected between the protection switch and the power module to obtain the sampling current of this branch. The centralized sampling unit takes the sampling current of multiple branches as input and is used to convert the sampling current of multiple branches into corresponding multi-channel digital signals. A digital processing unit, connected to a centralized sampling unit, is used to perform the aforementioned latch-up detection method on multiple digital signals; In the event of latch-up or microlatch-up, the protection switch controls the protection branch to shut down.

[0008] A third aspect of the present invention provides a latch-up detection device based on branch current, the device comprising: The current acquisition module is used to acquire the branch current from a protection branch. The signal conversion module is used to convert branch current into a time-frequency domain signal; The image construction module is used to construct grayscale images from time-frequency domain signals; The fault detection module is used to extract texture features from grayscale images and use a pre-trained machine learning model to determine whether latch-up or micro-latch-up has occurred in the corresponding protection branch.

[0009] A fourth aspect of the present invention provides a hardware processing apparatus for implementing a latch-up detection method based on branch current, comprising an FPGA, the FPGA being configured to include: The data input interface unit is used to receive input data, which is the branch current from a protection branch. The first processing logic unit is connected to the data input interface unit and is used to perform the step of converting the input data into a time-frequency domain signal to obtain the first intermediate data. The second processing logic unit is connected to the first processing logic unit and is used to perform the step of constructing a grayscale image from the first intermediate data to obtain the second intermediate data. The third processing logic unit, connected to the second processing logic unit, is used to perform the steps of extracting texture features of grayscale images from the second intermediate data, and using a pre-trained machine learning model to determine whether latch-up and micro-latch-up occur in the corresponding branch. The result output interface unit is connected to the third processing logic unit and is used to output the judgment results of latch-up and micro-latch-up of the corresponding protection branch.

[0010] The solution of the present invention has the following beneficial effects: 1) Instead of threshold detection and latch-up for the current of a single device, the current of the branch is detected directly. The number of detection points decreases exponentially, effectively reducing the number of current sensors, improving the utilization rate of PCB layout, and reducing the power consumption of a single board.

[0011] 2) The time-domain signal of the branch current is transformed by time-frequency domain to construct a grayscale image, extract the current texture features in the image, and make a judgment through a preset machine learning model. It has a high recognition accuracy for latch-up and micro-latch-up, especially for micro-latch-up, which only causes a small increase in current, and can achieve an accuracy of over 99%. It can also support the detection of various types of devices.

[0012] 3) When there are multiple branches in the circuit, the current of multiple branches is detected in parallel using FPGA, which is faster than the polling detection method using MCU. This can effectively protect the single-board circuit running on the track and prevent it from being damaged by latch-up or micro-latch-up.

[0013] 4) This detection method does not limit the type of device or circuit structure to be tested. The circuit structure can be combined and deformed according to the protected object, which is highly flexible. Attached Figure Description

[0014] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings: Figure 1 A schematic diagram of a latch detection and protection circuit structure used in conventional technology; Figure 2 A flowchart of a latch detection method provided in an embodiment of this disclosure; Figure 3 A schematic diagram comparing the normal branch current and the branch current when a device experiences micro-latch-up; Figure 4 A schematic diagram of the circuit structure for applying the latch detection method according to the embodiments of this disclosure; Figure 5 This is a schematic diagram of wavelet packet decomposition. Figure 6 This is a schematic diagram illustrating prediction using SVM. Figure 7 A comparative diagram showing grayscale images constructed when the branch current is normal and when a device in the branch experiences latch-up. Figure 8 A schematic diagram of the latch-up protection circuit based on branch current provided in an embodiment of this disclosure; Figure 9 Flowchart for implementing a latch detection method for FPGA; Figure 10 A structural block diagram of a latch-up detection device based on branch current provided in an embodiment of this disclosure; Figure 11 This is a structural block diagram of a hardware processing device for implementing a latch-up detection method based on branch current, as provided in an embodiment of this disclosure. Detailed Implementation

[0015] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this disclosure. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure. Furthermore, for clarity, parts unrelated to the described exemplary embodiments have been omitted from the drawings.

[0016] In this specification, it should be understood that terms such as "comprising" or "having" are intended to indicate the presence of features, figures, steps, behaviors, components, portions, or combinations thereof disclosed herein, and are not intended to exclude the possibility of one or more other features, figures, steps, behaviors, components, portions, or combinations thereof being present or added. It should also be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0017] For single-event latch-up (SEL) events on circuit boards, the traditional detection method is to monitor the current of each critical component and determine whether the current exceeds the SEL threshold to confirm whether an SEL has occurred. When an SEL occurs, the power switch is cut off to protect downstream components. Figure 1 The common structure of this traditional SEL detection and protection circuit is presented.

[0018] like Figure 1As shown, assuming there are n branches, each with m power domains, then n×m power supplies need to be detected. Detecting each power supply requires a corresponding sampling resistor and current sampling chip, which are connected to the MCU via the IIC (Internal Integrated Circuit Bus). For circuits with a large number of components, using a large number of sampling resistors and current sampling chips not only increases the power consumption of the detection circuit but also occupies a significant amount of PCB area. During detection, the MCU needs to traverse every measurement node, which also consumes considerable MCU resources. More importantly, this detection method cannot identify micro-latch states, hindering the implementation of rapid protection.

[0019] Therefore, this disclosure proposes a latch-up detection method based on branch current. For latch-up and micro-latch-up detection of devices, it no longer relies on a single fixed current threshold, but instead detects latch-up through the texture characteristics of the branch current. Based on this, this disclosure also provides a latch-up protection circuit structure constructed based on this detection method, which is illustrated below with reference to the accompanying drawings.

[0020] Figure 2 A flowchart of a latch-up detection method based on branch current provided in an embodiment of this disclosure.

[0021] like Figure 2 As shown, the detection method in this embodiment includes steps S110 to S140.

[0022] S110: Obtain the branch current from a protection branch.

[0023] S120: Converts branch current into a time-frequency domain signal.

[0024] S130: Construct a grayscale image from the time-frequency domain signal.

[0025] S140: Extract texture features from grayscale images and use a pre-trained machine learning model to determine whether latch-up or micro-latch-up occurs in the corresponding protection branch.

[0026] In step S110, the normal branch current and the branch current when a device experiences micro-latch-up are illustrated as follows: Figure 3 As shown.

[0027] The circuit implementing this detection method may contain multiple protection branches. In this case, the above steps are performed in parallel on each protection branch using an FPGA to complete the detection of multiple protection branches. In other embodiments, other forms of digital processing modules such as CPUs, MCUs, and DSPs can be used instead of FPGAs to implement the above detection method. The detection method of this embodiment can identify when a device in a branch experiences either latch-up or micro-latch-up faults, or both faults simultaneously.

[0028] In step S110, the branch current is taken from the line between the protection switch and the protected power supply module in the corresponding protection branch, and converted into a digital signal through sampling. The protection branch implementing this detection method can have Figure 4 The example structure. (e.g.) Figure 4 As shown, this circuit structure has n protection branches, such as branches for PLL modules, baseband processing modules, CPU processing modules, etc. Each branch has m protected power thresholds (m is just an example here). For instance, the nth branch protects the CPU unit, which includes m CPU DC-DC modules. Each branch has a sampling resistor and an operational amplifier unit to sample and amplify the current of that branch. The sampled currents from multiple branches are concentrated into a multi-channel synchronous sampling ADC for sampling, outputting multiple converted digital signals.

[0029] In step S120, the branch current can be converted into a time-frequency domain signal through N-layer wavelet packet decomposition.

[0030] Wavelet packet decomposition is a more refined signal analysis method than classical wavelet decomposition. By adaptively selecting to perform multi-level decomposition on both the low-frequency and high-frequency components of the signal simultaneously, it can construct a richer feature set, making it particularly suitable for processing complex signals containing abundant mid-to-high-frequency information. In this embodiment, wavelet packet decomposition is used to highlight the characteristics of the current signal in both the time and frequency domains. Compared to other transform methods, such as Hilbert transform and synchronous squeezing transform, wavelet packet decomposition achieves better detection results.

[0031] Figure 5 This is a schematic diagram of wavelet packet decomposition.

[0032] like Figure 5 As shown, the subscripts of the letters indicate the number of decomposition levels. The letter A represents the low-frequency part of the wavelet packet decomposition, which is an approximation, and D represents the high-frequency part after wavelet packet decomposition, which is the detail part. After the signal S is decomposed once, the low-frequency part A1 and the high-frequency part D1 are obtained. Then, A1 and D1 are decomposed into their respective low-frequency and high-frequency parts, respectively, to obtain AA2, DA2 and AD2, DD2, and so on, to obtain the third level or even more parameters.

[0033] In step S130, when constructing a grayscale image, the data of the time-frequency domain signal obtained after N-layer wavelet packet decomposition can be normalized, and then an image of size M*2 can be constructed. N The grayscale image, where M is the number of time-domain sampling points of the time-frequency domain signal, i.e., the number of sampling points when performing analog-to-digital conversion on the sampled current of the branch. N-level wavelet packet decomposition divides the signal into 2 sub-bands, each sub-band corresponding to a set of time-domain wavelet packet coefficients. Therefore, 2 N Each wavelet packet coefficient corresponds to a frequency band of the frequency domain signal.

[0034] In this embodiment, preferably, the wavelet packet decomposition layer N is 5 or 6, resulting in 32 or 64 coefficients as the vertical quantity of the grayscale image. The temporal sampling rate M can be 1024 or 2048. After training with actual samples, the detection and recognition rate is good, while also taking into account computational efficiency.

[0035] In step S140, the texture features of the grayscale image can be extracted using a grayscale-gradient co-occurrence matrix.

[0036] The Gray-Gradient Co-occurrence Matrix (GGCM) is a classic statistical method for image texture analysis. It comprehensively describes the roughness, contrast, and regularity of texture by simultaneously considering the gray value of each pixel and its local gradient value (i.e., the intensity of gray-level changes). Its core idea is that texture is determined not only by the absolute brightness (gray level) of pixels but also by the patterns of brightness changes and edges (gradients). This method combines these two factors to form a two-dimensional joint statistical matrix, from which quantitative features are extracted. Table 1 shows the extracted gray-level and gradient features. In practical implementation, several features can be selected based on the branch current load characteristics. The calculation formulas for the features in Table 1 are shown in Table 2.

[0037] Table 1 Gray-level gradient features Table 2 Formulas for Calculating Gray-Level Gradient Features Verification has shown that among the above features, the five features of large gradient dominance, small gradient dominance, gradient entropy, gradient average, and energy have good recognition effects on latch-up and micro-latch-up. Therefore, in this embodiment, the gray-level-gradient co-occurrence matrix is ​​used to extract the texture features of gray-level images, including these five features, balancing efficiency and performance.

[0038] In step S140, the pre-trained machine learning model can be, for example, a decision tree, random forest, support vector machine (SVM), artificial neural network model, or other model capable of binary classification. In this embodiment, SVM is preferred, as it can achieve better prediction results in the scenario of this embodiment.

[0039] The prediction process using SVM in this implementation is as follows: Figure 6 As shown.

[0040] like Figure 6As shown, image feature vectors can be obtained through the feature extraction method of gray-level-gradient co-occurrence matrix. For example, one or more feature parameters can be combined and input in Table 2. The support vector machine model has been pre-trained. If latch-up or micro-latch-up occurs in the branch, the corresponding judgment result will be output.

[0041] For example, Figure 7 The image shows a comparison of grayscale images constructed when the branch current is normal and when a device in the branch has latched up. This visual difference can be detected and identified using a machine learning model. Experimental results show that the method in this embodiment can achieve a latch-up and micro-latch recognition rate of over 99%.

[0042] When the method of this embodiment is applied in a circuit, the machine model output criterion result can be used to trigger the protection switch in the protection branch to perform the corresponding protection action, such as turning off the power supply to protect the downstream devices.

[0043] This implementation method does not employ the traditional approach of threshold detection for individual device currents to determine latch-up. Instead, it directly detects branch currents, resulting in an exponential decrease in the number of detection points, reducing the number of current sensors required, improving PCB layout utilization, and lowering single-board power consumption. The time-domain signal of the acquired branch current is transformed into a grayscale image, and current texture features are extracted. A pre-defined machine learning model is then used for judgment, demonstrating high accuracy in identifying latch-up and micro-latch-up, particularly in scenarios like micro-latch-up where the current increase is minimal. This method also supports the detection of various device types. Parallel detection of multiple branch currents is achieved using an FPGA, which is faster than polling detection using an MCU and provides better latch-up protection for on-orbit circuit boards.

[0044] Based on the same inventive concept, this specification also provides an embodiment of a latch-up protection circuit 200 based on branch current.

[0045] Figure 8 This is a schematic diagram of the latch-up protection circuit based on branch current provided in an embodiment of this disclosure.

[0046] like Figure 8 As shown, the protection circuit has multiple branches, each containing a protection switch 210 and a protected power module 220. The protection circuit 200 also includes: In each protection branch, a current sampling unit 230 is connected between the protection switch and the power module to obtain the sampling current of this branch. The centralized sampling unit 240 takes the sampling current of multiple branches as input and is used to convert the sampling current of multiple branches into corresponding multi-channel digital signals. The digital processing unit 250 is connected to the centralized sampling unit 240 and is configured to perform the aforementioned latch detection method on multiple digital signals; In the event of latch-up or microlatch-up, the protection switch 210 controls the power-off of that branch.

[0047] In some scenarios, it can be adopted Figure 4 The protection circuit structure is implemented by means of an FPGA for the digital processing unit 250, a multi-channel synchronous sampling ADC for the centralized sampling unit 240, and a sampling resistor + operational amplifier module for the current sampling unit 230. Figure 4 In the circuit, the current of multiple branches is sampled and sent to the ADC for centralized sampling through an operational amplifier. That is, the sampled current of multiple branches is uniformly concentrated to the ADC for sampling, and then the FPGA performs the detection method of this embodiment on each branch current in parallel.

[0048] In other implementations, the digital processing unit 250 may also be a CPU, MCU, or DSP, and the current sampling unit 230 may also be implemented using a Hall sensor. Furthermore, although... Figure 3 The illustration only shows a simple and similar single-stage structure for each protection branch. In practice, the modules in the protection branches can also have multi-stage structures or other forms of series-parallel variations. Figure 4 The specific structure of the protection branch shown does not constitute a limitation on the protection circuit structure or detection method of the embodiments of this disclosure.

[0049] The following is combined with Figure 4 The protection circuit structure and specific parameters are described, and the time consumption of implementing the latch detection method provided in this disclosure is analyzed. The implementation process is as follows: Figure 9 As shown.

[0050] like Figure 9 As shown, the detection method mainly includes the following six steps. For ease of explanation of the principle and process, only a single branch is used as an example; in actual operation, the FPGA can detect multiple branches in parallel. The specific parameters in this embodiment are merely illustrative preferred methods and are not necessary conditions for implementing the method of this invention.

[0051] Step 1: Acquisition and storage of raw signals.

[0052] use Figure 4 Taking branch 1 as an example, the sampling resistor on branch 1, combined with the operational amplifier circuit, can continuously sample the current on this branch. Assuming that the selected ADC has a sampling rate of 10 Mbps and an accuracy of 8 bits, theoretically, one sampling point can be obtained every 0.1 µs. A storage buffer with a storage depth of 1 kB is set in the BRAM of the FPGA, and one sampling point is stored in each byte. The number of sampling points is 1024, and the time taken is about 102.4 µs.

[0053] Step 2: Wavelet packet decomposition of the original signal.

[0054] For the 1024 sampled data points, a wavelet packet decomposition structure is constructed in the FPGA. The sampled data is decomposed into 6 layers of wavelet packets, resulting in 64 frequency bands. The original data is transformed into 1024*64 matrix data for image construction.

[0055] The FPGA clock frequency is 300MHz (all subsequent analyses will use 300MHz). A 4-point parallel pipeline decomposition is used. The computational load and time consumption during the decomposition process are analyzed in Table 3.

[0056] Table 3 Calculation and Time Consumption Analysis Therefore, the total clock cycle reference for the 6-layer decomposition is 6 × 2048 / 4 = 3072 clock cycles. Based on a main frequency of 300 MHz, it would require 10.24 µs.

[0057] Step 3: Construction of grayscale image.

[0058] The data is normalized, and the values ​​are mapped to 0~255, transforming the original data into a 1024*64 grayscale image.

[0059] The process mainly involves two stages: multiplication and rounding / truncation. Each pixel requires only one cycle, plus 200 control cycles. When using 64-bit parallel computing, the required cycle time is... (1024×64+1024×64) / 64+200=2248 cycles, which takes 7.49us.

[0060] Step 4: Calculate the gray-level-gradient co-occurrence matrix.

[0061] The steps involved in this process include: grayscale quantization, gradient calculation, gradient quantization, and GGCM statistics. Each stage takes one clock cycle per pixel. Therefore, with grayscale level L=64 and gradient level G=16, the resulting GGCM size is 64×16. Using 16 columns of parallel computation, with approximately 500 control cycles, the required clock cycles are: (64×1024×4) / 16+500=16884, and the total time is approximately 56.28us.

[0062] Step 5: Texture feature extraction.

[0063] Texture features extracted using the GGCM matrix involve the calculation of five texture feature quantities: large gradient dominance, small gradient dominance, gradient entropy, gradient average, and energy. These features can be computed in parallel, with the gradient entropy being the most computationally intensive. Parallel processing of 16 matrix elements takes approximately 1.53 μs. Therefore, the feature extraction time is approximately 1.53 μs.

[0064] Step Six: Fault Diagnosis.

[0065] The five obtained features are processed using a pre-trained SVM (Support Vector Machine) binary model with the RBF kernel function. The computation time is approximately 1151 cycles. With 10 parallel processing paths, the total number of cycles is approximately 1151 / 10 + 10 ≈ 125 cycles, taking about 0.42 µs. If latch-up / micro-latch-up is detected, the corresponding branch is powered down via a switching circuit. If no anomaly is detected, sampling continues into the next cycle.

[0066] Taking all six steps mentioned above as a whole, the time required from current sampling to result judgment and protection is approximately 102.4µs + 10.24µs + 7.49µs + 56.28µs + 1.53µs + 0.42µs = 178.36µs. Clearly, this process has a short detection time and strong real-time performance, especially for micro-latch detection, where the time is significantly better than current known methods, and it is applicable to various electronic components. Furthermore, experimental verification shows that the recognition rate for latches and micro-latches can reach over 99%, significantly better than existing technical solutions.

[0067] Corresponding to the methods of the foregoing embodiments, this disclosure also provides embodiments of a latch-up detection device 300 based on branch current.

[0068] Figure 10 This is a structural block diagram of a latch-up detection device based on branch current provided in an embodiment of this disclosure. The device 300 can be implemented by software, hardware, or a combination of both, and can execute the latch-up detection method described in the above embodiments.

[0069] like Figure 10 As shown, the detection device 300 includes a current acquisition module 310, a signal conversion module 320, an image construction module 330, and a fault detection module 340. The current acquisition module 310 is used to acquire the branch current from a protection branch, wherein the branch current is taken from the protection switch and the protected power supply module in the corresponding protection branch, and is sampled and converted into a digital signal.

[0070] Signal conversion module 320 is used to convert branch current into time-frequency domain signal.

[0071] Image construction module 330 is used to construct a grayscale image from a time-frequency domain signal.

[0072] The fault detection module 340 is used to extract the texture features of grayscale images and use a pre-trained machine learning model to determine whether latch-up and micro-latch-up have occurred in the corresponding protection branch.

[0073] The current acquired by the current acquisition module 310 can be obtained through... Figure 4 The current sampling and centralized sampling methods in the circuit structure are used to obtain the image. The method by which the image construction module 330 constructs a grayscale image from the time-frequency domain signal can be implemented with reference to the method in the aforementioned embodiments. The texture features of the grayscale image can be extracted using the aforementioned gray-level-gradient co-occurrence matrix, which can be referred to the aforementioned embodiments for details, and will not be repeated here. The detection device 300 can be pre-installed in a hardware module with digital processing capabilities, such as an FPGA, CPU, DSP, MCU, etc.

[0074] The detection device provided in this embodiment detects branch current, effectively reducing the number of current sensors and lowering the power consumption of the single board. After performing time-frequency domain transformation on the time-domain signal of the branch current, a grayscale image is constructed. Current texture features in the image are extracted, and a preset machine learning model is used for judgment. It has relatively accurate recognition of latch-up and micro-latch-up, and supports the detection of various types of devices.

[0075] Furthermore, this specification also provides an embodiment of a hardware processing device 400 for implementing a latch-up detection method based on branch current.

[0076] Figure 11 This is a structural block diagram of a hardware processing device 400 that implements a latch-up detection method based on branch current, according to an embodiment of this disclosure. The hardware processing device 400 includes an FPGA, which can execute the latch-up detection method described in the above embodiments.

[0077] like Figure 11 As shown, the FPGA in the hardware processing device 400 is configured to include a data input interface unit 410, a first processing logic unit 420, a second processing logic unit 430, a third processing logic unit 440, and a result output interface unit 450.

[0078] The data input interface unit 410 is used to receive input data, which is the branch current from a protection branch. The branch current is taken from the protection switch and the protected power supply module in the corresponding branch and is sampled and converted into a digital signal.

[0079] The first processing logic unit 420 is connected to the data input interface unit 410 and is used to perform the step of converting the input data into a time-frequency domain signal to obtain the first intermediate data.

[0080] The second processing logic unit 430, connected to the first processing logic unit 420, is used to perform the step of constructing a grayscale image from the first intermediate data to obtain the second intermediate data.

[0081] The third processing logic unit 440, connected to the second processing logic unit 430, is used to perform the steps of extracting texture features of grayscale images from the second intermediate data, and using a pre-trained machine learning model to determine whether latch-up and micro-latch-up occur in the corresponding branch.

[0082] The result output interface unit 450 is connected to the third processing logic unit 440 and is used to output the judgment result of whether latch-up and micro-latch-up have occurred in the corresponding branch.

[0083] The core of the hardware processing device in this embodiment can be a Xilinx Kintex-7 series FPGA. This device has ample logic resources and a high-performance architecture, supporting a 300MHz system master clock to meet the requirements for real-time, high-throughput parallel processing of multiple branch currents. The device front end is connected to a multi-channel synchronous sampling ADC; this example illustrates a single channel.

[0084] Driven by a 300MHz master clock, a highly parallel and pipelined processing line is implemented inside the FPGA, which significantly reduces detection latency.

[0085] The data input interface unit integrates multiple high-speed JESD204B or parallel LVDS interface cores for connecting to external high-speed, high-precision ADCs. This unit is responsible for receiving multi-branch current digital signals obtained from synchronous sampling, performing cross-clock domain processing, synchronizing the data to the 300MHz core clock domain, and storing it in a high-speed FIFO. The first processing logic unit (time-frequency domain conversion unit) adopts a parallel window processing architecture for wavelet packet decomposition. The second processing logic unit (grayscale image construction unit) performs numerical normalization on the wavelet packet decomposition data and directly maps the normalized two-dimensional time-frequency matrix to the grayscale image memory layout through hardware logic. This process is entirely controlled by a state machine and can complete the mapping of one row of pixels within one clock cycle. The third processing logic unit (RBF kernel decision unit) uses a hardware-based radial basis function support vector machine for decision-making, replacing the general neural network; feature extraction uses optimized fixed-point arithmetic circuits to calculate multiple texture statistical features of the image in parallel (such as energy and uniformity based on GGCM). The pre-trained SVM support vectors (a set of feature vectors) are stored in the FPGA's Block RAM. For each input feature vector, this unit uses a parallel multiply-accumulator array to simultaneously compute the high-latency complex exponential operations implemented in the FPGA within one clock cycle. The final result is compared with a threshold to directly generate a binary judgment of "normal" or "latch-up / micro-latch-up". The entire inference process is completed within several clock cycles, with latency in the microsecond range. For a detailed time consumption analysis, refer to the aforementioned embodiment.

[0086] In this embodiment, the exponent calculation of the RBF core can also be implemented using a hardware iterator of the CORDIC algorithm to save ROM resources. The 300MHz high-performance FPGA can be replaced by an architecture of multiple mid-to-low-end FPGAs working in parallel, or the functionality can be integrated into a single SoC FPGA containing a hard-core processor and an FPGA architecture. The hardware-accelerated RBF-SVM decision engine's design methodology is also applicable to implementation in application-specific integrated circuits (ASICs) to achieve the optimal power consumption and performance ratio.

[0087] The hardware processing device of this embodiment uses FPGA to implement the latch-up detection method described above. It enables parallel detection of current in multiple branches, which is faster than the polling detection method using MCU and provides better latch-up protection for single-board circuits operating on track.

[0088] Embodiments of this disclosure also provide a computer program product comprising a computer program that, when executed by a processor, causes the processor to implement the steps of the methods described in the foregoing embodiments.

[0089] Embodiments of this disclosure also provide a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the methods described in the foregoing embodiments.

[0090] The various embodiments in this disclosure are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for embodiments other than the method, such as apparatuses, circuit structures, hardware devices, computer program products, and computer-readable media, since they are basically similar to the method embodiments, the descriptions are relatively simple, and relevant details can be found in the description of the method embodiments. These embodiments also have similar beneficial technical effects to the corresponding method. Since the beneficial technical effects of the method have already been described in detail above, they will not be repeated here.

[0091] The foregoing has described specific embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0092] In the 1990s, improvements to a technology could be clearly distinguished as either hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the methodology). However, with technological advancements, many methodological improvements today can be considered direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved methodology into the hardware circuit. Therefore, it cannot be said that a methodological improvement cannot be implemented using hardware physical modules. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program and "integrate" a digital system onto a PLD themselves, without needing chip manufacturers to design and manufacture dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must also be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, the most commonly used are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0093] The controller can be implemented in any suitable manner. For example, it can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code form, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included therein for implementing various functions can also be considered as structures within the hardware component. Alternatively, the means for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0094] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0095] For ease of description, the above apparatus is described by dividing it into various functional unit modules. Of course, when implementing one or more embodiments of this specification, the functions of each unit module can be implemented in one or more software and / or hardware.

[0096] Those skilled in the art will understand that the embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, the embodiments of this specification can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the embodiments of this specification can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0097] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this specification. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data-optimized device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data-optimized device, produce a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0098] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data optimization device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0099] These computer program instructions can also be loaded onto a computer or other programmable data optimization device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable device for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0100] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0101] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0102] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0103] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0104] This specification can be described in the general context of computer-executable instructions that are executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This specification can also be practiced in distributed computing environments, where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside on local and remote computer storage media, including storage devices.

[0105] The above description is merely an embodiment of this disclosure and is not intended to limit the scope of this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of the claims of this disclosure.

Claims

1. A latch-up detection method based on branch current, characterized in that, The method includes: Obtain the branch current from a protection branch; Convert the branch current into a time-frequency domain signal; The time-frequency domain signal is constructed into a grayscale image; Extract the texture features of the grayscale image and use a pre-trained machine learning model to determine whether latch-up and micro-latch-up have occurred in the corresponding protection branch.

2. The method according to claim 1, characterized in that, The branch current is taken from the line between the protection switch and the protected power module in the corresponding protection branch, and is converted into a digital signal through sampling.

3. The method according to claim 1, characterized in that, Converting the branch current into a time-frequency domain signal includes: The branch current is converted into a time-frequency domain signal by N-layer wavelet packet decomposition.

4. The method according to claim 3, characterized in that, Constructing the time-frequency domain signal into a grayscale image includes: The time-frequency domain signal data is normalized and constructed into a form of size M*2. N The grayscale image, where M is the number of time-domain sampling points of the time-frequency domain signal.

5. The method according to claim 1, characterized in that, The pre-trained machine learning model is a support vector machine.

6. The method according to claim 1, characterized in that, Extracting the texture features of the grayscale image includes: Texture features of the grayscale image are extracted using a grayscale-gradient co-occurrence matrix.

7. The method according to claim 6, characterized in that, The feature quantities used to extract the texture features of the grayscale image using the grayscale-gradient co-occurrence matrix include at least: large gradient dominance, small gradient dominance, gradient entropy, gradient average, and energy.

8. A latch-up protection circuit based on branch current, the circuit comprising multiple protection branches, each protection branch containing a protection switch and a protected power supply module, characterized in that, The protection circuit also includes: In each protection branch, a current sampling unit is connected between the protection switch and the power module to obtain the sampling current of this branch. A centralized sampling unit, taking the sampling current of multiple branches as input, is used to convert the sampling current of multiple branches into corresponding multi-channel digital signals; The digital processing unit is connected to the centralized sampling unit and is configured to: sequentially perform time-frequency domain conversion, grayscale image construction, and texture feature extraction on the digital signal of each received protection branch, and generate a judgment signal on whether latch-up and micro-latch-up occur in the corresponding protection branch based on a pre-trained machine learning model. In the event of latch-up or microlatch-up, the protection switch controls the protection branch to shut down.

9. A latch-up detection device based on branch current, characterized in that, The device includes: The current acquisition module is used to acquire the branch current from a protection branch. A signal conversion module is used to convert the branch current into a time-frequency domain signal; An image construction module is used to construct a grayscale image from the time-frequency domain signal; The fault detection module is used to extract the texture features of the grayscale image and use a pre-trained machine learning model to determine whether latch-up and micro-latch-up have occurred in the corresponding protection branch.

10. A hardware processing device for implementing a latch-up detection method based on branch current, characterized in that, Includes an FPGA, the FPGA being configured to include: A data input interface unit is used to receive input data, wherein the input data is the branch current from a protection branch; The first processing logic unit is connected to the data input interface unit and is used to perform a step of converting the input data into a time-frequency domain signal to obtain the first intermediate data. The second processing logic unit is connected to the first processing logic unit and is used to perform the step of constructing a grayscale image on the first intermediate data to obtain the second intermediate data. The third processing logic unit, connected to the second processing logic unit, is used to perform the steps of extracting texture features of grayscale images from the second intermediate data, and using a pre-trained machine learning model to determine whether latch-up and micro-latch-up have occurred in the corresponding protection branch. The result output interface unit is connected to the third processing logic unit and is used to output the judgment result of whether latch-up and micro-latch-up have occurred in the corresponding protection branch.

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