Display device, display panel, and method of manufacturing a display device

Abstract

Disclosed are a display device, a display panel, and a method of manufacturing a display device. The display device includes a gate line extending in a first direction, a data line extending in a second direction crossing the gate line and discontinuously extending in a region overlapping the gate line, a thin film transistor having an active layer and disposed in a pixel region defined by the gate line and the data line crossing each other, and a pixel electrode connected to the thin film transistor, wherein the data line discontinuously extending in the region overlapping the gate line is electrically connected to each other through the active layer of the thin film transistor.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to a display device, a display panel, and a method of manufacturing the display device that can reduce the number of masking processes. Background Technology

[0002] Video display devices, which display various information on screens, are a core technology of the information and communication age, and are evolving towards thinner, lighter, more portable, and higher-performance devices. Therefore, display devices that can be manufactured in a lightweight and thin form are attracting attention.

[0003] Specific examples of such display devices include liquid crystal display (LCD) devices, quantum dot (QD) display devices, field emission display (FED) devices, and organic light-emitting diode (OLED) display devices.

[0004] Liquid crystal displays (LCDs) are currently the most widely used flat panel display devices. LCDs have field-generating electrodes such as pixel electrodes and common electrodes. By applying voltage to these electrodes, an electric field is generated in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules and controlling the polarization of incident light, thus enabling image display.

[0005] Recently, wide viewing angles have been achieved by using FFS (edge ​​field switching) or IPS (in-plane switching) liquid crystal display devices that form multiple domains with different liquid crystal orientations in a single pixel.

[0006] Each pixel of such a liquid crystal display device may have a thin-film transistor and a pixel electrode. Examples of thin-film transistors may include a coplanar thin-film transistor in which a semiconductor is placed at the bottom and a gate insulating film, a gate electrode, and source / drain electrodes are sequentially disposed thereon.

[0007] The description provided in the Background section should not be assumed to be prior art simply because it is mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter art, and the description in this section does not limit this disclosure. Summary of the Invention

[0008] The inventors have recognized that in related technologies, liquid crystal display devices having such coplanar thin-film transistors are manufactured using eight masking processes. Therefore, the production cost increases due to so many masking processes. Therefore, the object of this disclosure is to provide a display device, a display panel, and a method for manufacturing the display device that can reduce the number of masking processes.

[0009] The purpose of this disclosure is not limited to the foregoing, and other purposes not mentioned herein will be clearly understood by those skilled in the art from the following description.

[0010] An exemplary embodiment of this disclosure provides a display device comprising: a gate line extending in a first direction; a data line extending in a second direction intersecting the gate line and discontinuously extending in a region overlapping the gate line; a thin-film transistor having an active layer and disposed in a pixel region defined by the intersection of the gate line and the data line; and a pixel electrode connected to the thin-film transistor, wherein the data lines extending discontinuously in the region overlapping the gate line are electrically connected to each other through the active layer of the thin-film transistor.

[0011] Another exemplary embodiment of this disclosure provides a display panel including: a gate line extending in a first direction, a data line extending in a second direction intersecting the gate line and discontinuously extending in a region overlapping the gate line, a thin-film transistor having an active layer and disposed in a pixel region defined by the intersecting gate line and data line, and a pixel electrode connected to the thin-film transistor, wherein the data lines extending discontinuously in the region overlapping the gate line are electrically connected to each other through the active layer of the thin-film transistor.

[0012] Another exemplary embodiment of this disclosure provides a method for manufacturing a display device, the method comprising: forming an active layer on a substrate, the active layer having a source region, a channel region, and a drain region, and having a semiconductor layer and a conductive layer retained by stacking a semiconductor layer and a conductive layer thereon, wherein the conductive layer corresponding to the channel region is removed; forming a gate insulating film on the substrate on which the active layer is disposed; selectively removing the gate insulating film to form a first contact hole to expose the drain region of the active layer and forming a second contact hole and a third contact hole to expose the source region of the active layer; forming a gate line extending along a first direction on the gate insulating film, a gate electrode protruding from the gate line, and a gate electrode extending in a second direction intersecting the gate line to overlap with the gate line. A data line extending discontinuously in the region is covered by a first protective film formed on the front surface of the substrate to cover the gate line, the data line, and the gate electrode. A planarization layer is formed on the first protective film. A fourth contact hole is formed by selectively removing the first protective film and the planarization layer at the location where the first contact hole is formed. A common electrode and a common line are formed on the planarization layer. A second protective film is formed on the front surface of the substrate where the common electrode and the common line are disposed. A fifth contact hole is formed by selectively removing the second protective film at the location corresponding to the formation of the fourth contact hole. A pixel electrode is formed on the second protective film to be electrically connected to the drain region through the first contact hole, the fourth contact hole, and the fifth contact hole.

[0013] Specific details of other exemplary embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0014] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings:

[0015] Figure 1 This is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure;

[0016] Figure 2 This is a circuit diagram of pixels included in a display device according to an exemplary embodiment of the present disclosure;

[0017] Figure 3 This is a plan view showing the pixels of a liquid crystal display panel according to an exemplary embodiment of the present disclosure;

[0018] Figure 4 It is along Figure 3 A cross-sectional view of the thin-film transistor array substrate taken along line I-I'; and

[0019] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H , Figure 5I , Figure 5J , Figure 5K and Figure 5L This illustrates the manufacturing process of a thin-film transistor array substrate for a liquid crystal display panel according to an exemplary embodiment of the present disclosure. Figure 3 The cross-sectional view taken from line I-I'.

[0020] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. Detailed Implementation

[0021] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. The progression of the described processing steps and / or operations is illustrative; however, the order of steps and / or operations is not limited to that described herein and may be varied as is known in the art, except for steps and / or operations that must occur in a specific order.

[0022] Preferred embodiments of the present disclosure will be described below with reference to the accompanying drawings. Throughout the specification, the same reference numerals denote substantially the same parts.

[0023] In the following description, detailed descriptions of the technology or configuration related to this disclosure will be omitted if it is determined that such detailed descriptions would unnecessarily obscure the essential points of this disclosure. Furthermore, the component names used in the following description have been chosen for ease of writing and may differ from the component names of the actual product.

[0024] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, quantities, etc., disclosed in the accompanying drawings used to illustrate various embodiments of this disclosure are exemplary, and therefore, this disclosure is not limited to the matters shown in the drawings. Throughout this disclosure, the same reference numerals denote the same parts.

[0025] The dimensions of the various components shown in the accompanying drawings, including size and thickness, are shown for ease of description, and this disclosure is not limited to the size and thickness of the components shown. However, it should be noted that the relative dimensions of the components shown in the various accompanying drawings, including relative size, position, and thickness, are part of this disclosure.

[0026] In addition, when describing this disclosure, detailed descriptions are omitted if it is determined that a detailed description of relevant known technologies may unnecessarily obscure the key points of this disclosure.

[0027] When the terms “comprising,” “having,” “including,” “containing,” “constituting,” “made of,” “formed by,” “composed of,” etc., are used as mentioned herein, additional parts may be added unless “only” is used. When a component is referred to in the singular, the inclusion of a plural component is also included unless otherwise expressly stated.

[0028] In interpreting components included in the various embodiments of this disclosure, even without a separate explicit description, it is to be construed as including a range of errors.

[0029] When describing various embodiments of this disclosure, when describing positional relationships, terms such as "on," "above," "above," "below," "below," "beside," "under," "near," "close to," "adjacent to," "on the side," "close to," etc. are used. When describing the positional relationship between two parts, unless "exactly" or "directly" is used, one or more other parts may be located between the two parts.

[0030] Spatially relative terms such as “below,” “under,” “below,” “lower,” “above,” “upper,” etc., may be used in this document to describe the relationship between one element or feature and another element or feature as illustrated in the figures. It should be understood that, in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of elements in use or operation. For example, if an element in the figure is inverted, an element described as “below” or “below” other elements or features would be oriented as “above” other elements or features. Thus, the exemplary term “below” can include both lower and upper orientations. Similarly, the exemplary terms “above” or “above” can include both upper and lower orientations.

[0031] The word “exemplary” is used to indicate that something is an example or illustration. “Aspect” refers to an exemplary aspect. “Implementation,” “example,” “aspect,” etc., should not be construed as superior to or best of other implementations. Unless otherwise stated, implementation, example, exemplary implementation, aspect, etc., may refer to one or more implementations, one or more examples, one or more exemplary implementations, one or more aspects, etc. Furthermore, the word “may” encompasses all the meanings of the word “able to.”

[0032] When an element or layer is placed "on" another element or layer, the other layer or element can be directly inserted on or between the other element.

[0033] In describing various embodiments of this disclosure, when describing temporal relationships, such as "after", "next", "then", "before", etc., discontinuous cases may also be included when explaining temporal causality, unless "immediately" or "directly" is used.

[0034] In describing the various embodiments of this disclosure, terms such as "first" and "second" may be used to describe various components, but these terms are only used to distinguish identical or similar components. Therefore, unless otherwise stated, within the technical spirit of this disclosure, a component described as "first" in this disclosure may be the same as a component described as "second".

[0035] The term "at least one" should be understood to include all possible combinations that can be suggested from one or more related projects. For example, "at least one of the first, second, or third projects" can mean each of the first, second, or third projects, and can also mean all possible combinations that can be suggested from two or more of the first, second, and third projects.

[0036] As used herein, the term "device" can refer to a display device that includes a display panel and a driver for driving the display panel. Examples of display devices may include light-emitting elements, etc. Additionally, examples of devices may include laptops, televisions, computer monitors, automotive devices, wearable devices and automotive equipment, as well as assemblies of electronic devices (or equipment) or assemblies (or devices) that include light-emitting elements, etc., as complete products or end products, such as mobile electronic devices like smartphones or tablets, but embodiments of this disclosure are not limited thereto.

[0037] Features in the various embodiments of this disclosure can be partially or completely linked or combined with each other, various interlocks and drives are technically possible, and various embodiments can be implemented independently of each other or together in an associated relationship.

[0038] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will be further understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0039] In this disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode are used interchangeably. A source electrode can be a drain electrode, and a drain electrode can be a source electrode. Furthermore, a source electrode in any aspect of this disclosure can be a drain electrode in another aspect of this disclosure, and a drain electrode in any aspect of this disclosure can be a source electrode in another aspect of this disclosure.

[0040] In the specification, when adding reference numerals to elements in each figure, care should be taken to ensure that, whenever possible, the same reference numerals used to denote the element in other figures are used for that element. Furthermore, for ease of description, the scale of the constituent elements shown in the figures may differ from the actual scale. That is, the scale of the constituent elements shown in the figures should not be interpreted as the same as the scale shown in the figures.

[0041] In the following description, a display device according to an exemplary embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0042] Figure 1 This is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0043] Figure 2 This is a circuit diagram of pixels included in a display device according to an exemplary embodiment of the present disclosure.

[0044] like Figure 1 As shown, a display device according to an exemplary embodiment of this disclosure may include a liquid crystal display panel 100, a data driving circuit 102, a gating driving circuit 103, and a timing controller 101. A backlight unit may be disposed below the liquid crystal display panel 100 to uniformly radiate light onto the liquid crystal display panel 100. The backlight unit may be configured as a direct-type backlight unit or an edge-type backlight unit.

[0045] The liquid crystal display panel 100 may include a transistor array substrate (or a first substrate) and a color filter array substrate (or a second substrate), such as a thin-film transistor array substrate, facing each other and having a liquid crystal layer therebetween. A pixel array configured to display video signals may be formed on the liquid crystal display panel 100. The pixel array may include a plurality of pixels arranged in a matrix form by intersecting data lines and gate lines. The plurality of pixels may have red pixels, green pixels, and blue pixels. For example, the plurality of pixels may include red pixels, green pixels, and blue pixels, wherein the red pixels, green pixels, and blue pixels may be arranged in a repeating manner. Alternatively, the plurality of pixels may include red pixels, green pixels, blue pixels, and white pixels, wherein the red pixels, green pixels, blue pixels, and white pixels may be arranged in a repeating manner, or the red pixels, green pixels, blue pixels, and white pixels may be arranged in a quadrilateral type. For example, red pixels, blue pixels, and green pixels may be arranged sequentially along the row direction, or red pixels, blue pixels, green pixels, and white pixels may be arranged sequentially along the row direction. However, in embodiments of this disclosure, the color type, arrangement type, and arrangement order of the pixels are not limited, and can be configured in various forms according to light emission characteristics, device lifetime, and device specifications.

[0046] Furthermore, pixels can have different luminous areas depending on their light-emitting characteristics. For example, a pixel that emits light of a different color than the blue pixel can have a different luminous area than the blue pixel. For instance, red, blue, and green pixels, or red, blue, white, and green pixels, can each have different luminous areas.

[0047] Adjacent pixels can share the same data lines. Pixels can be used to display images of video signals by adjusting the amount of transmitted light based on the electric field difference between the data voltage applied to the pixel electrode and the common voltage applied to the common electrode. The common electrode can be formed on the thin-film transistor array substrate together with the pixel electrode in a horizontal field drive mode such as FFS (edge ​​field switching) mode or IPS (in-plane switching) mode.

[0048] The transistor array substrate may include data lines, gate lines, transistors, pixel electrodes connected 1:1 to the transistors, and storage capacitors Cst (not shown) connected 1:1 to the pixel electrodes. For example, the thin-film transistor array substrate may include data lines, gate lines, thin-film transistors, pixel electrodes connected 1:1 to the thin-film transistors, and storage capacitors Cst (not shown) connected 1:1 to the pixel electrodes. A black matrix and color filters may be formed on the color filter array substrate of the liquid crystal display panel 100. In an exemplary embodiment of this disclosure, a common electrode is formed on the thin-film transistor array substrate. A polarizer may be attached to each of the color filter array substrate and the thin-film transistor array substrate of the liquid crystal display panel 100.

[0049] The data driving circuit 102 may include multiple source driver ICs. The output channels of the source driver ICs can be connected 1:1 to the data lines of the pixel array. Each of the source driver ICs can receive digital video data from the timing controller 101. The source driver ICs can be used to convert the digital video data into positive / negative data voltages in response to source timing control signals from the timing controller 101, and supply the data voltages to the data lines of the pixel array through their output channels. The source driver ICs can be used to supply data voltages of opposite polarity to adjacent data lines under the control of the timing controller 101, maintaining the same polarity of the data voltage supplied to each data line within one frame period, and then reversing the polarity of the data voltage in the next frame period. Therefore, the source driver ICs are able to maintain the same polarity of the data voltage within one frame period and reverse the polarity of the data voltage within one frame period, essentially the same as the column inversion method.

[0050] The gating drive circuit 103 can be used to sequentially supply scan pulses (gating pulses) to the gating lines of the pixel array in response to a gating timing control signal from the timing controller 101. The timing controller 101 can be used to supply digital video data input from the external system board 104 to the source driver IC of the data drive circuit 102. The timing controller 101 is capable of generating a source timing control signal for controlling the operating timing of the data drive circuit 102 and a gating timing control signal for controlling the operating timing of the gating drive circuit 103.

[0051] The timing controller 101 can be configured to connect to various processors, such as microprocessors, mobile processors, application processors, etc., depending on the device installed therein.

[0052] The timing controller 101 can be implemented in a component separate from the data drive circuit 102, or integrated with the data drive circuit 102, so that the timing controller 101 and the data drive circuit 102 can be implemented in a single integrated circuit.

[0053] The timing controller 101 may be a timing controller used in typical display technologies, or a control device / apparatus capable of performing additional control functions beyond the typical functions of a timing controller. In one or more embodiments, the timing controller 101 may be one or more other control circuits different from the timing controller, or circuits or components within the control device / apparatus. The timing controller 101 may be implemented using various circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), processors, etc.

[0054] The timing controller 101 can be mounted on a printed circuit board or flexible printed circuit, and can be electrically connected to the data drive circuit 102 and the gating drive circuit 103 via the printed circuit board or flexible printed circuit.

[0055] The timing controller 101 can send signals to and receive signals from the data driving circuit 102 via one or more predetermined interfaces. For example, such interfaces may include a low-voltage differential signaling (LVDS) interface, an embedded point-to-point clock interface (EPI), a serial peripheral interface (SPI), etc. However, this disclosure is not limited thereto.

[0056] refer to Figure 2 In a display device according to an exemplary embodiment of the present disclosure, digital video data can be converted into an analog data voltage based on a gamma reference voltage, and then supplied to a data line DL. Simultaneously, a scan pulse can be supplied to a gate line GL, thereby charging the liquid crystal cell Clc with the data voltage. For this purpose, the gate electrode of a thin-film transistor (TFT) is connected to the gate line GL, the source electrode of the TFT is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and one electrode of a storage capacitor Cst1. A common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc. The storage capacitor Cst1 is used to maintain a constant voltage in the liquid crystal cell Clc by charging it with the data voltage applied from the data line DL when the TFT is turned on. When a scan pulse is applied to the gate line GL, the TFT is turned on, forming a channel between the source and drain electrodes, thus supplying the data voltage of the data line DL to the pixel electrode of the liquid crystal cell Clc. In this way, the orientation of the liquid crystal molecules in the liquid crystal cell Clc changes due to the electric field between the pixel electrode and the common electrode, thereby altering the incident light.

[0057] Figure 3 This is a plan view showing the pixels of a liquid crystal display panel according to an exemplary embodiment of the present disclosure. Figure 4 It is along Figure 3 A cross-sectional view of the thin-film transistor array substrate taken by the I-I' line.

[0058] Reference Figure 3 and Figure 4 According to an exemplary embodiment of the present disclosure, a liquid crystal display panel 100 may have pixels defined by a gate line GL extending along a first direction and a data line DL extending along a second direction intersecting the gate line GL. The data line DL may extend discontinuously in the region overlapping with the gate line GL. Furthermore, a common line CL may be provided to overlap with the gate line GL in a direction parallel to the gate line GL.

[0059] A pixel defined by intersecting gate lines GL and data lines DL may include a thin-film transistor TR and a pixel electrode PXL connected to the thin-film transistor TR. The pixel electrode PXL may have multiple slits to achieve the FFS (edge ​​field switching) mode described later.

[0060] The thin-film transistor TR may include an active layer ACT, a gate electrode GE protruding from the gate line GL and overlapping the active layer ACT, a source region SA electrically connected to the data line DL and formed in the active layer ACT on one side of the gate electrode GE, and a drain region DA electrically connected to the pixel electrode PXL and formed in the active layer ACT on the remaining side of the gate electrode GE.

[0061] Data lines DL that extend discontinuously in the region overlapping with the gate line GL can be electrically connected to each other through the active layer ACT.

[0062] The following describes the cross-sectional structure of a pixel on the thin-film transistor array substrate of a liquid crystal display panel.

[0063] like Figure 4 As shown, the active layer ACT can be disposed on the substrate 200. The active layer ACT may include a semiconductor layer 201 and a conductive layer 202. For example, the active layer ACT may include a semiconductor layer 201 disposed on the substrate 200 and a conductive layer 202 disposed on the semiconductor layer 201. The conductive layer 202 may not be formed below the gate electrode GE. Therefore, the corresponding regions of the active layer ACT on which the conductive layer 202 is disposed can be referred to as the source region SA and the drain region DA.

[0064] The semiconductor layer 201 of the active layer of the thin-film transistor can be formed of a semiconductor material, such as an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor, but is not limited thereto.

[0065] Oxide semiconductor materials offer excellent leakage current prevention and relatively low manufacturing costs. Oxide semiconductors can be made from metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or combinations of metals and their oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti). Specifically, oxide semiconductors can include, but are not limited to, zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO).

[0066] Polycrystalline semiconductor materials exhibit high mobility due to the fast movement speed of charge carriers such as electrons and holes, resulting in low energy consumption and excellent reliability. Polycrystalline semiconductors can be made of polycrystalline silicon (poly-Si), but are not limited to this.

[0067] Amorphous semiconductor materials can be made of amorphous silicon (a-Si), but are not limited to this.

[0068] For example, semiconductor layer 201 may include any one selected from amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon (LTPS), and oxide semiconductors. Conductive layer 202 may include a metal layer or a semiconductor layer doped with impurities. For example, conductive layer 202 may be made of a polycrystalline semiconductor material doped with a predetermined concentration of Group 5 or Group 3 impurity ions (e.g., phosphorus (P) or boron (B)), but is not limited thereto.

[0069] In the region where the data lines DL extend discontinuously with the gate line GL, they can be electrically connected to each other through the conductive layer 202 of the active layer ACT.

[0070] A gate insulating film 204 can be disposed on a substrate 200, on which an active layer ACT comprising a semiconductor layer 201 and a conductive layer 202 is placed. For example, the gate insulating film 204 can be formed as a single layer made of an inorganic material or as multiple layers made of different inorganic materials. For example, the gate insulating film 204 can be used by stacking inorganic layers such as silicon oxide (SiOx) films or silicon nitride (SiNx) films in a single-layer or multi-layer structure. For example, the gate insulating film 204 can be formed as a single layer or multiple layers of any one of silicon oxide (SiOx) films, silicon nitride (SiNx) films, and silicon oxynitride (SiON) films. For example, the gate insulating film 204 can be formed by a single layer or multiple layers of inorganic films. For example, the single layer of inorganic film can be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, while the multiple layers of inorganic films can be formed by alternately stacking at least one of one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiON) film and one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto.

[0071] The gate insulating film 204 may have a first contact hole C1, exposing the drain region DA. The gate insulating film 204 may have a second contact hole C2 and a third contact hole C3, exposing the source region SA. The first contact hole C1 may be a contact hole configured to connect to the pixel electrode PXL. The second contact hole C2 and the third contact hole C3 may be contact holes configured to electrically connect to a data line DL that extends discontinuously in the region overlapping with the gate line GL.

[0072] A gate line GL extending in the first direction and a data line DL extending in the second direction and intersecting the gate line GL can be disposed on the gate insulating film 204. The data line DL can extend discontinuously in the region overlapping with the gate line GL.

[0073] The ends of the data lines DL, which extend discontinuously in the region overlapping with the gate line GL, can be connected to the conductive layer 202 of the active layer ACT through the second contact hole C2 and the third contact hole C3. Therefore, the ends of the data lines DL, which extend discontinuously in the region overlapping with the gate line GL, can be electrically connected to each other through the conductive layer 202 of the active layer ACT.

[0074] The gate electrode GE protruding from the gate line GL can be disposed on the gate insulating film 204 in the portion of the active layer ACT from which the conductive layer 202 is removed.

[0075] The gate line GL, data line DL, and gate electrode GE can be formed of the same metallic material. For example, the gate line GL, data line DL, and gate electrode GE can have a single-layer or multi-layer structure made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof, but this disclosure is not limited thereto.

[0076] A first protective film 205 can be provided to cover the gate line GL, the data line DL, and the gate electrode GE. For example, the first protective film 205 can be formed as a single layer made of inorganic materials or as a multilayer made of different inorganic materials. For example, the first protective film 205 can be used by stacking inorganic layers such as silicon oxide (SiOx) films or silicon nitride (SiNx) films in a single-layer or multi-layer structure. For example, the first protective film 205 can be formed as a single layer or multiple layers of any one of silicon oxide (SiOx) films, silicon nitride (SiNx) films, and silicon oxynitride (SiON) films. For example, the first protective film 205 can be formed by a single layer or multiple layers of inorganic film. For example, the single layer of inorganic film can be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, while the multiple layers of inorganic film can be formed by alternately stacking at least one of one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiON) film and one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto.

[0077] The planarization layer 206 can be disposed on the first protective film 205 to achieve surface planarization. For example, the planarization layer 206 can be an organic insulating film made of acrylic acid, polyimide, benzocyclobutene resin or acrylate resin, but this disclosure is not limited thereto. The first protective film 205 and the planarization layer 206 may include a fourth contact hole C4 at the location where the first contact hole C1 is formed.

[0078] The common electrode CE and the common line CL can be disposed on the planarization layer 206. The common electrode CE can be integrally formed on the front surface of the substrate 200, excluding the first contact hole C1, the fourth contact hole C4, and the fifth contact hole C5. For example, the common electrode CE can be integrally formed on the front surface of the substrate 200, excluding the first contact hole C1, the fourth contact hole C4, and the fifth contact hole C5. Figure 3On the front surface outside region "A" shown. The common electrode CE can be made of a transparent conductive film. The transparent conductive film can be made of a transparent conductive material such as ITO (indium tin oxide) or IZO (indium zinc oxide). A common line CL can be disposed on the common electrode CE. The common electrode CE can be electrically connected to the common line CL. A common voltage can be applied to the common electrode CE through the common line CL. The common line CL can be formed of a metallic material. For example, the common line CL can have a single-layer or multi-layer structure made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof, but this disclosure is not limited thereto.

[0079] The second protective film 210 can be disposed on the front surface of the substrate where the common electrode CE and the common line CL are provided. For example, the second protective film 210 can be formed as a single layer made of inorganic material or as a multilayer made of different inorganic materials. For example, the second protective film 210 can be used by stacking inorganic layers such as silicon oxide (SiOx) film or silicon nitride (SiNx) film in a single layer or multilayer structure. For example, the second protective film 210 can be formed as a single layer or multiple layers of any one of silicon oxide (SiOx) film, silicon nitride (SiNx) film and silicon oxynitride (SiON) film. For example, the second protective film 210 can be formed by a single layer or multiple layers of inorganic films. For instance, the single-layer inorganic film can be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, while the multilayer inorganic film can be formed by alternately stacking at least one of one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiON) film, along with one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto. The second protective film 210 may include a fifth contact hole C5 at the location where the fourth contact hole C4 is formed.

[0080] The pixel electrode PXL can be disposed on the second protective film 210. The pixel electrode PXL can be made of a transparent conductive film, similar to the common electrode CE. The pixel electrode PXL can be electrically connected to the drain region DA of the thin-film transistor Tr through the first contact hole C1, the fourth contact hole C4, and the fifth contact hole C5. In order to form an edge field that depends on the voltage applied to the common electrode CE and the voltage applied to the pixel electrode PXL, the pixel electrode PXL can have multiple slits.

[0081] Although not shown in the accompanying drawings, a liquid crystal display panel is manufactured by joining a color filter array substrate, which includes a black matrix layer formed on the portion other than each pixel region on the opposing substrate, a color filter layer formed in each pixel region, and an outer coating covering the black matrix layer and the color filter layer, to the aforementioned thin film transistor array substrate with a predetermined gap, and filling a liquid crystal layer between the thin film transistor array substrate and the color filter array substrate.

[0082] The following describes a method for manufacturing a liquid crystal display panel with this configuration.

[0083] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H , Figure 5I , Figure 5J , Figure 5K and Figure 5L It shows along Figure 3 A cross-sectional view of the manufacturing process of a thin-film transistor array substrate for a liquid crystal display panel according to an exemplary embodiment of the present disclosure, taken along line I-I'.

[0084] like Figure 5A As shown, a semiconductor layer 201 and a conductive layer 202 are sequentially formed on a substrate 200. For example, the semiconductor layer 201 may include any one selected from amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon (LTPS), and oxide semiconductors. The conductive layer 202 may include a metal layer or a semiconductor layer doped with impurities. For example, the conductive layer 202 may be made of a polycrystalline semiconductor material doped with a predetermined concentration of Group 5 or Group 3 impurity ions (e.g., phosphorus (P) or boron (B)).

[0085] Next, a photoresist is deposited on the conductive layer 202, and a photoresist pattern 203 is formed to define the active layer ACT by using an exposure and development process with a halftone mask. The photoresist pattern 203 is located on the conductive layer 202 in the region corresponding to the active layer ACT. The photoresist pattern 203 is formed such that the region corresponding to the location where the gate electrode GE is to be formed or the channel region of the thin-film transistor is thinner than other regions.

[0086] In order to form the active layer ACT, the semiconductor layer 201 and the conductive layer 202 are etched by an etching process using a photoresist pattern 203 as a mask.

[0087] like Figure 5BAs shown, the photoresist pattern 203 is grayed out. For example, in the photoresist pattern 203, the photoresist pattern 203 corresponding to the region with a relatively low thickness is removed, and the photoresist pattern 203 corresponding to the region with a relatively high thickness is left, wherein the thickness of the region with a relatively low thickness is lower than the thickness of the region with a relatively high thickness.

[0088] like Figure 5C As shown, an ashed photoresist pattern 203a is used as a mask to etch the conductive layer 202 exposed by the ashed photoresist pattern 203a. Therefore, the active layer ACT has a stacked structure of semiconductor layer 201 and conductive layer 202, and the conductive layer 202 may not be formed at the location corresponding to the channel region of the thin-film transistor. After removing the conductive layer 202, the conductive layer 202 remaining on both sides can become the source region SA and the drain region DA. Thus, the first mask is used.

[0089] like Figure 5D As shown, a gate insulating film 204 is formed on a substrate 200 having an active layer ACT comprising a semiconductor layer 201 and a conductive layer 202. For example, the gate insulating film 204 may be formed as a single layer made of an inorganic material or as multiple layers made of different inorganic materials. For example, the gate insulating film 204 can be used by stacking inorganic layers such as silicon oxide (SiOx) films or silicon nitride (SiNx) films in a single-layer or multi-layer structure. For example, the gate insulating film 204 may be formed as a single layer or multiple layers of any one of silicon oxide (SiOx) films, silicon nitride (SiNx) films, and silicon oxynitride (SiON) films. For example, the gate insulating film 204 can be formed by a single layer or multiple layers of inorganic films. For example, the single layer of inorganic film can be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, while the multiple layers of inorganic films can be formed by alternately stacking at least one of one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiON) film and one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto.

[0090] By selectively removing the gate insulating film 204 through exposure and etching processes using a mask, a first contact hole C1 is formed, exposing the drain region DA of the active layer ACT, and a second contact hole C2 and a third contact hole C3 are formed, exposing the source region SA of the active layer ACT. The first contact hole C1 may be a contact hole configured to connect to the pixel electrode PXL. The second contact hole C2 and the third contact hole C3 may be contact holes configured to electrically connect to data lines DL that extend discontinuously in the region overlapping with the gate line GL. Thus, a second mask is used.

[0091] like Figure 5EAs shown, a metal layer is deposited on the gate insulating film 204, and the metal layer is selectively removed using a mask through an exposure and etching process, thereby forming a gate line GL extending in a first direction, a gate electrode GE protruding from the gate line GL, and a data line DL extending in a second direction intersecting the gate line GL. The data line DL is formed to extend discontinuously in the region overlapping with the gate line GL.

[0092] Data lines DL that extend discontinuously in the region overlapping with the gate line GL can be electrically connected to each other through the conductive layer 202 of the active layer ACT. For example, the ends of data lines DL that extend discontinuously in the region overlapping with the gate line GL are electrically connected to the conductive layer 202 of the active layer ACT through the second contact hole C2 and the third contact hole C3. Therefore, the ends of data lines DL that extend discontinuously in the region overlapping with the gate line GL can be electrically connected to each other through the conductive layer 202 of the active layer ACT.

[0093] Additionally, the gate electrode GE protruding from the gate line GL forms a gate insulating film 204 in the portion of the active layer ACT from which the conductive layer 202 is removed.

[0094] The gate line GL, data line DL, and gate electrode GE can be formed of the same metallic material. For example, the gate line GL, data line DL, and gate electrode GE can have a single-layer or multi-layer structure made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof, but this disclosure is not limited thereto. Thus, a third mask is used.

[0095] like Figure 5F As shown, a first protective film 205 is formed on the front surface of the substrate to cover the gate line GL, the data line DL, and the gate electrode GE. For example, the first protective film 205 can be formed as a single layer made of an inorganic material or as a multilayer made of different inorganic materials. For example, the first protective film 205 can be used by stacking inorganic layers such as silicon oxide (SiOx) films or silicon nitride (SiNx) films in a single-layer or multi-layer structure. For example, the first protective film 205 can be formed as a single layer or multiple layers of any one of silicon oxide (SiOx) films, silicon nitride (SiNx) films, and silicon oxynitride (SiON) films. For example, the first protective film 205 can be formed by a single layer or multiple layers of inorganic film. For example, the single layer of inorganic film can be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, while the multiple layers of inorganic film can be formed by alternately stacking at least one of one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiON) film and one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto.

[0096] A planarization layer 206 is formed on the first protective film 205 to achieve surface planarization. For example, the planarization layer 206 may be an organic insulating film made of acrylic acid, polyimide, benzocyclobutene resin or acrylate resin, but this disclosure is not limited thereto.

[0097] like Figure 5G As shown, a fourth contact hole C4 is formed by selectively removing the first protective film 205 and the planarization layer 206 at the location where the first contact hole C1 is formed using a mask through exposure and etching processes. Thus, a fourth mask is used.

[0098] like Figure 5H As shown, a transparent conductive film 207 and a metal layer 208 are sequentially formed on the planarization layer 206. For example, the transparent conductive film 207 can be made of a transparent conductive material such as ITO (indium tin oxide) or IZO (indium zinc oxide). The metal layer 208 can have a single-layer or multi-layer structure made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof, but this disclosure is not limited thereto.

[0099] Photoresist is deposited on metal layer 208, and a photoresist pattern 209 is formed to define the common electrode and common line using an exposure and development process with a halftone mask. The photoresist pattern 209 is formed such that the area corresponding to the location where the common line CL is to be formed is thicker than other areas.

[0100] like Figure 5I As shown, an etching process using a photoresist pattern 209 as a mask is employed to etch the transparent conductive film 207 and the metal layer 208. The photoresist pattern 209 is then greyed. For example, in the photoresist pattern 209, the photoresist pattern 209 corresponding to regions with relatively low thickness is removed, leaving the photoresist pattern 209 corresponding to regions with relatively high thickness, wherein the thickness of the regions with relatively low thickness is less than the thickness of the regions with relatively high thickness.

[0101] like Figure 5J As shown, an ashed photoresist pattern 209a is used as a mask to etch the metal layer 208 exposed by the ashed photoresist pattern 209a. Therefore, the common electrode CE and the common line CL can be disposed on the planarization layer 206. The common electrode CE can be integrally formed on the front surface of the substrate 200, excluding the first contact hole C1 and the fourth contact hole C4. For example, the common electrode CE can be integrally formed on the substrate 200 excluding the drain region DA. Figure 3On the front surface outside region "A" shown. The common electrode CE can be electrically connected to the common line CL. Thus, a fifth mask is used.

[0102] like Figure 5K As shown, a second protective film 210 is formed on the front surface of a substrate on which a common electrode CE and a common line CL are disposed. For example, the second protective film 210 may be formed as a single layer made of an inorganic material or as a multilayer made of different inorganic materials. For example, the second protective film 210 may be used by stacking inorganic layers such as silicon oxide (SiOx) films or silicon nitride (SiNx) films in a single-layer or multi-layer structure. For example, the second protective film 210 may be formed as a single layer or multiple layers of any one of silicon oxide (SiOx) films, silicon nitride (SiNx) films, and silicon oxynitride (SiON) films. For example, the second protective film 210 can be formed by a single or multiple inorganic film. For instance, the single inorganic film can be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, while the multiple inorganic film can be formed by alternately stacking at least one of one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiON) film, along with one or more layers of amorphous silicon (a-Si), but this disclosure is not limited thereto. Using a mask, the second protective film 210 corresponding to the location where the fourth contact hole C4 is formed is selectively removed through exposure and etching processes to form the fifth contact hole C5. Thus, a sixth mask is used.

[0103] like Figure 5L As shown, a transparent conductive film, such as ITO (indium tin oxide) or IZO (indium zinc oxide), is deposited on the second protective film 210. Then, the pixel electrode PXL is formed by selectively removing the transparent conductive film through an exposure and etching process using a seventh mask. The pixel electrode PXL can be electrically connected to the drain region DA of the thin-film transistor Tr through the first contact hole C1, the fourth contact hole C4, and the fifth contact hole C5. To form an edge field that depends on the voltage applied to the common electrode CE and the voltage applied to the pixel electrode PXL, the pixel electrode PXL can have multiple slits. Thus, the seventh mask is used.

[0104] Although not shown in the accompanying drawings, a liquid crystal display panel is manufactured by joining a color filter array substrate, which includes a black matrix layer formed on the portion other than each pixel region on the opposing substrate, a color filter layer formed in each pixel region, and an outer coating covering the black matrix layer and the color filter layer, to the thin film transistor array substrate with a predetermined gap, and filling a liquid crystal layer between the thin film transistor array substrate and the color filter array substrate.

[0105] In the display device and manufacturing method of the same according to the exemplary embodiments of the present disclosure as described above, the gate line and data line are formed as a single wiring, and a conductive layer is provided to the active layer and thus connected to the data line, thereby reducing the number of mask processes.

[0106] In addition, production costs can be reduced because the number of mask processes can be decreased.

[0107] Because the number of masking processes can be reduced, the energy consumed in producing display devices can be reduced, and the generation of greenhouse gases due to manufacturing processes can be reduced, thereby achieving ESG (Environmental, Social, and Governance) goals.

[0108] The backlight shielding layer can be formed by applying gate electrode material and flip panel to the semiconductor region of the active layer.

[0109] A display device according to one or more exemplary embodiments of this disclosure can be described as follows:

[0110] According to one or more exemplary embodiments of this disclosure, a display device includes: a gate line extending in a first direction; a data line extending in a second direction intersecting the gate line and extending discontinuously in a region overlapping with the gate line; a thin-film transistor having an active layer and disposed in a pixel region defined by the intersecting gate line and the data line; and a pixel electrode connected to the thin-film transistor, wherein the data lines extending discontinuously in the region overlapping with the gate line are electrically connected to each other through the active layer of the thin-film transistor.

[0111] According to one or more exemplary embodiments of this disclosure, the gate line and the data line are disposed on the same layer using the same material.

[0112] According to one or more exemplary embodiments of the present disclosure, the active layer of the thin-film transistor includes: a semiconductor layer; and a conductive layer disposed on the semiconductor layer, wherein a portion of the conductive layer corresponding to the channel region of the thin-film transistor is removed, and the remaining regions of the conductive layer are the source and drain regions of the thin-film transistor.

[0113] According to one or more exemplary embodiments of this disclosure, the data lines extending discontinuously in the region overlapping with the gate lines are electrically connected to each other through the conductive layer of the active layer.

[0114] According to one or more exemplary embodiments of the present disclosure, the display device further includes: a planarization layer disposed on the thin-film transistor; a common electrode disposed on the planarization layer; and a protective film disposed on the common electrode to protect the common electrode, wherein the planarization layer and the protective film have contact holes to expose the drain region, and wherein the pixel electrode is disposed on the protective film and electrically connected to the drain region through the contact holes.

[0115] According to one or more exemplary embodiments of this disclosure, the pixel electrode has a plurality of slits.

[0116] According to one or more exemplary embodiments of the present disclosure, the display device further includes: a gate insulating film disposed on the active layer, the gate insulating film having a second contact hole and a third contact hole to expose the source region of the active layer of the thin-film transistor.

[0117] According to one or more exemplary embodiments of this disclosure, the data lines extending discontinuously in the region overlapping with the gate line are electrically connected to each other by the active layer of the thin-film transistor through the second contact hole and the third contact hole.

[0118] According to one or more exemplary embodiments of the present disclosure, the active layer of the thin-film transistor includes: a semiconductor layer; and a conductive layer disposed on the semiconductor layer, wherein the data lines extending discontinuously in the region overlapping the gate lines are electrically connected to each other by the conductive layer of the active layer through the second contact hole and the third contact hole.

[0119] According to one or more exemplary embodiments of this disclosure, a display panel includes: a gate line extending in a first direction; a data line extending in a second direction intersecting the gate line and extending discontinuously in a region overlapping with the gate line; a thin-film transistor having an active layer and disposed in a pixel region defined by the intersecting gate line and the data line; and a pixel electrode connected to the thin-film transistor, wherein the data lines extending discontinuously in the region overlapping with the gate line are electrically connected to each other through the active layer of the thin-film transistor.

[0120] According to one or more exemplary embodiments of this disclosure, a method of manufacturing a display device includes the following steps: forming an active layer on a substrate, the active layer including a source region, a channel region, and a drain region, and including a conductive layer and a semiconductor layer laminated on the substrate, wherein the conductive layer corresponding to the channel region is removed; forming a gate insulating film on the substrate on which the active layer is disposed; forming a first contact hole to expose the drain region of the active layer by selectively removing the gate insulating film, and forming a second contact hole and a third contact hole to expose the source region of the active layer; forming a gate line extending in a first direction on the gate insulating film, a gate electrode protruding from the gate line, and a second direction extending in a direction intersecting the gate line to overlap with the gate line. The data lines extend discontinuously in the region; a first protective film is formed on the front surface of the substrate to cover the gate lines, the data lines, and the gate electrode; a planarization layer is formed on the first protective film; a fourth contact hole is formed by selectively removing the first protective film and the planarization layer at the location where the first contact hole is formed; a common electrode and a common line are formed on the planarization layer; a second protective film is formed on the front surface of the substrate on which the common electrode and the common line are disposed; a fifth contact hole is formed by selectively removing the second protective film corresponding to the location where the fourth contact hole is formed; and a pixel electrode is formed on the second protective film to be electrically connected to the drain region through the first contact hole, the fourth contact hole, and the fifth contact hole.

[0121] According to one or more exemplary embodiments of this disclosure, the gate line and the data line are formed on the same layer using the same material.

[0122] According to one or more exemplary embodiments of this disclosure, forming the active layer includes the following steps: sequentially forming the semiconductor layer and the conductive layer on the substrate; forming a photoresist pattern defining the active layer on the conductive layer using an exposure process and a development process with a halftone mask; removing the semiconductor layer and the conductive layer using the photoresist pattern as a mask; and ashing the photoresist pattern and using the ashed photoresist pattern as a mask to remove the portion of the conductive layer corresponding to the channel region.

[0123] According to one or more exemplary embodiments of this disclosure, the data lines extending discontinuously in the region overlapping with the gate line are electrically connected to each other by the conductive layer through the second contact hole and the third contact hole.

[0124] According to one or more exemplary embodiments of the present disclosure, the gate electrode is formed in the channel region of the active layer on the gate insulating film.

[0125] According to one or more exemplary embodiments of this disclosure, the steps of forming the common electrode and the common line include: sequentially forming a transparent conductive film and a metal layer on the planarization layer; forming a photoresist pattern defining the common electrode on the metal layer using an exposure process and a development process with a halftone mask; patterning the common electrode by removing the transparent conductive film and the metal layer using the photoresist pattern as a mask; ashing the photoresist pattern; and forming the common line by removing the metal layer using the ashing photoresist pattern as a mask.

[0126] According to one or more exemplary embodiments of this disclosure, the pixel electrode has a plurality of slits.

[0127] As is evident from the foregoing, the display device, display panel, and method of manufacturing the display device according to the exemplary embodiments of this disclosure have the following effects.

[0128] Since the gate lines and data lines are formed as a single wiring, and the conductive layer is provided to the active layer and thus connected to the data lines, the number of mask processes can be reduced.

[0129] Because the number of mask processes can be reduced, manufacturing costs can be lowered.

[0130] Because the number of masking processes can be reduced, the energy consumed in producing display devices can be reduced, and the generation of greenhouse gases due to manufacturing processes can be reduced, thereby achieving ESG (Environmental, Social, and Governance) goals.

[0131] The backlight shielding layer can be formed by applying gate electrode material and flip panel to the semiconductor region of the active layer.

[0132] The effects of the exemplary embodiments are not limited to those described above, and further effects are included in this disclosure.

[0133] This disclosure is not limited to the exemplary embodiments and drawings described above, and it will be apparent to those skilled in the art that various substitutions, modifications and alterations can be made without departing from the spirit of this disclosure.

[0134] Cross-references to related applications

[0135] This application claims priority and benefit to Korean Patent Application No. 10-2025-0010427, filed on January 23, 2025, the entire contents of which are hereby expressly incorporated herein for all purposes.

Claims

1. A display device, the display device comprising: A gate line extending in a first direction; A data line that extends in a second direction intersecting the gate line and extends discontinuously in the region where it intersects the gate line; A thin-film transistor having an active layer and disposed in a pixel region defined by the intersecting gate lines and data lines; as well as Pixel electrode, the pixel electrode being connected to the thin-film transistor. The data lines, which extend discontinuously in the region overlapping with the gate line, are electrically connected to each other through the active layer of the thin-film transistor.

2. The display device according to claim 1, wherein, The gate lines and the data lines are made of the same material and are disposed on the same layer.

3. The display device according to claim 1, wherein, The active layer of the thin-film transistor includes: Semiconductor layer; and A conductive layer is disposed on the semiconductor layer. In this process, the portion of the conductive layer corresponding to the channel region of the thin-film transistor is removed, and the remaining regions of the conductive layer are the source and drain regions of the thin-film transistor.

4. The display device according to claim 3, wherein, The data lines, which extend discontinuously in the region where they overlap with the gate lines, are electrically connected to each other through the conductive layer of the active layer.

5. The display device according to claim 3, further comprising: A planarization layer is disposed on the thin-film transistor; A common electrode is disposed on the planarization layer; as well as A protective film is disposed on the common electrode to protect the common electrode. The planarization layer and the protective film have contact holes, which expose the drain region. The pixel electrode is disposed on the protective film and is electrically connected to the drain region through the contact hole.

6. The display device according to claim 1, wherein, The pixel electrode has multiple slits.

7. The display device according to claim 1, further comprising: A gate insulating film disposed on the active layer, the gate insulating film having a second contact hole and a third contact hole to expose the source region of the active layer of the thin-film transistor.

8. The display device according to claim 7, wherein, The data lines, which extend discontinuously in the region overlapping with the gate line, are electrically connected to each other by the active layer of the thin-film transistor through the second contact hole and the third contact hole.

9. The display device according to claim 8, wherein, The active layer of the thin-film transistor includes: Semiconductor layer; and A conductive layer is disposed on the semiconductor layer. The data lines that extend discontinuously in the region overlapping with the gate line are electrically connected to each other by the conductive layer of the active layer through the second contact hole and the third contact hole.

10. A display panel comprising: A gate line extending in a first direction; A data line that extends in a second direction intersecting the gate line and extends discontinuously in the region where it intersects the gate line; A thin-film transistor having an active layer and disposed in a pixel region defined by the intersecting gate lines and data lines; as well as Pixel electrode, the pixel electrode being connected to the thin-film transistor. The data lines, which extend discontinuously in the region overlapping with the gate line, are electrically connected to each other through the active layer of the thin-film transistor.

11. A method for manufacturing a display device, the method comprising the following steps: An active layer is formed on a substrate, the active layer including a source region, a channel region and a drain region and including a conductive layer and a semiconductor layer laminated on the substrate, wherein the conductive layer corresponding to the channel region is removed; A gate insulating film is formed on the substrate on which the active layer is disposed; By selectively removing the gate insulating film, a first contact hole is formed to expose the drain region of the active layer, and a second and third contact hole are formed to expose the source region of the active layer. A gate line extending in a first direction is formed on the gate insulating film, a gate electrode protruding from the gate line, and a data line extending in a second direction intersecting the gate line to extend discontinuously in the region overlapping with the gate line; A first protective film is formed on the front surface of the substrate to cover the gate line, the data line and the gate electrode; A planarization layer is formed on the first protective film; A fourth contact hole is formed by selectively removing the first protective film and the planarization layer at the location where the first contact hole is formed; A common electrode and a common line are formed on the planarization layer; A second protective film is formed on the front surface of the substrate on which the common electrode and the common line are disposed; The fifth contact hole is formed by selectively removing the second protective film corresponding to the location where the fourth contact hole is formed; and A pixel electrode is formed on the second protective film to be electrically connected to the drain region through the first contact hole, the fourth contact hole, and the fifth contact hole.

12. The method according to claim 11, wherein, The gate line and the data line are formed on the same layer using the same material.

13. The method according to claim 11, wherein, The steps for forming the active layer include the following: The semiconductor layer and the conductive layer are sequentially formed on the substrate; A photoresist pattern defining the active layer is formed on the conductive layer using an exposure and development process with a halftone mask. The semiconductor layer and the conductive layer are removed using the photoresist pattern as a mask; and The photoresist pattern is ashed, and the ashed photoresist pattern is used as a mask to remove the portion of the conductive layer corresponding to the channel region.

14. The method according to claim 11, wherein, The data lines, which extend discontinuously in the region overlapping with the gate line, are electrically connected to each other by the conductive layer through the second contact hole and the third contact hole.

15. The method according to claim 11, wherein, The gate electrode is formed on the gate insulating film in the channel region of the active layer.

16. The method according to claim 11, wherein, The steps of forming the common electrode and the common line include the following steps: A transparent conductive film and a metal layer are sequentially formed on the planarization layer; A photoresist pattern defining the common electrode is formed on the metal layer using an exposure and development process with a halftone mask. The common electrode is patterned by removing the transparent conductive film and the metal layer using the photoresist pattern as a mask. Ashing the photoresist pattern; and The common line is formed by removing the metal layer using an ashened photoresist pattern as a mask.

17. The method according to claim 11, wherein, The pixel electrode has multiple slits.

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