Group history read method for improving quality of service of solid state drive

Abstract

The present application relates to a method of reading data from a memory and an associated memory system. The method comprises: reading data from a memory bank of the memory; calculating a bank divergence metric for a read bias used to read the data from the memory bank; when the bank divergence metric satisfies a threshold, dividing the memory bank into a first sub-bank and a second sub-bank, wherein an error rate of the first sub-bank is lower than an error rate of the second sub-bank; reading data from the first and second sub-banks; calculating respective sub-bank divergence metrics for a read bias used to read the data from the first and second sub-banks; and when one of the sub-bank divergence metrics satisfies the threshold, dividing the one of the first and second sub-banks that satisfies the threshold into a third sub-bank.

Description

Technical Field

[0001] Embodiments of this disclosure relate to memory systems and methods of operating such memory systems, and more particularly, to the operation of solid-state drives. Background Technology

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with memory devices (i.e., data storage devices). Data storage devices are used as either the main memory or secondary memory devices in portable electronic devices.

[0003] Because data storage devices that use memory devices have no moving parts, they offer excellent stability, durability, high data access speeds, and low power consumption. Examples of data storage devices with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and solid-state drives (SSDs).

[0004] An SSD may include a flash memory component and a controller. The controller includes electronics that bridge the flash memory component to the SSD input / output (I / O) interface. The SSD controller may include an embedded processor that can run functional components such as firmware (FW). SSD functional components are device-specific and can be updated in most cases.

[0005] Two main types of flash memory components are named after NAND and NOR logic gates. A single flash memory cell exhibits internal characteristics similar to its corresponding gate. NAND flash memory can be written to and read in blocks (or pages), which are typically much smaller than the entire memory space. NOR flash memory allows individual machine words (bytes) to be written to the erase location or read independently. NAND flash memory is primarily used in memory cards, USB flash drives, solid-state drives, and similar products for general data storage and transfer.

[0006] NAND flash memory-based storage devices are widely adopted due to their faster read / write performance, lower power consumption, and shock resistance. However, they are generally more expensive than hard disk drives (HDDs). In an effort to reduce costs, NAND flash memory manufacturers have been pushing the limits of their manufacturing processes below 20nm, which typically results in shorter lifespans, reduced data reliability, or decreased quality of service.

[0007] Against this backdrop, embodiments of the present invention have emerged. Summary of the Invention

[0008] An aspect of the present invention includes a method for reading data from memory. The method includes: reading data from a group of memories in the memory; calculating a group divergence metric for read biases of the data from the group of memories; dividing the group of memories into a first subgroup and a second subgroup when the group divergence metric meets a threshold, wherein the error rate of the first subgroup is lower than the error rate of the second subgroup; reading data from the first and second subgroups; calculating respective subgroup divergence metrics for read biases of the data from the first and second subgroups; and dividing a subgroup of the first and second subgroups that meets the threshold into a third subgroup when one of the subgroup divergence metrics meets the threshold.

[0009] Other aspects of the invention include a memory system comprising a memory device and a controller in communication with the memory device, the controller being configured to: read data from a group of memories of the memory device; calculate a group divergence metric for a read bias used to read data from the group of memories; divide the group of memories into a first subgroup and a second subgroup when the group divergence metric satisfies a threshold, wherein the error rate of the first subgroup is lower than the error rate of the second subgroup; read data from the first and second subgroups; calculate a respective subgroup divergence metric for a read bias used to read data from the first and second subgroups; and divide a subgroup of the first and second subgroups that satisfies the threshold into a third subgroup when one of the subgroup divergence metrics satisfies the threshold.

[0010] Other features, aspects and advantages of the invention will become clearer from the following description and in conjunction with the accompanying drawings. Attached Figure Description

[0011] Figure 1 This is a block diagram schematically illustrating a memory system according to an embodiment of the present invention.

[0012] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention.

[0013] Figure 3 This is a circuit diagram illustrating a memory block of a memory device in a memory system according to an embodiment of the present invention.

[0014] Figure 4 This is a diagram of an exemplary memory system according to an embodiment of the present invention.

[0015] Figure 5 This is a diagram of an exemplary memory system including different decoders according to an embodiment of the present invention.

[0016] Figure 6 It is a matrix description of the LDPC code.

[0017] Figure 7A and Figure 7BThe Tanner diagram representation of the LDPC code, including the user bits, check nodes, and parity bits, is shown.

[0018] Figure 8 This is a description of group A being divided into group A1 and group A2 according to an embodiment of the present invention.

[0019] Figure 9 This is a flowchart describing a method for reading data from a memory according to an embodiment of the present invention. Detailed Implementation

[0020] Various embodiments are described in more detail below with reference to the accompanying drawings. However, the invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, references herein to “embodiment,” “another embodiment,” etc., are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. Throughout this disclosure, the same reference numerals denote the same parts in the drawings and embodiments of the invention.

[0021] This invention can be embodied in a variety of ways, including as a process; an apparatus; a system; a composition of matter; a computer program product implemented on a computer-readable storage medium; and / or a processor, such as a processor suitable for executing instructions stored in and / or provided by memory linked to the processor. In this specification, these embodiments or any other form in which the invention may take the form of can be referred to as technology. Generally, the order of steps of the disclosed process can be varied within the scope of this invention. Unless otherwise stated, components such as processors or memory described as suitable for performing tasks can be implemented as general-purpose components temporarily configured to perform tasks at a given time or as specific components manufactured for performing tasks. As used herein, the term "processor" refers to one or more means, circuits, and / or processing cores suitable for processing data such as computer program instructions.

[0022] The following provides a detailed description of embodiments of the present invention, along with accompanying drawings illustrating various aspects of the invention. The invention is described in conjunction with these embodiments, but is not limited to any particular embodiment. The scope of the invention is limited only by the claims, and the invention encompasses many alternatives, modifications, and equivalents. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for illustrative purposes; the invention may be practiced without some or all of these specific details. For brevity, technical materials known in the art related to the invention are not described in detail, thereby avoiding unnecessarily obscuring the invention.

[0023] Figure 1 This is a block diagram schematically illustrating a memory system 10 according to an embodiment of the present invention.

[0024] Reference Figure 1 The memory system 10 may include a memory controller 100 and a semiconductor memory device 200, which may represent more than one such device. The semiconductor memory device 200 may be a flash memory device.

[0025] The memory controller 100 can control all operations of the semiconductor memory device 200.

[0026] The semiconductor memory device 200 can perform one or more erase, program, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive commands (CMD), addresses (ADDR), and data (DATA) via input / output (I / O) lines. The semiconductor memory device 200 can receive power (PWR) via power lines and control signals (CTRL) via control lines. The control signals (CTRL) may include command latch enable (CLE), address latch enable (ALE), chip enable (CE), write enable (WE), and read enable (RE) signals, etc.

[0027] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device (e.g., a solid-state drive (SSD)). The SSD may include a storage device for storing data therein. When the memory system 10 is used in an SSD, the operating speed of a host (not shown) connected to the memory system 10 can be significantly improved.

[0028] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device (e.g., a memory card). For example, the memory controller 100 and the semiconductor memory device 200 can be integrated to configure PC cards, Compact Flash (CF) cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMCs), Reduced Size Multimedia Cards (RS-MMCs), Micro Size MMCs (Micro MMCs), Secure Digital (SD) cards, Mini Secure Digital (Mini SD) cards, Micro Secure Digital (Micro SD) cards, Secure Digital High Capacity (SDHC) cards, and / or Universal Flash Memory (UFS) cards, according to the Personal Computer Memory Card International Association (PCMCIA).

[0029] In another embodiment, the memory system 10 may be configured as one of a variety of components in electronic devices such as: a computer, an ultra-mobile PC (UMPC), a workstation, a netbook computer, a personal digital assistant (PDA), a portable computer, a network tablet PC, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable gaming device, a navigation device, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a 3D television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device for a data center, a device capable of receiving and transmitting information in a wireless environment, a radio frequency identification (RFID) device, and one of a variety of electronic devices in a home network, one of a variety of electronic devices in a computer network, one of a variety of electronic devices in a telematics network, or one of a variety of components in a computing system.

[0030] Figure 2 This is a detailed block diagram illustrating a memory system according to an embodiment of the present invention. For example, Figure 2 The memory system can be described Figure 1 The memory system 10 shown is shown.

[0031] Reference Figure 2 The memory system 10 may include a controller 100 and a memory device 200. The memory system 10 can operate in response to requests from a host device, and in particular, stores data to be accessed by the host device.

[0032] The host device can be implemented using any of a variety of electronic devices. In some embodiments, the host device may include electronic devices such as desktop computers, workstations, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, and / or digital video recorders and digital video players. In some embodiments, the host device may include portable electronic devices such as mobile phones, smartphones, e-book readers, MP3 players, portable multimedia players (PMPs), and / or portable game consoles.

[0033] The memory device 200 can store data to be accessed by the host device.

[0034] The memory device 200 may be implemented using volatile memory devices (e.g., dynamic random access memory (DRAM) and / or static random access memory (SRAM)) or non-volatile memory devices (e.g., read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM) and / or resistive RAM (RRAM)).

[0035] The controller 100 can control the storage of data in the memory device 200. For example, the controller 100 can control the memory device 200 in response to a request from the host device. The controller 100 can provide data read from the memory device 200 to the host device, and can store data provided by the host device into the memory device 200.

[0036] The controller 100 may include a storage device 110 connected via a bus 160, a control component 120 which may be implemented as a processor (e.g., a central processing unit (CPU)), an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150.

[0037] Storage device 110 can be used as working memory for memory system 10 and controller 100, and stores data for driving memory system 10 and controller 100. When controller 100 controls the operation of memory device 200, storage device 110 can store data used by controller 100 and memory device 200 for operations such as read operations, write operations, programming operations and erase operations.

[0038] Storage device 110 can be implemented using volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, storage device 110 can store data used by the host device in storage device 200 for read and write operations. To store data, storage device 110 may include program memory, data memory, write buffer, read buffer, mapping buffer, etc.

[0039] Control component 120 can control the general operation of storage system 10, as well as write or read operations on memory device 200, in response to write or read requests from host device. Control component 120 can drive firmware called a flash translation layer (FTL) to control the general operation of storage system 10. For example, FTL can perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block handling. L2P mapping is called logical block addressing (LBA).

[0040] ECC component 130 can detect and correct errors in data read from memory device 200 during a read operation. When the number of error bits is greater than or equal to the threshold number of correctable error bits, ECC component 130 may not correct the error bits, but may instead output an error correction failure signal indicating that the error bit correction has failed.

[0041] ECC component 130 can perform error correction operations based on coding modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhri-Hocquenghem (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM). Therefore, ECC component 130 can include all circuitry, systems, or means for appropriate error correction operations.

[0042] The host interface 140 can communicate with the host device through one or more of the following interface protocols: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0043] Memory interface 150 can provide an interface between controller 100 and memory device 200, allowing controller 100 to control memory device 200 in response to requests from host device. Memory interface 150 can generate control signals for memory device 200 and process data under the control of control component 120. When memory device 200 is flash memory (e.g., NAND flash memory), memory interface 150 can generate control signals for memory and process data under the control of control component 120.

[0044] The memory device 200 may include a memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer 250 (which may be in the form of a page buffer array), column decoder 260, and input / output circuitry 270. The memory cell array 210 may include multiple memory blocks 211 capable of storing data. The voltage generation circuitry 230, row decoder 240, page buffer array 250, column decoder 260, and input / output circuitry 270 may form peripheral circuitry for the memory cell array 210. This peripheral circuitry may perform programming, reading, or erasing operations on the memory cell array 210. The control circuitry 220 may control the peripheral circuitry.

[0045] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as erase voltage and pass voltage.

[0046] The row decoder 240 can communicate electrically with the voltage generation circuit 230 and a plurality of memory blocks 211. The row decoder 240 can select at least one of the plurality of memory blocks 211 in response to the row address RADD generated by the control circuit 220 and send the operating voltage supplied from the voltage generation circuit 230 to the selected memory block.

[0047] Page buffer 250 can be accessed via bit line BL (e.g. Figure 3 (As shown) It is in electrical communication with the memory cell array 210. The page buffer 250 can precharge the bit line BL with a positive voltage in response to a page buffer control signal generated by the control circuit 220, send data to and receive data from the selected memory block during programming and reading operations, or temporarily store the sent data.

[0048] The column decoder 260 can send data to and receive data from the page buffer 250, or send data to and receive data from the input / output circuit 270.

[0049] The input / output circuit 270 can send commands and addresses received from an external device (e.g., controller 100) to the control circuit 220, and send data from the external device to the column decoder 260 or output data from the column decoder 260 to the external device.

[0050] The control circuit 220 can control the peripheral circuits in response to commands and addresses.

[0051] Figure 3 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present invention. For example, Figure 3 The storage block can be Figure 2 Any one of the storage blocks 211 in the memory cell array 210 shown.

[0052] Reference Figure 3 An exemplary storage block 211 may include multiple word lines WL0 to WLn-1, a drain select line DSL, and a source select line SSL connected to a line decoder 240. These lines may be arranged in parallel, with multiple word lines located between DSL and SSL.

[0053] The exemplary memory block 211 may further include multiple cell strings 221 respectively connected to bit lines BL0 to BLm-1. Each cell string may include one or more drain select transistors (DSTs) and one or more source select transistors (SSTs). In the illustrated embodiment, each cell string has one DST and one SST. Within the cell string, multiple memory cells or memory cell transistors MC0 to MCn-1 may be serially connected between the select transistors DST and SST. Each memory cell may be configured as a multi-layer cell (MLC) storing multiple bits of data information.

[0054] The source of each SST in a cell string can be connected to the common source line CSL, and the drain of each DST can be connected to the corresponding bit line. The gate of an SST in a cell string can be connected to SSL, and the gate of a DST in a cell string can be connected to DSL. The gates of memory cells spanning cell strings can be connected to the respective word lines. That is, the gate of memory cell MC0 is connected to the corresponding word line WL0, the gate of memory cell MC1 is connected to the corresponding word line WL1, and so on. A group of memory cells connected to a specific word line can be called a physical page. Therefore, the number of physical pages in memory block 211 can correspond to the number of word lines.

[0055] Page buffer array 250 may include multiple page buffers 251 connected to bit lines BL0 to BLm-1. Page buffers 251 may operate in response to page buffer control signals. For example, during a read operation or a verification operation, page buffers 251 may temporarily store data received through bit lines BL0 to BLm-1 or sense the voltage or current of the bit lines.

[0056] In some embodiments, memory block 211 may include NAND flash memory cells. However, memory block 211 is not limited to this cell type, but may include NOR flash memory cells. Memory cell array 210 may be implemented as a hybrid flash memory in which two or more types of memory cells are combined, or as a single NAND flash memory in which a controller is embedded within the memory chip.

[0057] Reference Figure 4 The diagram schematically illustrates a general example of a memory system 40. The memory system 40 may include volatile memory 400 (e.g., DRAM), non-volatile memory (NVM) 402 (e.g., NAND), control components or control logic 404 (as described herein), error correction code (ECC) module 406 (as described herein), and a bus 408 through which these components of the memory system 40 communicate. The volatile memory 400 may include a logical bit address (LBA) table 410 for mapping physical addresses of bits to logical addresses. The NVM 402 may include multiple memory blocks (and / or multiple superblocks), as well as open blocks 430 for host writes and open blocks 440 for garbage collection (GC). The memory system 40 illustrates a general memory system. Those skilled in the art will understand from this disclosure that additional / alternative components may be used with the memory system to implement the present invention.

[0058] The terms used in this document, such as “NAND” or “NVM”, can refer to non-volatile memory, such as flash memory that can implement error correction code processing. Additionally, “DRAM” can refer to volatile memory, which may include components such as controllers and ECC modules.

[0059] In embodiments of the present invention, the memory system 10 may include a plurality of decoders configured to decode low-density parity-check (LDPC) codes.

[0060] There are many iterative decoding algorithms for LDPC codes, such as bit-flip (BF) decoding, belief propagation (BP) decoding, sum-product (SP) decoding, minimum sum (MS) decoding, and Min-Max decoding.

[0061] According to embodiments of the present invention, such as Figure 5 As shown, the memory system 10 may include a memory device 200 and a memory controller 100, wherein the memory device 200 may be a NAND device. The memory system 10 may include a decoding component 502, which includes a bit-flip (BF) decoder 503 for running a BF decoding algorithm to decode codewords read from the memory device 200, and a minimum-sum (MS) decoder 504 for performing an MS decoding algorithm. The BF decoder 503 and the MS decoder 504 may be implemented in the ECC component 130 in the memory controller 100 (e.g., ...). Figure 2The codewords received by the memory controller 100 from the memory device 200 may be temporarily stored in the buffer or storage device 505 of the memory controller 100 and then passed to one or more decoders. In one embodiment of the invention, the MS decoder 504 is a mixed-precision MS decoder (as described above, and will be described in more detail below).

[0062] The memory system 10 may include other components (not shown), such as a checksum module that calculates a checksum for the codeword retrieved from the memory device 200 before decoding. The checksum module may be implemented within the memory controller 100 prior to the storage device 505. The memory system 10 may further include cyclic redundancy check (CRC) modules disposed downstream of the BF decoder 503 and the MS decoder 504, respectively. The CRC modules may be implemented within the memory controller 100.

[0063] Of the two decoding algorithms, MS decoding (performed by its associated decoder 504) is more powerful due to the higher complexity required to process soft input information. However, the weaker BF decoding (performed by its associated decoder 503) is useful when the number of errors is small.

[0064] MS decoding can be used as part of iterative LDPC decoding. An LDPC code is a linear block code defined by a sparse parity check matrix H, which consists of zeros and ones. The term "sparse matrix" is used in this paper to refer to a matrix where the number of non-zero values ​​in each column and each row is much smaller than its dimension. The term "column weight" is used in this paper to refer to the number of non-zero values ​​in a specific column of the parity check matrix H. The term "row weight" is used in this paper to refer to the number of non-zero values ​​in a specific row of the parity check matrix H. Generally, if the column weights of all columns in the parity check matrix corresponding to the LDPC code are similar, the code is called a "regular" LDPC code. On the other hand, if at least one column weight is different from the other column weights, the LDPC code is called an "irregular" LDPC code. Generally, irregular LDPC codes provide better error correction capabilities than regular LDPC codes.

[0065] LDPC codes are typically represented using a bipartite graph. One set of nodes (variable or bit nodes) corresponds to the elements of the codeword, and another set of nodes (e.g., check nodes) corresponds to a set of parity check constraints satisfied by the codeword. Edge connections are usually randomly selected. Avoiding short cycles in the graph can improve the error correction capability of the LDPC code. In a (r, c) regular code, each of the n variable nodes (V1, V2, ..., Vn) is connected to r check nodes, and each of the m check nodes (C1, C2, ..., Cm) is connected to c bit nodes. In irregular LDPC codes, the degree of check nodes is non-uniform. Similarly, the degree of variable nodes is also non-uniform. In QC-LDPC codes, the parity check matrix H is constructed as p×p matrix blocks such that the bits in a block participate in only one check equation in the block, and each check equation in the block involves only one bit in the block. In QC-LDPC codes, a codeword cyclically shifted by p produces another codeword. Here, p is the size of a square matrix, which is either a zero matrix or a cyclic matrix. This is a summary of cyclic codes, where a codeword is cyclically shifted by 1 to produce another codeword. A p×p matrix block can be a zero matrix or a cyclically shifted identity matrix of size p×p.

[0066] Figure 6 An example parity check matrix H 600 is shown. Figure 7A An example bipartite graph corresponding to parity check matrix 600 is shown.

[0067] like Figure 6 As shown, the exemplary parity check matrix 600 has six column vectors and four row vectors. Figure 7A The network 702 shown illustrates the network corresponding to the parity check matrix 600 and represents a bipartite graph. Various types of bipartite graphs are possible, including, for example, Tanner graphs. Figure 7B A Tanner diagram representation of an LDPC code with user bit 71, parity bit 72, and parity node 73 is shown.

[0068] Typically, the variable nodes in network 702 correspond to the column vectors in parity check matrix 600. The parity nodes in network 702 correspond to the row vectors in parity check matrix 600. The interconnections between nodes are determined by the values ​​of parity check matrix 200. Specifically, "1" indicates that the corresponding parity node is connected to the variable node. "0" indicates no connection. For example, the "1" in the leftmost column vector and the second row vector from the top in parity check matrix 600 corresponds to the connection between variable node 704 and parity node 710.

[0069] Message-passing algorithms can be used to decode LDPC codes. Several variations of message-passing algorithms exist in this field, such as the Minimum Sum (MS) algorithm and the Product-Sum (SPA) algorithm. Message passing uses a network of variable nodes and check nodes, such as... Figure 7A As shown.

[0070] A hard-decision message passing algorithm can be executed. In the first step, each of the variable nodes sends a message to one or more check nodes connected to it. In this case, the message is a value that each of the variable nodes considers to be correct.

[0071] In the second step, each check node calculates a response using the information previously received from the variable nodes and sends it to the variable nodes connected to it. This step can be called Check Node Update (CNU). The response message corresponds to the value that the check node believes the variable node should have based on information received from other variable nodes connected to that check node. This response is calculated using a parity check equation that forces the sum of the values ​​of all variable nodes connected to a particular check node to be zero (modulo 2).

[0072] At this point, if all equations of all check nodes are satisfied, the decoding algorithm declares that the correct codeword has been found and terminates. If the correct codeword is not found, the algorithm continues iterating using the message received by the variable node from the check node, along with another update from the variable node, to determine whether the bit at its position should be 0 or 1 using the majority decision principle. The variable node then sends this hard decision message to the check nodes connected to it. Iteration continues until the correct codeword is found, performing a certain number of iterations based on the checksum of the codeword (e.g., the decoded codeword), or a maximum number of iterations if the correct codeword is not found.

[0073] In each iteration of decoding, the system (user) bit 71 and the low-degree parity bit 72 can be decoded alternately (e.g., ...). Figure 7B (As shown). User bit 71 can be decoded one by one using, for example, an MS operation. Low-degree parity bit 72 can be jointly decoded using the result of user bit 71. The result of the joint decoding can be used for the next iteration.

[0074] NAND flash memory organization

[0075] In NAND flash memory, cells are organized into word lines (WLs), and WLs are organized into blocks. A die typically contains thousands of blocks. To read data, a sense bias (hereinafter referred to as the voltage threshold Vt) is applied to the target word line (WL) being read, and a "0 / 1" is returned based on the voltage of each cell on the WL. To reduce errors, an optimal voltage needs to be applied. The optimal Vt for each WL may differ, depending on the NAND conditions at the time, such as retention time, read interference count, endurance cycle, WL index, block index, and die coordinates on the wafer.

[0076] Due to this complexity, die- and / or block-based history read algorithms have been applied to existing memory device products to track optimal read biases, thereby minimizing the failure rate of first reads and improving Quality of Service (QoS).

[0077] This disclosure addresses the problems previously identified by the inventors regarding die and block history reads and proposes a novel history read strategy, hereinafter referred to as "Group History Read" or GHR. In one embodiment, the Group History Read scheme dynamically adjusts its strategy to achieve optimal QoS for contemporaneous NAND conditions.

[0078] Die and Block History Reading

[0079] Die history reads refer to a process where all pages within the same die share a common read bias for the first read. If any page within the same die fails on the first read but recovers in a deeper defense phase (subsequent error correction), the read bias used in the successful defense phase replaces the die history read entry and is used as the first read bias for all future pages within the same die until the read bias is updated again. Block history reads are performed similarly to die history reads, except that the read bias is updated / used for all pages within the same block. In one embodiment, dies and block histories can use different biases for each page type, meaning, for example, all least significant bit (LSB) pages within a die share the same LSB die history read bias, all most significant bit (MSB) pages within a die share the same MSB die history read bias, and so on.

[0080] Historical reads typically track optimal read biases, thus reducing the failure rate of the first read and providing good QoS for the host. Block historical reads could be considered better than die historical reads because they offer greater flexibility and allow different blocks to have their own optimal read biases. However, the inventors have found through testing that this assumption is incorrect.

[0081] The reason is that the update complexity of block history reads is thousands of times higher than that of die history reads. Consider a die containing 2000 blocks, where data is written and retained for 15 days. After 15 days of retention, all pages in the die will fail on the first read, and it typically takes 3 reads to find the optimal bias to recover the data after the 15-day retention. Therefore, it takes 6000 reads to fully update the block history read entries for this die. In comparison, die history reads typically only require 3 reads to update the history read bias to the optimal value. On the other hand, die history reads can be iterative. For example, suppose 1000 blocks in the die have the optimal Vt at V1, while another 1000 blocks have the optimal Vt at V2. If V1 and V2 (each working well means the data read back is decorative for both the first and second 1000 blocks) are still far apart, a die history read using V1 will cause the first read of the second 1000 blocks to fail. Similarly, using V2's die history read will cause the first read of the first 1000 blocks to fail. In contrast, if block history read is used, a second read will not be triggered. This is not a simple question of which strategy—die or block—is more beneficial for QoS; the answer depends on the NAND conditions at the time.

[0082] In one embodiment of this disclosure, a novel process is provided designed to provide an optimal strategy for arbitrary and dynamic NAND conditions.

[0083] Group History Read (GHR)

[0084] To illustrate how the optimal strategy depends on NAND conditions, die history will be the optimal strategy when all blocks in the die have similar optimal Vt. On the other hand, block history reading will be the optimal strategy if all blocks have sufficiently different optimal Vt.

[0085] The GHR strategy can utilize a divergence metric (DM) to measure the similarity of the best Vt values ​​of pages within the same group. In one embodiment, if the DM is greater than a certain threshold, the group is divided into smaller subgroups. The GHR strategy provides a relatively simple and efficient algorithm for group partitioning. The GHR strategy can determine how best to handle cold data.

[0086] granularity of the group

[0087] Depending on the chosen implementation, a group can consist of multiple pages within a block, such as a WL / page group, or a block or superblock, or even an entire die. Smaller granularity requires more memory to store the program used to update Vt, but offers greater flexibility and higher update complexity. In one embodiment of this disclosure, the GHR strategy uses small granularity only when necessary.

[0088] Divergence metric (DM)

[0089] To determine whether all pages in the same group have similar optimal voltage thresholds, such as Figure 8 The NAND controller 801 shown (or it could be) Figure 2 The control component 120 or control circuit 220 records the maximum and minimum failure bit counts (maxFBC and minFBC) for each group. The function f(maxFBC, minFBC) can be used to indicate / track the divergence of a group. An example of such a function could be 2(maxFBC - minFBC) / (maxFBC + minFBC).

[0090] Grouping

[0091] In one embodiment of this disclosure, when both conditions are met: a) DM is greater than a threshold and b) maxFBC is close to the ECC correction capability of the NAND controller. For example, if maxFBC is greater than 70% of the ECC correction capability, the group can be divided into smaller groups using the following partitioning algorithm.

[0092] Is DM greater than a threshold, such as 50%? Yes or no. If yes, and if maxFBC is close to the ECC correction capability of the NAND controller, for example, if maxFBC is greater than 70% of the ECC correction capability, then group A is divided into smaller subgroups. This disclosure does not limit these values ​​of maxFBC and DM. Other values ​​of maxFBC ranging from 60% to 95% may be used. Other values ​​of DM ranging from 20% to 80% may be used.

[0093] When it is necessary to divide group A into smaller groups, the following recursive algorithm can be applied.

[0094] Divide group A into two subgroups, A1 and A2, such that any page associated with minFBC is assigned to subgroup A1, and any page associated with maxFBC is assigned to subgroup A2. Figure 8 This illustrates the partitioning of the NAND controller 801. More host read commands are processed on the page. The DM, maxFBC, and minFBC of all groups are calculated, and it is determined whether additional groups or subgroups need to be partitioned. If so, proceed to step 1. Otherwise, proceed to step 2. Group history read and group partitioning.

[0095] When the first page read / group history read fails Figure 8The NAND controller 801 can assign a predetermined number (e.g., minimum and hard decoding correction capability) as the maxFBC of the page to check whether the above two partitioning conditions are met (i.e., whether DM is greater than the threshold and whether maxFBC is close to the ECC correction capability). If the conditions are met, the NAND controller 801 starts the group partitioning operation using the above recursive algorithm.

[0096] In the "group partitioning" operation, group A is divided into two subgroups, A1 and A2. Although the partitioning of the minFBC and maxFBC pages is deterministic (any page associated with minFBC is partitioned into subgroup A1, and any page associated with maxFBC is partitioned into subgroup A2), other pages can also be randomly distributed into subgroups A1 and A2. If any subgroup satisfies the conditions of the partitioning algorithm described above, it may result in multiple rounds of partitioning.

[0097] The following extension of the recursive algorithm described above can be used, but at the cost of requiring more memory for the GHR strategy. In one embodiment, the NAND controller 801 generates two queues (Q1 and Q2). The NAND controller 801 sets two FBC thresholds alpha and beta, for example, 30% and 60% of the ECC correction capability. This disclosure is not limited to these exemplary thresholds. Thresholds of 20% and 80%, 10% and 90%, or 5% and 95% can be used. If the FBC of a page is less than alpha, the NAND controller 801 indexes the page for Q1. If the FBC of a page is greater than beta, the NAND controller 801 indexes the page for Q2. When A is partitioned, the NAND controller 801 can put the page indexed by Q1 into A1, the page indexed by Q2 into A2, and randomly place the remaining unindexed pages into subgroups A1 and A2. The sizes of Q1 and Q2 can be finitely small. (When the queue size is zero, it degrades to the original recursive algorithm described above.) When one or both queues Q1 and Q2 become full, the NAND controller 801 is programmed not to add another page index. This makes subgroup A1 more likely to have relatively low FBC pages, and subgroup A2 more likely to have relatively high FBC pages. In this way, the divergence metric of subgroup A1 is reduced compared to that of group A.

[0098] Combination

[0099] The NAND controller 801 can merge sets S of two or more groups when all of the following conditions are met:

[0100] The optimal Vt values ​​for all groups in S are similar; the maxFBC for all groups is less than 70% of the ECC correction; and the DM for all groups is less than 50%. As stated above, this disclosure does not limit these values ​​of maxFBC and DM. Other values ​​of maxFBC ranging from 60% to 95% may be used. Other values ​​of DM ranging from 20% to 80% may be used.

[0101] In the merged set, all pages in each group will share the same optimal read bias. If any page enters a deeper stage of the defense process, the group's historical read bias will be replaced with the successfully found read bias. In one embodiment, the NAND controller 801 can determine whether two different read biases are similar by using a distance metric between the two read biases, such as Euclidean distance or weighted Euclidean distance.

[0102] In one embodiment, the NAND controller 801 monitors the conditions for group partitioning and merging (within a predetermined periodic time interval), and performs partitioning and merging if the conditions of the partitioning algorithm described above are met. Due to this periodic dynamic grouping, even if NAND conditions change and data traffic changes, the NAND controller 801 (programmed with the monitoring and merging algorithm) is able to maintain optimal read bias (aimed at improving the success rate of the first read, i.e., minimizing the trigger rate of the second read).

[0103] Cold data processing

[0104] In the group history read algorithm described above, no additional reads are required; the NAND controller 801 relies solely on host reads to perform group partitioning / merging and history read bias updates. For cold data blocks, no host reads are available to execute the group history read algorithm.

[0105] Typically, cold data blocks have no QoS requirements (or only minimal QoS requirements). In one embodiment, the NAND controller 801 treats all cold blocks as a special group, referred to as the cold data group, and the first read bias can be tracked using classic die or block history reads. Another approach is to perform a group history read on the cold data blocks using media scan reads (where all pages in the SSD are scanned every n days, e.g., every 20 days). Media scan reads are a mechanism to prevent data loss due to data retention. When a media scan read finds that the FBC of certain pages is above a predetermined threshold, data on the associated blocks can be reclaimed.

[0106] Use of metadata

[0107] If certain metadata exists in the firmware, such as average / maximum 1 count and asymmetric error rate, retention time, read interference count, endurance, etc., the NAND controller 801 can use this metadata to improve group partitioning and merging. This metadata supplements the FBC when determining which subgroups of read pages will be partitioned into have a lower divergence metric.

[0108] Data recycling

[0109] In one embodiment, when a block is reclaimed, the data associated with that block should be removed from the group. When a new block is opened, it should be assigned to a newly created group with a default history read.

[0110] Power outage

[0111] In one embodiment, during a normal power outage, group information and group history read bias should be stored in a single-level cell (SLC) area of ​​the memory. Upon the next power-on, the information will be loaded back into the FW. In another embodiment, during a sudden power outage, group information and group history read bias information may fail to be stored in the SLC area. Upon the next power-on, the initial state value of the group's voltage threshold (Vt) will be applied, and the aforementioned group history read algorithm can be used in conjunction with host reads to help adjust the group and group history read information for optimal performance.

[0112] Operating method

[0113] Figure 9 This is a flowchart describing a method for reading data from a memory according to an embodiment of the present invention. Figure 9 As shown, the method reads data from a memory bank of memory. At 901, the method calculates a group divergence metric for the read bias used to read data from the memory bank. At 903, when the group divergence metric meets a threshold, the method divides the memory bank into a first subgroup and a second subgroup, wherein the error rate of the first subgroup is lower than that of the second subgroup. At 905, the method reads data from the first and second subgroups. At 907, the method calculates respective subgroup divergence metrics for the read bias used to read data from the first and second subgroups. At 909, when one of the subgroup divergence metrics meets a threshold, the method divides the subgroup that meets the threshold from the first and second subgroups into a third subgroup.

[0114] In one aspect of this method, the divergence metric is a function of at least one of the maximum failure bit count (maxFBC) and the minimum failure bit count (minFBC).

[0115] In one aspect of this method, the divergence metric is calculated based on 2(maxFBC-minFBC) / (maxFBC+minFBC).

[0116] One aspect of this method is that the memory is partitioned based on the fact that maxFBC is less than the error correction capability.

[0117] In one aspect of the method, the first subgroup includes a first page of data read from a memory group associated with minFBC, and the second subgroup includes a second page of data read from a memory group associated with maxFBC.

[0118] In one aspect of the method, a first queue and a second queue are provided, wherein the first queue indexes all pages of data for which the Failure Bit Count (FBC) is less than 30% of the error correction capacity to be partitioned into a first subgroup, and the second queue indexes all pages of data for which the FBC is greater than 60% of the error correction capacity to be partitioned into a second subgroup.

[0119] In one aspect of the method, any subgroups, including at least the first and second subgroups, are combined together to form a set of two or more groups, all of which have similar optimal read thresholds and all have a maxFBC of less than 70% of the error correction capability.

[0120] In one aspect of the method, the memory bank includes one of word line groups, page groups, blocks, superblocks, and memory dies, and the first subgroup and the second subgroup include partitions from one of the word line groups, page groups, blocks, superblocks, and memory dies.

[0121] In one aspect of this method, cold data blocks are placed into a fourth subgroup.

[0122] In one aspect of the method, the optimal read thresholds for the first and second subgroups are stored in a single-layer cell page.

[0123] Memory system

[0124] In this invention, a memory system is provided, including a memory device and a controller communicating with the memory device and configured to control the memory device. The controller is configured to: read data from a group of memories of the memory device; calculate a group divergence metric for a read bias used to read data from the group of memories; divide the group of memories into a first subgroup and a second subgroup when the group divergence metric meets a threshold, wherein the error rate of the first subgroup is lower than the error rate of the second subgroup; read data from the first subgroup and the second subgroup; calculate a respective subgroup divergence metric for a read bias used to read data from the first subgroup and the second subgroup; and divide one of the first and second subgroups (that meets the threshold) into a third subgroup when one of the subgroup divergence metrics meets the threshold.

[0125] In one aspect of the system, the divergence metric is a function of at least one of the maximum failure bit count (maxFBC) and the minimum failure bit count (minFBC).

[0126] On one side of the system, the divergence metric is calculated based on 2(maxFBC-minFBC) / (maxFBC+minFBC).

[0127] In one aspect of the system, the controller is configured to partition the memory based on maxFBC being less than the error correction capability.

[0128] In one aspect of the system, the first subgroup includes a first page of data read from the memory group associated with minFBC, and the second subgroup includes a second page of data read from the memory group associated with maxFBC.

[0129] In one aspect of the system, the controller is configured to provide a first queue and a second queue, wherein the first queue indexes all pages of data for which the Failure Bit Count (FBC) is less than 30% of the error correction capability to be assigned to a first subgroup, and the second queue indexes all pages of data for which the FBC is greater than 60% of the error correction capability to be assigned to a second subgroup.

[0130] In one aspect of the system, the controller is configured to combine any subgroups, including at least the first and second subgroups, together to form a set of two or more groups, all of which have similar optimal read thresholds and all have a maxFBC of less than 70% of the error correction capability.

[0131] In one aspect of the system, the memory bank includes one of word line groups, page groups, blocks, superblocks, and memory dies, and the first and second subgroups include divisions from one of word line groups, page groups, blocks, superblocks, and memory dies.

[0132] In one aspect of the system, the controller is configured to place cold data blocks into a fourth subgroup.

[0133] In one aspect of the system, the controller is configured to store the optimal read thresholds for the first and second subgroups into a single-level cell page.

[0134] Although the foregoing embodiments have been described in some detail for clarity and understanding, the invention is not limited to the details provided. As those skilled in the art will understand from the foregoing disclosure, many alternative ways of carrying out the invention exist. Therefore, the disclosed embodiments are illustrative and not restrictive.

Claims

1. A method for reading data from a memory, comprising: Read data from the memory group of the memory; Calculate the group divergence metric for the read bias used to read the data from the memory group; When the group divergence metric meets the threshold, the memory group is divided into a first subgroup and a second subgroup, wherein the error rate of the first subgroup is lower than the error rate of the second subgroup. Read data from the first subgroup and the second subgroup; Calculate the respective subgroup divergence measure for the read bias used to read data from the first subgroup and the second subgroup; as well as When one of the subgroup divergence metrics satisfies the threshold, the subgroup that satisfies the threshold in the first subgroup and the second subgroup is divided into a third subgroup.

2. The method according to claim 1, wherein, The divergence metric is a function of at least one of the maximum failure bit count (maxFBC) and the minimum failure bit count (minFBC).

3. The method according to claim 2, wherein, The divergence metric is calculated based on 2(maxFBC-minFBC) / (maxFBC+minFBC).

4. The method according to claim 2, wherein, The memory is partitioned based on the maximum FBC being less than the error correction capability.

5. The method according to claim 4, wherein, The first subgroup includes a first page of data read from the memory group associated with the minFBC, and The second subgroup includes a second page of data read from the memory group associated with the maxFBC.

6. The method of claim 4, further comprising: Provide a first queue and a second queue, wherein, The first queue indexes all pages of data for which the Failure Bit Count (FBC) is less than 30% of the error correction capacity, and assigns them to the first subgroup. The second queue indexes all pages of data for which the FBC is greater than 60% of the error correction capability, and divides them into the second subgroup.

7. The method of claim 1, further comprising: Any subgroup that includes at least the first subgroup and the second subgroup is combined together to form a set of two or more groups, both of which have similar optimal read thresholds and both have a maxFBC of less than 70% of the error correction capability.

8. The method according to claim 1, wherein, The memory bank includes one of the following: word line group, page group, block, superblock, and memory die. The first subgroup and the second subgroup comprise a division from one of the word line group, the page group, the block, the superblock, and the memory die.

9. The method of claim 1, further comprising: Place the cold data block into the fourth subgroup.

10. The method of claim 1, further comprising: The optimal read thresholds for the first subgroup and the second subgroup are stored in a single-level cell page.

11. A memory system, comprising: Memory devices; as well as A controller that communicates with and controls the memory device, wherein the controller: Read data from the memory group of the memory device; Calculate the group divergence metric for the read bias used to read the data from the memory group; When the group divergence metric meets the threshold, the memory group is divided into a first subgroup and a second subgroup, wherein the error rate of the first subgroup is lower than the error rate of the second subgroup. Read data from the first subgroup and the second subgroup; Calculate the respective subgroup divergence measure for the read bias used to read data from the first subgroup and the second subgroup; as well as When one of the subgroup divergence metrics satisfies the threshold, the subgroup that satisfies the threshold in the first subgroup and the second subgroup is divided into a third subgroup.

12. The system according to claim 11, wherein, The divergence metric is a function of at least one of the maximum failure bit count (maxFBC) and the minimum failure bit count (minFBC).

13. The system according to claim 12, wherein, The divergence metric is calculated based on 2(maxFBC-minFBC) / (maxFBC+minFBC).

14. The system according to claim 12, wherein, The controller partitions the memory device based on the maximum FBC being less than the error correction capability.

15. The system according to claim 14, wherein, The first subgroup includes a first page of data read from the memory group associated with the minFBC, and The second subgroup includes a second page of data read from the memory group associated with the maxFBC.

16. The system according to claim 15, wherein, The controller provides a first queue and a second queue. The first queue indexes all pages of data for which the Failure Bit Count (FBC) is less than 30% of the error correction capacity, and assigns them to the first subgroup. The second queue indexes all pages of data for which the FBC is greater than 60% of the error correction capability, and divides them into the second subgroup.

17. The system according to claim 15, wherein, The controller will combine any subgroups of at least the first subgroup and the second subgroup together to form a set of two or more groups, both of which have similar optimal read thresholds and both have a maxFBC of less than 70% of the error correction capability.

18. The system according to claim 11, wherein, The memory bank includes one of the following: word line group, page group, block, superblock, and memory die. The first subgroup and the second subgroup comprise a division from one of the word line group, the page group, the block, the superblock, and the memory die.

19. The system according to claim 18, wherein, The controller places the cold data block into the fourth subgroup.

20. The system according to claim 19, wherein, The controller stores the optimal read thresholds for the first subgroup and the second subgroup into a single-layer cell page.

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