A unified computing architecture and method based on quantum-classical ternary field

Abstract

The application discloses a kind of unified computing architecture and method based on quantum-classical ternary field, belong to quantum computing and computer architecture technical field.The architecture includes: quantum-classical unified field layer, for the computing resources of quantum state and classical state is mapped as a continuous ternary computing field;Ternary logic operation layer is connected with the quantum-classical unified field layer, using the three logic states of manifesting pole (+1), returning pole (-1) and operating central axis (0) to carry out unified logic operation to the data in the ternary computing field;Field balance control layer is connected with the ternary logic operation layer, and built-in single composite operation hardware module consisting of exponential operation, logarithmic operation and difference operation, for real-time monitoring the operation state deviation of the ternary computing field, and through closed loop feedback, the operation process converges to steady state.The application first unifies quantum state and classical state in a ternary field framework and carries out calculation, through the ternary collaborative mechanism of "manifesting pole execution, returning pole verification, operating central axis calibration", the seamless switching between quantum and classical two computing paradigms, collaborative operation and zeroing closed loop are realized, applicable to quantum-classical hybrid computing chip, all-optical computing system and next-generation general-purpose computing platform.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing and computer architecture technology, specifically relating to a method and architecture for computing in a unified ternary field framework that integrates quantum and classical states. It is applicable to quantum-classical hybrid computing chips, all-optical computing systems and next-generation general-purpose computing platforms. Background Technology

[0002] With the rapid development of quantum computing technology, quantum-classical hybrid computing has become a core path to practical quantum computing. However, existing quantum-classical hybrid computing schemes suffer from the following fundamental technical shortcomings: First, existing hybrid architectures are "cooperative" rather than "unified." Mainstream solutions (such as NVIDIA NVQLink, IBM Qiskit Runtime, and quantum-classical fusion computing units) all adopt a "cooperative" architecture: a classical processor and a quantum processor run independently, exchanging data and scheduling tasks through a high-speed interconnect. This approach essentially "stitches together" two different computing paradigms without changing their respective computational logic. The quantum processor still uses qubits and quantum gates, while the classical processor still uses binary logic gates. They only cooperate at the task level, without achieving true "unification" at the computational logic level. This leads to high quantum-classical data conversion overhead, complex system synchronization mechanisms, and severe limitations on overall computing performance due to interface bottlenecks.

[0003] Secondly, existing solutions lack dynamic balancing control over the computation process itself. Whether in purely classical or purely quantum computing, an imbalance in computational resources can arise between parallel divergent computation (such as quantum superposition expansion) and convergent verification (such as quantum error correction and state vector measurement). Existing hybrid computing architectures lack a built-in, unified field-level control mechanism to dynamically balance these two computational loads, often resulting in one end being overloaded while the other remains idle, thus reducing overall computational efficiency.

[0004] Third, quantum error correction is a recognized core challenge in this field. The physical qubit overhead required to build fault-tolerant quantum computers using traditional architectures such as surface codes is enormous, typically requiring thousands of physical qubits to achieve reliable computation for a single logical qubit. Therefore, how to preprocess or correct quantum states on NISQ (noisy medium-scale quantum) devices at the classical level to reduce the overhead requirements for physical qubits has become an independent technical problem in hybrid architecture design.

[0005] Therefore, a novel unified computing architecture is urgently needed to deeply integrate quantum and classical states at the computational logic level, constructing a unified "computational field" and achieving dynamic control of the computational process through a built-in field balancing mechanism. The technical concept of this invention is inspired by ancient Chinese numerology and combines modern quantum computing with classical computing techniques. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of existing technologies by providing a unified computing architecture and method based on the quantum-classical ternary field, in order to solve the problems of lack of uniformity at the computing logic level and lack of dynamic balance control mechanism in existing quantum-classical hybrid computing schemes.

[0007] To achieve the above objectives, the present invention provides the following technical solution: A unified computational method based on quantum-classical ternary field domains includes the following steps: S1: Quantum-Classical Unified Field Construction Steps — Map quantum state computing resources and classical state computing resources into a continuous ternary computing field, wherein each computing node in the ternary computing field simultaneously contains quantum state components and classical state components.

[0008] S2: Ternary Logic Operation Steps—Using three logic states—explicit pole (+1), hidden pole (-1), and operational axis (0)—unified logic operations are performed on the data in the ternary computation field. The explicit pole (+1) is responsible for performing parallel divergent computation in a quantum superposition-like state; the hidden pole (-1) is responsible for performing convergent verification in a classical deterministic state; and the operational axis (0) is responsible for coordinating the state switching and data synchronization between the explicit pole and the hidden pole.

[0009] S3: Field balance control step - Through a single composite operation consisting of exponential operation, logarithmic operation and difference operation, the operational state deviation value B between the manifest pole and the recessive pole is calculated in real time, and the allocation of operational resources is dynamically adjusted according to the deviation value, so that the entire ternary computational field operation process always approaches the preset steady-state benchmark.

[0010] Furthermore, the functional form of the single composite operation is: B = e^( |P_explicit - P_repository| ) -ln(Z_base). When B approaches zero, the optimal operational balance is achieved between the explicit pole and the repository pole; when B deviates from zero, the field balance control layer adjusts the allocation of operational resources according to the sign and magnitude of B.

[0011] Furthermore, the quantum superposition-like parallel divergent computation performed by the manifest pole uses a three-state logic code (-1, 0, +1) to replace the two-state superposition state (0, 1) of the traditional qubit, in order to improve the unit information density, and uses the computational resources of classical deterministic states to correct the quantum state of the NISQ device at the logic level.

[0012] This invention also provides a unified computing architecture for performing the above-described methods, comprising a quantum-classical unified field layer, a ternary logic operation layer, and a field balance control layer. The field balance control layer incorporates a single composite computing hardware module, and the response cycle of the entire hardware module does not exceed 50 microseconds. Detailed Implementation

[0013] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can refer to and implement it.

[0014] Example 1: Construction of the Quantum-Classical Unified Field Layer The quantum-classical unified field layer is the foundational layer of this architecture. It maps quantum-state computing resources and classical-state computing resources into a continuous ternary computing field. This ternary computing field is an abstract computing space in which each computing node simultaneously contains both quantum-state and classical-state components. The quantum-state components are implemented using qubits in the quantum processing unit (QPU), while the classical-state components are implemented using binary or ternary logic units in the classical processing unit (CPU / GPU).

[0015] The mapping between quantum state components and classical state components is achieved through a unified coding layer. This coding layer maps the state of a qubit (superposition state |ψ>= α|0>+ β|1>) to a ternary logic coding (-1, 0, +1) format, where: the ground state |0> corresponds to the hidden pole (-1), representing a deterministic convergent state; the ground state |1> corresponds to the manifest pole (+1), representing a deterministic divergent state; and when both α and β in the superposition state α|0>+ β|1> are non-zero, it corresponds to the operational axis (0), representing the dynamic equilibrium state between quantum and classical computing resources.

[0016] Through this mapping, quantum states and classical states acquire a unified logical expression within the same ternary computational field. Switching between quantum operations and classical operations does not require additional data format conversion; instead, it is directly accomplished through three-state logical encoding within a unified encoding layer.

[0017] Example 2: Implementation of ternary logic operations The ternary logic operation layer is the core computing layer of this architecture. It uses three logic states—explicit pole (+1), recessive pole (-1), and operational axis (0)—to perform unified logic operations on the data in the ternary computing field.

[0018] The explicit pole (+1) is responsible for performing parallel divergent computations quasi-quantum superposition. The explicit pole uses a three-state logic encoding (-1, 0, +1), with each three-state logic unit having an information capacity of log23 bits (approximately 1.585 bits), which is about 58.5% higher than traditional binary (1 bit) and traditional two-state quantum superposition (constrained by the Holevo bound, the information obtainable is no more than 1 bit), respectively. With the same number of logic encoding bits, the three-state logic unit can represent more information states and perform more complex computational tasks. Simultaneously, the explicit pole utilizes a multi-core parallel architecture to simulate the parallel processing capabilities of quantum superposition, distributing computational tasks across multiple parallel computing cores for synchronous processing, achieving an acceleration effect equivalent to quantum parallel computing.

[0019] The locator (-1) is responsible for performing convergent verification of classical deterministic states. The locator utilizes the computational resources of classical deterministic states to perform deterministic verification of the parallel computation results output by the explicit locator, including: consistency verification of the three-state encoded results output by the explicit locator; error correction processing of noisy intermediate states generated by quantum computing subtasks; and deterministic confirmation of the final computation results. At the logical level, the locator corrects the quantum states of the NISQ device: utilizing the redundancy characteristics of three-state encoding (each three-state logic unit can represent three states, but only two states are valid information), it converts random errors caused by quantum noise into detectable logical errors, which are then corrected by the locator's logic verification circuit. This reduces the error correction overhead of physical qubits after using the three-state logic encoding of this invention, and correspondingly increases the number of logical qubits that can be supported under the same conditions, thereby alleviating the excessive dependence on the number of physical qubits at the logical level.

[0020] The central axis (0) is responsible for coordinating the state switching and data synchronization between the explicit pole and the hidden pole. The central axis logic unit has a built-in high-speed data exchange matrix, which is used to transmit intermediate calculation results and verification feedback between the explicit pole and the hidden pole in real time. After the explicit pole completes a batch of parallel divergent calculations, it pushes the intermediate results to the high-speed data exchange matrix; the hidden pole pulls the intermediate results from the high-speed data exchange matrix, performs convergent verification, and pushes the verification results back to the high-speed data exchange matrix; the central axis determines whether to perform the next round of iterative calculation based on the verification results.

[0021] Example 3: Hardware Implementation of the Field Equilibrium Control Layer The field balance control layer is the core layer of this architecture. Its main body is a B-value calculation circuit composed of three cascaded stages: an exponential operation circuit, a logarithmic operation circuit, and a differential amplifier circuit.

[0022] Level 1: Deviation Calculation Circuit. The deviation calculation circuit receives the current computational load value P_explicit and the current computational load value P_returning from the explicit pole and the return pole of the ternary logic operation layer, and calculates the absolute deviation between them: ΔP = |P_explicit - P_returning|. The computational load value is defined as the ratio of the number of currently active computing tasks to the maximum number of parallel tasks for each pole, expressed as a percentage (0 to 100).

[0023] Level 2: CORDIC exponentiation circuit. It directly calculates e^ΔP at the hardware level using the Coordinate Rotation Digital Arithmetic (CORDIC) method. The CORDIC algorithm requires only addition, subtraction, and shift operations, eliminating the need for multipliers, making it suitable for implementation on FPGAs or application-specific integrated circuits (ASICs). The calculation precision is 32-bit floating-point precision.

[0024] Level 3: Look-up table logarithmic operation circuit. ln(Z_base) is calculated using a preset look-up table (LUT), where Z_base is the steady-state reference value of the ternary computation field (typically 1.0, ln(1.0) = 0).

[0025] Level 4: 32-bit fixed-point differential arithmetic circuit. Subtracting ln(Z_base) from e^ΔP yields the final field state deviation value B = e^ΔP - ln(Z_base). The entire hardware module has a delay of no more than 50 microseconds from receiving the computational load value to outputting the B value.

[0026] Meaning and control strategy of B value: (1) When B ≈ 0 (deviation less than ±0.1), the computational load between the explicit pole and the hidden pole is in a balanced state, the field balance control layer does not intervene, and the system maintains the current computational state. (2) When B>0.3 and continues to exceed the set period, the load of the explicit pole is higher than that of the hidden pole (excessive parallel divergent computation), the field balance control layer generates a "hidden pole tightening" instruction, which converts some of the parallel divergent computation tasks of the explicit pole into convergent verification tasks of the hidden pole. Specific measures include: lowering the clock frequency or working voltage of the parallel computation core of the explicit pole to bring the current computational load back to a reasonable range; or increasing the power consumption and thread budget of the hidden pole to make the overall resource allocation tend to be balanced. (3) When B < -0.3 and continues to exceed the set period, the load of the storage pole is higher than that of the explicit pole (over-convergence verification). The field balance control layer generates an "explicit activation" instruction to convert part of the verification task of the storage pole into a parallel divergent computing task of the explicit pole, thereby accelerating the feedback processing by enabling more parallel processing units.

[0027] Example 4: Application in quantum chemical simulation The objective computational task is to calculate the ground-state energy of a water molecule using a variable quantum eigenvalue solver (VQE).

[0028] In the initial stage, the explicit pole is allocated more computational resources to generate a large number of candidate quantum state parameters. As the computation progresses, the candidate parameters output by the explicit pole are passed to the hidden pole in batches. The hidden pole performs classical calculations of the energy expectation value and convergence verification for each candidate parameter.

[0029] The field balance control layer collects the load values ​​of the manifest and recessive poles in real time. In the early stage of iteration, the load of the manifest pole is high (P_manifestation ≈ 0.8), while the recessive pole is relatively idle (P_recessive ≈ 0.3), B ≈ e^0.5 - 0 ≈ 1.65; the field balance control layer triggers regulation, reducing the clock frequency of the manifest pole or increasing the processing threads of the recessive pole, so that the load gradually moves towards balance.

[0030] After about 50 iterations, the system enters dynamic equilibrium, with P_explicit ≈ 0.52, P_residual ≈ 0.48, B ≈ e^0.04 - 0 ≈ 0.04, and the value of B approaches zero, indicating that the system has reached its optimal computational efficiency.

[0031] Compared with traditional pure classical computing and pure quantum computing, the ternary field unified computing architecture of this invention can effectively reduce the overall computation time in quantum chemical simulations, while reducing the dependence on quantum computing resources.

[0032] Example 5: Application in multi-objective optimization problems Taking the bi-objective path optimization problem as an example, the explicit pole is responsible for generating multiple candidate path solutions in parallel, the hidden pole sorts and filters the candidate paths according to two objective functions (shortest path and lowest energy consumption), and the operational axis returns the filtered "elite solution set" to the explicit pole as the initial population for the next iteration.

[0033] The field balance control layer continuously adjusts the generation scale of the manifest poles and the screening efficiency of the return poles, so that the two maintain a load balance in each iteration, thereby accelerating the overall convergence. Beneficial effects

[0034] For the first time, quantum and classical states are unified in a ternary field framework at the computational logic level. The manifestation pole (+1) performs parallel divergent computation of quantum superposition-like state, the hidden pole (-1) performs convergent verification of classical deterministic state, and the operation axis (0) coordinates the state switching and data synchronization between the two. This achieves a fundamental unification of quantum-classical computing rather than a physical splicing.

[0035] By replacing the binary superposition state (0, 1) of traditional qubits with a three-state logic code (-1, 0, +1), the information capacity of each three-state logic unit can reach log23 bits, which is about 58.5% higher than that of traditional binary. Furthermore, by utilizing the computational resources of classical deterministic states to correct the quantum states of NISQ devices at the logic level, the overhead dependence of traditional fault-tolerant quantum computing on a huge number of physical qubits is reduced.

[0036] Through a single composite computing hardware module of the field balance control layer, the calculation and management of the operation state deviation value B are completed within a response period of no more than 50 microseconds, realizing real-time dynamic optimization of the entire ternary computing field operation process. The overall convergence speed of complex computing tasks such as multi-objective optimization can be improved.

[0037] This architecture is suitable for quantum-classical hybrid computing chips, all-optical computing systems, and next-generation general-purpose computing platforms, and has good architectural adaptability to different underlying physical implementation methods. Attached Figure Description

[0038] Figure 1 Overall architecture diagram of the unified quantum-classical ternary field computing architecture Figure 2 Schematic diagram of the internal structure of the ternary logic operation layer Figure 3 Hardware structure diagram of the field balance control layer Figure 4 Flowchart of field balance control.

Claims

1. A unified computational method based on quantum-classical ternary field domains, characterized in that, Includes the following steps: S1: Quantum-classical unified field construction steps—Map quantum state computing resources and classical state computing resources into a continuous ternary computing field, wherein each computing node in the ternary computing field simultaneously contains quantum state components and classical state components. S2: Ternary logic operation steps - using three logic states, namely, the explicit pole (+1), the hidden pole (-1), and the operational axis (0), to perform unified logic operations on the data in the ternary computation field; the explicit pole (+1) is responsible for performing parallel divergent computation in a quantum superposition-like state, the hidden pole (-1) is responsible for performing convergent verification in a classical deterministic state, and the operational axis (0) is responsible for coordinating the state switching and data synchronization between the explicit pole and the hidden pole; S3: Field balance control step - Through a single composite operation consisting of exponential operation, logarithmic operation and difference operation, the operational state deviation value B between the manifest pole and the hidden pole in the ternary computing field is calculated in real time, and the operational resource allocation of the manifest pole and the hidden pole is dynamically adjusted according to the deviation value B, so that the entire operation process of the ternary computing field always approaches the preset steady-state benchmark.

2. The method according to claim 1, characterized in that, The single composite operation described in step S3 adopts the following function: B = e^( |P_explicit - P_repository| ) - ln(Z_base), where P_explicit is the current computational load value of the explicit pole, P_repository is the current computational load value of the repository pole, and Z_base is the steady-state baseline value of the ternary computational field. When B approaches zero, the optimal computational balance is achieved between the explicit pole and the repository pole. When B deviates from zero, the field balance control layer adjusts the allocation of computational resources according to the sign and magnitude of B.

3. The method according to claim 2, characterized in that, When B > 0, the load on the explicit pole is higher than that on the hidden pole, and the parallel divergent computing task of part of the explicit pole is converted into the convergent verification task of the hidden pole; when B < 0, the load on the hidden pole is higher than that on the explicit pole, and the verification task of part of the hidden pole is converted into the parallel divergent computing task on the explicit pole.

4. The method according to claim 1, characterized in that, The quantum superposition-like parallel divergent computation performed by the explicit pole in step S2 uses a three-state logic code (-1, 0, +1) to replace the two-state superposition state (0, 1) of the traditional quantum bit. The information capacity of each three-state logic unit is log23 bits, and the quantum state of the noisy medium-scale quantum (NISQ) device is corrected at the logic level.

5. The method according to claim 1, characterized in that, In step S2, the state switching and data synchronization of the central axis (0) are achieved through a field balance controller at the hardware level. The state switching delay between the manifest pole (+1) and the return pole (-1) does not exceed the time limit determined by the response cycle of the single composite computing hardware module.

6. A unified computing architecture based on a quantum-classical ternary field, for executing the method of any one of claims 1 to 5, characterized in that, include: The quantum-classical unified field layer is used to map quantum state computing resources and classical state computing resources into a continuous ternary computing field. The ternary logic operation layer, connected to the quantum-classical unified field layer, includes an explicit pole logic unit (+1), a hidden pole logic unit (-1), and a dynamic central axis logic unit (0), which are used to perform unified logic operations on the data in the ternary computation field. The field balance control layer is connected to the ternary logic operation layer. It has a built-in single composite operation hardware module consisting of an exponential operation circuit, a logarithmic operation circuit, and a difference operation circuit. It is used to calculate the operation state deviation value B in real time and dynamically adjust the allocation of operation resources between the manifest pole and the storage pole according to the deviation value.

7. The unified computing architecture according to claim 6, characterized in that, In the single composite computing hardware module of the field balance control layer, the exponential operation circuit is implemented in hardware using a coordinate rotation digital calculation method, the logarithmic operation circuit is implemented in hardware using a lookup table, and the difference operation circuit is a 32-bit fixed-point operation circuit; the response period of the entire hardware module does not exceed 50 microseconds.

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