Display panel, detection method and display device

Abstract

The application provides a display panel, which comprises an auxiliary detection circuit, an array detection circuit and a screen body detection circuit; the auxiliary detection circuit is configured to comprise an auxiliary detection demultiplexing control line, an auxiliary detection input signal line and an auxiliary detection transistor; the auxiliary detection input signal line is connected to the array detection circuit through the auxiliary detection transistor; when the array detection circuit is abnormal, the array detection can be completed by opening the transistor in the array detection circuit and with the aid of the auxiliary detection circuit, so that the display panel is not scrapped due to the abnormality of the array detection circuit; meanwhile, the auxiliary detection circuit can be used to detect whether the circuit from the binding area to the screen body detection circuit is normal before the screen body detection, so that the cost is avoided due to the existence of the blind area of the screen body detection.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In the production and testing process of related display panels, the LED illumination test in the CT segment (Cell unit segment, assembly segment) can only identify signal breakage defects between the CT circuit and the AA display area. For trace breakage defects above the CT circuit, there is a detection blind spot, making it impossible to perform pre-testing and confirmation in the CT segment. As a result, CT unit screens with such defects still enter the module assembly process normally. After going through multiple processes in the module segment, the defects are detected, resulting in a large waste of related materials, labor and process costs in the module segment, increasing the manufacturing cost of display modules and reducing production efficiency. Therefore, how to eliminate the detection blind spot in the CT segment has become one of the problems that need to be solved to improve yield, production efficiency and reduce costs. Summary of the Invention

[0003] In view of this, the present invention provides a display panel to solve the problem of how to eliminate blind spots in CT segment detection.

[0004] In a first aspect, the present invention provides a display panel, the display panel including an auxiliary detection circuit, an array detection circuit, and a screen detection circuit; the array detection circuit includes: multiple demultiplexed control lines and multiple array detection transistor groups; the screen detection circuit includes: multiple selection signal lines, multiple screen detection transistor groups, and multiple input signal lines; wherein, the multiple demultiplexed control lines in the array detection circuit are electrically connected to the control terminal of each transistor in the corresponding multiple array detection transistor groups; the second terminal of each transistor in the multiple array detection transistor groups is electrically connected to the driving circuit of the corresponding display panel; the control terminal of each transistor in the multiple screen detection transistor groups is electrically connected to the corresponding selection signal line, the second terminal of each transistor in the multiple screen detection transistor groups is electrically connected to the driving circuit of the display panel, and the first terminal of each transistor in the multiple screen detection transistor groups is electrically connected to the corresponding input signal line; the auxiliary detection circuit is electrically connected to the first terminal of each transistor in the corresponding transistor group in the array detection circuit.

[0005] In conjunction with the first aspect, in some embodiments, the auxiliary detection circuit includes an auxiliary detection demultiplexing control line, an auxiliary detection input signal line, and an auxiliary detection transistor. The auxiliary detection demultiplexing control line is electrically connected to the control terminal of the auxiliary detection transistor, the auxiliary detection input signal line is electrically connected to the first terminal of the auxiliary detection transistor, and the second terminal of the auxiliary detection transistor is electrically connected to the first terminal of each transistor in the array detection circuit.

[0006] Furthermore, the array detection circuit includes multiple demultiplexing control lines, including a first demultiplexing control line, a second demultiplexing control line, a third demultiplexing control line, and a fourth demultiplexing control line, and multiple array detection transistor groups, including a first transistor group and a second transistor group. The first demultiplexing control line, the second demultiplexing control line, the third demultiplexing control line, and the fourth demultiplexing control line are electrically connected to the control terminals of the corresponding transistors in the first transistor group and the second transistor group, respectively.

[0007] Furthermore, the first transistor group includes a first transistor and a second transistor, the control terminal of the first transistor is electrically connected to a first demultiplexing control line, and the control terminal of the second transistor is electrically connected to a second demultiplexing control line.

[0008] Furthermore, the second transistor group includes a third transistor and a fourth transistor, with the control terminal of the third transistor electrically connected to the third demultiplexing control line and the control terminal of the fourth transistor electrically connected to the fourth demultiplexing control line.

[0009] In conjunction with the first aspect, in some embodiments, the above-mentioned display panel includes a plurality of arrayed display units, each display unit including red sub-pixels, blue sub-pixels and green sub-pixels.

[0010] Furthermore, the second terminal of the first transistor is electrically connected to the red and blue sub-pixels of the same column of display units, and the second terminal of the second transistor is electrically connected to the green sub-pixel of the same column of display units.

[0011] Preferably, there are multiple green sub-pixels in the same display unit.

[0012] In conjunction with the first aspect, in some embodiments, the multiple selection signal lines in the screen detection circuit include a first selection signal line, a second selection signal line, and a third selection signal line; the multiple screen detection transistor groups include a third transistor group, a fourth transistor group, and a fifth transistor group, and the first selection signal line, the second selection signal line, and the third selection signal line are electrically connected to the control terminals of the corresponding transistors in the third transistor group, the fourth transistor group, and the fifth transistor group, respectively.

[0013] Furthermore, the control terminals of the transistors in the third transistor group are electrically connected to the first selection signal line, the control terminals of the transistors in the fourth transistor group are electrically connected to the second selection signal line, and the control terminals of the transistors in the fifth transistor group are electrically connected to the third selection signal line.

[0014] In conjunction with the first aspect, in some embodiments, the above-mentioned display panel includes a plurality of arrayed display units, each display unit including a red sub-pixel, a blue sub-pixel, and a green sub-pixel; the multiple input signal lines in the screen detection circuit include a first input signal line, a second input signal line, and a third input signal line.

[0015] Furthermore, the third transistor group includes a fifth transistor and a sixth transistor. The second terminal of the fifth transistor is electrically connected to the red sub-pixel and the blue sub-pixel in the same column of display units; the second terminal of the sixth transistor is electrically connected to the red sub-pixel and the blue sub-pixel in another column of display units. The first selection signal line and the first input signal line are configured to select the red sub-pixel electrically connected to the third transistor group.

[0016] Furthermore, the fourth transistor group includes a seventh transistor and an eighth transistor. The second terminal of the seventh transistor is electrically connected to the red sub-pixel and the blue sub-pixel in the same column of display units; the second terminal of the eighth transistor is electrically connected to the red sub-pixel and the blue sub-pixel in another column of display units. The second selection signal line and the second input signal line are configured to select the blue sub-pixel electrically connected to the fourth transistor group.

[0017] Furthermore, the fifth transistor group includes a ninth transistor and a tenth transistor, the second terminal of the ninth transistor being electrically connected to a green sub-pixel in the same column of display units; the second terminal of the tenth transistor being electrically connected to a green sub-pixel in another column of display units, and the third selection signal line and the third input signal line being configured to select the green sub-pixel electrically connected to the fifth transistor group.

[0018] In conjunction with the first aspect, in some embodiments, the array detection circuit further includes pads, and the auxiliary detection circuit is connected to the array detection circuit through the pads.

[0019] Furthermore, the auxiliary detection circuit is configured such that when the array detection circuit is turned on, the auxiliary detection input signal line transmits a detection signal to the display unit, and when there is a break in the line, the display panel displays a bright line.

[0020] Secondly, the present invention provides a method for detecting a display panel provided in any of the above embodiments. The method includes: providing a first voltage to multiple selection signal lines, providing a 0-volt voltage to multiple input signal lines to turn off the screen detection circuit, wherein the first voltage is a voltage that turns off the transistors in the screen detection circuit; providing a second voltage to multiple demultiplexing control lines to turn on the array detection circuit, wherein the second voltage is a voltage that turns on the transistors in the array detection circuit; providing a third voltage to an auxiliary detection demultiplexing control line to turn on the auxiliary detection transistors; and inputting a detection signal to the auxiliary detection input signal line to detect whether there is a malfunction in the driving circuit of the display panel.

[0021] In conjunction with the second aspect, the detection method also includes, before the step of providing a second voltage to multiple demultiplexing control lines to turn on the array detection circuit, confirming whether the array detection circuit is unable to detect normally.

[0022] Thirdly, the present invention provides a display panel, which includes the display panel provided in any of the embodiments of the first aspect above, or includes a display panel that performs array detection by the detection method provided in any of the embodiments of the second aspect above.

[0023] This invention provides a display panel in which an auxiliary detection circuit is set to perform pre-detection of blind spots in the screen detection, ensuring that display panels with defects in the bonding area to the screen detection circuit area do not enter the module manufacturing process, and enabling the recycling of some display panels that cannot complete the array detection and are scrapped due to abnormal array detection circuits but do not affect the various performance indicators of the display panel, thereby improving yield, production efficiency and reducing costs.

[0024] It should be understood that the description in this section is not intended to identify key or important features of embodiments of the invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the display panel structure in related technologies;

[0027] Figure 2 This is a schematic diagram of the display panel structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the display panel-related detection circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the display panel-related detection circuit provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of another display panel-related detection circuit provided by an embodiment of the present invention; Figure 6 This is a schematic diagram of a portion of the pixel array of the display panel provided in an embodiment of the present invention; Figure 7 This is a partial structural schematic diagram of the display motherboard provided in an embodiment of the present invention; Figure 8 These are the detection method steps for a display panel based on the embodiments of the present invention. Figure 9This is a partial structural model diagram of a display device provided by the present invention.

[0028] Explanation of reference numerals in the attached figures: 10 - Display panel area; 20 - Non-display panel area 110 - Screen detection circuit 120 - Bonding area 130 - Array detection circuit; 140 - Auxiliary detection circuit T11 - First transistor; T12 - Second transistor T21 - Third transistor; T22 - Fourth transistor T31 - Fifth transistor; T32 - Sixth transistor T41 - Seventh transistor; T42 - Eighth transistor T51 - Ninth transistor; T52 - Tenth transistor T61 - Auxiliary Detection Transistor 100-Display Panel 200-Display device Detailed Implementation To enable those skilled in the art to better understand the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0029] As described in the background section, the display panel in the related technology, see reference. Figure 1 The display panel includes an AT circuit (array detection circuit) 130A and a CT circuit (screen detection circuit) 110A to detect defective panels generated during the manufacturing process. The display panel also includes a bonding area 120A. Among the defective panels that fail the AT test, some panels meet the performance standards due to AT circuit defects. Among the panels that pass the CT test, some panels enter the module process due to circuit defects in the bonding area, IC area, and other blind spots in the screen detection process, which lead to a large waste of materials, labor, and process costs in the module process, increasing the manufacturing cost of the display module and reducing production efficiency.

[0030] In view of this, the present invention provides a display panel, with reference to... Figure 2 The display panel includes an auxiliary detection circuit 140, an array detection circuit 130, and a screen detection circuit 110; Reference Figure 3The array detection circuit 130 includes multiple demultiplexed control lines and multiple array detection transistor groups; the screen detection circuit 110 includes multiple selection signal lines, multiple screen detection transistor groups, and multiple input signal lines; wherein, the multiple demultiplexed control lines in the array detection circuit 130 are electrically connected to the control terminal of each transistor in the corresponding multiple array detection transistor groups; the second terminal of each transistor in the multiple array detection transistor groups is electrically connected to the driving circuit of the corresponding display panel; the control terminal of each transistor in the multiple screen detection transistor groups is electrically connected to the corresponding selection signal line, the second terminal of each transistor in the multiple screen detection transistor groups is electrically connected to the driving circuit of the display panel, and the first terminal of each transistor in the multiple screen detection transistor groups is electrically connected to the corresponding input signal line; the auxiliary detection circuit 140 is electrically connected to the first terminal of each transistor in the corresponding transistor group in the array detection circuit 130; Figure 2 The display panel shown also includes a bonding area 120, which is located between the screen detection circuit 110 and the array detection circuit 130.

[0031] In conjunction with the first aspect, please continue to refer to the appendix. Figure 3 and attached Figure 4 In some embodiments, the auxiliary detection circuit 140 includes an auxiliary detection demultiplexing control line DMUX_5, an auxiliary detection input signal line D_RGB, and an auxiliary detection transistor T61. The auxiliary detection demultiplexing control line DMUX_5 is electrically connected to the control terminal of the auxiliary detection transistor T61, the auxiliary detection input signal line D_RGB is electrically connected to the first terminal of the auxiliary detection transistor T61, and the second terminal of the auxiliary detection transistor T61 is electrically connected to the first terminal of each transistor in the array detection circuit.

[0032] Optionally, the first terminal of the transistor is the drain electrode, and the second terminal of the transistor is the source electrode.

[0033] Specifically, please continue to refer to the appendix. Figure 4 The array detection circuit has multiple demultiplexing control lines, including a first demultiplexing control line DMUX_1, a second demultiplexing control line DMUX_2, a third demultiplexing control line DMUX_3, and a fourth demultiplexing control line DMUX_4. The array detection transistor groups include a first transistor group (T11, T12) and a second transistor group (T21, T22). The first demultiplexing control line DMUX_1, the second demultiplexing control line DMUX_2, the third demultiplexing control line DMUX_3, and the fourth demultiplexing control line DMUX_4 are electrically connected to the control terminals of the corresponding transistors in the first transistor group (T11, T12) and the second transistor group (T21, T22), respectively.

[0034] Specifically, please continue to refer to the appendix. Figure 4The first transistor group (T11, T12) includes a first transistor T11 and a second transistor T12. The control terminal of the first transistor T11 is electrically connected to the first demultiplexing control line DMUX_1, and the control terminal of the second transistor T12 is electrically connected to the second demultiplexing control line DMUX_2.

[0035] Further, please continue to refer to the appendix. Figure 4 The second transistor group (T21, T22) includes a third transistor and a fourth transistor. The control terminal of the third transistor is electrically connected to the third demultiplexing control line DMUX_3, and the control terminal of the fourth transistor is electrically connected to the fourth demultiplexing control line DMUX_4.

[0036] In conjunction with the above implementation methods, continue to refer to the appendix. Figure 4 In some embodiments, the display panel includes a plurality of arrayed display units, each display unit including a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G.

[0037] Further, refer to Figure 4 and Figure 6 The second terminal of the first transistor T11 is electrically connected to the red and blue sub-pixels of the same column of display units, and the second terminal of the second transistor T12 is electrically connected to the green sub-pixel of the same column of display units. Optionally, the pixel array can have various representations. Preferably, there are two green sub-pixels in the same display unit.

[0038] In conjunction with the above implementation methods, continue to refer to the appendix. Figure 4 In some embodiments, the multiple selection signal lines in the screen detection circuit 110 include a first selection signal line SW_1, a second selection signal line SW_2, and a third selection signal line SW_3; the multiple screen detection transistor groups include a third transistor group (T31, T32), a fourth transistor group (T41, T42), and a fifth transistor group (T51, T52), and the first selection signal line SW_1, the second selection signal line SW_2, and the third selection signal line SW_3 are electrically connected to the control terminals of the corresponding transistors in the third transistor group (T31, T32), the fourth transistor group (T41, T42), and the fifth transistor group (T51, T52), respectively.

[0039] Further, please continue to refer to the appendix. Figure 4 The control terminals of the transistors in the third transistor group (T31, T32) are electrically connected to the first selection signal line SW_1, the control terminals of the transistors in the fourth transistor group (T41, T42) are electrically connected to the second selection signal line SW_2, and the control terminals of the transistors in the fifth transistor group (T51, T52) are electrically connected to the third selection signal line SW_3.

[0040] In conjunction with the above embodiments, in some embodiments, the display panel includes a plurality of arrayed display units, each display unit including a red sub-pixel, a blue sub-pixel, and a green sub-pixel; the multiple input signal lines in the screen detection circuit 110 include a first input signal line D_R, a second input signal line D_B, and a third input signal line D_G.

[0041] Furthermore, the third transistor group (T31, T32) includes a fifth transistor T31 and a sixth transistor T32. The second terminal of the fifth transistor T31 is electrically connected to the red sub-pixel and the blue sub-pixel in the same column of display units; the second terminal of the sixth transistor T32 is electrically connected to the red sub-pixel and the blue sub-pixel in another column of display units. The first selection signal line SW_1 and the first input signal line D_R are configured to select the red sub-pixel electrically connected by the third transistor group (T31, T32).

[0042] Further, please continue to refer to the appendix. Figure 4 The fourth transistor group (T41, T42) includes a seventh transistor T41 and an eighth transistor T42. The second terminal of the seventh transistor T41 is electrically connected to the red and blue sub-pixels in the same column of display units. The second terminal of the eighth transistor T42 is electrically connected to the red and blue sub-pixels in another column of display units. The second selection signal line SW_2 and the second input signal line D_B are configured to select the blue sub-pixel electrically connected to the fourth transistor group (T41, T42).

[0043] Further, please continue to refer to the appendix. Figure 4 The fifth transistor group (T51, T52) includes a ninth transistor T51 and a tenth transistor T52. The second terminal of the ninth transistor T51 is electrically connected to a green sub-pixel in the same column of display units; the second terminal of the tenth transistor T52 is electrically connected to a green sub-pixel in another column of display units. The third selection signal line SW_3 and the third input signal line D_G are configured to select the green sub-pixel electrically connected to the fifth transistor group (T51, T52).

[0044] Furthermore, the auxiliary detection circuit 140 is configured such that when the array detection circuit is turned on, the auxiliary detection input signal line D_RGB transmits a detection signal to the display unit, and when there is a break in the line, the display panel displays a bright line.

[0045] In another embodiment of the present invention, the provided display panel is referenced. Figure 2 and Figure 5The system includes an auxiliary detection circuit 140, an array detection circuit 130, and a screen detection circuit 110. The array detection circuit 130 includes multiple pads 150, multiple demultiplexing control lines, and multiple array detection transistor groups. The screen detection circuit 110 includes multiple selection signal lines, multiple screen detection transistor groups, and multiple input signal lines. The multiple demultiplexing control lines in the array detection circuit 130 are electrically connected to the control terminals of each transistor in the corresponding multiple array detection transistor groups. The second terminals of the transistors in the multiple array detection transistor groups are all electrically connected to the driving circuit of the corresponding display panel. The control terminal of each transistor in the multiple screen detection transistor groups is electrically connected to the corresponding selection signal line, the second terminal of each transistor in the multiple screen detection transistor groups is electrically connected to the driving circuit of the display panel, and the first terminal of each transistor in the multiple screen detection transistor groups is electrically connected to the corresponding input signal line. The auxiliary detection circuit 140 is electrically connected to the first terminal of each transistor in the multiple array detection transistor groups via multiple pads 150.

[0046] In conjunction with the above implementation methods, please continue to refer to the appendix. Figure 5 In some embodiments, the auxiliary detection circuit 140 includes an auxiliary detection demultiplexing control line DMUX_5, an auxiliary detection input signal line D_RGB, and an auxiliary detection transistor T61. The auxiliary detection demultiplexing control line DMUX_5 is electrically connected to the control terminal of the auxiliary detection transistor T61, the auxiliary detection input signal line D_RGB is electrically connected to the first terminal of the auxiliary detection transistor T61, and the second terminal of the auxiliary detection transistor T61 is electrically connected to the first terminal of each transistor in the array detection circuit.

[0047] Optionally, the first terminal of the transistor is the drain electrode, and the second terminal of the transistor is the source electrode.

[0048] Specifically, please continue to refer to the appendix. Figure 5 The array detection circuit 130 has multiple demultiplexing control lines including a first demultiplexing control line DMUX_1, a second demultiplexing control line DMUX_2, a third demultiplexing control line DMUX_3, and a fourth demultiplexing control line DMUX_4. The array detection transistor groups include a first transistor group (T11, T12) and a second transistor group (T21, T22). The first demultiplexing control line DMUX_1, the second demultiplexing control line DMUX_2, the third demultiplexing control line DMUX_3, and the fourth demultiplexing control line DMUX_4 are electrically connected to the control terminals of the corresponding transistors in the first transistor group (T11, T12) and the second transistor group (T21, T22), respectively.

[0049] Specifically, please continue to refer to the appendix. Figure 5The first transistor group (T11, T12) includes a first transistor T11 and a second transistor T12. The control terminal of the first transistor T11 is electrically connected to the first demultiplexing control line DMUX_1, and the control terminal of the second transistor T12 is electrically connected to the second demultiplexing control line DMUX_2.

[0050] Further, please continue to refer to the appendix. Figure 5 The second transistor group (T21, T22) includes a third transistor and a fourth transistor. The control terminal of the third transistor is electrically connected to the third demultiplexing control line DMUX_3, and the control terminal of the fourth transistor is electrically connected to the fourth demultiplexing control line DMUX_4.

[0051] In conjunction with the above implementation methods, continue to refer to the appendix. Figure 5 In some embodiments, the display panel includes a plurality of arrayed display units, each display unit including a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G.

[0052] Further, refer to the appendix Figure 5 , Figure 6 The second terminal of the first transistor T11 is electrically connected to the red and blue sub-pixels of the same column of display units, and the second terminal of the second transistor T12 is electrically connected to the green sub-pixel of the same column of display units. Optionally, the pixel array of the display panel can have multiple representations; preferably, there are two green sub-pixels in the same display unit.

[0053] In conjunction with the above implementation methods, continue to refer to the appendix. Figure 4 In some embodiments, the multiple selection signal lines in the screen detection circuit 110 include a first selection signal line SW_1, a second selection signal line SW_2, and a third selection signal line SW_3; the multiple screen detection transistor groups include a third transistor group (T31, T32), a fourth transistor group (T41, T42), and a fifth transistor group (T51, T52), and the first selection signal line SW_1, the second selection signal line SW_2, and the third selection signal line SW_3 are electrically connected to the control terminals of the corresponding transistors in the third transistor group (T31, T32), the fourth transistor group (T41, T42), and the fifth transistor group (T51, T52), respectively.

[0054] Further, please continue to refer to the appendix. Figure 5 The control terminals of the transistors in the third transistor group (T31, T32) are electrically connected to the first selection signal line SW_1, the control terminals of the transistors in the fourth transistor group (T41, T42) are electrically connected to the second selection signal line SW_2, and the control terminals of the transistors in the fifth transistor group (T51, T52) are electrically connected to the third selection signal line SW_3.

[0055] In conjunction with the above embodiments, in some embodiments, the display panel includes a plurality of arrayed display units, each display unit including a red sub-pixel, a blue sub-pixel, and a green sub-pixel; the multiple input signal lines in the screen detection circuit 110 include a first input signal line D_R, a second input signal line D_B, and a third input signal line D_G.

[0056] Furthermore, the third transistor group (T31, T32) includes a fifth transistor T31 and a sixth transistor T32. The second terminal of the fifth transistor T31 is electrically connected to the red sub-pixel and the blue sub-pixel in the same column of display units; the second terminal of the sixth transistor T32 is electrically connected to the red sub-pixel and the blue sub-pixel in another column of display units. The first selection signal line SW_1 and the first input signal line D_R are configured to select the red sub-pixel electrically connected by the third transistor group (T31, T32).

[0057] Further, please continue to refer to the appendix. Figure 5 The fourth transistor group (T41, T42) includes a seventh transistor T41 and an eighth transistor T42. The second terminal of the seventh transistor T41 is electrically connected to the red and blue sub-pixels in the same column of display units. The second terminal of the eighth transistor T42 is electrically connected to the red and blue sub-pixels in another column of display units. The second selection signal line SW_2 and the second input signal line D_B are configured to select the blue sub-pixel electrically connected to the fourth transistor group (T41, T42).

[0058] Further, please continue to refer to the appendix. Figure 5 The fifth transistor group (T51, T52) includes a ninth transistor T51 and a tenth transistor T52. The second terminal of the ninth transistor T51 is electrically connected to a green sub-pixel in the same column of display units; the second terminal of the tenth transistor T52 is electrically connected to a green sub-pixel in another column of display units. The third selection signal line SW_3 and the third input signal line D_G are configured to select the green sub-pixel electrically connected to the fifth transistor group (T51, T52).

[0059] Furthermore, the auxiliary detection circuit 140 is configured such that when the array detection circuit 130 is turned on, the auxiliary detection input signal line D_RGB transmits a detection signal to the display unit, and when there is a break in the line, the display panel displays a bright line.

[0060] In conjunction with the above embodiments, a cutting area is provided between the array detection circuit 130 and the multiple pads 150, and the cutting area is cut after the display panel completes module assembly.

[0061] In conjunction with the above implementation methods, refer to Figure 7The present invention provides a display motherboard, which includes a display panel area and a non-display panel area, wherein the display panel area includes at least one display panel provided in the above embodiments.

[0062] Furthermore, during the fabrication of the display motherboard, the auxiliary detection circuit and the array detection circuit are completed under the same fabrication process.

[0063] Optionally, the display panel in the display motherboard may include multiple pads. The auxiliary detection circuit is connected to the array detection circuit through the pads. The auxiliary detection circuit and the pads are manufactured in the same process as the array detection circuit, without the need for additional process costs.

[0064] On the other hand, reference Figure 8 The present invention provides a method for detecting a display panel provided in any of the above embodiments, the method comprising: S100: Confirmed that the array detection circuit is no longer able to detect normally.

[0065] S200: Provides a first voltage to multiple selection signal lines and a 0 voltage signal to multiple input signal lines to turn off the screen detection circuit. The first voltage is the voltage that turns off the transistors in the screen detection circuit.

[0066] Optionally, the first voltage is +7V.

[0067] S300: Provides a second voltage to multiple demultiplexing control lines to turn on the array detection circuit. The second voltage is the voltage that turns on the transistors in the array detection circuit.

[0068] Optionally, the second voltage is -7V.

[0069] S400: Provides a third voltage to the auxiliary detection demultiplexing control line to turn on the auxiliary detection transistor; inputs a detection signal to the auxiliary detection input signal line to detect whether there is a malfunction in the display panel's driving circuit.

[0070] Optionally, the third voltage is -7V, and the auxiliary detection input signal line inputs a +8V detection signal.

[0071] This invention provides a display panel in which an auxiliary detection circuit is set to perform pre-detection of blind spots in the screen detection, ensuring that display panels with defects in the bonding area to the screen detection circuit area do not enter the module manufacturing process, and enabling the recycling of some display panels that cannot complete the array detection and are scrapped due to abnormal array detection circuits but do not affect the various performance indicators of the display panel, thereby improving yield, production efficiency and reducing costs.

[0072] In other embodiments of the present invention, a display device 200 is also provided, such as... Figure 9 As shown, the display device includes the display panel 100 provided in any embodiment of the present invention. Therefore, the display device provided in the embodiments of the present invention also has the beneficial effects described in any of the above embodiments. Figure 9 This is a schematic diagram of the structure of a display device 200 provided in an embodiment of the present invention, with reference to... Figure 9 The display device 200 is the application terminal of the display panel 100 provided by the present invention, and may include, but is not limited to, the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0073] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include, Auxiliary detection circuit, array detection circuit, and screen detection circuit; The array detection circuit includes: multiple demultiplexing control lines and multiple array detection transistor groups; the screen detection circuit includes: multiple selection signal lines, multiple screen detection transistor groups, and multiple input signal lines; wherein... The multiple demultiplexing control lines in the array detection circuit are electrically connected to the control terminal of each transistor in the corresponding multiple array detection transistor groups; the second terminal of each transistor in the multiple array detection transistor groups is electrically connected to the corresponding driving circuit of the display panel. The control terminal of each transistor in the plurality of screen detection transistor groups is electrically connected to the corresponding selection signal line, the second terminal of each transistor in the plurality of screen detection transistor groups is electrically connected to the driving circuit of the display panel, and the first terminal of each transistor in the plurality of screen detection transistor groups is electrically connected to the corresponding input signal line. The auxiliary detection circuit is electrically connected to the first terminal of each transistor in the corresponding plurality of array detection transistor groups.

2. The display panel according to claim 1, characterized in that, The auxiliary detection circuit includes an auxiliary detection demultiplexing control line, an auxiliary detection input signal line, and an auxiliary detection transistor. The auxiliary detection demultiplexing control line is electrically connected to the control terminal of the auxiliary detection transistor, the auxiliary detection input signal line is electrically connected to the first terminal of the auxiliary detection transistor, and the second terminal of the auxiliary detection transistor is electrically connected to the first terminal of each transistor in the array detection circuit.

3. The display panel according to claim 2, characterized in that, The array detection circuit includes a first demultiplexing control line, a second demultiplexing control line, a third demultiplexing control line, and a fourth demultiplexing control line. The array detection transistor groups include a first transistor group and a second transistor group. The first demultiplexing control line, the second demultiplexing control line, the third demultiplexing control line, and the fourth demultiplexing control line are electrically connected to the control terminals of the corresponding transistors in the first transistor group and the second transistor group, respectively. Preferably, the first transistor group includes a first transistor and a second transistor, wherein the control terminal of the first transistor is electrically connected to a first demultiplexing control line, and the control terminal of the second transistor is electrically connected to a second demultiplexing control line; Preferably, the second transistor group includes a third transistor and a fourth transistor, wherein the control terminal of the third transistor is electrically connected to a third demultiplexing control line, and the control terminal of the fourth transistor is electrically connected to a fourth demultiplexing control line.

4. The display panel according to claim 3, characterized in that, The display panel includes multiple arrayed display units, each display unit including red sub-pixels, blue sub-pixels, and green sub-pixels; The second terminal of the first transistor is electrically connected to the red and blue sub-pixels of the same column of the display unit, and the second terminal of the second transistor is electrically connected to the green sub-pixels of the same column of the display unit; Preferably, in the same display unit, there are multiple green sub-pixels.

5. The display panel according to claim 2, characterized in that, The multiple selection signal lines in the screen detection circuit include a first selection signal line, a second selection signal line, and a third selection signal line; the multiple screen detection transistor groups include a third transistor group, a fourth transistor group, and a fifth transistor group, and the first selection signal line, the second selection signal line, and the third selection signal line are electrically connected to the control terminals of the corresponding transistors in the third transistor group, the fourth transistor group, and the fifth transistor group, respectively. Preferably, the control terminals of the transistors in the third transistor group are electrically connected to the first selection signal line, the control terminals of the transistors in the fourth transistor group are electrically connected to the second selection signal line, and the control terminals of the transistors in the fifth transistor group are electrically connected to the third selection signal line.

6. The display panel according to claim 5, characterized in that, The display panel includes multiple arrayed display units, each display unit including red sub-pixels, blue sub-pixels, and green sub-pixels; the multiple input signal lines in the screen detection circuit include a first input signal line, a second input signal line, and a third input signal line; The third transistor group includes a fifth transistor and a sixth transistor. The second terminal of the fifth transistor is electrically connected to a red sub-pixel and a blue sub-pixel in the same column of display units. The second terminal of the sixth transistor is electrically connected to a red sub-pixel and a blue sub-pixel in another column of display units. The first selection signal line and the first input signal line are configured to select the red sub-pixel electrically connected to the third transistor group. The fourth transistor group includes a seventh transistor and an eighth transistor. The second terminal of the seventh transistor is electrically connected to a red sub-pixel and a blue sub-pixel in the same column of display units. The second terminal of the eighth transistor is electrically connected to a red sub-pixel and a blue sub-pixel in another column of display units. The second selection signal line and the second input signal line are configured to select the blue sub-pixel electrically connected to the fourth transistor group. The fifth transistor group includes a ninth transistor and a tenth transistor. The second terminal of the ninth transistor is electrically connected to a green sub-pixel in the same column of display units. The second terminal of the tenth transistor is electrically connected to a green sub-pixel in another column of display units. The third selection signal line and the third input signal line are configured to select the green sub-pixel electrically connected to the fifth transistor group.

7. The display panel according to any one of claims 3-5, characterized in that, The array detection circuit includes pads, and the auxiliary detection circuit is connected to the array detection circuit through the pads. The auxiliary detection circuit is configured such that when the array detection circuit is turned on, the auxiliary detection input signal line transmits a detection signal to the display unit, and when there is a break in the line, the display panel displays a bright line.

8. A method for detecting a display panel according to any one of claims 1-7, characterized in that, include, A first voltage is provided to the plurality of selection signal lines, and a 0-volt voltage is provided to the plurality of input signal lines to turn off the screen detection circuit. The first voltage is the voltage that turns off the transistors in the screen detection circuit. A second voltage is provided to the multiple demultiplexing control lines to turn on the array detection circuit. The second voltage is the voltage that turns on the transistors in the array detection circuit. A third voltage is provided to the auxiliary detection demultiplexing control line to turn on the auxiliary detection transistor; Input a detection signal to the auxiliary detection input signal line to detect whether there is a malfunction in the drive circuit of the display panel.

9. The detection method according to claim 8, characterized in that, Before the step of providing a second voltage to the multiple demultiplexing control lines to turn on the array detection circuit, it is confirmed whether the array detection circuit is unable to detect normally.

10. A display panel, characterized in that, Includes the display panel as described in any one of claims 1-7, or includes a display panel subjected to array detection by the detection method as described in claim 8 or 9.

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