Pixel circuit and driving method, display panel, and display device

Abstract

The pixel circuit and the driving method, the display panel and the display device provided by the embodiments of the present disclosure add a first reset circuit to the second electrode of the driving transistor, input different initialization voltages of the first initialization signal to the second electrode of the driving transistor through the first reset circuit in the refresh time period and the holding time period, so as to realize the differential setting of the voltage of the second electrode of the driving transistor in the refresh time period and the holding time period, and further realize the adjustable difference of the brightness and the chroma of the refresh area and the holding area, eliminate the split-screen phenomenon, and improve the picture quality effect.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to pixel circuits and driving methods, display panels, and display devices. Background Technology

[0002] Current partial refresh products reset the drain potential of the driving transistor in the refresh area of ​​the display screen after writing data voltage to ensure image quality. However, the refresh rate of the hold area is reduced, resulting in a difference in refresh rates between the hold area and the refresh area. For example, the refresh area may have a refresh rate of 120Hz, while the hold area may have a refresh rate of 1Hz. The pixel circuits used in partial refresh display in related technologies cannot independently correct the drain potential of the driving transistor in the hold area, leading to differences in brightness and color between the hold area and the refresh area, resulting in a split-screen phenomenon. Summary of the Invention

[0003] This disclosure provides a pixel circuit, including:

[0004] A driving transistor, wherein the first terminal of the driving transistor is used to couple to a first power supply voltage terminal, and the second terminal of the driving transistor is used to couple to a light-emitting device;

[0005] A data writing circuit, coupled to the first terminal of the driving transistor, is configured to input the data voltage of the data signal terminal into the first terminal of the driving transistor in response to a signal at the scan signal terminal.

[0006] A compensation circuit, coupled to the second and control terminals of the driving transistor, is configured to turn on the second and control terminals of the driving transistor in response to a signal at the compensation signal terminal.

[0007] A first reset circuit, coupled to the second terminal of the driving transistor, is configured to input a first initialization signal from the first initialization signal terminal to the second terminal of the driving transistor in response to a signal from the first reset control terminal.

[0008] During the refresh period, the first initialization signal input to the second terminal of the driving transistor has a first initialization voltage; during the hold period, the first initialization signal input to the second terminal of the driving transistor has a second initialization voltage, and the first initialization voltage is different from the second initialization voltage.

[0009] In some possible implementations, the first initialization voltage is less than the second initialization voltage.

[0010] In some possible implementations, the first reset circuit includes a first transistor;

[0011] The control electrode of the first transistor is coupled to the first reset control terminal, the first electrode of the first transistor is coupled to the first initialization signal terminal, and the second electrode of the first transistor is coupled to the second electrode of the driving transistor.

[0012] In some possible implementations, it also includes:

[0013] The second reset circuit, coupled to the first terminal of the driving transistor, is configured to input the second initialization signal from the second initialization signal terminal to the first terminal of the driving transistor in response to a signal from the second reset control terminal.

[0014] In some possible implementations, during the refresh time period, the second initialization signal input to the first terminal of the driving transistor has a third initialization voltage;

[0015] During the holding period, the second initialization signal input to the first terminal of the driving transistor has a fourth initialization voltage;

[0016] The third initialization voltage is different from the fourth initialization voltage.

[0017] In some possible implementations, the third initialization voltage is less than the fourth initialization voltage.

[0018] In some possible implementations, the second reset circuit includes a second transistor, the control terminal of which is coupled to the second reset control terminal, the first terminal of which is coupled to the second initialization signal terminal, and the second terminal of which is coupled to the first terminal of the driving transistor.

[0019] In some possible implementations, the first reset control terminal and the second reset control terminal are the same signal terminal.

[0020] In some possible implementations, it also includes:

[0021] A third reset circuit, coupled to the second terminal of the driving transistor, is configured to input a signal from the third initialization signal terminal into the second terminal of the driving transistor in response to a signal from the third reset control terminal.

[0022] In some possible implementations, the third reset circuit includes a third transistor, the control terminal of which is coupled to the third reset control terminal, the first terminal of which is coupled to the third initialization signal terminal, and the second terminal of which is coupled to the second terminal of the driving transistor.

[0023] In some possible implementations, it also includes:

[0024] A storage capacitor, wherein the first terminal of the storage capacitor is used to couple to the first power supply voltage terminal, and the second terminal of the storage capacitor is coupled to the control terminal of the driving transistor;

[0025] The fourth reset circuit, coupled to the first electrode of the light-emitting device, is configured to input the signal of the fourth initialization signal terminal into the first electrode of the light-emitting device in response to the signal of the fourth reset control terminal.

[0026] The fifth reset circuit, coupled to the second or control terminal of the driving transistor, is configured to input the signal of the fifth initialization signal terminal to the second or control terminal of the driving transistor in response to a signal at the fifth reset control terminal.

[0027] A first light-emitting control circuit is coupled between the first terminal of the driving transistor and the first power supply voltage terminal, and is configured to input the signal from the first power supply voltage terminal into the first terminal of the driving transistor in response to the signal from the first light-emitting control terminal.

[0028] The second light-emitting control circuit, coupled between the second terminal of the driving transistor and the light-emitting device, is configured to conduct the second terminal of the driving transistor and the light-emitting device in response to a signal from the second light-emitting control terminal.

[0029] In some possible implementations, the fourth reset circuit includes a fourth transistor, the control terminal of which is coupled to the fourth reset control terminal, the first terminal of which is coupled to the fourth initialization signal terminal, and the second terminal of which is coupled to the first terminal of the light-emitting device; or...

[0030] The fifth reset circuit includes a fifth transistor, the control electrode of which is coupled to the fifth reset control terminal, the first electrode of which is coupled to the fifth initialization signal terminal, and the second electrode of which is coupled to the second electrode or control electrode of the driving transistor; or...

[0031] The first light-emitting control circuit includes a first light-emitting control transistor, the control electrode of the first light-emitting control transistor is coupled to the first light-emitting control terminal, the first electrode of the first light-emitting control transistor is coupled to the first power supply voltage terminal, and the second electrode of the first light-emitting control transistor is coupled to the first electrode of the driving transistor; or...

[0032] The second light-emitting control circuit includes a second light-emitting control transistor, the control electrode of the second light-emitting control transistor is coupled to the second light-emitting control terminal, the first electrode of the second light-emitting control transistor is coupled to the second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is coupled to the first electrode of the light-emitting device.

[0033] In some possible implementations, the third reset control terminal and the fourth reset control terminal are the same signal terminal.

[0034] In some possible implementations, it also includes:

[0035] The sixth reset circuit, coupled to the first terminal of the driving transistor, is configured to input the signal of the sixth initialization signal terminal into the first terminal of the driving transistor in response to a signal from the sixth reset control terminal.

[0036] In some possible implementations, the sixth reset circuit includes a sixth transistor, the control terminal of which is coupled to the sixth reset control terminal, the first terminal of which is coupled to the sixth initialization signal terminal, and the second terminal of which is coupled to the first terminal of the driving transistor.

[0037] This disclosure also provides a driving method for driving the aforementioned pixel circuit, comprising:

[0038] The pixel circuit operates in each display frame, which includes a refresh time period and a hold time period.

[0039] The refresh time period includes:

[0040] During the data writing phase, the data writing circuit responds to the signal at the scan signal terminal by inputting the data voltage at the data signal terminal into the first terminal of the driving transistor; the compensation circuit responds to the signal at the compensation signal terminal by turning on the control terminal and the second terminal of the driving transistor.

[0041] During the reset phase, the first reset circuit responds to the signal at the first reset control terminal by inputting the first initialization signal at the first initialization signal terminal to the second terminal of the driving transistor; wherein, the first initialization signal input by the first reset circuit to the second terminal of the driving transistor has a first initialization voltage;

[0042] During the light-emitting stage, the driving transistor drives the light-emitting device to emit light;

[0043] The duration of the hold includes:

[0044] During the reset phase, the first reset circuit responds to the signal at the first reset control terminal by inputting a first initialization signal from the first initialization signal terminal to the second terminal of the driving transistor; wherein the first initialization signal input by the first reset circuit to the second terminal of the driving transistor has a second initialization voltage, and the first initialization voltage is different from the second initialization voltage.

[0045] During the light-emitting stage, the driving transistor drives the light-emitting device to emit light.

[0046] In some possible implementations, the first initialization voltage is less than the second initialization voltage.

[0047] In some possible implementations, the refresh time period, including the reset phase, further includes:

[0048] In response to the signal at the second reset control terminal, the second reset circuit inputs the second initialization signal at the second initialization signal terminal to the first terminal of the driving transistor; wherein, the second initialization signal input by the second reset circuit to the first terminal of the driving transistor has a third initialization voltage;

[0049] The reset phase included in the holding time period also includes:

[0050] The second reset circuit responds to the signal at the second reset control terminal by inputting a second initialization signal from the second initialization signal terminal to the first terminal of the driving transistor; wherein the second initialization signal input by the second reset circuit to the first terminal of the driving transistor has a fourth initialization voltage, and the third initialization voltage is different from the fourth initialization voltage.

[0051] In some possible implementations, the third initialization voltage is less than the fourth initialization voltage.

[0052] This disclosure also provides a display panel including a plurality of the aforementioned pixel circuits.

[0053] In some possible implementations, the display panel includes multiple first initialization signal lines, with a first initialization signal terminal in a column of pixel circuits coupled to one of the first initialization signal lines; or,

[0054] The display panel includes multiple second initialization signal lines, with the second initialization signal terminal in a column of pixel circuits coupled to one of the second initialization signal lines; or...

[0055] The display panel includes a third initialization signal line, and the third initialization signal terminal in any pixel circuit is coupled to the third initialization signal line.

[0056] In some possible implementations, the system further includes multiple first gate lines and a first gate driving circuit coupled to the multiple first gate lines, wherein the first gate driving circuit includes a plurality of cascaded first shift register units; wherein,

[0057] The input signal terminal of the first shift register unit of the first stage is coupled to the first frame trigger signal terminal;

[0058] The signal output terminal of the first shift register unit of the nth stage is coupled to the input signal terminal of the first shift register unit of the (n+m)th stage. The signal output terminal of the first shift register unit of the nth stage is coupled to the first reset control terminal in the pixel circuit of the i-th row through a first gate line; where m, n, and i are all positive integers.

[0059] In some possible implementations, the signal output terminal of the nth stage first shift register unit is also coupled to the second reset control terminal in the xth row pixel circuit via a first gate line; where x is a positive integer.

[0060] In some possible implementations, the first gate line coupled to the first reset control terminal and the second reset control terminal in a row pixel circuit is the same.

[0061] In some possible implementations, the system further includes multiple second gate lines and a second gate drive circuit coupled to the multiple second gate lines, the second gate drive circuit including a plurality of cascaded second shift register units; wherein,

[0062] The input signal terminal of the first-stage second shift register unit is coupled to the second frame trigger signal terminal;

[0063] The signal output terminal of the second shift register unit of the nth stage is coupled to the input signal terminal of the second shift register unit of the (n+j)th stage. The signal output terminal of the second shift register unit of the nth stage is coupled to the third reset control terminal in the pixel circuit of the kth row through a second gate line; where n, j, and k are all positive integers.

[0064] This disclosure also provides a display device, including the display panel described above. Attached Figure Description

[0065] Figures 1 to 13 Some schematic diagrams of pixel circuits provided in the embodiments of this disclosure;

[0066] Figure 14 Some structural schematic diagrams of the display panel provided in the embodiments of this disclosure;

[0067] Figure 15 Some timing diagrams of the first initialization signal and the second initialization signal provided in the embodiments of this disclosure;

[0068] Figure 16 Further structural schematic diagrams of the display panel provided in embodiments of this disclosure;

[0069] Figures 17 to 19 Some signal timing diagrams of the pixel circuit provided in the embodiments of this disclosure. Detailed Implementation

[0070] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0071] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0072] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual scale and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0073] Typically, a display panel may include multiple pixel units, each pixel unit including pixel circuitry. For example, the pixel circuitry may include transistors, capacitors, and light-emitting devices, with the transistors and capacitors working together to drive the light-emitting devices to emit light.

[0074] For example, the light-emitting device may include: organic light-emitting diode (OLED), quantum dot light-emitting diode (QLED), micro light-emitting diode (Micro LED), and mini light-emitting diode (Mini LED).

[0075] For example, such as Figure 1As shown, the pixel circuit may include an 8T1C circuit, specifically including: at least one of initialization transistors M1, M7, and M8; a compensation transistor M2; a driving transistor M3; a data writing transistor M4; light-emitting control transistors M5 and M6; and a storage capacitor Cs. Specifically, the control electrode of the initialization transistor M1 is coupled to the first reset control terminal Reset1, its first electrode is coupled to the first initialization signal terminal Vint1, and its second electrode is coupled to the third node N3. The control electrode of the scanning transistor M2 is coupled to the compensation signal terminal Gate_N, its first electrode is coupled to the first node N1, and its second electrode is coupled to the third node N3. The control electrode of the driving transistor M3 is coupled to the first node N1, its first electrode is coupled to the second node N2, and its second electrode is coupled to the third node N3. The control electrode of the data writing transistor M4 is coupled to the scanning signal terminal Gate_P, its first electrode is coupled to the data signal terminal Data, and its second electrode is coupled to the second node N2. The control electrode of the light-emitting control transistor M5 is coupled to the light-emitting control terminal EM, its first electrode is coupled to the first power supply voltage terminal VDD, and its second electrode is coupled to the second node N2. The control electrode of the light-emitting control transistor M6 is coupled to the light-emitting control terminal EM, its first electrode is coupled to the third node N3, and its second electrode is coupled to the first electrode of the light-emitting device P. The control electrode of the initialization transistor M7 is coupled to the second reset control terminal Reset2, its first electrode is coupled to the second initialization signal terminal Vint2, and its second electrode is coupled to the first electrode of the light-emitting device P. The control electrode of the initialization transistor M8 is coupled to the third reset control terminal Reset3, its first electrode is coupled to the third initialization signal terminal Vint3, and its second electrode is coupled to the second node N2. The first electrode of the storage capacitor Cs is coupled to the first power supply voltage terminal VDD, and its second electrode is coupled to the first node N1. The second electrode of the light-emitting device P is coupled to the second power supply voltage terminal VSS.

[0076] For example, the initialization transistor M1 is turned on under the control of the valid level of the signal at the first reset control terminal Reset1, and turned off under the control of the invalid level of the signal at the first reset control terminal Reset1. Optionally, as Figure 1 As shown, the initialization transistor M1 can be set to a P-type transistor, in which case the effective level of the signal at the first reset control terminal Reset1 is low, and the ineffective level is high. Alternatively, the initialization transistor M1 can be set to an N-type transistor, in which case the effective level of the signal at the first reset control terminal Reset1 is high, and the ineffective level is low.

[0077] For example, the compensation transistor M2 is turned on when the signal at the compensation signal terminal Gate_N is active, and turned off when the signal at the compensation signal terminal Gate_N is inactive. Optionally, as... Figure 1As shown, the compensation transistor M2 can be set as a P-type transistor, in which case the effective level of the signal at the compensation signal terminal Gate_N is low, and the ineffective level is high. Alternatively, the compensation transistor M2 can be set as an N-type transistor, in which case the effective level of the signal at the compensation signal terminal Gate_N is high, and the ineffective level is low.

[0078] For example, the driving transistor M3 is turned on under the control of an active signal level of the first node N1, and turned off under the control of an inactive signal level of the first node N1. Optionally, as Figure 1 As shown, the driving transistor M3 can be set as a P-type transistor, in which case the effective level of the signal at the first node N1 is low and the ineffective level is high. Alternatively, the driving transistor M3 can be set as an N-type transistor, in which case the effective level of the signal at the first node N1 is high and the ineffective level is low.

[0079] For example, the data write transistor M4 is turned on when the signal at the scan signal terminal Gate_P is active, and turned off when the signal at the scan signal terminal Gate_P is inactive. Optionally, as... Figure 1 As shown, the data write transistor M4 can be set as a P-type transistor, in which case the effective level of the Gate_P signal is low and the invalid level is high. Alternatively, the data write transistor M4 can be set as an N-type transistor, in which case the effective level of the Gate_P signal is high and the invalid level is low.

[0080] For example, the light-emitting control transistor M5 is turned on under the control of an active signal level at the light-emitting control terminal EM, and turned off under the control of an inactive signal level at the light-emitting control terminal EM. Optionally, as... Figure 1 As shown, the light-emitting control transistor M5 can be set as a P-type transistor, in which case the effective level of the signal at the light-emitting control terminal EM is low, and the ineffective level is high. Alternatively, the light-emitting control transistor M5 can be set as an N-type transistor, in which case the effective level of the signal at the light-emitting control terminal EM is high, and the ineffective level is low.

[0081] For example, the light-emitting control transistor M6 is turned on under the control of an active signal level at the light-emitting control terminal EM, and turned off under the control of an inactive signal level at the light-emitting control terminal EM. Optionally, as... Figure 1 As shown, the light-emitting control transistor M6 can be set as a P-type transistor, in which case the effective level of the signal at the light-emitting control terminal EM is low, and the ineffective level is high. Alternatively, the light-emitting control transistor M6 can be set as an N-type transistor, in which case the effective level of the signal at the light-emitting control terminal EM is high, and the ineffective level is low.

[0082] For example, the initialization transistor M7 is turned on under the control of the valid level of the signal at the second reset control terminal Reset2, and turned off under the control of the invalid level of the signal at the second reset control terminal Reset2. Optionally, as Figure 1 As shown, the initialization transistor M7 can be set to a P-type transistor, in which case the effective level of the signal at the second reset control terminal Reset2 is low, and the ineffective level is high. Alternatively, the initialization transistor M7 can be set to an N-type transistor, in which case the effective level of the signal at the second reset control terminal Reset2 is high, and the ineffective level is low.

[0083] For example, the initialization transistor M8 is turned on under the control of the active level of the signal at the third reset control terminal Reset3, and turned off under the control of the inactive level of the signal at the third reset control terminal Reset3. Optionally, as Figure 1 As shown, the initialization transistor M8 can be set to a P-type transistor, in which case the effective level of the signal at the third reset control terminal Reset3 is low, and the ineffective level is high. Alternatively, the initialization transistor M8 can be set to an N-type transistor, in which case the effective level of the signal at the third reset control terminal Reset3 is high, and the ineffective level is low.

[0084] For example, the voltages of the signals at the first initialization signal terminal Vint1, the second initialization signal terminal Vint2, and the third initialization signal terminal Vint3 can be positive or negative voltages.

[0085] In some embodiments of this disclosure, the first power supply voltage terminal VDD can be loaded with a constant first power supply voltage, and the first power supply voltage is generally positive. The second power supply voltage terminal VSS can be configured to load a constant second power supply voltage, and the second power supply voltage is generally ground voltage or a negative value. In practical applications, the specific values ​​of the first and second power supply voltages can be designed and determined according to the actual application environment, and are not limited thereto.

[0086] In some embodiments of this disclosure, the first terminal of the transistor can be used as its source and the second terminal as its drain, depending on the type of the transistor and the signal received by its control terminal; or, conversely, the first terminal of the transistor can be used as its drain and the second terminal as its source. This can be designed and determined according to the actual application environment, and no specific distinction is made here.

[0087] The above are merely examples illustrating the specific structure of the pixel circuit provided in the embodiments of this disclosure. In specific implementations, the pixel circuit is not limited to the structure provided in the embodiments of this disclosure, but may also be other structures known to those skilled in the art. These are all within the protection scope of this disclosure and are not specifically limited here.

[0088] Current partial refresh products, for the refresh area on the display screen, such as... Figure 1 As shown, after writing the data voltage, the pixel circuit resets the potential of the third node N3 to ensure image quality. However, the refresh rate of the hold area is decreasing, resulting in a difference in refresh rates between the hold area and the refresh area. For example, the refresh rate may be 1Hz in the hold area and 120Hz in the refresh area. The pixel circuit performing partial refresh display cannot independently correct the potential of the third node N3 in the hold area, causing the driving transistor to become biased. This affects the stability of the current supplied to the light-emitting device, leading to differences in brightness and color between the hold area and the refresh area, resulting in a split-screen phenomenon.

[0089] To address the aforementioned issues, the pixel circuit provided in this embodiment adds a first reset circuit to the drain of the driving transistor. During the refresh and hold periods, the first reset circuit inputs different initialization voltages of the first initialization signal to the second terminal of the driving transistor, thereby achieving differentiated voltage settings for the drain of the driving transistor during the hold and refresh periods. This enables adjustable brightness and chromaticity differences between the refresh and hold areas, eliminates screen splitting, and improves image quality.

[0090] In the embodiments disclosed herein, such as Figure 2 As shown, the pixel circuit may include:

[0091] The first terminal of the driving transistor 1 is used to couple to the first power supply voltage terminal VDD, and the second terminal of the driving transistor 1 is used to couple to the light-emitting device P.

[0092] The data writing circuit 2, coupled to the first terminal of the driving transistor 1, is configured to input the data voltage of the data signal terminal Data into the first terminal of the driving transistor 1 in response to the signal of the scan signal terminal Gate_P.

[0093] The compensation circuit 3, coupled to the second and control terminals of the driving transistor 1, is configured to turn on the second and control terminals of the driving transistor 1 in response to the signal at the compensation signal terminal Gate_N.

[0094] The first reset circuit 4 is coupled to the second terminal of the driving transistor 1 and is configured to input the first initialization signal of the first initialization signal terminal Vint_F1 into the second terminal of the driving transistor 1 in response to the signal of the first reset control terminal Reset_F1.

[0095] During the refresh period, the first initialization signal of the second electrode of the input driving transistor 1 has a first initialization voltage vint1; during the hold period, the first initialization signal of the second electrode of the input driving transistor 1 has a second initialization voltage vint2, and the first initialization voltage vint1 and the second initialization voltage vint2 are different.

[0096] The pixel circuit provided in this embodiment adds a first reset circuit to the second electrode of the driving transistor. The first reset circuit inputs different initialization voltages of the first initialization signal to the second electrode of the driving transistor during the refresh time period and the hold time period, respectively, so as to realize the differential setting of the voltage of the second electrode of the driving transistor during the hold time period and the refresh time period. This enables the brightness and color difference between the refresh area and the hold area to be adjustable, eliminates the split screen phenomenon, and improves the image quality.

[0097] For example, the voltage value of the first initialization signal at the first initialization signal terminal Vint_F1 is positive.

[0098] In the pixel circuit provided in the embodiments of this disclosure, the first initialization voltage vint1 is less than the second initialization voltage vint2. For example, the first initialization voltage vint1 is 1V and the second initialization voltage vint2 is 5V.

[0099] In the pixel circuit provided in the embodiments of this disclosure, such as Figure 3 As shown, it also includes:

[0100] The second reset circuit 5, coupled to the first terminal of the driving transistor 1, is configured to input the second initialization signal of the second initialization signal terminal Vint_F2 into the first terminal of the driving transistor 1 in response to the signal of the second reset control terminal Reset_F2.

[0101] For example, the voltage value of the second initialization signal at the second initialization signal terminal Vint_F2 is positive.

[0102] In the pixel circuit provided in the embodiments of this disclosure, during the refresh time period, the second initialization signal of the first pole of the input driving transistor 1 has a third initialization voltage vint3;

[0103] During the holding period, the second initialization signal of the first pole of the input drive transistor 1 has a fourth initialization voltage vint4;

[0104] The third initialization voltage, vint3, is different from the fourth initialization voltage, vint4.

[0105] In the pixel circuit provided in the embodiments of this disclosure, the third initialization voltage vint3 is less than the fourth initialization voltage vint4. For example, the third initialization voltage vint3 is 1V and the fourth initialization voltage vint4 is 3V.

[0106] The pixel circuit provided in this embodiment adds a second reset circuit to the first electrode of the driving transistor. The second reset circuit inputs different initialization voltages of the second initialization signal to the first electrode of the driving transistor during the refresh time period and the hold time period, respectively, so as to realize the differential setting of the voltage of the first electrode of the driving transistor during the hold time period and the refresh time period. This enables the brightness and chromaticity differences between the refresh area and the hold area to be adjustable, eliminates the split-screen phenomenon, and improves the image quality.

[0107] For example, the first reset control terminal Reset_F1 and the second reset control terminal Reset_F2 are the same signal terminal.

[0108] In the pixel circuit provided in the embodiments of this disclosure, such as Figure 4 , Figure 5 As shown, it also includes:

[0109] The third reset circuit 6, coupled to the second terminal of the driving transistor 1, is configured to input the signal of the third initialization signal terminal Vint_F3 into the second terminal of the driving transistor 1 in response to the signal of the third reset control terminal Reset_F3.

[0110] The pixel circuit provided in this embodiment of the present disclosure, by adding a third reset circuit to the second terminal of the driving transistor, can reset the second terminal of the driving transistor by inputting the signal of the third initialization signal terminal to the second terminal of the driving transistor after the data voltage is written, thereby ensuring image quality.

[0111] For example, the voltage value of the signal at the third initialization signal terminal Vint_F3 is positive.

[0112] In the pixel circuit provided in the embodiments of this disclosure, such as Figures 6 to 9 As shown, it also includes:

[0113] Storage capacitor Cs, the first terminal of storage capacitor Cs is used to couple to the first power supply voltage terminal VDD, and the second terminal of storage capacitor Cs is coupled to the control terminal of driving transistor 1.

[0114] The fourth reset circuit 7, coupled to the first pole of the light-emitting device P, is configured to input the signal of the fourth initialization signal terminal Vint_F4 into the first pole of the light-emitting device P in response to the signal of the fourth reset control terminal Reset_F4.

[0115] The fifth reset circuit 8, coupled to the second or control terminal of the driving transistor 1, is configured to input the signal of the fifth initialization signal terminal Vint_F5 into the second or control terminal of the driving transistor 1 in response to the signal of the fifth reset control terminal Reset_F5.

[0116] The first light-emitting control circuit 9 is coupled between the first terminal of the driving transistor 1 and the first power supply voltage terminal VDD, and is configured to input the signal of the first power supply voltage terminal VDD into the first terminal of the driving transistor 1 in response to the signal of the first light-emitting control terminal EM1.

[0117] The second light-emitting control circuit 10 is coupled between the second terminal of the driving transistor 1 and the light-emitting device P, and is configured to conduct the second terminal of the driving transistor 1 and the light-emitting device P in response to the signal of the second light-emitting control terminal EM2.

[0118] The pixel circuit provided in this embodiment of the present disclosure, under the control of the signal of the fourth reset control terminal by the fourth reset circuit, inputs the signal of the fourth initialization signal terminal to the first electrode of the light-emitting device to clear the residual charge of the first electrode of the light-emitting device, and under the control of the signal of the fifth reset control terminal by the fifth reset circuit, inputs the signal of the fifth initialization signal terminal to the second electrode or control electrode of the driving transistor to clear the residual charge of the second electrode or control electrode of the driving transistor, so that the driving transistor can be turned on when the data writing stage begins.

[0119] For example, the third reset control terminal Reset_F3 and the fourth reset control terminal Reset_F4 are the same signal terminal.

[0120] For example, the first light-emitting control terminal EM1 and the second light-emitting control terminal EM2 are the same signal terminal.

[0121] In the pixel circuit provided in the embodiments of this disclosure, such as Figure 10 As shown, it also includes:

[0122] The sixth reset circuit 11, coupled to the first terminal of the driving transistor 1, is configured to input the signal of the sixth initialization signal terminal Vint_F6 into the first terminal of the driving transistor 1 in response to the signal of the sixth reset control terminal Reset_F6.

[0123] For example, the third reset control terminal Reset_F3, the fourth reset control terminal Reset_F4, and the sixth reset control terminal Reset_F6 are the same signal terminal.

[0124] The pixel circuit provided in this embodiment of the present disclosure, under the control of the signal of the sixth reset control terminal by the sixth reset circuit, inputs the signal of the sixth initialization signal terminal to the first terminal of the driving transistor, so as to reset the first terminal of the driving transistor after the data voltage is written to the first terminal of the driving transistor, thereby improving the hysteresis phenomenon of the driving transistor and enhancing the display effect.

[0125] In the pixel circuit provided in the embodiments of this disclosure, such as Figures 11 to 13 As shown, the data writing circuit 2 may include a data writing transistor M2. The control terminal of the data writing transistor M2 is coupled to the scan signal terminal Gate_P, the first terminal of the data writing transistor M2 is coupled to the data signal terminal Data, and the second terminal of the data writing transistor M2 is coupled to the first terminal of the driving transistor M1.

[0126] The compensation circuit 3 may include a compensation transistor M3. The control terminal of the compensation transistor M3 is coupled to the compensation signal terminal Gate_N. The first terminal of the compensation transistor M3 is coupled to the second terminal of the driving transistor M1. The second terminal of the compensation transistor M3 is coupled to the control terminal of the driving transistor M1.

[0127] The first reset circuit 4 may include a first transistor T1, the control terminal of the first transistor T1 is coupled to the first reset control terminal Reset_F1, the first terminal of the first transistor T1 is coupled to the first initialization signal terminal Vint_F1, and the second terminal of the first transistor T1 is coupled to the second terminal of the driving transistor M1.

[0128] The second reset circuit 5 may include a second transistor T2, the control terminal of the second transistor T2 is coupled to the second reset control terminal Reset_F2, the first terminal of the second transistor T2 is coupled to the second initialization signal terminal Vint_F2, and the second terminal of the second transistor T2 is coupled to the first terminal of the driving transistor M1.

[0129] The third reset circuit 6 may include a third transistor T3. The control terminal of the third transistor T3 is coupled to the third reset control terminal Reset_F3. The first terminal of the third transistor T3 is coupled to the third initialization signal terminal Vint_F3. The second terminal of the third transistor T3 is coupled to the second terminal of the driving transistor M1.

[0130] The fourth reset circuit 7 may include a fourth transistor T4, the control terminal of the fourth transistor T4 is coupled to the fourth reset control terminal Reset_F4, the first terminal of the fourth transistor T4 is coupled to the fourth initialization signal terminal Vint_F4, and the second terminal of the fourth transistor T4 is coupled to the first terminal of the light-emitting device P.

[0131] The fifth reset circuit 8 may include a fifth transistor T5. The control electrode of the fifth transistor T5 is coupled to the fifth reset control terminal Reset_F5. The first electrode of the fifth transistor T5 is coupled to the fifth initialization signal terminal Vint_F5. The second electrode of the fifth transistor T5 is coupled to the second electrode or control electrode of the driving transistor M1.

[0132] For example, such as Figure 11 , Figure 13 As shown, the second terminal of the fifth transistor T5 is coupled to the second terminal of the driving transistor M1.

[0133] For example, such as Figure 12 As shown, the second electrode of the fifth transistor T5 is coupled to the control electrode of the driving transistor M1.

[0134] The first light-emitting control circuit 9 may include a first light-emitting control transistor M4. The control electrode of the first light-emitting control transistor M4 is coupled to the first light-emitting control terminal EM1. The first electrode of the first light-emitting control transistor M4 is coupled to the first power supply voltage terminal VDD. The second electrode of the first light-emitting control transistor M4 is coupled to the first electrode of the driving transistor M1.

[0135] The second light-emitting control circuit 10 may include a second light-emitting control transistor M5. The control electrode of the second light-emitting control transistor M5 is coupled to the second light-emitting control terminal EM2. The first electrode of the second light-emitting control transistor M5 is coupled to the second electrode of the driving transistor M1. The second electrode of the second light-emitting control transistor M5 is coupled to the first electrode of the light-emitting device P.

[0136] For example, such as Figure 11 , Figure 13 As shown, the compensation transistor M3 can be an N-type transistor, while the other transistors can be P-type transistors.

[0137] For example, such as Figure 12 As shown, the fifth transistor T5 and the compensation transistor M3 can be N-type transistors, while the other transistors can be P-type transistors.

[0138] For example, the fifth transistor T5 and the compensation transistor M3 are oxide transistors with low leakage current, which can better maintain the potential of the control electrode of the driving transistor.

[0139] In the pixel circuit provided in the embodiments of this disclosure, such as Figure 13 As shown, the sixth reset circuit 11 may include a sixth transistor T6. The control terminal of the sixth transistor T6 is coupled to the sixth reset control terminal Reset_F6, the first terminal of the sixth transistor T6 is coupled to the sixth initialization signal terminal Vint_F6, and the second terminal of the sixth transistor T6 is coupled to the first terminal of the driving transistor M1.

[0140] This disclosure also provides a display panel, such as... Figure 14 As shown, it includes multiple pixel circuits px as described above.

[0141] For example, such as Figure 14 As shown, the display panel may include multiple first initialization signal lines V1, and a first initialization signal terminal (not shown in the figure) in a column of pixel circuits is coupled to a first initialization signal line V1.

[0142] For example, such as Figure 14 As shown, the display panel may include multiple second initialization signal lines V2, and a second initialization signal terminal (not shown in the figure) in a column of pixel circuits is coupled to one of the second initialization signal lines V2.

[0143] For example, the first initialization signal line V1 is used to transmit the first initialization signal F1, such as Figure 15 As shown, for the refresh region, the first initialization signal F1 has a first initialization voltage vint1, and for the hold region, the first initialization signal F1 has a second initialization voltage vint2; the second initialization signal line V2 is used to transmit the second initialization signal F2, and for the refresh region, the second initialization signal F2 has a third initialization voltage vint3, and for the hold region, the first initialization signal F2 has a fourth initialization voltage vint4.

[0144] For example, such as Figure 14 As shown, the display panel may include a third initialization signal line V3, and the third initialization signal terminal (not shown in the figure) in any pixel circuit is coupled to the third initialization signal line V3.

[0145] For example, such as Figure 14 As shown, it may also include multiple first gate lines S1 and a first gate drive circuit GOA1 (Gate On Array, a drive circuit disposed on the display panel) coupled to the multiple first gate lines S1. The first gate drive circuit GOA1 includes multiple cascaded first shift register units SR1; wherein,

[0146] The input signal terminal of the first shift register unit SR1(1) of the first stage is coupled to the first frame trigger signal terminal (not shown in the figure);

[0147] The signal output terminal of the first shift register unit SR1(n) of the nth stage is coupled to the input signal terminal of the first shift register unit SR1(n+m) of the (n+m)th stage. The signal output terminal of the first shift register unit SR1(n) of the nth stage is coupled to the first reset control terminal in the pixel circuit of the i-th row through a first gate line S1 (not shown in the figure); where m, n and i are all positive integers.

[0148] For example, m can be a natural number such as 1, 2, 3, 4, etc. For example, as... Figure 14 As shown, when m is 1, in two adjacent first shift register units SR1, the input signal of the next-level first shift register unit SR1(n) is provided by the output signal of the previous-level first shift register unit SR1(n-1). For example, when m is 2, the output signal of the (n-2)th-level first shift register unit SR1(n-2) is coupled to the input signal of the nth-level first shift register unit SR1(n), and the output signal of the (n-1)th-level first shift register unit SR1(n-1) is coupled to the input signal of the (n+1)th-level first shift register unit SR1(n+1). Other levels of first shift register units SR1 have the same connection logic, which will not be described further here.

[0149] For example, the signal output terminal of the first shift register unit SR1(n) of the nth stage is also coupled to the second reset control terminal in the pixel circuit of the xth row through a first gate line S1; where x is a positive integer.

[0150] For example, the first gate line S1 coupled to the first reset control terminal and the second reset control terminal in a row pixel circuit is the same.

[0151] In the display panel provided in the embodiments of this disclosure, such as Figure 14 As shown, it also includes multiple second gate lines S2 and a second gate drive circuit GOA2 coupled to the multiple second gate lines S2. The second gate drive circuit GOA2 includes multiple cascaded second shift register units SR2; wherein,

[0152] The input signal terminal of the first-stage second shift register unit SR2(1) is coupled to the second frame trigger signal terminal (not shown in the figure);

[0153] The signal output terminal of the second shift register unit SR2(n) of the nth stage is coupled to the input signal terminal of the second shift register unit SR2(n+j) of the n+jth stage. The signal output terminal of the second shift register unit SR2(n) of the nth stage is coupled to the third reset control terminal in the pixel circuit of the kth row through a second gate line S2 (not shown in the figure); where n, j, and k are all positive integers.

[0154] For example, j can be a natural number such as 1, 2, 3, 4, etc. For example, as... Figure 14As shown, when j is 1, in two adjacent stages of the second shift register unit, the input signal of the next stage second shift register unit SR2(n) is provided by the output signal of the previous stage second shift register unit SR2(n-1). For example, when j is 2, the output signal of the (n-2)th stage second shift register unit SR2(n-2) is coupled to the input signal of the nth stage second shift register unit SR2(n), and the output signal of the (n-1)th stage second shift register unit SR2(n-1) is coupled to the input signal of the (n+1)th stage second shift register unit SR2(n+1). Other stages of the second shift register unit SR2 have the same connection logic, which will not be described further here.

[0155] For example, the signal output terminal of the second shift register unit SR2(n) of the nth stage is also coupled to the fourth reset control terminal in the pixel circuit of the yth row through a second gate line S2; where y is a positive integer.

[0156] For example, the signal output terminal of the second shift register unit SR2(n) of the nth stage is also coupled to the sixth reset control terminal in the pixel circuit of the zth row through a second gate line S2; where z is a positive integer.

[0157] For example, the second gate line S2 coupled to the third reset control terminal, the fourth reset control terminal, and the sixth reset control terminal in a row pixel circuit is the same.

[0158] For example, the above-mentioned display panel, such as Figure 16 As shown, it may include: a first gate drive circuit GOA1, a second gate drive circuit GOA2, a third gate drive circuit GOA3, a fourth gate drive circuit GOA4, a fifth gate drive circuit GOA5, a sixth gate drive circuit GOA6, a first initialization signal line V1, a second initialization signal line V2, a third initialization signal line V3, a fourth initialization line V4, a fifth initialization signal line V5, and a sixth initialization signal line V6, wherein...

[0159] The signal output terminal of the first gate driving circuit GOA1 is coupled to the first light emission control terminal and the second light emission control terminal in the pixel circuit through a corresponding signal lead, providing light emission control signals to the first light emission control terminal and the second light emission control terminal respectively.

[0160] The signal output terminal of the second gate drive circuit GOA2 is coupled to the fifth reset control terminal in the pixel circuit through a corresponding signal lead, providing a fifth reset signal to the fifth reset control terminal.

[0161] The signal output terminal of the third gate drive circuit GOA3 is coupled to the compensation signal terminal in the pixel circuit through a corresponding signal lead, providing a compensation signal to the compensation signal terminal.

[0162] The signal output terminal of the fourth gate drive circuit GOA4 is coupled to the scan signal terminal in the pixel circuit through a corresponding signal lead, providing a scan signal to the scan signal terminal.

[0163] The signal output terminal of the fifth gate drive circuit GOA5 is coupled to the first reset control terminal and the second reset control terminal in the pixel circuit through a corresponding signal lead, providing the first reset signal and the second reset signal to the first reset control terminal and the second reset control terminal respectively.

[0164] The signal output terminal of the sixth gate drive circuit GOA6 is coupled to the third reset control terminal, the fourth reset control terminal, and the sixth reset control terminal in the pixel circuit through a corresponding signal lead, providing the third reset signal, the fourth reset signal, and the sixth reset signal to the third reset control terminal, the fourth reset control terminal, and the sixth reset control terminal, respectively.

[0165] like Figure 16 As shown, px(n-1,m-1) represents the pixel circuit in the (n-1)th row and (m-1)th column, px(n-1,m) represents the pixel circuit in the (n-1)th row and (m)th column, and px(n-1,m+1) represents the pixel circuit in the (n-1)th row and (m+1)th column; px(n,m-1) represents the pixel circuit in the nth row and (m-1)th column, px(n,m) represents the pixel circuit in the nth row and (m)th column, and px(n,m+1) represents the pixel circuit in the nth row and (m+1)th column; px(n+1,m-1) represents the pixel circuit in the (n+1)th row and (m)th column, px(n+1,m) represents the pixel circuit in the (n+1)th row and (m)th column, and px(n+1,m+1) represents the pixel circuit in the (n+1)th row and (m+1)th column.

[0166] GOA1(n-1) represents the (n-1)th level light emission control signal generation circuit, GOA1(n) represents the nth level light emission control signal generation circuit, and GOA1(n+1) represents the (n+1)th level light emission control signal generation circuit.

[0167] GOA2(n-1) represents the fifth reset signal generation circuit of the (n-1)th stage, GOA2(n) represents the fifth reset signal generation circuit of the nth stage, and GOA2(n+1) represents the fifth reset signal generation circuit of the (n+1)th stage.

[0168] GOA3(n-1) represents the (n-1)th level compensation signal generation circuit, GOA3(n) represents the nth level compensation signal generation circuit, and GOA3(n+1) represents the (n+1)th level compensation signal generation circuit.

[0169] GOA4(n-1) represents the (n-1)th level scan signal generation circuit, GOA4(n-1) represents the nth level scan signal generation circuit, and GOA4(n+1) represents the (n+1)th level scan signal generation circuit.

[0170] GOA5(n-1) represents the circuit for generating the first and second reset signals at the (n-1)th stage, GOA5(n) represents the circuit for generating the first and second reset signals at the nth stage, and GOA5(n+1) represents the circuit for generating the first and second reset signals at the (n+1)th stage.

[0171] GOA6(n-1) represents the circuit for generating the third, fourth, and sixth reset signals at level (n-1), GOA6(n) represents the circuit for generating the third, fourth, and sixth reset signals at level n, and GOA6(n+1) represents the circuit for generating the third, fourth, and sixth reset signals at level (n+1).

[0172] V1(m-1) represents the first initialization signal line of the (m-1)th column, V1(m) represents the first initialization signal line of the mth column, V1(m+1) represents the first initialization signal line of the (m+1)th column; V2(m-1) represents the second initialization signal line of the (m-1)th column, V2(m) represents the second initialization signal line of the mth column, V2(m+1) represents the second initialization signal line of the (m+1)th column.

[0173] For example, such as Figure 16 As shown, the third initialization signal terminal in the row pixel circuit is coupled to the third initialization signal line V3 through a correspondingly configured signal lead.

[0174] For example, such as Figure 16 As shown, the fourth initialization signal terminal in the row pixel circuit is coupled to the fourth initialization signal line V4 through a correspondingly configured signal lead.

[0175] For example, such as Figure 16 As shown, the fifth initialization signal terminal in the row pixel circuit is coupled to the fifth initialization signal line V5 through a correspondingly configured signal lead.

[0176] For example, such as Figure 16 As shown, the third initialization signal terminal in the row pixel circuit is coupled to the third initialization signal line V3 through a correspondingly configured signal lead.

[0177] This disclosure also provides a display device, including the display panel described above.

[0178] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0179] This disclosure also provides a driving method for driving such as Figure 2 The pixel circuit shown includes:

[0180] The pixel circuitry operates in each display frame, which includes a refresh period and a hold period.

[0181] Refresh time period, including:

[0182] During the data writing phase, the data writing circuit 2 responds to the signal at the scan signal terminal Gate_P and inputs the data voltage at the data signal terminal Data to the first terminal of the driving transistor 1; the compensation circuit 3 responds to the signal at the compensation signal terminal Gate_N and turns on the control terminal and the second terminal of the driving transistor 1.

[0183] During the reset phase, the first reset circuit 4 responds to the signal of the first reset control terminal Reset_F1 and inputs the first initialization signal of the first initialization signal terminal Vint_F1 to the second terminal of the driving transistor 1; wherein, the first initialization signal input by the first reset circuit 4 to the second terminal of the driving transistor 1 has a first initialization voltage vint1;

[0184] During the light-emitting stage, driving transistor 1 drives light-emitting device P to emit light;

[0185] The duration of the period includes:

[0186] During the reset phase, the first reset circuit 4 responds to the signal of the first reset control terminal Reset_F1 and inputs the first initialization signal of the first initialization signal terminal Vint_F1 to the second terminal of the driving transistor 1; wherein, the first initialization signal input by the first reset circuit 4 to the second terminal of the driving transistor 1 has a second initialization voltage vint2, and the first initialization voltage vint1 is different from the second initialization voltage vint2;

[0187] During the light-emitting stage, driving transistor 1 drives light-emitting device P to emit light.

[0188] For example, the first initialization voltage vint1 is less than the second initialization voltage vint2.

[0189] In the driving method provided in the embodiments of this disclosure, the refresh time period includes a reset phase, which further includes:

[0190] In response to the signal from the second reset control terminal Reset_F2, the second reset circuit 5 inputs the second initialization signal from the second initialization signal terminal Vint_F2 to the first terminal of the driving transistor 1; wherein, the second initialization signal input from the second reset circuit 5 to the first terminal of the driving transistor 1 has a third initialization voltage vint3;

[0191] The reset phase, which is included in the retention period, also includes:

[0192] In response to the signal from the second reset control terminal Reset_F2, the second reset circuit 5 inputs the second initialization signal from the second initialization signal terminal Vint_F2 to the first terminal of the driving transistor 1; wherein, the second initialization signal input from the second reset circuit 5 to the first terminal of the driving transistor 1 has a fourth initialization voltage vint4, and the third initialization voltage vint3 is different from the fourth initialization voltage vint4.

[0193] For example, the third initialization voltage vint3 is less than the fourth initialization voltage vint4.

[0194] The driving method provided in this embodiment increases the drain-source voltage of the driving transistor during a portion of the holding period by inputting a second initialization voltage, which is larger than the first initialization voltage, vint1, into the second terminal of the driving transistor, and a fourth initialization voltage, which is larger than the third initialization voltage, vint3, into the first terminal of the driving transistor. This reduces the brightness and chromaticity difference between the holding and refresh regions and improves the screen splitting phenomenon between the holding and refresh regions.

[0195] The following is based on Figure 13 Taking the pixel circuit shown as an example, combined with Figures 17 to 19 The signal timing diagram shown describes the operation of the pixel circuit provided in the embodiments of this disclosure.

[0196] Specifically, such as Figure 17As shown, the refresh time period can include the first reset phase t1, the data writing phase t2, the second reset phase t3, the third reset phase t4, and the light emission phase t5, which are set sequentially. Here, em represents the signals of the first light emission control terminal EM1 and the second light emission control terminal EM2, reset5 represents the signal of the fifth reset control terminal Reset_F5, gate_n represents the signal of the compensation signal terminal Gate_N, gate_p represents the signal of the scan signal terminal Gate_P, reset3 represents the signal of the third reset control terminal Reset_F3, reset4 represents the signal of the fourth reset control terminal Reset_F4, reset6 represents the signal of the sixth reset control terminal Reset_F6, reset1 represents the signal of the first reset control terminal Reset_F1, and reset2 represents the signal of the second reset control terminal Reset_F2.

[0197] In the first reset phase t1, em is high, reset5 is low, gate_n is high, gate_p is high, reset3 is high, reset4 is high, reset6 is high, reset1 is high, and reset2 is high.

[0198] The fifth transistor T5 is turned on under the control of the signal reset5 at the fifth reset control terminal Reset_F5. The turned-on fifth transistor T5 inputs the signal from the fifth initialization signal terminal Vint_F5 to drive the second terminal of transistor M1.

[0199] During the data writing phase t2, em is high, reset5 is high, gate_n is high, gate_p is low, reset3 is high, reset4 is high, reset6 is high, reset1 is high, and reset2 is high.

[0200] The data writing transistor M2 is turned on under the control of the gate_p signal at the scan signal terminal Gate_P; at the same time, under the storage effect of the storage capacitor Cs, the first node N1 maintains the low level of the previous stage, controlling the drive transistor M1 to turn on; the compensation transistor M3 is turned on under the control of the gate_n signal at the compensation signal terminal Gate_N. The turned-on data writing transistor M2, drive transistor M1 and compensation transistor M3 provide the data voltage at the data signal terminal Data to the first node N1.

[0201] In the second reset phase t3, em is high, reset5 is high, gate_n is low, gate_p is high, reset3 is low, reset4 is low, reset6 is low, reset1 is high, and reset2 is high.

[0202] The third transistor T3 is turned on under the control of the signal reset3 at the third reset control terminal Reset_F3. The turned-on third transistor T3 inputs the signal Vint_F3 at the third initialization signal terminal to drive the second terminal of transistor M1. The fourth transistor T4 is turned on under the control of the signal reset4 at the fourth reset control terminal Reset_F4. The turned-on fourth transistor T4 inputs the signal Vint_F4 at the fourth initialization signal terminal to drive the first terminal of light-emitting device P. The sixth transistor T6 is turned on under the control of the signal reset6 at the sixth reset control terminal Reset_F6. The turned-on sixth transistor T6 inputs the signal Vint_F6 at the sixth initialization signal terminal to drive the first terminal of transistor M1.

[0203] In the third reset phase t4, em is high, reset5 is high, gate_n is low, gate_p is high, reset3 is high, reset4 is high, reset6 is high, reset1 is low, and reset2 is low.

[0204] The first transistor T1 is turned on under the control of the signal reset1 at the first reset control terminal Reset_F1. The turned-on first transistor T1 inputs the first initialization voltage vint1 of the first initialization signal at the first initialization signal terminal Vint_F1 to the second terminal of the driving transistor M1. The second transistor T2 is turned on under the control of the signal reset2 at the second reset control terminal Reset_F2. The turned-on second transistor T2 inputs the third initialization voltage vint3 of the second initialization signal at the second initialization signal terminal Vint_F2 to the first terminal of the driving transistor M1.

[0205] During the light-emitting phase t5, em is low, reset5 is high, gate_n is low, gate_p is high, reset3 is high, reset4 is high, reset6 is high, reset1 is high, and reset2 is high.

[0206] The light-emitting control transistor M4 is turned on under the control of the signal em at the first light-emitting control terminal EM1. At the same time, under the storage effect of the storage capacitor Cs, the first node N1 maintains the low level of the previous stage, controlling the driving transistor M1 to turn on. The light-emitting control transistor M5 is turned on under the control of the signal em at the second light-emitting control terminal EM2. The turned-on light-emitting control transistors M4 and M5 and the driving transistor M1 transmit the first power supply voltage VDD at the first power supply voltage terminal to the first electrode of the light-emitting device P, and the light-emitting device P emits light.

[0207] Specifically, such as Figure 18As shown, the refresh time period can include the sequentially set first reset phase t1, data writing phase t2, second reset phase t3, third reset phase t4, and light emission phase t5. Compared to Figure 16 As shown in the timing diagram, in the third reset phase t4, the signal reset1 of the first reset control terminal Reset_F1 is at a high level, and the first transistor T1 is turned off under the control of the signal reset1 of the first reset control terminal Reset_F1; the signal reset2 of the second reset control terminal Reset_F2 is at a high level, and the second transistor T2 is turned off under the control of the signal reset2 of the second reset control terminal Reset_F2. That is, in the third reset phase of the refresh time period, the first initialization signal of the first initialization signal terminal Vint_F1 and the second initialization signal of the second initialization signal terminal Vint_F2 will not be input to the second and first terminals of the driving transistor M1 respectively.

[0208] Specifically, such as Figure 19 As shown, the holding time period may include the first reset phase t1, the data writing phase t2, the second reset phase t3, the third reset phase t4, and the light emission phase t5, which are set sequentially.

[0209] In the first reset phase t1, em is high, reset5 is low, gate_n is low, gate_p is high, reset3 is high, reset4 is high, reset6 is high, reset1 is high, and reset2 is high.

[0210] The fifth transistor T5 is turned on under the control of the signal reset5 at the fifth reset control terminal Reset_F5. The turned-on fifth transistor T5 inputs the signal from the fifth initialization signal terminal Vint_F5 to drive the second terminal of transistor M1.

[0211] During the data writing phase t2, em is high, reset5 is high, gate_n is low, gate_p is high, reset3 is high, reset4 is high, reset6 is high, reset1 is high, and reset2 is high.

[0212] The data writing transistor M2 is turned off under the control of the gate_p signal at the scan signal terminal Gate_P; the compensation transistor M3 is turned off under the control of the gate_n signal at the compensation signal terminal Gate_N, that is, no data voltage is written to the first node N1.

[0213] In the second reset phase t3, em is high, reset5 is high, gate_n is low, gate_p is high, reset3 is low, reset4 is low, reset6 is low, reset1 is high, and reset2 is high.

[0214] The third transistor T3 is turned on under the control of the signal reset3 at the third reset control terminal Reset_F3. The turned-on third transistor T3 inputs the signal Vint_F3 at the third initialization signal terminal to drive the second terminal of transistor M1. The fourth transistor T4 is turned on under the control of the signal reset4 at the fourth reset control terminal Reset_F4. The turned-on fourth transistor T4 inputs the signal Vint_F4 at the fourth initialization signal terminal to drive the first terminal of light-emitting device P. The sixth transistor T6 is turned on under the control of the signal reset6 at the sixth reset control terminal Reset_F6. The turned-on sixth transistor T6 inputs the signal Vint_F6 at the sixth initialization signal terminal to drive the first terminal of transistor M1.

[0215] In the third reset phase t4, em is high, reset5 is high, gate_n is low, gate_p is high, reset3 is high, reset4 is high, reset6 is high, reset1 is low, and reset2 is low.

[0216] The first transistor T1 is turned on under the control of the signal reset1 at the first reset control terminal Reset_F1. The turned-on first transistor T1 inputs the second initialization voltage vint2 of the first initialization signal at the first initialization signal terminal Vint_F1 to the second terminal of the driving transistor M1. The second transistor T2 is turned on under the control of the signal reset2 at the second reset control terminal Reset_F2. The turned-on second transistor T2 inputs the fourth initialization voltage vint4 of the second initialization signal at the second initialization signal terminal Vint_F2 to the first terminal of the driving transistor M1.

[0217] During the light-emitting phase t5, em is low, reset5 is high, gate_n is low, gate_p is high, reset3 is high, reset4 is high, reset6 is high, reset1 is high, and reset2 is high.

[0218] The light-emitting control transistor M4 is turned on under the control of the signal em at the first light-emitting control terminal EM1. At the same time, under the storage effect of the storage capacitor Cs, the first node N1 maintains the low level of the previous stage, controlling the driving transistor M1 to turn on. The light-emitting control transistor M5 is turned on under the control of the signal em at the second light-emitting control terminal EM2. The turned-on light-emitting control transistors M4 and M5 and the driving transistor M1 transmit the first power supply voltage VDD at the first power supply voltage terminal to the first electrode of the light-emitting device P, and the light-emitting device P emits light.

[0219] The pixel circuit, display panel, and display device provided in this disclosure embodiment add a first reset circuit to the second electrode of the driving transistor. The first reset circuit inputs different initialization voltages of the first initialization signal to the second electrode of the driving transistor during the refresh time period and the hold time period, respectively, so as to realize the differential setting of the voltage of the second electrode of the driving transistor during the hold time period and the refresh time period. This enables the brightness and color difference between the refresh area and the hold area to be adjustable, eliminates the split screen phenomenon, and improves the image quality.

[0220] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0221] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A pixel circuit, wherein, include: A driving transistor, wherein the first terminal of the driving transistor is used to couple to a first power supply voltage terminal, and the second terminal of the driving transistor is used to couple to a light-emitting device; A data writing circuit, coupled to the first terminal of the driving transistor, is configured to input the data voltage of the data signal terminal into the first terminal of the driving transistor in response to a signal at the scan signal terminal. A compensation circuit, coupled to the second and control terminals of the driving transistor, is configured to turn on the second and control terminals of the driving transistor in response to a signal at the compensation signal terminal. A first reset circuit, coupled to the second terminal of the driving transistor, is configured to input a first initialization signal from the first initialization signal terminal to the second terminal of the driving transistor in response to a signal from the first reset control terminal. During the refresh period, the first initialization signal input to the second terminal of the driving transistor has a first initialization voltage; during the hold period, the first initialization signal input to the second terminal of the driving transistor has a second initialization voltage, and the first initialization voltage is different from the second initialization voltage.

2. The pixel circuit as described in claim 1, wherein, The first initialization voltage is less than the second initialization voltage.

3. The pixel circuit as described in claim 1, wherein, The first reset circuit includes a first transistor; The control electrode of the first transistor is coupled to the first reset control terminal, the first electrode of the first transistor is coupled to the first initialization signal terminal, and the second electrode of the first transistor is coupled to the second electrode of the driving transistor.

4. The pixel circuit according to any one of claims 1-3, wherein, Also includes: The second reset circuit, coupled to the first terminal of the driving transistor, is configured to input the second initialization signal from the second initialization signal terminal to the first terminal of the driving transistor in response to a signal from the second reset control terminal.

5. The pixel circuit as described in claim 4, wherein, During the refresh time period, the second initialization signal input to the first terminal of the driving transistor has a third initialization voltage; During the holding period, the second initialization signal input to the first terminal of the driving transistor has a fourth initialization voltage; The third initialization voltage is different from the fourth initialization voltage.

6. The pixel circuit as described in claim 5, wherein, The third initialization voltage is less than the fourth initialization voltage.

7. The pixel circuit as described in claim 4, wherein, The second reset circuit includes a second transistor, the control terminal of the second transistor is coupled to the second reset control terminal, the first terminal of the second transistor is coupled to the second initialization signal terminal, and the second terminal of the second transistor is coupled to the first terminal of the driving transistor.

8. The pixel circuit as described in claim 4, wherein, The first reset control terminal and the second reset control terminal are the same signal terminal.

9. The pixel circuit according to any one of claims 1-8, wherein, Also includes: A third reset circuit, coupled to the second terminal of the driving transistor, is configured to input a signal from the third initialization signal terminal into the second terminal of the driving transistor in response to a signal from the third reset control terminal.

10. The pixel circuit as claimed in claim 9, wherein, The third reset circuit includes a third transistor, the control electrode of the third transistor is coupled to the third reset control terminal, the first electrode of the third transistor is coupled to the third initialization signal terminal, and the second electrode of the third transistor is coupled to the second electrode of the driving transistor.

11. The pixel circuit as claimed in claim 10, wherein, Also includes: A storage capacitor, wherein the first terminal of the storage capacitor is used to couple to the first power supply voltage terminal, and the second terminal of the storage capacitor is coupled to the control terminal of the driving transistor; The fourth reset circuit, coupled to the first electrode of the light-emitting device, is configured to input the signal of the fourth initialization signal terminal into the first electrode of the light-emitting device in response to the signal of the fourth reset control terminal. The fifth reset circuit, coupled to the second or control terminal of the driving transistor, is configured to input the signal of the fifth initialization signal terminal to the second or control terminal of the driving transistor in response to a signal at the fifth reset control terminal. A first light-emitting control circuit is coupled between the first terminal of the driving transistor and the first power supply voltage terminal, and is configured to input the signal from the first power supply voltage terminal into the first terminal of the driving transistor in response to the signal from the first light-emitting control terminal. The second light-emitting control circuit, coupled between the second terminal of the driving transistor and the light-emitting device, is configured to conduct the second terminal of the driving transistor and the light-emitting device in response to a signal from the second light-emitting control terminal.

12. The pixel circuit as claimed in claim 11, wherein, The fourth reset circuit includes a fourth transistor, the control electrode of which is coupled to the fourth reset control terminal, the first electrode of which is coupled to the fourth initialization signal terminal, and the second electrode of which is coupled to the first electrode of the light-emitting device; or... The fifth reset circuit includes a fifth transistor, the control electrode of which is coupled to the fifth reset control terminal, the first electrode of which is coupled to the fifth initialization signal terminal, and the second electrode of which is coupled to the second electrode or control electrode of the driving transistor; or... The first light-emitting control circuit includes a first light-emitting control transistor, the control electrode of the first light-emitting control transistor is coupled to the first light-emitting control terminal, the first electrode of the first light-emitting control transistor is coupled to the first power supply voltage terminal, and the second electrode of the first light-emitting control transistor is coupled to the first electrode of the driving transistor; or... The second light-emitting control circuit includes a second light-emitting control transistor, the control electrode of the second light-emitting control transistor is coupled to the second light-emitting control terminal, the first electrode of the second light-emitting control transistor is coupled to the second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is coupled to the first electrode of the light-emitting device.

13. The pixel circuit as claimed in claim 11, wherein, The third reset control terminal and the fourth reset control terminal are the same signal terminal.

14. The pixel circuit according to any one of claims 1-13, wherein, Also includes: The sixth reset circuit, coupled to the first terminal of the driving transistor, is configured to input the signal of the sixth initialization signal terminal into the first terminal of the driving transistor in response to a signal from the sixth reset control terminal.

15. The pixel circuit as claimed in claim 14, wherein, The sixth reset circuit includes a sixth transistor, the control electrode of the sixth transistor is coupled to the sixth reset control terminal, the first electrode of the sixth transistor is coupled to the sixth initialization signal terminal, and the second electrode of the sixth transistor is coupled to the first electrode of the driving transistor.

16. A driving method for driving a pixel circuit as described in any one of claims 1-15, wherein, include: The pixel circuit operates in each display frame, which includes a refresh time period and a hold time period. The refresh time period includes: During the data writing phase, the data writing circuit responds to the signal at the scan signal terminal by inputting the data voltage at the data signal terminal into the first terminal of the driving transistor; the compensation circuit responds to the signal at the compensation signal terminal by turning on the control terminal and the second terminal of the driving transistor. During the reset phase, the first reset circuit responds to the signal at the first reset control terminal by inputting the first initialization signal at the first initialization signal terminal to the second terminal of the driving transistor; wherein, the first initialization signal input by the first reset circuit to the second terminal of the driving transistor has a first initialization voltage; During the light-emitting stage, the driving transistor drives the light-emitting device to emit light; The duration of the hold includes: During the reset phase, the first reset circuit responds to the signal at the first reset control terminal by inputting a first initialization signal from the first initialization signal terminal to the second terminal of the driving transistor; wherein the first initialization signal input by the first reset circuit to the second terminal of the driving transistor has a second initialization voltage, and the first initialization voltage is different from the second initialization voltage. During the light-emitting stage, the driving transistor drives the light-emitting device to emit light.

17. The driving method as described in claim 16, wherein, The first initialization voltage is less than the second initialization voltage.

18. The driving method as described in claim 16 or 17, wherein, The refresh time period includes the reset phase, which further includes: In response to the signal at the second reset control terminal, the second reset circuit inputs the second initialization signal at the second initialization signal terminal to the first terminal of the driving transistor; wherein, the second initialization signal input by the second reset circuit to the first terminal of the driving transistor has a third initialization voltage; The reset phase included in the holding time period also includes: The second reset circuit responds to the signal at the second reset control terminal by inputting a second initialization signal from the second initialization signal terminal to the first terminal of the driving transistor; wherein the second initialization signal input by the second reset circuit to the first terminal of the driving transistor has a fourth initialization voltage, and the third initialization voltage is different from the fourth initialization voltage.

19. The driving method as described in claim 18, wherein, The third initialization voltage is less than the fourth initialization voltage.

20. A display panel, wherein, It includes multiple pixel circuits as described in any one of claims 1-15.

21. The display panel as claimed in claim 20, wherein, The display panel includes multiple first initialization signal lines, and the first initialization signal terminal in a column of pixel circuits is coupled to one of the first initialization signal lines; or... The display panel includes multiple second initialization signal lines, with the second initialization signal terminal in a column of pixel circuits coupled to one of the second initialization signal lines; or... The display panel includes a third initialization signal line, and the third initialization signal terminal in any pixel circuit is coupled to the third initialization signal line.

22. The display panel as claimed in claim 20 or 21, wherein, It also includes multiple first gate lines and a first gate driving circuit coupled to the multiple first gate lines, wherein the first gate driving circuit includes multiple cascaded first shift register units; wherein, The input signal terminal of the first shift register unit of the first stage is coupled to the first frame trigger signal terminal; The signal output terminal of the first shift register unit of the nth stage is coupled to the input signal terminal of the first shift register unit of the (n+m)th stage. The signal output terminal of the first shift register unit of the nth stage is coupled to the first reset control terminal in the pixel circuit of the i-th row through a first gate line; where m, n, and i are all positive integers.

23. The display panel as claimed in claim 22, wherein, The signal output terminal of the nth-level first shift register unit is also coupled to the second reset control terminal in the x-row pixel circuit through a first gate line; where x is a positive integer.

24. The display panel as claimed in claim 23, wherein, The first gate line coupled to the first reset control terminal and the second reset control terminal in a row pixel circuit is the same.

25. The display panel as claimed in claim 23 or 24, wherein, It also includes multiple second gate lines and a second gate driving circuit coupled to the multiple second gate lines, wherein the second gate driving circuit includes multiple cascaded second shift register units; wherein, The input signal terminal of the first-stage second shift register unit is coupled to the second frame trigger signal terminal; The signal output terminal of the second shift register unit of the nth stage is coupled to the input signal terminal of the second shift register unit of the (n+j)th stage. The signal output terminal of the second shift register unit of the nth stage is coupled to the third reset control terminal in the pixel circuit of the kth row through a second gate line; where n, j, and k are all positive integers.

26. A display device, wherein, Includes the display panel as described in any one of claims 20-25.

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