Display device and electronic device including the same

Abstract

A display device and an electronic apparatus including the same are disclosed. The display device includes a substrate, first-first gate lines and first-second gate lines spaced apart from each other and extending in a first direction on the substrate, a data line extending in a second direction crossing the first direction, and first and second pixel circuits disposed along the first direction with the data line between the first and second pixel circuits, each of the first and second pixel circuits including a first electrode layer connected to a first semiconductor layer of a first transistor and including a first gap spaced apart from a second gate electrode of a second transistor in a plan view, and a first wiring disposed above the first electrode layer, extending in the second direction, and covering at least a portion of the first gap in the plan view.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0009815, filed on January 22, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to display devices and electronic devices including the display devices. Background Technology

[0004] In recent years, display devices have been developed for a wider range of purposes. At the same time, these devices have become thinner and lighter, further expanding their potential applications.

[0005] A typical display device includes a display panel comprising display elements that form pixels and pixel circuitry that controls electrical signals applied to the display elements. Each pixel circuit typically includes a thin-film transistor (TFT), a capacitor, and multiple wirings.

[0006] As display devices adapt to increasingly diverse purposes, various design approaches are being explored to improve display quality. Summary of the Invention

[0007] Embodiments of this disclosure include a display device with high reliability and an electronic device including the display device.

[0008] According to an embodiment, a display device includes: a substrate; first-first gate lines and first-second gate lines, spaced apart from each other and extending on the substrate in a first direction; a data line extending in a second direction intersecting the first direction; and a first pixel circuit and a second pixel circuit disposed along the first direction, with the data line between the first pixel circuit and the second pixel circuit. The first pixel circuit is connected to the first-first gate line, and the second pixel circuit is connected to the first-second gate line. Each of the first pixel circuit and the second pixel circuit includes: a first transistor including a first semiconductor layer and a first gate electrode; a second transistor including a second semiconductor layer and a second gate electrode, the second transistor being connected to the data line; a first electrode layer connected to the first semiconductor layer, overlapping the first gate electrode, and including a first gap spaced apart from the second gate electrode in a plan view; and a first wiring disposed above the first electrode layer, extending in the second direction, and covering at least a portion of the first gap in a plan view.

[0009] In one embodiment, each of the first pixel circuit and the second pixel circuit further includes a third semiconductor layer integrated with the second semiconductor layer and a third gate electrode overlapping the third semiconductor layer. The first electrode layer also includes a second gap spaced apart from the third gate electrode in a plan view, and the first wiring covers at least a portion of the second gap in the plan view.

[0010] In one embodiment, the first wiring is branched into a first branch and a second branch, the first branch covering at least a portion of the first gap and the second branch covering at least a portion of the second gap, and the second branch of the first pixel circuit is continuously disposed in the region overlapping with the first electrode layer, and the second branch of the second pixel circuit includes a discontinuous gap in the region overlapping with the first electrode layer.

[0011] In one embodiment, each of the first pixel circuit and the second pixel circuit further includes a third semiconductor layer integrated with the second semiconductor layer and a third gate electrode overlapping the third semiconductor layer. The first electrode layer also includes a second gap spaced apart from the third gate electrode in a plan view, and the first wiring exposes the second gap in a plan view.

[0012] In one implementation, the area where the first wiring of the first pixel circuit overlaps with the first electrode layer is different from the area where the first wiring of the second pixel circuit overlaps with the first electrode layer.

[0013] In one embodiment, the display device further includes a first emission control line and a second emission control line extending in a first direction. The first electrode layer also includes a third gap, which is a portion spaced apart from the first emission control line in a plan view, and the area of ​​the third gap covered by the first wiring in the first pixel circuit is approximately equal to the area of ​​the third gap covered by the first wiring in the second pixel circuit.

[0014] In one embodiment, the first electrode layer further includes a fourth gap, which is a portion spaced apart from the second emission control line in the plan view, and the area of ​​the fourth gap covered by the first wiring in the first pixel circuit is approximately equal to the area of ​​the fourth gap covered by the first wiring in the second pixel circuit.

[0015] In one embodiment, the first electrode layer at least partially overlaps with the first emission control line.

[0016] In this implementation, the first pixel circuit and the second pixel circuit share a data line.

[0017] In one embodiment, the display device further includes: a first light-emitting diode connected to a first pixel circuit; and a second light-emitting diode connected to a second pixel circuit. The first and second light-emitting diodes emit light of the same color.

[0018] In one embodiment, each of the first pixel circuit and the second pixel circuit further includes a holding capacitor, and the capacitance of the holding capacitor of the first pixel circuit is different from the capacitance of the holding capacitor of the second pixel circuit.

[0019] In one embodiment, the holding capacitor includes: a first holding electrode disposed below a first semiconductor layer; a second holding electrode disposed in the same layer as the first semiconductor layer; a third holding electrode integrated with the first electrode layer; and a fourth holding electrode disposed above the third holding electrode. The fourth holding electrode is integrated with the first wiring.

[0020] In one implementation, the first wiring includes wiring configured to transmit a constant voltage.

[0021] According to an embodiment of this disclosure, an electronic device includes a display device. The display device includes: a substrate; first-first gate lines and first-second gate lines spaced apart from each other and extending on the substrate in a first direction; a data line extending in a second direction intersecting the first direction; and a first pixel circuit and a second pixel circuit disposed along the first direction, with the data line between the first pixel circuit and the second pixel circuit. The first pixel circuit is connected to the first-first gate line, and the second pixel circuit is connected to the first-second gate line. Each of the first pixel circuit and the second pixel circuit includes: a first transistor including a first semiconductor layer and a first gate electrode; a second transistor including a second semiconductor layer and a second gate electrode, the second transistor being connected to the data line; a first electrode layer connected to the first semiconductor layer, overlapping the first gate electrode, and including a first gap spaced apart from the second gate electrode in a plan view; and a first wiring disposed above the first electrode layer, extending in the second direction, and covering at least a portion of the first gap in a plan view.

[0022] In one embodiment, each of the first pixel circuit and the second pixel circuit further includes a third semiconductor layer integrated with the second semiconductor layer and a third gate electrode overlapping the third semiconductor layer. The first electrode layer also includes a second gap spaced apart from the third gate electrode in a plan view, and the area of ​​the first wiring of the first pixel circuit covering the second gap is approximately equal to the area of ​​the first wiring of the second pixel circuit covering the second gap.

[0023] In one embodiment, each of the first pixel circuit and the second pixel circuit further includes a holding capacitor, and the capacitance of the holding capacitor of the first pixel circuit is different from the capacitance of the holding capacitor of the second pixel circuit.

[0024] In one embodiment, the electronic device further includes a first emission control line and a second emission control line extending in a first direction. The first electrode layer also includes a third gap, which is a portion spaced apart from the first emission control line in a plan view, and the area of ​​the third gap covered by the first wiring in the first pixel circuit is approximately equal to the area of ​​the third gap covered by the first wiring in the second pixel circuit.

[0025] In this implementation, the first pixel circuit and the second pixel circuit share a data line.

[0026] In one implementation, the first wiring includes wiring configured to transmit a constant voltage.

[0027] In this implementation, the electronic device is one of a smartphone, a tablet PC, a laptop PC, a television (TV), a desktop monitor, smart glasses, a head-mounted display, a smartwatch, a vehicle dashboard, a central dashboard, a central information display (CID), and an interior mirror display. Attached Figure Description

[0028] The above and other features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which: Figure 1 This is a schematic plan view of a display device according to an embodiment; Figure 2 This is a schematic diagram illustrating an equivalent circuit diagram of a light-emitting diode (LED) as a light-emitting element corresponding to a pixel of a display device, and a pixel circuit electrically connected to the LED, according to an embodiment. Figure 3 This is a schematic cross-sectional view showing a portion of the display device according to an embodiment; Figure 4 It is a schematic plan view showing a portion of the wiring and pixel circuitry arranged in the display area of ​​a display device according to an embodiment; Figure 5 This is a schematic layout diagram showing the positions of transistors, storage capacitors, and holding capacitors in a pixel circuit included in a display device according to an embodiment. Figures 6 to 10 It is shown schematically. Figure 5 A layout diagram of the components (such as transistors, storage capacitors, and holding capacitors) for each layer of the display device; Figure 11 This is a plan view of some components of the display device according to an embodiment; Figure 12 This is a plan view of some components of the display device according to an embodiment; Figure 13This is a plan view of some components of the display device according to an embodiment; Figure 14 This is a plan view of some components of the display device according to an embodiment; Figure 15 This is a plan view of some components of the display device according to an embodiment; Figure 16 This is a plan view of some components of the display device according to an embodiment; Figure 17 This is a plan view of some components of the display device according to an embodiment; Figure 18 This is a plan view of some components of the display device according to an embodiment; Figure 19 It is a block diagram of an electronic device according to an embodiment; and Figure 20 Several schematic diagrams of electronic devices according to various embodiments are shown. Detailed Implementation

[0029] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings. Throughout the drawings, similar reference numerals may refer to similar elements.

[0030] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” may mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or any variation thereof.

[0031] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and these elements are not limited by these terms. Therefore, a “first” element in one embodiment may be described as a “second” element in another embodiment.

[0032] As used in this article, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0033] In the following implementation, terms such as “comprising” or “including” specify the presence of the stated features or components, but do not preclude the addition of one or more other features or components.

[0034] It will be understood that when a component is referred to as being "on" another component, "connected to" (e.g., electrically connected to) another component, "linked to" another component, or "adjacent to" another component, it may be directly on, directly connected to, directly linked to, or directly adjacent to the other component, or there may be intervening components. It will also be understood that when a component is referred to as being "between" two components, it may be the only component between the two components, or there may be one or more intervening components. It will also be understood that when a component is referred to as "covering" another component, it may be the only component covering that other component, or one or more intervening components may also cover that other component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0035] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” and “upper” are used herein to describe the relationship between one element or feature and another element(s) as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below,” “under,” or “below” other elements or features will consequently be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can encompass both above and below orientations.

[0036] When a particular implementation can be carried out differently, a specific process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously, or in the reverse order of the described sequence.

[0037] In this document, as will be understood by those skilled in the art, when two or more elements or values ​​are described as substantially the same or approximately equal to each other, it should be understood that the elements or values ​​are identical to each other, equal to each other within measurement error, or, if measurably unequal, sufficiently close in value to be functionally equal to each other. For example, given the measurement discussed and the error associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the term “approximately” as used herein includes the value and means within an acceptable deviation of a particular value as determined by those skilled in the art. For example, “approximately” may mean within one or more standard deviations as understood by those skilled in the art, such as within ±30%, ±20%, ±10%, or ±5% of the value. Furthermore, it should be understood that although a parameter may be described herein as having an “approximately” specific value, as will be understood by those skilled in the art, depending on the implementation, the parameter may be exactly that specific value or an approximation of that specific value within measurement error. Other uses of these and similar terms to describe relationships between components should be interpreted in a similar manner.

[0038] Embodiments of this disclosure relate to display devices that can improve electrical uniformity in pixel circuits and reduce brightness variations. For example, a display device according to an embodiment includes multiple pixel circuits sharing a data line, and each pixel circuit includes a gate line, an electrode layer, and wiring arranged to control parasitic capacitance and reduce current deviation. By strategically controlling how the first wiring overlaps with specific gaps in the electrode layer and the gate electrode, the display device can maintain consistent electrical characteristics across adjacent pixels.

[0039] The embodiments of this disclosure allow for more uniform adjustment of holding capacitance and parasitic capacitance within the pixel circuitry, regardless of structural variations. This structural uniformity contributes to improved display quality by reducing brightness inconsistencies between adjacent light-emitting elements. The arrangement of shared lines, branch wiring, and intentional gap coverage can provide a compact and efficient pixel layout ideal for high-resolution and thin display panels.

[0040] Figure 1 This is a schematic plan view of the display device 1 according to an embodiment.

[0041] refer to Figure 1The display device 1 may include a display area DA and a peripheral area PA disposed outside the display area DA. The display area DA is the portion in which an image is displayed and may include multiple pixels PX. The display area DA may have any of a variety of shapes, such as circular, elliptical, polygonal, and shapes of specific graphics. The multiple pixels PX may be implemented using various light-emitting elements (such as, for example, organic light-emitting elements, inorganic light-emitting elements, and quantum dot light-emitting elements), wherein the light-emitting elements are driven by being connected to pixel circuitry.

[0042] The peripheral region PA of the display device 1 can be disposed outside the display region DA. A driver integrated circuit (IC) configured to provide electrical signals to be applied to the display region DA can be disposed in the peripheral region PA, and various wirings configured to transmit electrical signals generated in the driver IC can be disposed in the peripheral region PA.

[0043] Figure 2 This is a schematic diagram illustrating an equivalent circuit of a light-emitting diode (LED) as a light-emitting element corresponding to a pixel PX of the display device 1, and a pixel circuit PC electrically connected to the LED, according to an embodiment.

[0044] The pixel circuit PC can be electrically connected to a first gate line GWL configured to transmit a first gate signal GW, a second gate line GRL configured to transmit a second gate signal GR, a third gate line EML configured to transmit a third gate signal EM, a fourth gate line GBL configured to transmit a fourth gate signal GB, a fifth gate line EMBL configured to transmit a fifth gate signal EMB, and a data line DL configured to transmit a data signal DATA. The light emission of the light-emitting diode (LED) is controlled by the third gate signal EM and the fifth gate signal EMB; therefore, the third gate signal EM and the fifth gate signal EMB can be referred to as emission control signals, and the third gate line EML and the fifth gate line EMBL can be referred to as emission control lines. The third gate line EML can be referred to as the first emission control line, and the fifth gate line EMBL can be referred to as the second emission control line.

[0045] The pixel circuit PC can be electrically connected to the drive voltage line PL configured to transmit the drive voltage ELVDD, the reference voltage line VRL configured to transmit the reference voltage Vref, and the first initialization voltage line VAL configured to transmit the first initialization voltage Vaint.

[0046] The pixel circuit PC may include a first transistor T1 to a sixth transistor T6, a storage capacitor Cst, a holding capacitor Chold, and an auxiliary capacitor Ca.

[0047] The first transistor T1 can be a drive transistor configured to output a drive current corresponding to the data signal DATA, and the second transistor T2 to the sixth transistor T6 can be switching transistors configured to transmit signals.

[0048] According to an embodiment, each of the first transistors T1 to the sixth transistor T6 may comprise an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) (NMOS). Such first transistors T1 to the sixth transistor T6 may each comprise an oxide semiconductor material. However, this disclosure is not limited thereto, and at least one of the first transistors T1 to the sixth transistor T6 may comprise a p-channel MOSFET (PMOS). Various modifications are possible; for example, the fifth transistor T5 and / or the sixth transistor T6 may be provided as PMOS transistors, and the remaining transistors may be provided as NMOS transistors.

[0049] Depending on the voltage of the first terminal and the second terminal, the first terminal (or first electrode) and the second terminal (or second electrode) of each of the first transistors T1 to T6 can be either a source (or source electrode) or a drain (or drain electrode). For example, depending on the voltage of the first terminal and the second terminal, the first terminal can be a drain and the second terminal can be a source, or the first terminal can be a source and the second terminal can be a drain. In the following text, the node to which the first-first gate electrode of the first transistor T1 is connected can be defined as the first node N1, and the node to which the second terminal of the first transistor T1 is connected can be defined as the second node N2.

[0050] The first transistor T1 can be connected to the drive voltage line PL and the light-emitting diode (LED). The first transistor T1 can be connected between the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may include a first gate (or first gate electrode), a first terminal, and a second terminal connected to the second node N2. The first transistor T1 may include a first-first gate connected to the first node N1. The first transistor T1 may also include a first-second gate connected to its second terminal. The first-first gate and the first-second gate may be disposed in different layers and face each other. For example, the first-first gate and the first-second gate of the first transistor T1 may face each other, and a semiconductor layer is disposed between them. In this specification, the first gate (or first gate electrode) of the first transistor T1 may refer to the first-first gate (or first-first gate electrode) involved in turning the first transistor T1 on or off.

[0051] The gate (or first-first gate) of the first transistor T1 can be connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the storage capacitor Cst. The first-second gate of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the storage capacitor Cst, and the holding capacitor Chold. The first terminal of the first transistor T1 can be connected to the drive voltage line PL via the fifth transistor T5, and its second terminal can be connected to the pixel electrode of the light-emitting diode (LED) via the sixth transistor T6. The first terminal of the first transistor T1 can be connected to the second terminal of the fifth transistor T5. The second terminal of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the storage capacitor Cst, and the holding capacitor Chold. The first transistor T1 can be configured to control the amount of drive current flowing through the LED by receiving a data signal DATA according to the switching operation of the second transistor T2.

[0052] The second transistor T2 can be connected to the data line DL and the first gate of the first transistor T1. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second terminal of the second transistor T2 can be connected to the first gate of the first transistor T1, the first terminal of the third transistor T3, and the storage capacitor Cst. The second transistor T2 can be turned on by a first gate signal GW transmitted to the first gate line GWL to electrically connect the data line DL and the first node N1 to each other, and can be configured to transmit the data signal DATA transmitted to the data line DL to the first node N1.

[0053] A third transistor T3 can be connected to the first gate of the first transistor T1 and the reference voltage line VRL. The third transistor T3 may include a gate connected to the second gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3 can be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and a storage capacitor Cst. The third transistor T3 can be turned on by a second gate signal GR transmitted to the second gate line GRL to transmit the reference voltage Vref transmitted to the reference voltage line VRL to the first node N1.

[0054] A fourth transistor T4 can be connected to a sixth transistor T6 and a first initialization voltage line VAL. The fourth transistor T4 can be connected between a light-emitting diode (LED) and the first initialization voltage line VAL. The fourth transistor T4 may include a gate connected to a fourth gate line GBL, a first terminal connected to a third node N3, and a second terminal connected to the first initialization voltage line VAL. The first terminal of the fourth transistor T4 can be connected to the second terminal of the sixth transistor T6 and the pixel electrode of the LED. The fourth transistor T4 can be turned on by a fourth gate signal GB transmitted to the fourth gate line GBL to transmit a first initialization voltage Vaint transmitted to the first initialization voltage line VAL to the third node N3 and initialize the pixel electrode (e.g., the anode) of the LED.

[0055] The fifth transistor T5 can be connected to the drive voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate connected to the third gate line EML, a first terminal connected to the drive voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 can be turned on or off according to the third gate signal EM transmitted to the third gate line EML.

[0056] The sixth transistor T6 can be connected to the first transistor T1 and the light-emitting diode (LED). The sixth transistor T6 can be connected between the second node N2 and the third node N3. The sixth transistor T6 may include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first terminal of the sixth transistor T6 can be connected to the second terminal of the first transistor T1, a storage capacitor Cst, and a holding capacitor Chold. The second terminal of the sixth transistor T6 can be connected to the first terminal of the fourth transistor T4 and the pixel electrode of the LED. The sixth transistor T6 can be turned on or off according to the fifth gate signal EMB transmitted to the fifth gate line EMBL.

[0057] A storage capacitor Cst can be connected between the first gate and the second terminal of the first transistor T1. The first electrode of the storage capacitor Cst can be connected to the first node N1, and its second electrode can be connected to the second node N2. The first electrode of the storage capacitor Cst can be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the storage capacitor Cst can be connected to the second terminal and the first gate of the first transistor T1, the second electrode of the holding capacitor Chold, and the first terminal of the sixth transistor T6. The storage capacitor Cst can store the data voltage obtained by compensating for the threshold voltage of the first transistor T1.

[0058] When the third transistor T3 and the fifth transistor T5 are turned on, the first transistor T1 can be turned on. When the voltage at the second terminal of the first transistor T1 is reduced to the difference (Vref-Vth1) between the reference voltage Vref and the threshold voltage (Vth1) of the first transistor T1, the first transistor T1 is turned off, and the voltage corresponding to the threshold voltage (Vth1) of the first transistor T1 is stored in the storage capacitor Cst, and therefore, the threshold voltage (Vth1) of the first transistor T1 can be compensated.

[0059] A holding capacitor Chold can be connected between the drive voltage line PL and the second node N2. The first electrode of the holding capacitor Chold can be connected to the drive voltage line PL. The second electrode of the holding capacitor Chold can be connected to the second terminal of the first transistor T1 and the first-second gate, the second electrode of the storage capacitor Cst, and the first terminal of the sixth transistor T6. The holding capacitor Chold can store a compensation voltage used to compensate for the threshold voltage (Vth1) of the first transistor T1.

[0060] The capacitance of each of the storage capacitor Cst and the holding capacitor Chold can vary according to the color of the light emitted from the light-emitting diode (LED).

[0061] The auxiliary capacitor Ca can be electrically connected to the sixth transistor T6, the sustaining voltage line VSSL, and the pixel electrode of the light-emitting diode (LED). The auxiliary capacitor Ca can prevent the problem of increased black brightness when the sixth transistor T6 is turned off by storing and maintaining the voltage corresponding to the voltage difference between the pixel electrode of the LED and the sustaining voltage line VSSL.

[0062] A light-emitting diode (LED) can be connected to a first transistor T1 via a sixth transistor T6. The LED may include a pixel electrode (anode) connected to a third node N3 and a opposite electrode (cathode) facing the pixel electrode, and the opposite electrode may receive a common voltage ELVSS. According to an embodiment, the opposite electrode (cathode) may extend to the display area DA to be electrically connected to a sustaining voltage line VSSL configured to provide the common voltage ELVSS. The drive current output from the first transistor T1 flows through the LED via a conducting fifth transistor T5 and a conducting sixth transistor T6, and the LED can emit light with a brightness corresponding to the magnitude of the drive current.

[0063] As described above, the first transistor T1 to the sixth transistor T6 may comprise an oxide semiconductor material. Because oxide semiconductors exhibit high carrier mobility and low leakage current, the voltage drop can remain small even during extended driving periods. In other words, the use of oxide semiconductors helps reduce color changes in the displayed image during low-frequency driving (which might otherwise be caused by the voltage drop), thereby achieving stable operation under such conditions. Therefore, by forming the first transistor T1 to the sixth transistor T6 with an oxide semiconductor material, embodiments can provide a display device that can suppress leakage current while simultaneously reducing overall power consumption.

[0064] In addition to reducing leakage current and supporting low-frequency operation, the use of oxide semiconductor materials in all of the transistors T1 to T6 in the embodiment also helps to stabilize the current characteristics of the pixel circuit across the shared data line DL. In the embodiments of this disclosure, the first pixel circuit PC1 (see...) Figure 4 ) and the second pixel circuit PC2 (see Figure 4 Driven by different gate signals, but symmetrically set and electrically balanced using matched parasitic structures. The uniform electrical behavior achievable through oxide semiconductors can help suppress variations in threshold voltage drift and help maintain brightness consistency regardless of differences in gate timing.

[0065] Figure 2 The pixel circuit PC shown includes six transistors, but this disclosure is not limited thereto. For example, according to an embodiment, the pixel circuit PC may have five or fewer transistors, or seven or more.

[0066] Figure 3 This is a schematic cross-sectional view showing a portion of the display device 1 according to an embodiment.

[0067] refer to Figure 3 The display device 1 may include light-emitting diodes (LEDs) disposed in the display area DA. The LEDs are disposed on the substrate 100, and the pixel circuitry PC may be disposed between the substrate 100 and the LEDs. According to an embodiment, Figure 3 The diagram shows a first transistor T1, a storage capacitor Cst, and a holding capacitor Chold, which are some components of the pixel circuit PC. However, the pixel circuit PC is not limited to this.

[0068] The first transistor T1 may include a first semiconductor layer A1 and a first gate electrode G1 overlapping the first semiconductor layer A1. The first transistor T1 may be a driving transistor.

[0069] The storage capacitor Cst may include a first storage electrode C11, a second storage electrode C12, and a third storage electrode C13 disposed in different layers and overlapping each other.

[0070] The first storage electrode C11 and the third storage electrode C13 can be connected to each other through a contact hole. The second storage electrode C12 can be connected to the first gate electrode G1. The second storage electrode C12 can be integrated with the first gate electrode G1. The third storage electrode C13 can be connected to the first semiconductor layer A1 through a contact hole.

[0071] The holding capacitor Chold may include a first holding electrode C21, a second holding electrode C22, a third holding electrode C23, and a fourth holding electrode C24 disposed in different layers and overlapping each other.

[0072] The first holding electrode C21 and the third holding electrode C23 can be connected to each other through contact holes. The second holding electrode C22 and the fourth holding electrode C24 can receive the same constant voltage. The first holding electrode C21 can be connected to the first storage electrode C11. The first holding electrode C21 can be integrated with the first storage electrode C11. The second holding electrode C22 can be disposed in the same layer as the first semiconductor layer A1. The third holding electrode C23 can be integrated with the third storage electrode C13. The fourth holding electrode C24 can be integrated with the first wiring PLb.

[0073] For example, see the reference below. Figures 11 to 13 Further described, in the embodiment, the configuration of the holding capacitor Chold, including the integration of the fourth holding electrode C24 with the first wiring PLb, allows the capacitance of the holding capacitor Chold to be adjusted by modifying the degree of overlap between the fourth holding electrode C24 and the underlying third holding electrode C23. This arrangement allows different capacitance values ​​to be applied to the holding capacitors of adjacent pixel circuits (such as the first pixel circuit PC1 and the second pixel circuit PC2), even when they share a common data line DL. By adjusting the capacitor structure in this way, the embodiment can maintain uniform current drive characteristics and reduce brightness deviations that may be caused by variations in signal timing.

[0074] Substrate 100 may comprise a glass material or a polymer resin. According to an embodiment, substrate 100 may have an alternating stacked structure comprising a base layer of polymer resin and a barrier layer comprising an inorganic insulating material (such as, for example, silicon oxide or silicon nitride). The polymer resin may include polymer resins such as, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0075] A lower metal layer BML and a lower driving voltage line PLA can be disposed on the substrate 100. The lower metal layer BML can perform the functions of the first storage electrode C11 of the storage capacitor Cst and the first holding electrode C21 of the holding capacitor Chold. In other words, the lower metal layer BML may include the first storage electrode C11 and the first holding electrode C21. The first storage electrode C11 and the first holding electrode C21 can be disposed on the substrate 100.

[0076] The lower drive voltage line PLA can be configured to transmit the drive voltage ELVDD (see [link]). Figure 2 ) wiring.

[0077] The lower metal layer BML and the lower driving voltage line PLA can comprise one or more materials, such as, for example, aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). According to some embodiments, the lower metal layer BML can be a single layer of Mo, a bilayer structure with Mo and Ti layers stacked, or a trilayer structure with Ti, Al, and Ti layers stacked.

[0078] A first insulating layer 111 may be disposed on the substrate 100 to cover the lower metal layer BML and the lower driving voltage line PLA. In other words, the first insulating layer 111 may cover the first storage electrode C11 of the storage capacitor Cst and the first holding electrode C21 of the holding capacitor Chold. The first insulating layer 111 may comprise an inorganic insulating material such as, for example, silicon oxide, silicon nitride, or silicon nitride, and may have a single-layer or multi-layer structure comprising the inorganic insulating material. A semiconductor layer may be disposed on the first insulating layer 111.

[0079] A semiconductor layer can be disposed on the first insulating layer 111. At this point, Figure 3 A first semiconductor layer A1 of a first transistor T1 and a second holding electrode C22 of a holding capacitor Chold are shown disposed on a first insulating layer 111. The first semiconductor layer A1 may include a channel region CH1 and conductive regions disposed on opposite sides of the channel region CH1, and at this point, Figure 3 A first region B1, which is one of the conductive regions, is shown on one side of the channel region CH1. The second holding electrode C22 of the holding capacitor Chold may comprise the same material as the first semiconductor layer A1 and may be conductive. The second holding electrode C22 may overlap with the first holding electrode C21, and a first insulating layer 111 is placed between the second holding electrode C22 and the first holding electrode C21.

[0080] The first semiconductor layer A1 and the second holding electrode C22 of the holding capacitor Chold can comprise at least one oxide semiconductor material, such as, for example, indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the first semiconductor layer A1 can comprise an InSnZnO (ITZO) semiconductor layer or an InGaZnO (IGZO) semiconductor layer. Conductive processes based on plasma processing can be performed in certain regions of the first semiconductor layer A1 and the second holding electrode C22.

[0081] A second insulating layer 112 may be disposed on the first insulating layer 111 to cover the first semiconductor layer A1 and the second holding electrode C22 of the holding capacitor Chold. The second insulating layer 112 may comprise an inorganic insulating material such as, for example, silicon oxide, silicon nitride, or silicon nitride, and may have a single-layer or multi-layer structure comprising the inorganic insulating material.

[0082] A first conductive layer CL1 may be disposed on the second insulating layer 112. The first conductive layer CL1 may perform the functions of the first gate electrode G1 and the second storage electrode C12 of the storage capacitor Cst. In other words, the first conductive layer CL1 may include the first gate electrode G1 and the second storage electrode C12 of the storage capacitor Cst. The first gate electrode G1 may overlap with the channel region CH1 of the first semiconductor layer A1, and the second insulating layer 112 is located between the first gate electrode G1 and the channel region CH1. The second storage electrode C12 may overlap with the first storage electrode C11, and the first insulating layer 111 and the second insulating layer 112 are located between the second storage electrode C12 and the first storage electrode C11.

[0083] The first conductive layer CL1 may include one or more materials, such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). According to some embodiments, the first conductive layer CL1 may be a single Mo layer, may have a bilayer structure in which Mo and Ti layers are stacked, or may have a trilayer structure in which Ti, Al, and Ti layers are stacked.

[0084] The third insulating layer 113 may be disposed on the second insulating layer 112 and cover the first conductive layer CL1. The third insulating layer 113 may be disposed on the first gate electrode G1 and the second storage electrode C12 of the storage capacitor Cst. The third insulating layer 113 may include an inorganic insulating material such as, for example, silicon oxide, silicon nitride, or silicon nitride, and may have a single-layer or multi-layer structure including the inorganic insulating material.

[0085] The first electrode layer CL2, data line DL, and connection electrode CM can be disposed on the third insulating layer 113. The first electrode layer CL2 can perform the functions of the third storage electrode C13 of the storage capacitor Cst and the third holding electrode C23 of the holding capacitor Chold. The first electrode layer CL2 can be connected to the lower metal layer BML of the first semiconductor layer A1 and the first region B1 through contact holes, respectively. In other words, the third storage electrode C13 can be connected to the first storage electrode C11 through contact holes. The third storage electrode C13 can overlap with the second storage electrode C12, and the third insulating layer 113 is disposed between the third storage electrode C13 and the second storage electrode C12. The third holding electrode C23 can overlap with the second holding electrode C22, and the second insulating layer 112 and the third insulating layer 113 are disposed between the third holding electrode C23 and the second holding electrode C22.

[0086] The data line DL can be disposed in the same layer as the first electrode layer CL2. The data line DL can also be disposed in the same layer as the third storage electrode C13 and the third holding electrode C23. The connecting electrode CM can connect the second holding electrode C22 and the lower drive voltage line PLA to each other via contact holes. In other words, the second holding electrode C22 can be connected to the lower drive voltage line PLA via the connecting electrode CM and receives a drive voltage as a constant voltage.

[0087] The first electrode layer CL2, the data line DL, and the connecting electrode CM may each comprise one or more materials, such as, for example, aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). According to some embodiments, the first electrode layer CL2, the data line DL, and the connecting electrode CM may be a single layer of Mo, may have a bilayer structure in which Mo and Ti layers are stacked, or may have a trilayer structure in which Ti, Al, and Ti layers are stacked.

[0088] A fourth insulating layer 114 may be disposed on the third insulating layer 113 and cover the first electrode layer CL2, the data line DL, and the connection electrode CM. The fourth insulating layer 114 may include an organic insulating material. For example, the fourth insulating layer 114 may include photoresist, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, polymer derivatives having phenol-based groups, acryloyl-based polymers, imide-based polymers, aryl ether-based polymers, amide-based polymers, fluorine-based polymers, p-xylene-based polymers, vinyl alcohol-based polymers, or compounds thereof.

[0089] The first wiring PLb may be disposed on the fourth insulating layer 114. In an embodiment, a portion of the first wiring PLb may perform the function of the fourth holding electrode C24 of the holding capacitor Chold. In an embodiment, the fourth holding electrode C24 may be provided as a portion of the first wiring PLb. The fourth holding electrode C24 may be disposed on the fourth insulating layer 114 and may overlap with the third holding electrode C23, with the fourth insulating layer 114 disposed between the fourth holding electrode C24 and the third holding electrode C23. The first wiring PLb may be a wiring configured to transmit a constant voltage and may include, for example, a drive voltage line, an initialization voltage line, a sustaining voltage line, or a reference voltage line.

[0090] According to some implementations, the overlap area between the first wiring PLb and the third holding electrode C23 can be selectively adjusted to modify the effective capacitance of the holding capacitor Chold. Since the first wiring PLb can serve as both a constant voltage line and a fourth holding electrode C24, its layout can be adapted to each pixel circuit to compensate for differences in gate timing or signal interference. For example, in adjacent pixel circuits sharing the same data line DL but receiving different gate signals, the shape or continuity of the first wiring PLb above the third holding electrode C23 can be varied to maintain consistent current-driven behavior and reduce the possibility of brightness deviation.

[0091] The first wiring PLb and the fourth holding electrode C24 may each comprise one or more materials, such as, for example, aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). According to some embodiments, the first wiring PLb and the fourth holding electrode C24 may be a single layer of Mo, may have a bilayer structure in which Mo and Ti layers are stacked, or may have a trilayer structure in which Ti, Al, and Ti layers are stacked.

[0092] The fifth insulating layer 115 may be disposed on the fourth insulating layer 114 and cover the first wiring PLb and the fourth holding electrode C24. The fifth insulating layer 115 may include an organic insulating material. For example, the fifth insulating layer 115 may include photoresist, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene, polymer derivatives having phenol-based groups, acryloyl-based polymers, imide-based polymers, aryl ether-based polymers, amide-based polymers, fluorine-based polymers, p-xylene-based polymers, vinyl alcohol-based polymers, or compounds thereof.

[0093] The light-emitting diode (LED) can be disposed on the fifth insulating layer 115. The LED may include a pixel electrode 210, an emitting layer 222, and a counter electrode 230.

[0094] Pixel electrode 210 may be disposed on the fifth insulating layer 115. Pixel electrode 210 may include a reflective layer, which may include, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. According to an embodiment, pixel electrode 210 may also include a conductive oxide layer on and / or below the reflective layer. The conductive oxide layer may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or zinc aluminum oxide (AZO). According to an embodiment, pixel electrode 210 may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0095] A dam layer 123 may be disposed on the pixel electrode 210. The dam layer 123 may include an opening 123OP overlapping the pixel electrode 210 and may cover the edge of the pixel electrode 210. The dam layer 123 may include an organic insulating material. According to some embodiments, the dam layer 123 may include a light-transmitting organic insulating material. According to some embodiments, the dam layer 123 may include an organic insulating material containing a light-shielding material. According to some embodiments, the dam layer 123 may include a polyimide (PI)-based binder and a mixture therein of red, green, and blue pigments. According to some embodiments, the dam layer 123 may include a carbon-based binder resin and a mixture of lactam black and blue pigments. According to some embodiments, the dam layer 123 may include carbon black. The dam layer 123 may enhance the contrast of the display device 1.

[0096] Spacers 125 may be disposed on the dam layer 123. Spacers 125 may comprise a material different from that of the dam layer 123. For example, the dam layer 123 and spacers 125 may comprise different materials (e.g., the dam layer 123 may comprise a negative photosensitive material, while the spacers 125 may comprise a positive photosensitive material) and may be formed by separate masking processes. According to an embodiment, spacers 125 may comprise the same material as the dam layer 123 and may be formed together with the dam layer 123 by the same masking process (e.g., a halftone masking process).

[0097] The emitting layer 222 may include high-molecular-weight organic materials or low-molecular-weight organic materials that emit light of a specific color. Depending on the light-emitting diode (LED), the emitting layer 222 may include materials that emit red, green, or blue light.

[0098] Functional layers may be further disposed below and / or above the emitter layer 222. For example, a first functional layer 221 may be further disposed between the pixel electrode 210 and the emitter layer 222, and a second functional layer 223 may be further disposed between the emitter layer 222 and the opposing electrode 230 described below. The first functional layer 221 may include a hole transport layer and / or a hole injection layer. The second functional layer 223 may include an electron transport layer and / or an electron injection layer.

[0099] The counter electrode 230 may include a conductive material having a low work function. For example, the counter electrode 230 may include a (semi-)transparent layer comprising, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or alloys thereof. The counter electrode 230 may also include a layer comprising, for example, ITO, IZO, ZnO, or In2O3, on the (semi-)transparent layer comprising such a material.

[0100] Unlike the pixel electrode 210, which is individually formed to correspond to the light-emitting diode (LED), the opposing electrode 230 can extend to correspond to the pixel electrode 210. For example, the pixel electrode 210 of one LED and the pixel electrode 210 of another LED can be separated from each other and spaced apart, but the opposing electrode 230, which overlaps with the pixel electrode 210, can extend to cover the pixel electrode 210.

[0101] The encapsulation layer 300 can be disposed on the light-emitting diode (LED) and includes at least one inorganic encapsulation layer and at least one organic encapsulation layer. According to an embodiment, Figure 3 The encapsulation layer 300 is shown to include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330.

[0102] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may comprise at least one inorganic insulating material, such as, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon nitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be a single layer or multiple layers comprising the above materials. The organic encapsulation layer 320 may comprise a polymer-based material. Examples of polymer-based materials may include acrylic resins, epoxy resins, polyimides, and polyethylene. According to an embodiment, the organic encapsulation layer 320 may comprise acrylates.

[0103] Figure 4 This is a schematic plan view showing a portion of the wiring and pixel circuitry arranged in the display area DA of the display device 1 according to an embodiment.

[0104] refer to Figure 4 The display device 1 may include a first gate line GWL1 and a first gate line GWL2 extending in a first direction (x-axis direction), and a data line DL and a wiring WL extending in a second direction (y-axis direction) intersecting the first direction. Furthermore, the display device 1 may include a lower drive voltage line PLA extending in the first direction and a first wiring PLb extending in the second direction.

[0105] The pixel circuitry PC can be positioned within the display area DA along a first direction (e.g., the +x-axis direction and / or the -x-axis direction) and a second direction (e.g., the +y-axis direction and / or the -y-axis direction), and Figure 4 The diagram shows a first pixel circuit PC1 and a second pixel circuit PC2 arranged adjacent to each other in the same row (e.g., in the i-th row (where i is a natural number greater than 0)).

[0106] According to an embodiment, the first pixel circuit PC1 and the second pixel circuit PC2 can share a data line DL. In other words, the second transistors of the first pixel circuit PC1 and the second pixel circuit PC2 can be connected to the same data line DL. The first pixel circuit PC1 and the second pixel circuit PC2 can be arranged along a first direction, and the data line DL is disposed between the first pixel circuit PC1 and the second pixel circuit PC2. The data line DL can extend in a second direction between the first pixel circuit PC1 and the second pixel circuit PC2.

[0107] According to the implementation, the first pixel circuit PC1 and the second pixel circuit PC2 share a data line DL, and therefore, the number of data lines DL can be reduced, and thus the number of IC chips configured to provide data signals can be reduced, thereby reducing power consumption and cost.

[0108] Furthermore, by sharing the data line DL, the data line DL can be placed on one side of the pixel circuit PC, and other wiring WL can be placed on the other side of the pixel circuit PC in the same layer as the data line DL, thereby effectively utilizing the available space. For example, wiring WL can be used as an initialization voltage line, configured as a sustaining voltage line to transmit a common voltage, etc.

[0109] In a configuration where adjacent pixel circuits (such as the first pixel circuit PC1 and the second pixel circuit PC2) share a single data line DL, each pixel circuit can be controlled by a different gate line. As a result, signal timing and transistor switching behavior can vary between the two pixel circuits regardless of their physical symmetry. While this arrangement can improve wiring efficiency and reduce the number of data lines and driver ICs, it can also introduce electrical imbalances that may lead to inconsistencies in pixel operation or brightness.

[0110] To address this issue, according to one implementation, circuit elements with different capacitance values, such as holding capacitors Chold, can be formed in the corresponding pixel circuits. Additionally, the layout structure integrated with the fourth holding electrode C24 (such as the first wiring PLb) can be selectively patterned to control overlap with the underlying electrode layer (such as the third holding electrode C23). This approach allows for fine-tuning of the electrical behavior of each pixel circuit PC based on its gate drive conditions, providing stable and uniform display performance even in a shared-line architecture.

[0111] A first pixel circuit PC1 can be connected to a first light-emitting diode (LED) to drive the first LED, and a second pixel circuit PC2 can be connected to a second LED to drive the second LED. According to the embodiment, the first and second LEDs can emit light of the same color. In other words, the pixel circuit PCs sharing the data line DL can be connected to LEDs emitting light of the same color. Therefore, the brightness difference due to color can be ignored, and thus, power consumption can be reduced.

[0112] The pixel circuit PC of the shared data line DL can receive different gate signals. The first pixel circuit PC1 can be connected to the first-to-first gate line GWL1, and the second pixel circuit PC2 can be connected to the first-to-second gate line GWL2. The pixel circuit PC located on the left side of the shared data line DL can be connected to the first-to-first gate line GWL1, and the pixel circuit PC located on the right side of the shared data line DL can be connected to the first-to-second gate line GWL2.

[0113] The driving voltage line PL may include a lower driving voltage line PLA and a first wiring PLb disposed in different layers. In this case, the first wiring PLb may be an upper driving voltage line. The lower driving voltage line PLA may extend in a first direction, and the first wiring PLb, as the upper driving voltage line, may extend in a second direction. The lower driving voltage line PLA and the first wiring PLb, as the upper driving voltage line, may be connected to each other via contact holes CNT to form a mesh structure. Corresponding to some pixel circuits, the first wiring PLb may be an initialization voltage line, a sustaining voltage line, a reference voltage line, or wiring configured to transmit a constant voltage. In this case, in the embodiment, the first wiring PLb is not connected to the lower driving voltage line PLA.

[0114] Figure 5 This is a schematic diagram showing the layout of the first transistor T1 to the sixth transistor T6, the storage capacitor Cst, and the holding capacitor Chold in a pixel circuit included in a display device according to an embodiment. Figures 6 to 10 It is shown schematically. Figure 5 The layout diagram of the components (such as, for example, the first transistor T1 to the sixth transistor T6, the storage capacitor Cst, and the holding capacitor Chold) of the display device for each layer.

[0115] like Figures 5 to 10 As shown, the display device may include a first pixel circuit PC1 and a second pixel circuit PC2, which are arranged parallel to each other in a first direction, and a data line DL is disposed between them. Figures 5 to 10 The structure shown can be repeated in the first direction (x-axis direction) and / or the second direction (y-axis direction).

[0116] The first pixel circuit PC1 and the second pixel circuit PC2 may each include a first transistor T1 through a sixth transistor T6, a storage capacitor Cst, and a holding capacitor Chold. Based on the data line DL, most of the components included in the first pixel circuit PC1 may be symmetrical with those included in the second pixel circuit PC2. According to some embodiments, some components may not be symmetrical. For example, based on the data line DL, the second transistor T2 and the third transistor T3 may not be symmetrical. Furthermore, the capacitances of the storage capacitor Cst and / or the holding capacitor Chold may be different from each other.

[0117] refer to Figure 3 and Figure 6The first-first lower gate line GWL1a, the first-second lower gate line GWL2a, the reference voltage line VRL, the second gate line GRL, the lower metal layer BML, the lower drive voltage line PLA, the sustaining voltage line VSSL, the first initialization voltage line VAL1, and the second initialization voltage line VAL2 can be disposed on the substrate 100.

[0118] The first-first lower gate line GWL1a, the first-second lower gate line GWL2a, the reference voltage line VRL, the second gate line GRL, the lower drive voltage line PLA, the sustaining voltage line VSSL, the first initialization voltage line VAL1, and the second initialization voltage line VAL2 can extend in the first direction (x-axis direction).

[0119] The first-first lower gate line GWL1a can be configured to transmit the first gate signal GW to the first pixel circuit PC1 (see...). Figure 2 Furthermore, the first-second lower gate line GWL2a can be configured to transmit the first gate signal GW to the second pixel circuit PC2. The reference voltage line VRL can be configured to transmit the reference voltage Vref, and the second gate line GRL can be configured to transmit the second gate signal GR (see [link to relevant documentation]). Figure 2 The sustaining voltage line VSSL can be configured to transmit the common voltage ELVSS (see [link]). Figure 2 ).

[0120] The lower drive voltage line PLA can be configured to transmit the drive voltage ELVDD (see [link]). Figure 2 The lower drive voltage line PLA may include a shielding portion SHP protruding in the y-axis direction between the first pixel circuit PC1 and the second pixel circuit PC2. A constant voltage is applied to the shielding portion SHP, and thus, interference caused by unintentional electrical signals that may be applied to the pixel circuits can be blocked.

[0121] In a pixel layout where the first pixel circuit PC1 and the second pixel circuit PC2 share a data line DL but are driven by different gate signals, maintaining electrical separation between the circuits typically becomes important for signal integrity. According to an embodiment, a shielded portion SHP formed as a protrusion of the lower drive voltage line PLA between the circuits can help reduce unwanted coupling between adjacent components by applying a constant voltage in the inter-pixel region. Even under different control conditions, this arrangement can help stabilize the current flowing in each circuit and support consistent brightness output.

[0122] The first initialization voltage line VAL1 can be configured to transmit a first initialization voltage to a pixel circuit configured to drive green and blue pixels. The second initialization voltage line VAL2 can be configured to transmit a second initialization voltage to a pixel circuit configured to drive a red pixel. According to some embodiments, the first initialization voltage and the second initialization voltage can have different values.

[0123] The lower metal layer BML can have an isolated shape and can be configured for each pixel circuit. The lower metal layer BML can perform the functions of the first storage electrode C11 and the first holding electrode C21. The lower metal layer BML can overlap with the first semiconductor layer A1 and the first gate electrode G1 described below, and therefore, can prevent or reduce light incident from the outside onto the first semiconductor layer A1. The lower metal layer BML can serve as the lower gate electrode of the first transistor T1.

[0124] First insulating layer 111 (see...) Figure 3 The first-first lower gate line GWL1a, the first-second lower gate line GWL2a, the reference voltage line VRL, the lower metal layer BML, the lower drive voltage line PLA, the sustaining voltage line VSSL, the first initialization voltage line VAL1, and the second initialization voltage line VAL2 can be set on the first-first lower gate line GWL1a, the first-second lower gate line GWL2a, the reference voltage line VRL, the lower metal layer BML, the lower drive voltage line PLA, the sustaining voltage line VSSL, the first initialization voltage line VAL1, and the second initialization voltage line VAL2.

[0125] refer to Figure 3 and Figure 7 The first semiconductor layer A1 to the sixth semiconductor layer A6 and the second holding electrode C22 can be disposed on the first insulating layer 111. The first semiconductor layer A1 to the sixth semiconductor layer A6 and the second holding electrode C22 can be made of the same material.

[0126] The first semiconductor layer A1 and the fifth semiconductor layer A5 can be integrally connected to each other. The second semiconductor layer A2 and the third semiconductor layer A3 can be integrally connected to each other. The fourth semiconductor layer A4 and the sixth semiconductor layer A6 can be integrally connected to each other. The first semiconductor layer A1 can be disposed adjacent to the second semiconductor layer A2 and the third semiconductor layer A3, while being separated from and spaced apart from the second semiconductor layer A2 and the third semiconductor layer A3. The fifth semiconductor layer A5 can be disposed adjacent to the sixth semiconductor layer A6, while being separated from and spaced apart from the sixth semiconductor layer A6.

[0127] The second holding electrode C22 may overlap with the lower metal layer BML. At least a portion of the lower metal layer BML that overlaps with the second holding electrode C22 may be the first holding electrode C21 of the holding capacitor Chold. The second holding electrode C22 may have an isolated shape and may be configured for each pixel circuit. A portion of the second holding electrode C22 may overlap with the lower drive voltage line PLA and may be electrically connected to the lower drive voltage line PLA to transmit the drive voltage.

[0128] Second insulating layer 112 (see Figure 3 ) can be set Figure 7 The structure shown is, for example, provided on the first semiconductor layer A1 to the sixth semiconductor layer A6 and the second holding electrode C22.

[0129] refer to Figure 3 and Figure 8 The first-first upper gate line GWL1b, the first-second upper gate line GWL2b, the third gate line EML, the fourth gate line GBL, the fifth gate line EMBL, the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 can be disposed on the second insulating layer 112.

[0130] The first-first upper gate line GWL1b, the first-second upper gate line GWL2b, the third gate line EML, the fourth gate line GBL, and the fifth gate line EMBL can extend in the first direction (x-axis direction).

[0131] The first-first upper gate line GWL1b can be configured to transmit the first gate signal GW to the first pixel circuit PC1 (see...). Figure 2 The first-second upper gate line GWL2b can be configured to transmit the first gate signal GW to the second pixel circuit PC2. The first-first upper gate line GWL1b can overlap with the first-first lower gate line GWL1a. The first-second upper gate line GWL2b can overlap with the first-second lower gate line GWL2a. The first-first gate line GWL1 can include the first-first upper gate line GWL1b and the first-first lower gate line GWL1a. The first-second gate line GWL2 can include the first-second upper gate line GWL2b and the first-second lower gate line GWL2a.

[0132] The third gate line EML can transmit the third gate signal EM, the fourth gate line GBL can transmit the fourth gate signal GB, and the fifth gate line EMBL can transmit the fifth gate signal EMB. The third gate line EML can be the first emit control line, and the fifth gate line EMBL can be the second emit control line.

[0133] The first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 may have isolated shapes. The first gate electrode G1 may overlap with the first semiconductor layer A1 to form the first transistor T1. The first gate electrode G1 may perform the function of the second storage electrode C12 of the storage capacitor Cst. The first gate electrode G1 may overlap with the lower metal layer BML.

[0134] The second gate electrode G2 can overlap with the second semiconductor layer A2 to form the second transistor T2. The third gate electrode G3 can overlap with the third semiconductor layer A3 to form the third transistor T3.

[0135] The third gate line EML can overlap with the fifth semiconductor layer A5, and the portion of the third gate line EML that overlaps with the fifth semiconductor layer A5 can function as the fifth gate electrode. The fourth gate line GBL can overlap with the fourth semiconductor layer A4, and the portion of the fourth gate line GBL that overlaps with the fourth semiconductor layer A4 can function as the fourth gate electrode. The fifth gate line EML can overlap with the sixth semiconductor layer A6, and the portion of the fifth gate line EML that overlaps with the sixth semiconductor layer A6 can function as the sixth gate electrode.

[0136] Third insulating layer 113 (see Figure 3 ) can be set Figure 8 The structure shown is on the diagram.

[0137] refer to Figure 3 and Figure 9 The data line DL, the first electrode layer CL2, and the connecting electrodes CM and CM' can be disposed on the third insulating layer 113. The data line DL, the first electrode layer CL2, and the connecting electrodes CM and CM' can all be made of the same material.

[0138] The data line DL can extend in a second direction (y-axis direction) between the first pixel circuit PC1 and the second pixel circuit PC2. The first pixel circuit PC1 and the second pixel circuit PC2 can share the data line DL.

[0139] The first electrode layer CL2 may include a third storage electrode C13 for the storage capacitor Cst and a third holding electrode C23 for the holding capacitor Chold. Connecting electrodes CM and CM' may be used to connect components disposed beneath it to each other. The first electrode layer CL2 and the connecting electrodes CM and CM' may be provided in an isolated configuration.

[0140] Fourth insulating layer 114 (see Figure 3 ) can be set Figure 9 The structure shown is on the diagram.

[0141] refer to Figure 3 and Figure 10The first wiring PLb can be disposed on the fourth insulating layer 114. The first wiring PLb can extend in a second direction. The first wiring PLb can overlap with the first electrode layer CL2. The first wiring PLb can branch into two branches in the region overlapping with the first electrode layer CL2. In an embodiment, the first wiring PLb can include a first branch PLb1 and a second branch PLb2. In an embodiment, the first wiring PLb can include an opening PL_OP in the region overlapping with the first electrode layer CL2, from which a central portion has been removed. The first wiring PLb disposed on opposite sides of the opening PL_OP can be referred to as the first branch PLb1 and the second branch PLb2, respectively. The first branch PLb1 can overlap with the second gate electrode G2 of the second transistor T2. The second branch PLb2 can overlap with the third gate electrode G3 of the third transistor T3.

[0142] The first electrode layer CL2 can perform the function of the third holding electrode C23 for holding capacitor Chold, and the region of the first wiring PLb that overlaps with the first electrode layer CL2 can perform the function of the fourth holding electrode C24 for holding capacitor Chold. In other words, the first branch PLb1 and the second branch PLb2 can perform the function of the fourth holding electrode C24 for holding capacitor Chold.

[0143] By altering the geometry of the first wiring PLb in the region overlapping with the first electrode layer CL2, the effective capacitance of the holding capacitor Chold can be adjusted on a per-pixel circuit basis. For example, by extending or segmenting the first branch PLb1 or the second branch PLb2, the overlap area with the underlying electrode layer can be increased or decreased. This allows for independent customization of the capacitance values ​​for the holding capacitors of the first pixel circuit PC1 and the second pixel circuit PC2, even if the circuits share a common data line DL. This structural flexibility allows for compensation of differences in gate signal timing or parasitic coupling and can help maintain uniform electrical and optical behavior across the display.

[0144] The first pixel circuit PC1 and the second pixel circuit PC2 are respectively connected to the first-first gate line GWL1 and the first-second gate line GWL2 to receive the first gate signal. Due to this mechanism, there may be a brightness difference between the first light-emitting diode driven by the first pixel circuit PC1 and the second light-emitting diode driven by the second pixel circuit PC2.

[0145] To reduce this brightness difference, the capacitance of the storage capacitor Cst and / or the holding capacitor Chold of the first pixel circuit PC1 can be different from the capacitance of the storage capacitor Cst and / or the holding capacitor Chold of the second pixel circuit PC2.

[0146] The dispersion of current deviation can be reduced by adjusting the values ​​of the storage capacitor Cst and / or the holding capacitor Chold for each pixel circuit while simultaneously adjusting the interference between the gate signal and the first electrode layer CL2 to be the same. Embodiments of this disclosure provide structures that can reduce such current deviation.

[0147] Figure 11 This is a plan view of some components of a display device according to an embodiment. For example, Figure 11 The diagram shows a second gate electrode G2, a third gate electrode G3, a first electrode layer CL2, and a first wiring PLb included in a first pixel circuit PC1 and a second pixel circuit PC2 with a shared data line DL.

[0148] refer to Figure 11 The first electrode layer CL2 may include a first gap GA1 spaced apart from the second gate electrode G2 in the plan view. Furthermore, the first electrode layer CL2 may include a second gap GA2 spaced apart from the third gate electrode G3 in the plan view.

[0149] In one embodiment, the area covered by the first wiring PLb of the first pixel circuit PC1 covering the first gap GA1 and the second gap GA2 can be the same as the area covered by the first wiring PLb of the second pixel circuit PC2 covering the first gap GA1 and the second gap GA2.

[0150] The first wiring PLb may at least partially cover the first gap GA1. The first wiring PLb may at least partially cover the second gap GA2. The first wiring PLb may branch into a first branch PLb1 and a second branch PLb2. The first branch PLb1 may be continuously arranged from the second gate electrode G2 to the first electrode layer CL2. The second branch PLb2 may be continuously arranged from the third gate electrode G3 to the first electrode layer CL2. The first wiring PLb may be a wiring configured to transmit a constant voltage.

[0151] This arrangement can also be applied to the first pixel circuit PC1 and the second pixel circuit PC2 that share the data line DL.

[0152] The gate signals applied to the second gate electrode G2 and the third gate electrode G3 may induce coupling signals in the first electrode layer CL2. Therefore, parasitic capacitance may occur in the pixel circuit, which may cause current deviations in the pixel circuit.

[0153] In one implementation, the first wiring PLb covers the first gap GA1 and the second gap GA2 in the first pixel circuit PC1 and the second pixel circuit PC2 with the same area, thereby adjusting the parasitic capacitance formed in the first pixel circuit PC1 and the parasitic capacitance formed in the second pixel circuit PC2 to the same value.

[0154] With the above arrangement, the effect of gate signal coupling on the pixel circuit PC can be controlled by managing the spatial relationship between the gate electrode and the constant voltage wiring (such as the first wiring PLb). When the parasitic capacitances associated with the first gap GA1 and the second gap GA2 are matched between the first pixel circuit PC1 and the second pixel circuit PC2, the current characteristics of the two circuits can be aligned more closely, regardless of differences in gate control timing. This can help maintain consistent brightness between adjacent pixels operating across a shared data line DL but under separate gate signal conditions.

[0155] Figure 12 This is a plan view of some components of a display device according to an embodiment. Figure 12 In, with Figure 11 Similar reference numerals indicate similar components.

[0156] refer to Figure 12 The area covered by the first wiring PLb of the first pixel circuit PC1 covering the first gap GA1 and the second gap GA2 can be the same as the area covered by the first wiring PLb of the second pixel circuit PC2 covering the first gap GA1 and the second gap GA2.

[0157] In one implementation, the capacitance of the holding capacitor Chold of the first pixel circuit PC1 may be different from the capacitance of the holding capacitor Chold of the second pixel circuit PC2. The holding capacitor Chold may include a fourth holding electrode C24 provided as part of the first wiring PLb and a third holding electrode C23 provided as part of the first electrode layer CL2.

[0158] The first branch PLb1 of the fourth holding electrode C24 of the first pixel circuit PC1 can be continuously disposed in the region overlapping with the third holding electrode C23. The first branch PLb1 of the fourth holding electrode C24 of the second pixel circuit PC2 can include a discontinuous gap in the region overlapping with the third holding electrode C23. Therefore, the capacitance of the holding capacitor Chold of the first pixel circuit PC1 can be greater than the capacitance of the holding capacitor Chold of the second pixel circuit PC2. The capacitance of the holding capacitor Chold can be adjusted to reduce the brightness deviation of the light-emitting diodes connected to each pixel circuit.

[0159] In this way, according to the implementation, the physical pattern of the fourth holding electrode C24 can be selectively varied among pixel circuits PC that otherwise share structural symmetry, through branching or segmentation of the first branch PLb1. This method allows the capacitance of the holding capacitor Chold to be individually customized for each pixel circuit PC, even when the parasitic capacitance from the gate signal coupling is equal. By doing so, the pixel drive current can be modulated to compensate for variations in circuit behavior that may be caused by differences in gate signal timing or signal delay. As a result, uniform brightness output across the first pixel circuit PC1 and the second pixel circuit PC2 can be achieved, regardless of operation under asynchronous control.

[0160] Figure 13 This is a plan view of some components of a display device according to an embodiment. Figure 13 In, with Figure 11 Similar reference numerals indicate similar components.

[0161] refer to Figure 13 The area covered by the first wiring PLb of the first pixel circuit PC1 covering the first gap GA1 and the second gap GA2 can be the same as the area covered by the first wiring PLb of the second pixel circuit PC2 covering the first gap GA1 and the second gap GA2.

[0162] In this implementation, the first wiring PLb may at least partially cover the first gap GA1. The first wiring PLb may expose the second gap GA2, rather than covering it. In other words, similar to how the second gap GA2 of the first pixel circuit PC1 is exposed by the first wiring PLb, the second gap GA2 of the second pixel circuit PC2 may also be exposed by the first wiring PLb.

[0163] The first wiring PLb can branch into a first branch PLb1 and a second branch PLb2. The first branch PLb1 can be continuously arranged from the second gate electrode G2 to the first electrode layer CL2. The second branch PLb2 can expose the second gap GA2.

[0164] In this implementation, the area of ​​the first wiring PLb of the first pixel circuit PC1 overlapping with the first electrode layer CL2 may be different from the area of ​​the first wiring PLb of the second pixel circuit PC2 overlapping with the first electrode layer CL2. The area of ​​the second branch PLb2 of the first pixel circuit PC1 exposing the first electrode layer CL2 may be larger than the area of ​​the second branch PLb2 of the second pixel circuit PC2 exposing the first electrode layer CL2.

[0165] This can indicate that the capacitance of the holding capacitor Chold in the first pixel circuit PC1 is different from the capacitance of the holding capacitor Chold in the second pixel circuit PC2.

[0166] Figure 14 This is a plan view of some components of a display device according to an embodiment. Figure 14 In, with Figure 11 Similar reference numerals indicate similar components.

[0167] refer to Figure 14 The area covered by the first wiring PLb of the first pixel circuit PC1 covering the first gap GA1 and the second gap GA2 can be the same as the area covered by the first wiring PLb of the second pixel circuit PC2 covering the first gap GA1 and the second gap GA2.

[0168] In this implementation, the first wiring PLb may at least partially cover the first gap GA1. The first wiring PLb may expose the second gap GA2, rather than covering it. In other words, similar to how the second gap GA2 of the first pixel circuit PC1 is exposed by the first wiring PLb, the second gap GA2 of the second pixel circuit PC2 may also be exposed by the first wiring PLb.

[0169] The first wiring PLb can be provided as a narrow first wiring PLb, without being branched according to the first electrode layer CL2. This arrangement can be provided similarly for the first pixel circuit PC1 and the second pixel circuit PC2.

[0170] Figure 15 This is a plan view of some components of a display device according to an embodiment. For example, Figure 15 The diagram shows a first electrode layer CL2, a first wiring PLb, a first emission control line EML, and a second emission control line EMBL, all included in a first pixel circuit PC1 and a second pixel circuit PC2 with a shared data line DL.

[0171] refer to Figure 15 The first electrode layer CL2 may include a third gap GA3 spaced apart from the first transmit control line EML in the plan view. The first electrode layer CL2 may include a region that partially overlaps with the first transmit control line EML. The third gap GA3 may be disposed in the remaining region other than the overlapping region. In addition, the first electrode layer CL2 may include a fourth gap GA4 spaced apart from the second transmit control line EMBL in the plan view.

[0172] In one implementation, the area covered by the first wiring PLb of the first pixel circuit PC1 covering the third gap GA3 and the fourth gap GA4 can be the same as the area covered by the first wiring PLb of the second pixel circuit PC2 covering the third gap GA3 and the fourth gap GA4.

[0173] The first wiring PLb can cover the third gap GA3 and the fourth gap GA4. This arrangement can also be applied to the first pixel circuit PC1 and the second pixel circuit PC2.

[0174] The gate signals applied to the first emitter control line EML and the second emitter control line EMBL may induce coupling signals in the first electrode layer CL2. Therefore, parasitic capacitance may occur in the pixel circuit, which could lead to current deviations in the pixel circuit.

[0175] In one implementation, the first wiring PLb covers the third gap GA3 and the fourth gap GA4 in the first pixel circuit PC1 and the second pixel circuit PC2 with the same area, thereby adjusting the parasitic capacitance formed in the first pixel circuit PC1 and the parasitic capacitance formed in the second pixel circuit PC2 to the same value.

[0176] Figure 16 This is a plan view of some components of a display device according to an embodiment. Figure 16 In, with Figure 15 Similar reference numerals indicate similar components.

[0177] refer to Figure 16 The area covered by the first wiring PLb of the first pixel circuit PC1 covering the third gap GA3 and the fourth gap GA4 can be the same as the area covered by the first wiring PLb of the second pixel circuit PC2 covering the third gap GA3 and the fourth gap GA4.

[0178] The first wiring PLb can expose the central portion of the third gap GA3 and cover the fourth gap GA4. This arrangement can be applied similarly to the first pixel circuit PC1 and the second pixel circuit PC2. Therefore, the same parasitic capacitance can be formed in the first pixel circuit PC1 and the second pixel circuit PC2.

[0179] Figure 17 This is a plan view of some components of a display device according to an embodiment. Figure 17 In, with Figure 15 Similar reference numerals indicate similar components.

[0180] refer to Figure 17 The area covered by the first wiring PLb of the first pixel circuit PC1 covering the third gap GA3 and the fourth gap GA4 can be the same as the area covered by the first wiring PLb of the second pixel circuit PC2 covering the third gap GA3 and the fourth gap GA4.

[0181] The first wiring PLb can cover the third gap GA3 and expose the fourth gap GA4. This arrangement can be applied similarly to the first pixel circuit PC1 and the second pixel circuit PC2. Therefore, the same parasitic capacitance can be formed in the first pixel circuit PC1 and the second pixel circuit PC2.

[0182] In one embodiment, the first electrode layer CL2 may include a third gap GA3 spaced apart from the first emission control line EML in the plan view. A first wiring PLb may cover the third gap GA3 in both the first pixel circuit PC1 and the second pixel circuit PC2. The area of ​​the first wiring PLb covering the third gap GA3 in the first pixel circuit PC1 may be approximately equal to the area of ​​the first wiring PLb covering the third gap GA3 in the second pixel circuit PC2, which can reduce the variation in parasitic capacitance between adjacent pixel circuits PC.

[0183] In one implementation, the first electrode layer CL2 may include a fourth gap GA4 spaced apart from the second emitter control line EMBL in the plan view. Similar to the arrangement described for the third gap GA3, the first wiring PLb may at least partially cover the fourth gap GA4 in both the first pixel circuit PC1 and the second pixel circuit PC2. The area of ​​the first wiring PLb covering the fourth gap GA4 in the first pixel circuit PC1 may be approximately equal to the area of ​​the first wiring PLb covering the fourth gap GA4 in the second pixel circuit PC2, which helps to balance parasitic capacitances between adjacent pixel circuits.

[0184] refer to Figure 18 The area covered by the first wiring PLb of the first pixel circuit PC1 covering the third gap GA3 and the fourth gap GA4 can be the same as the area covered by the first wiring PLb of the second pixel circuit PC2 covering the third gap GA3 and the fourth gap GA4.

[0185] The first wiring PLb can expose most of the third gap GA3 and the fourth gap GA4. This arrangement can be applied similarly to the first pixel circuit PC1 and the second pixel circuit PC2. Therefore, the same parasitic capacitance can be formed in the first pixel circuit PC1 and the second pixel circuit PC2.

[0186] The above is for reference only. Figures 11 to 18 The described implementation can be modified in various ways, such as, for example, implemented individually or in combination with each other. According to the above implementation, the brightness difference between light-emitting diodes can be reduced by adjusting the capacitance values ​​of the storage capacitor and / or holding capacitor of the pixel circuit sharing the data line DL.

[0187] The display device according to the above embodiments can be applied to any of various electronic devices. The electronic device according to the embodiments may include the above-described display device, and may also include modules or devices with other additional functions in addition to the display device.

[0188] Figure 19 This is a block diagram of an electronic device 10 according to an embodiment. (See reference) Figure 19The electronic device 10 according to the embodiments may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0189] The processor 12 may include at least one of, for example, a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0190] The memory 13 can store data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0191] The power module 14 may include a power module (such as, for example, a power adapter or battery device) and a power conversion module configured to convert the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0192] At least one of the components of electronic device 10 may be included in the display device according to the above embodiments. Some of the individual modules that are functionally included in a single module may be included in the display device, and other modules may be provided separately from the display device. For example, the display device may include display module 11, and processor 12, memory 13, and power module 14 may be provided as other devices in electronic device 10 besides the display device.

[0193] Figure 20 Several schematic diagrams of electronic devices according to various embodiments are shown.

[0194] refer to Figure 20 According to the embodiments, the display device applied thereto can include not only image display electronic devices (such as, for example, smartphone 10_1a, tablet PC 10_1b, laptop PC 10_1c, television (TV) 10_1d and desktop monitor 10_1e), but also wearable electronic devices (such as, for example, smart glasses 10_2a, head-mounted display 10_2b and smartwatch 10_2c) and vehicle electronic devices 10_3 including display modules (such as, for example, vehicle dashboard, central instrument panel, central information display (CID) set on the dashboard and interior mirror display).

[0195] As described above, the display device and electronic device according to embodiments of the present disclosure can provide substantially the same parasitic capacitance for each pixel circuit, thereby resulting in high reliability.

[0196] While this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A display device, comprising: Substrate; The first-first gate line and the first-second gate line are spaced apart from each other and extend on the substrate in a first direction; The data cable extends in a second direction that intersects the first direction; as well as The first pixel circuit and the second pixel circuit are arranged along the first direction, and the data line is arranged between the first pixel circuit and the second pixel circuit. Wherein, the first pixel circuit is connected to the first-first gate line, and the second pixel circuit is connected to the first-second gate line, and Each of the first pixel circuit and the second pixel circuit includes: The first transistor includes a first semiconductor layer and a first gate electrode; The second transistor includes a second semiconductor layer and a second gate electrode, and is connected to the data line; A first electrode layer, connected to the first semiconductor layer, overlapping the first gate electrode, and including a first gap spaced apart from the second gate electrode in a plan view; and A first wiring is disposed above the first electrode layer, extends in the second direction, and covers at least a portion of the first gap in the plan view.

2. The display device according to claim 1, wherein, Each of the first pixel circuit and the second pixel circuit further includes a third semiconductor layer integrated with the second semiconductor layer and a third gate electrode overlapping the third semiconductor layer. The first electrode layer further includes a second gap spaced apart from the third gate electrode in the plan view, and The first wiring covers at least a portion of the second gap in the plan view.

3. The display device according to claim 2, wherein, The first wiring is branched into a first branch and a second branch. The first branch covers at least a portion of the first gap, and the second branch covers at least a portion of the second gap, and The second branch of the first pixel circuit is continuously disposed in the region overlapping with the first electrode layer, and the second branch of the second pixel circuit includes discontinuous gaps in the region overlapping with the first electrode layer.

4. The display device according to claim 1, wherein, Each of the first pixel circuit and the second pixel circuit further includes a third semiconductor layer integrated with the second semiconductor layer and a third gate electrode overlapping the third semiconductor layer. The first electrode layer further includes a second gap spaced apart from the third gate electrode in the plan view, and The first wiring exposes the second gap in the plan view.

5. The display device according to claim 4, wherein, The area where the first wiring of the first pixel circuit overlaps with the first electrode layer is different from the area where the first wiring of the second pixel circuit overlaps with the first electrode layer.

6. The display device according to claim 1, further comprising: The first and second launch control lines extend in the first direction. The first electrode layer further includes a third gap, which is a portion spaced apart from the first emission control line in the plan view. The area of ​​the third gap covered by the first wiring in the first pixel circuit is equal to the area of ​​the third gap covered by the first wiring in the second pixel circuit.

7. The display device according to claim 6, wherein, The first electrode layer further includes a fourth gap, which is a portion spaced apart from the second emission control line in the plan view. The area of ​​the fourth gap covered by the first wiring in the first pixel circuit is equal to the area of ​​the fourth gap covered by the first wiring in the second pixel circuit.

8. The display device according to claim 6, wherein, The first electrode layer at least partially overlaps with the first emission control line.

9. The display device according to claim 1, wherein, The first pixel circuit and the second pixel circuit share the data line.

10. The display device according to claim 1, further comprising: A first light-emitting diode is connected to the first pixel circuit; as well as The second light-emitting diode is connected to the second pixel circuit. The first LED and the second LED emit light of the same color.

11. The display device according to claim 1, wherein, Each of the first pixel circuit and the second pixel circuit further includes a holding capacitor, and The capacitance of the holding capacitor in the first pixel circuit is different from the capacitance of the holding capacitor in the second pixel circuit.

12. The display device according to claim 11, wherein, The holding capacitor includes: The first holding electrode is disposed below the first semiconductor layer; The second holding electrode is disposed in the same layer as the first semiconductor layer; A third holding electrode is integrated with the first electrode layer; and The fourth holding electrode is disposed above the third holding electrode. The fourth holding electrode is integrated with the first wiring.

13. The display device according to claim 1, wherein, The first wiring includes wiring configured to transmit a constant voltage.

14. An electronic device including a display device, wherein, The display device includes: Substrate; The first-first gate line and the first-second gate line are spaced apart from each other and extend on the substrate in a first direction; The data cable extends in a second direction intersecting the first direction; and The first pixel circuit and the second pixel circuit are arranged along the first direction, and the data line is arranged between the first pixel circuit and the second pixel circuit. Wherein, the first pixel circuit is connected to the first-first gate line, and the second pixel circuit is connected to the first-second gate line, and Each of the first pixel circuit and the second pixel circuit includes: The first transistor includes a first semiconductor layer and a first gate electrode; The second transistor includes a second semiconductor layer and a second gate electrode, and is connected to the data line; A first electrode layer, connected to the first semiconductor layer, overlapping the first gate electrode, and including a first gap spaced apart from the second gate electrode in a plan view; and A first wiring is disposed above the first electrode layer, extends in the second direction, and covers at least a portion of the first gap in the plan view.

15. The electronic device according to claim 14, wherein, Each of the first pixel circuit and the second pixel circuit further includes a third semiconductor layer integrated with the second semiconductor layer and a third gate electrode overlapping the third semiconductor layer. The first electrode layer further includes a second gap spaced apart from the third gate electrode in the plan view, and The area of ​​the first wiring of the first pixel circuit covering the second gap is equal to the area of ​​the first wiring of the second pixel circuit covering the second gap.

16. The electronic device according to claim 14, wherein, Each of the first pixel circuit and the second pixel circuit further includes a holding capacitor, and The capacitance of the holding capacitor in the first pixel circuit is different from the capacitance of the holding capacitor in the second pixel circuit.

17. The electronic device according to claim 14, wherein the display device further comprises: The first and second launch control lines extend in the first direction. The first electrode layer further includes a third gap, which is a portion spaced apart from the first emission control line in the plan view. The area of ​​the third gap covered by the first wiring in the first pixel circuit is equal to the area of ​​the third gap covered by the first wiring in the second pixel circuit.

18. The electronic device according to claim 14, wherein, The first pixel circuit and the second pixel circuit share the data line.

19. The electronic device according to claim 14, wherein, The first wiring includes wiring configured to transmit a constant voltage.

20. The electronic device according to claim 14, wherein, The electronic device is one of the following: smartphone, tablet PC, laptop PC, television, desktop monitor, smart glasses, head-mounted display, smartwatch, vehicle dashboard, central dashboard, central information display, and interior mirror display.

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