Manufacturing method of solder resist structure of homogeneous sandwich step and semiconductor device

Abstract

The application discloses a manufacturing method of a homogeneous sandwich step solder resist structure and a semiconductor device. The semiconductor device comprises a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, a passivation layer above the interlayer dielectric layer, and a homogeneous sandwich step solder resist structure. The homogeneous sandwich step solder resist structure comprises a first solder resist layer, a second solder resist layer, a plated metal layer and a third solder resist layer arranged in sequence above the passivation layer, forming a three-layer homogeneous solder resist sandwich structure. Compared with the existing single-layer solder resist scheme, the three-layer homogeneous solder resist sandwich design greatly increases the total thickness and compactness of the solder resist layer, and the solder resist effect is significantly improved. Through the cooperation of the three-layer homogeneous solder resist sandwich, the invasion path of moisture and solder is changed from a simple straight line to a complex broken line, significantly prolonging the invasion path length and enhancing the protection effect, effectively preventing the occurrence of PI peeling.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a method for fabricating a solder resist structure with homogeneous sandwich steps and a semiconductor device thereof. Background Technology

[0002] In the manufacturing process of silicon carbide (SiC) MOSFET power devices, the electroplating treatment of the source pads and the fabrication of the solder resist layer are critical steps affecting the reliability of the device package. Currently, the commonly used industry solution is to electroplat a NiPdAu solderable metal layer onto the source pads, followed by the formation of a polyimide (PI) solder resist layer (i.e., the PI2 solder resist solution). While this solution can prevent solder diffusion and protect the device surface to some extent, it has revealed the following problems in practical applications: First, there is the issue of PI peeling. The adhesion strength between the polyimide solder resist layer and the underlying metal or dielectric layer is limited. Under the high-temperature chemical solution immersion in the electroless plating process and the thermal cycling during subsequent packaging, the PI layer is easily peeled off from the underlying surface, resulting in partial or complete loss of the solder resist function.

[0003] Second, there is the issue of solder intrusion. At the interface between the PI solder resist layer and the electroless metallized layer, due to the difference in material properties, tiny gaps inevitably exist. During high-temperature reflow soldering, the molten solder has good fluidity and can easily seep into the device through these gaps, potentially causing electrical short circuits between adjacent source pads.

[0004] Third, there is the issue of moisture intrusion. Polyimide materials have a certain degree of hygroscopicity, and moisture can gradually diffuse into the device along the interface between the PI layer and the underlying structure. Under high temperature and high humidity bias test conditions, the presence of moisture will accelerate the electrochemical migration of metals, leading to device performance degradation or even failure.

[0005] While existing technologies employ two-layer polyimide stacked structures, such as stacking PI1 and PI2 to form a step difference to increase insulation withstand voltage, these solutions are mainly used for insulation between sensors and have not been optimized for solder resist issues during the source pad plating process, nor have they formed an effective barrier against moisture and solder intrusion. Summary of the Invention

[0006] The purpose of this invention is to provide a method for fabricating a solder resist structure of homogeneous sandwich steps and a semiconductor device to solve the problems existing in the prior art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: This application provides a homogeneous sandwich step solder resist structure applied to the source pad region of a semiconductor device. The semiconductor device includes a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, and a passivation layer above the interlayer dielectric layer, comprising: A first solder mask layer is disposed above the passivation layer; wherein the first solder mask layer has a first opening, the first opening exposing a portion of the source pad; A second solder resist layer is disposed above the first solder resist layer; wherein, the second solder resist layer has a second opening, so that a first step structure is formed between the first solder resist layer and the second solder resist layer; A metal plating layer is disposed within the first opening and the second opening; A third solder resist layer is disposed above the second solder resist layer; wherein, the third solder resist layer has a third opening, the third opening exposes part of the upper surface of the electroplated metal layer, and a second step structure is formed between the third solder resist layer and the second solder resist layer.

[0008] The aforementioned homogeneous sandwich-type solder resist structure consists of a first solder resist layer, a second solder resist layer, a chemically plated metal layer, and a third solder resist layer sequentially disposed above the passivation layer, forming a three-layer homogeneous solder resist sandwich structure. Compared to existing single-layer solder resist solutions, the three-layer homogeneous solder resist sandwich design significantly increases the total thickness and density of the solder resist layers, resulting in a marked improvement in solder resist performance. Through the synergistic interaction of the three homogeneous solder resist sandwich layers, the intrusion path of moisture and solder is transformed from a simple linear path to a complex zigzag path, significantly extending the intrusion path length, enhancing the protective effect, and effectively preventing PI peeling.

[0009] In one preferred embodiment, the first solder mask layer, the second solder mask layer, and the third solder mask layer are all semiconductor packaging material layers.

[0010] In one preferred embodiment, the first solder mask layer, the second solder mask layer, and the third solder mask layer are all polyimide layers.

[0011] In one preferred embodiment, the electroplated metal layer is a NiPdAu stacked structure.

[0012] In one preferred embodiment, the size of the second opening is smaller than the size of the first opening; Alternatively, the size of the second opening is larger than the size of the first opening; This creates a first step structure between the first solder resist layer and the second solder resist layer.

[0013] In one preferred embodiment, the size of the third opening is smaller than the size of the second opening; Alternatively, the size of the third opening is larger than the size of the second opening; This creates a second step structure between the third solder resist layer and the second solder resist layer.

[0014] In one preferred embodiment, an adhesion layer is provided between the first solder resist layer and the passivation layer; The adhesion layer is used to improve the bonding strength between the first solder resist layer and the passivation layer.

[0015] In one preferred embodiment, the thickness of the second solder resist layer is greater than the thickness of the first solder resist layer and the third solder resist layer, serving as the main solder resist layer.

[0016] In one preferred embodiment, the thickness of the first solder resist layer is less than the thickness of the second solder resist layer and the third solder resist layer, so as to improve the bonding strength between the first solder resist layer and the passivation layer.

[0017] This application also provides a semiconductor device.

[0018] A semiconductor device includes a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, a passivation layer above the interlayer dielectric layer, and a solder resist structure of homogeneous sandwich steps.

[0019] The aforementioned semiconductor device includes a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, a passivation layer above the interlayer dielectric layer, and a homogeneous sandwich-step solder resist structure. The homogeneous sandwich-step solder resist structure consists of a first solder resist layer, a second solder resist layer, a plating metal layer, and a third solder resist layer sequentially disposed above the passivation layer, forming a three-layer homogeneous solder resist sandwich structure. Compared to existing single-layer solder resist solutions, the three-layer homogeneous solder resist sandwich design significantly increases the total thickness and density of the solder resist layers, resulting in a significant improvement in solder resist performance. Through the interaction of the three homogeneous solder resist sandwich layers, the intrusion path of moisture and solder is transformed from a simple linear path to a complex zigzag path, significantly extending the intrusion path length, enhancing the protective effect, and effectively preventing PI peeling. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings. Figure 1 This is a schematic cross-sectional view of the weld resistance structure of a homogeneous sandwich step according to an embodiment of the application; Figure 2This is a three-dimensional schematic diagram of the resist welding structure of a homogeneous sandwich step according to an embodiment of the application; Figure 3 A flowchart illustrating the fabrication method of a weld resistance structure for a homogeneous sandwich step according to an embodiment of the application; Figure 4 This is a schematic diagram of the fabrication process of a weld resistance structure for a homogeneous sandwich step according to an embodiment of the application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] To facilitate understanding of the embodiments of this application, further explanation and description will be provided below with reference to the accompanying drawings and specific embodiments. These embodiments do not constitute a limitation on the embodiments of this application. In the drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0023] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “(the)” are also intended to include the plural forms. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0024] This application provides a weld resistance structure for a homogeneous sandwich step.

[0025] Figure 1 This is a schematic cross-sectional view of the weld resistance structure of a homogeneous sandwich step according to an embodiment of the application, as shown below. Figure 1As shown, a homogeneous sandwich step solder resist structure of one embodiment is applied to the source pad region of a semiconductor device. The semiconductor device includes a semiconductor substrate, an interlayer dielectric layer located above the semiconductor substrate, and a passivation layer (PAS) located above the interlayer dielectric layer, comprising: A first solder mask layer 100 is disposed above the passivation layer; wherein the first solder mask layer 100 has a first opening, and the first opening exposes a portion of the source pad; A second solder resist layer 101 is disposed above the first solder resist layer 100; wherein, the second solder resist layer 101 has a second opening, so that a first step structure is formed between the first solder resist layer 100 and the second solder resist layer 101; A metal plating layer 102 is disposed in the first opening and the second opening; The second solder resist layer 103 is disposed above the second solder resist layer 101; wherein, the second solder resist layer 103 has a third opening, the third opening exposes part of the upper surface of the electroplated metal layer 102, and a second step structure is formed between the second solder resist layer 103 and the second solder resist layer 101.

[0026] like Figure 1 As shown, a first solder resist layer 100 is disposed above the passivation layer. The first solder resist layer 100 is a semiconductor packaging material layer, preferably a polyimide layer. The first solder resist layer 100 can be formed by coating, exposure, development, and curing processes. Before curing, the thickness of the first solder resist layer 100 is approximately 2-6 μm. After curing, due to solvent evaporation and cross-linking shrinkage, the thickness decreases to approximately 1-3 μm. The first solder resist layer 100 has a first opening that exposes a portion of the upper surface of the passivation layer.

[0027] like Figure 1 As shown, a second solder resist layer 101 is disposed above the first solder resist layer 100. The second solder resist layer 101 is a semiconductor packaging material layer, preferably a polyimide layer. The second solder resist layer 101 is formed by coating, exposure, development, and curing processes, and has a thickness of approximately 14-18 μm. The second solder resist layer 101 covers at least a portion of its upper surface. A second opening is formed in the second solder resist layer 101, and the size of the second opening is different from the size of the first opening, so that a first step is formed between the first solder resist layer 100 and the second solder resist layer 101.

[0028] like Figure 1 As shown, the electroless metallized layer 102 is disposed within the first opening and the second opening. The electroless metallized layer 102 is preferably a NiPdAu stacked structure, and its sidewalls are in contact with the first solder resist layer 100 and the second solder resist layer 101.

[0029] like Figure 1As shown, a second solder resist layer 103 is disposed above the electroless metal plating layer 102 and the second solder resist layer 101. The second solder resist layer 103 is a semiconductor packaging material layer, preferably a polyimide layer. It is formed through coating, exposure, development, and curing processes, and has a thickness of approximately 6-10 μm. A third opening is provided in the second solder resist layer 103, exposing a portion of the upper surface of the electroless metal plating layer 102, allowing the upper surface of the electroless metal plating layer 102 to contact external solder to achieve electrical connection. A second step is formed between the second solder resist layer 103 and the second solder resist layer 101.

[0030] Preferably, the size of the second opening is smaller than the size of the first opening; Alternatively, the size of the second opening is larger than the size of the first opening; This creates a first step structure between the first solder mask layer 100 and the second solder mask layer 101.

[0031] Preferably, the size of the third opening is smaller than the size of the second opening; Alternatively, the size of the third opening is larger than the size of the second opening; This forms a second step structure between the second solder resist layer 103 and the second solder resist layer 101.

[0032] The first solder resist layer 100, the second solder resist layer 101, the electroplated metal layer 102, and the second solder resist layer 103 form a sandwich stepped structure. Specifically, the first stepped structure is located at the boundary between the first solder resist layer 100 and the second solder resist layer 101, and the second stepped structure is located at the boundary between the second solder resist layer 101 and the second solder resist layer 103. The first stepped structure and the second stepped structure are staggered in the vertical direction, together forming a multi-layered moisture intrusion path extension structure.

[0033] Preferably, an adhesion layer is provided between the first solder resist layer 100 and the passivation layer; The adhesion layer is used to improve the bonding strength between the first solder resist layer 100 and the passivation layer.

[0034] Preferably, the adhesion layer is a hexamethyldisilazane (HMDS) layer, formed by vapor deposition, with a thickness of 5 nm to 20 nm, used to improve the bonding strength between the first solder resist layer 100 and the passivation layer.

[0035] Preferably, the thickness of the second solder resist layer 101 is greater than the thickness of the first solder resist layer 100 and the second solder resist layer 103, and it serves as the main solder resist layer.

[0036] The second weld resist layer 101 has the largest thickness and serves as the main weld resist layer, thereby improving the structural strength of the weld resist structure of the homogeneous sandwich step.

[0037] Preferably, the thickness of the first solder resist layer 100 is less than the thickness of the second solder resist layer 101 and the second solder resist layer 103, so as to improve the bonding strength between the first solder resist layer 100 and the passivation layer.

[0038] The first solder resist layer 100 preferably has a thickness of 1.5μm to 2.5μm. As a thin layer, it is used to reduce the internal stress of curing shrinkage and reduce the risk of warping and cracking.

[0039] Figure 2 This is a three-dimensional schematic diagram of the weld resistance structure of a homogeneous sandwich step according to an embodiment of the application, as shown below. Figure 2 As shown, two interlayer interfaces (PI1 / PI2 interface and PI2 / PI3 interface) are formed between the first solder resist layer 100, the second solder resist layer 101, and the second solder resist layer 103. The interfaces between polyimide layers are weak points for moisture intrusion, and moisture mainly migrates along the interlayer interfaces of polyimide layers. In this embodiment, the interfaces between multiple PI layers are not straight and continuous, but are formed by a stepped structure to form a discontinuous distribution. Moisture encounters resistance when crossing each interface, thus being weakened layer by layer.

[0040] Meanwhile, the presence of the first and second step structures transforms the moisture intrusion path from a simple straight line to a complex polygonal line, significantly extending the intrusion path length and effectively delaying or preventing moisture intrusion.

[0041] In this embodiment, the second solder resist layer 103 serves as the outermost solder resist barrier, initially blocking the diffusion of solder. If the solder breaks through the second solder resist layer 103, the geometric abrupt change at the second step structure forces the solder wetting front to change direction and reduce speed, making it difficult for it to continue penetrating inward.

[0042] In this embodiment, the thinner first solder resist layer 100 serves as the underlayer, exhibiting lower curing shrinkage and less internal stress. The stepped structure between the three PI layers buffers and disperses the thermal stress generated during temperature changes, effectively preventing PI peeling.

[0043] The homogeneous sandwich step solder resist structure of any of the above embodiments comprises a first solder resist layer 100, a second solder resist layer 101, a chemically plated metal layer 102, and a second solder resist layer 103 sequentially disposed above the passivation layer, forming a three-layer homogeneous solder resist sandwich structure. Compared with the existing single-layer solder resist scheme, the three-layer homogeneous solder resist sandwich design greatly increases the total thickness and density of the solder resist layer, and the solder resist effect is significantly improved. Through the cooperation of the three homogeneous solder resist sandwich layers, the intrusion path of moisture and solder is changed from a simple linear type to a complex zigzag type, which significantly extends the intrusion path length, enhances the protection effect, and effectively prevents piping.

[0044] This application also provides a semiconductor device.

[0045] A semiconductor device includes a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, a passivation layer above the interlayer dielectric layer, and a solder resist structure of homogeneous sandwich steps.

[0046] The aforementioned semiconductor device includes a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, a passivation layer above the interlayer dielectric layer, and a solder resist structure with homogeneous sandwich steps. The solder resist structure with homogeneous sandwich steps consists of a first solder resist layer 100, a second solder resist layer 101, a plating metal layer 102, and a second solder resist layer 103 sequentially disposed above the passivation layer, forming a three-layer homogeneous solder resist sandwich structure. Compared to existing single-layer solder resist solutions, the three-layer homogeneous solder resist sandwich design significantly increases the total thickness and density of the solder resist layers, resulting in a significant improvement in solder resist performance. Through the interaction of the three homogeneous solder resist sandwich layers, the intrusion path of moisture and solder is transformed from a simple linear path to a complex zigzag path, significantly extending the intrusion path length, enhancing the protective effect, and effectively preventing PI peeling.

[0047] This application also provides a method for manufacturing a weld resistance structure of a homogeneous sandwich step.

[0048] Figure 3 This is a flowchart illustrating a method for fabricating a weld resistance structure for a homogeneous sandwich step according to an embodiment of the application. Figure 3 As shown, a method for fabricating a weld resist structure of a homogeneous sandwich step according to an embodiment of the application includes steps S100 to S102: S100, deposit a first solder mask layer 100 above the passivation layer, and pattern the first solder mask layer 100 to form a first opening; S101, a second solder resist layer 101 and a second solder resist layer 103 are sequentially formed on the first solder resist layer 100, and a second opening and a third opening are formed. S102, a chemically plated metal layer 102 is formed based on the through first opening, second opening and third opening.

[0049] The provided semiconductor wafer has completed the front-end processes, on which a semiconductor substrate, an interlayer dielectric layer, and a passivation layer have been formed.

[0050] Figure 4 This is a schematic diagram of the fabrication process of a homogeneous sandwich step weld resistance structure according to an embodiment of the application, as shown below. Figure 4 As shown, a first solder resist layer 100 is formed above the passivation layer.

[0051] Preferably, a spin-coating process is used to coat the photosensitive polyimide precursor solution, and the spin-coating speed is controlled to achieve a pre-cured film thickness of 4 μm. After pre-baking (approximately 90°C–120°C), exposure, development, and curing (approximately 300°C–350°C), a cured first solder resist layer 100 with a thickness of approximately 2 μm is formed. A first opening is formed in the first solder resist layer 100, such as… Figure 4 As shown. The location of the first opening corresponds to the location of the source pad to be formed later.

[0052] like Figure 4 As shown, a second solder resist layer 101 is formed above the first solder resist layer 100. Specifically, a photosensitive polyimide precursor solution is coated again using a spin coating process, followed by pre-baking, exposure, development, and curing processes to form a second solder resist layer 101 with a thickness of approximately 16 μm. A second opening is formed in the second solder resist layer 101, the size of which is smaller than the size of the first opening, thereby forming a first step between the first solder resist layer 100 and the second solder resist layer 101.

[0053] like Figure 4 As shown, a metallized layer 102 is formed in the first opening and the second opening. After the metallization is completed, the metallized layer 102 fills the first opening and the second opening, forming a source pad that is electrically connected to the passivation layer.

[0054] like Figure 4 As shown, a second solder resist layer 103 is formed above the electroplated metal layer 102 and the second solder resist layer 101. Specifically, a photosensitive polyimide precursor solution is coated again using a spin coating process, and after pre-baking, exposure, development, and curing processes, the second solder resist layer 103 is formed. A third opening is formed in the second solder resist layer 103, exposing part of the upper surface of the electroplated metal layer 102. A second step is formed between the second solder resist layer 103 and the second solder resist layer 101.

[0055] Preferably, the homogeneous sandwich step solder resist structure of this application embodiment is widely used in the manufacturing and packaging process of silicon carbide MOSFET power devices, and has the advantages of improved yield and controllable cost, and has good industrial application prospects and economic value.

[0056] The aforementioned method for fabricating a homogeneous sandwich-step solder resist structure involves fabricating a semiconductor device comprising a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, a passivation layer above the interlayer dielectric layer, and a homogeneous sandwich-step solder resist structure. The homogeneous sandwich-step solder resist structure comprises a first solder resist layer 100, a second solder resist layer 101, a plating metal layer 102, and a second solder resist layer 103 sequentially disposed above the passivation layer, forming a three-layer homogeneous solder resist sandwich structure. Compared to existing single-layer solder resist solutions, the three-layer homogeneous solder resist sandwich design significantly increases the total thickness and density of the solder resist layers, resulting in a significant improvement in solder resist performance. Through the interaction of the three homogeneous solder resist sandwich layers, the intrusion path of moisture and solder is transformed from a simple linear path to a complex zigzag path, significantly extending the intrusion path length, enhancing the protective effect, and effectively preventing PI peeling.

[0057] The following points should be noted regarding this application: (1) The accompanying drawings of the embodiments of this application only involve the structures involved in the embodiments of this application. Other structures can be referred to the general design.

[0058] (2) For clarity, the thickness and dimensions of layers or structures are enlarged in the accompanying drawings used to describe embodiments of the invention. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0059] (3) Where there is no conflict, the embodiments and features in the embodiments of this application can be combined with each other to obtain new embodiments. The above are only specific implementations of this application, but the protection scope of this application is not limited thereto, and the protection scope of this application shall be determined by the protection scope of the claims.

[0060] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0061] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

[0062] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a weld resistance structure of a homogeneous sandwich step, characterized in that, Including the following steps: A first solder mask layer is deposited above the passivation layer, and the first solder mask layer is patterned to form a first opening; A second solder resist layer and a second solder resist layer are sequentially formed on the first solder resist layer, and a second opening and a third opening are formed thereon; A metallized layer is formed based on the through first opening, second opening, and third opening.

2. The method for manufacturing the weld resistance structure of the homogeneous sandwich step according to claim 1, characterized in that, The first solder resist layer, the second solder resist layer, and the third solder resist layer are all semiconductor packaging material layers.

3. The method for manufacturing the weld resistance structure of the homogeneous sandwich step according to claim 2, characterized in that, The first solder resist layer, the second solder resist layer, and the third solder resist layer are all polyimide layers.

4. The method for manufacturing the weld resistance structure of the homogeneous sandwich step according to claim 1, characterized in that, The electroplated metal layer has a NiPdAu stacked structure.

5. The method for manufacturing the weld resistance structure of the homogeneous sandwich step according to claim 1, characterized in that, The size of the second opening is smaller than the size of the first opening; Alternatively, the size of the second opening is larger than the size of the first opening; This creates a first step structure between the first solder resist layer and the second solder resist layer.

6. The method for manufacturing the weld resistance structure of the homogeneous sandwich step according to claim 1, characterized in that, The size of the third opening is smaller than the size of the second opening; Alternatively, the size of the third opening is larger than the size of the second opening; This creates a second step structure between the third solder resist layer and the second solder resist layer.

7. The method for manufacturing the weld resistance structure of the homogeneous sandwich step according to claim 1, characterized in that, An adhesion layer is provided between the first solder mask layer and the passivation layer; The adhesion layer is used to improve the bonding strength between the first solder resist layer and the passivation layer.

8. The method for manufacturing the weld resistance structure of the homogeneous sandwich step according to claim 1, characterized in that, The thickness of the second solder resist layer is greater than the thickness of the first solder resist layer and the third solder resist layer, and it serves as the main solder resist layer.

9. The method for manufacturing the weld resistance structure of the homogeneous sandwich step according to claim 1, characterized in that, The thickness of the first solder resist layer is less than the thickness of the second solder resist layer and the third solder resist layer, so as to improve the bonding strength between the first solder resist layer and the passivation layer.

10. A semiconductor device, characterized in that, The method for fabricating a homogeneous sandwich step solder resist structure includes a semiconductor substrate, an interlayer dielectric layer above the semiconductor substrate, a passivation layer above the interlayer dielectric layer, and a method for fabricating a homogeneous sandwich step solder resist structure as described in any one of claims 1 to 9.

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