A solid state drive system and method of accessing a NAND flash memory device

Abstract

The application provides a solid state disk system and a method for accessing a NAND flash memory device. The solid state disk system comprises at least one master node, at least one network switch and at least one NAND flash memory node. The at least one master node can communicate with the at least one network switch through a network protocol, and the at least one network switch communicates with the at least one NAND flash memory node through the network protocol. In the application, the master node is decoupled from the NAND flash memory node, so that the NAND node is not affected even if the master node fails, thereby reducing the cost of hardware failure.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a solid-state drive system, a method for accessing NAND flash memory devices, a computing device, a cluster of computing devices, a computer program product, and a computer-readable storage medium. Background Technology

[0002] Solid-state drives (SSDs) are a technology that uses electronic storage media for data storage and retrieval. Due to structural differences, SSDs do not have concepts such as read / write heads, tracks, or cylinders; they are mainly composed of a control unit and solid-state storage cells. Based on the storage media used, they are divided into SSDs based on NAND flash memory devices (i.e., SSDs where NAND flash memory devices are directly used as the storage medium) and SSDs based on dynamic random access storage (DRAM) (i.e., SSDs where DRAM chips are directly used as the storage medium). SSDs based on NAND flash memory devices are the most common, being portable and their data protection is independent of power supply control; while DRAM-based SSDs are less common and require an independent power supply to protect data security.

[0003] With the increasing demand for high capacity and high performance from artificial intelligence (AI) applications, and the continuous reduction in the cost of NAND flash memory devices, the development trend of SSDs is evolving towards larger capacities. Currently, the industry has already launched 128TB and 256TB high-capacity SSDs. For example, in an SSD architecture based on NAND flash memory devices, the controller, DRAM, and NAND flash memory devices are housed in a single module. Failure of any one component necessitates the replacement of the entire SSD. For instance, a controller failure can render the entire SSD inoperable, even though the NAND flash memory devices themselves may be functional. The entire SSD becomes unusable simply because the controller and NAND flash memory devices are soldered together. Typically, the NAND flash memory device accounts for over 80% of the cost of an SSD, and discarding it in this situation results in significant cost losses. It can be seen that in this approach, failure of low-cost components such as the controller forces the high-cost NAND flash memory device to be scrapped as well, resulting in substantial resource waste and cost losses.

[0004] Therefore, a solid-state drive system is needed to reduce the cost of hardware failure. Summary of the Invention

[0005] This application provides a solid-state drive system, a method for accessing NAND flash memory devices, a computing device, a computing device cluster, a computer program product, and a computer-readable storage medium, which reduces hardware failure costs by decoupling and separating the controller device and the NAND flash memory device in the SSD system.

[0006] In a first aspect, a solid-state drive (SSD) system is provided. The SSD system includes at least one master control node, at least one network switch, and at least one NAND flash memory node. Each master control node includes at least one master control device, and each NAND flash memory node includes at least one NAND flash memory device. The at least one master control node establishes a network connection with the at least one NAND flash memory node through the at least one network switch. The at least one master control node is used to communicate with the at least one network switch through a network protocol. The at least one network switch is used to communicate with the at least one NAND flash memory node through a network protocol.

[0007] Based on the above technical solution, this application decouples and separates the controller node from the NAND flash memory node. Even if the controller node fails, it will not affect the NAND node, thereby reducing hardware failure costs. Specifically, in traditional solutions, the controller, DRAM, and NAND flash memory are packaged together in an SSD. Failure of any component will render the entire SSD unusable, and NAND accounts for 80%-95% of the cost. This solution separates the controller from the NAND flash memory device. When the controller fails, only the controller needs to be replaced, avoiding the waste of NAND flash memory and significantly reducing cost losses caused by failure.

[0008] In addition, in this solution, by forming a master control resource pool from multiple master control devices and a NAND flash memory pool from multiple NAND flash memory devices, the system can dynamically allocate master control resources and NAND resources according to business needs, realize on-demand expansion of storage capacity and elastic scheduling of performance, and significantly improve resource utilization.

[0009] In conjunction with the first aspect, in one possible implementation, the solid-state drive system further includes at least one protocol conversion chip and at least one network switch for communicating with at least one NAND flash memory node via a network protocol, including: at least one network switch for communicating with at least one protocol conversion chip via the network protocol; at least one protocol conversion chip for converting the network protocol into an open NAND flash memory interface protocol; and at least one protocol conversion chip for communicating with at least one NAND flash memory device via the open NAND flash memory interface protocol.

[0010] Based on the above solutions, this application, considering that NAND flash memory devices support short-range internal interfaces such as ONFi and cannot directly access the network, proposes a protocol conversion chip to convert the ONFi protocol into standard network protocols such as CXL and NVMe-oF. This makes the NAND flash memory device an independent storage resource that can be accessed by any network controller, laying the physical foundation for storage pooling. Furthermore, the protocol conversion chip reduces the complexity of network protocols, and the NAND flash memory device requires no modification, still using the standard ONFi interface. This allows the system to flexibly select NAND flash memory devices from different manufacturers and with different specifications, without being limited by specific network protocols, reducing supply chain dependence and procurement costs.

[0011] In conjunction with the first aspect, in one possible implementation, the at least one master node is configured to send a broadcast request message to at least one network switch, the broadcast request message being configured to instruct each NAND flash memory device to report its respective configuration space information, the configuration space information being used by the master node to identify and access the NAND flash memory device; the at least one network switch is configured to obtain the respective configuration space information of each NAND flash memory device according to the broadcast request message.

[0012] For example, the configuration space information includes the identification information of the NAND flash memory device, the identification information of at least one chip in the NAND flash memory device, and the structural information of each chip. The structural information is used to indicate the mapping relationship between the identification of the logic unit, the plane identification, the block identification, and the page identification in each chip.

[0013] In conjunction with the first aspect, in one possible implementation, the solid-state drive system further includes at least one management module. Each management module is used to store global mapping relationships, which include multiple mapping relationships. These multiple mapping relationships are used to indicate at least one logical address managed by each of the multiple master controllers, the physical address corresponding to each logical address, and path information. The physical address is used to indicate the target NAND flash memory device corresponding to the logical address, the target chip in the target NAND flash memory device, the target logical unit in the target chip, the target plane in the target logical unit, the target block in the target plane, and the target page in the target block. The path information is used to indicate routing information of the network topology from the master controller to the physical address.

[0014] Based on the above technical solution, this application records the correspondence between all logical addresses and NAND flash memory device locations through this global mapping relationship, providing a resource view for the entire storage system and avoiding the problem of inconsistent mapping information in a multi-master environment. Furthermore, the global mapping relationship allows any master device to access any NAND device, and data can be flexibly migrated between different master devices. When a master device fails, other master devices can quickly take over the NAND flash memory devices they are responsible for based on the global mapping table, realizing dynamic resource reallocation and failover.

[0015] In conjunction with the first aspect, in one possible implementation, the solid-state drive system further includes at least one management module. Each management module stores global mapping relationships, which include multiple mapping relationships indicating the correspondence between multiple virtual address information and multiple real address information. The multiple virtual address information indicates at least one logical address managed by each of the multiple master devices, and the physical address of the virtual NAND flash memory device corresponding to each logical address. The multiple real address information indicates the physical address and path information of the real NAND flash memory device corresponding to the physical address of each virtual NAND flash memory device. The physical address indicates the target NAND flash memory device corresponding to the logical address, the target chip in the target NAND flash memory device, the target logical unit in the target chip, the target plane in the target logical unit, the target block in the target plane, and the target page in the target block. The path information indicates the routing information of the network topology from the master device to the physical address.

[0016] Based on the above technical solution, the new SSD architecture provided in this application is compatible with existing technologies, meaning that it does not require modification of the FTL table in the controller device. Each controller node still uses the existing FTL table to map the local virtual NAND flash memory device to the remote real NAND flash memory device through a global mapping relationship.

[0017] In conjunction with the first aspect, in one possible implementation, each master node is also used to store local mapping relationships, which are subsets of global mapping relationships. The local mapping relationships are mapping relationships related to some or all of the master control devices included in the master node.

[0018] Based on the above technical solution, in this application, the local mapping table resides in the local memory of the main control device. When performing address translation, the main control device does not need to query the network; it reads directly from the local memory, reducing latency from microseconds at the network level to nanoseconds at the memory level, thus improving input / output (I / O) response speed. Furthermore, the address mapping of hot data is cached locally by each main control device, avoiding network traffic and processing overhead caused by querying the management module for each I / O operation. This ensures the system remains stable even when dealing with massive concurrent I / O, extending the system's performance ceiling.

[0019] In conjunction with the first aspect, in one possible implementation, each NAND flash memory node includes multiple NAND flash memory devices. Some of the multiple NAND flash memory devices are used to store at least one data shard of the original data, and the remaining NAND flash memory devices are used to store at least one verification data. The original data consists of multiple data shards, which correspond to some of the NAND flash memory devices. Each verification data is obtained by performing calculations on the multiple data shards.

[0020] Based on the above technical solution, in this application, by using EC technology for data storage, data reliability between different NAND flash memory devices can be achieved.

[0021] In conjunction with the first aspect, in one possible implementation, each NAND flash memory device includes multiple chips, some of which are used to store at least one data shard of the original data, and the remaining chips are used to store at least one verification data. The original data consists of multiple data shards, which correspond to some of the chips, and each verification data is obtained by performing calculations on the multiple data shards.

[0022] Based on the above technical solution, in this application, by using EC technology for data storage, the reliability between different chips / particles within a NAND flash memory device can be achieved.

[0023] As can be seen, this application utilizes a networked NAND resource pool, combined with EC technology, to distribute data blocks and parity blocks across different NAND devices and / or different chips, achieving dual reliability between NAND devices and between chips. When a single chip or even the entire NAND device fails, the system can automatically recover lost data using the remaining data blocks and parity blocks, ensuring uninterrupted service and no data loss.

[0024] In conjunction with the first aspect, in one possible implementation, the first master control node includes a first master control device and a second master control device. The global mapping relationship includes at least one first mapping relationship. Each first mapping relationship is used to indicate at least one first logical address managed by the first master control device, the first physical address corresponding to each first logical address, and the first path information. When the first master control device fails, at least one management module is used to update at least one first mapping relationship. The updated first mapping relationship is used to indicate at least one first logical address managed by the second master control device, the updated first physical address corresponding to each first logical address, and the updated first path information. The second master control device is used to obtain the updated at least one first mapping relationship from at least one management module. The second master control device is used to access data according to the updated at least one first mapping relationship.

[0025] Based on the above technical solution, in this application, the global resource mapping is uniformly managed through the management module, and a hot standby master control device is configured. When the master control device fails, it can switch to the standby master control device, and at the same time restore the FTL mapping table from the backup to achieve rapid takeover, thereby improving the availability and operation and maintenance efficiency of the system.

[0026] What is needed is that the beneficial effects of the methods and devices provided below can be understood by referring to the relevant content in the first aspect, and will not be repeated here.

[0027] Secondly, a method for accessing NAND flash memory devices is provided. This method is applied to a solid-state drive system, which includes at least one master controller node, at least one network switch, and at least one NAND flash memory node. Each master controller node includes at least one master controller device, and each NAND flash memory node includes at least one NAND flash memory device. The at least one master controller node establishes a network connection with the at least one NAND flash memory node through the at least one network switch. The at least one master controller node communicates with the at least one network switch through a network protocol, and the at least one network switch communicates with the at least one NAND flash memory node through a network protocol.

[0028] In conjunction with the second aspect, in one possible implementation, the solid-state drive system further includes at least one protocol conversion chip and at least one network switch, communicating with at least one NAND flash memory node via a network protocol, including: at least one network switch communicating with at least one protocol conversion chip via a network protocol; at least one protocol conversion chip converting the network protocol into an open NAND flash memory interface protocol; and at least one protocol conversion chip communicating with at least one NAND flash memory device via the open NAND flash memory interface protocol.

[0029] In conjunction with the second aspect, in one possible implementation, the method further includes: at least one master node sending a broadcast request message to at least one network switch, the broadcast request message being used to instruct each NAND flash memory device to report its respective configuration space information, the configuration space information being used by the master node to identify and access the NAND flash memory device; and at least one network switch obtaining the respective configuration space information of each NAND flash memory device according to the broadcast request message.

[0030] In conjunction with the second aspect, in one possible implementation, the configuration space information includes identification information of the NAND flash memory device, identification information of at least one chip in the NAND flash memory device, and structural information of each chip. The structural information is used to indicate the mapping relationship between the identifiers of logic cells, plane identifiers, block identifiers, and page identifiers in each chip.

[0031] In conjunction with the second aspect, in one possible implementation, the solid-state drive system further includes at least one management module. Each management module is used to store global mapping relationships, which include multiple mapping relationships. These multiple mapping relationships are used to indicate at least one logical address managed by each of the multiple master controllers, the physical address corresponding to each logical address, and path information. The physical address is used to indicate the target NAND flash memory device corresponding to the logical address, the target chip in the target NAND flash memory device, the target logical unit in the target chip, the target plane in the target logical unit, the target block in the target plane, and the target page in the target block. The path information is used to indicate the routing information of the network topology from the master controller to the physical address.

[0032] In conjunction with the second aspect, in one possible implementation, the solid-state drive system further includes at least one management module. Each management module stores global mapping relationships, which include multiple mapping relationships indicating the correspondence between multiple virtual address information and multiple real address information. The multiple virtual address information indicates at least one logical address managed by each of the multiple master devices, and the physical address of the virtual NAND flash memory device corresponding to each logical address. The multiple real address information indicates the physical address and path information of the real NAND flash memory device corresponding to the physical address of each virtual NAND flash memory device. The physical address indicates the target NAND flash memory device corresponding to the logical address, the target chip in the target NAND flash memory device, the target logical unit in the target chip, the target plane in the target logical unit, the target block in the target plane, and the target page in the target block. The path information indicates the routing information of the network topology from the master device to the physical address.

[0033] In conjunction with the second aspect, in one possible implementation, each master node is also used to store local mapping relationships, which are subsets of global mapping relationships. The local mapping relationships are mapping relationships related to some or all of the master control devices included in the master node.

[0034] In conjunction with the second aspect, in one possible implementation, each NAND flash memory node includes multiple NAND flash memory devices. Some of the multiple NAND flash memory devices are used to store at least one data shard of the original data, and the remaining NAND flash memory devices are used to store at least one verification data. The original data consists of multiple data shards, which correspond to the aforementioned partial NAND flash memory devices. Each verification data is obtained by performing calculations on the multiple data shards.

[0035] In conjunction with the second aspect, in one possible implementation, each NAND flash memory device includes multiple chips, some of which are used to store at least one data shard of the original data, and the remaining chips are used to store at least one verification data. The original data consists of multiple data shards, which correspond to some of the chips, and each verification data is obtained by performing calculations on the multiple data shards.

[0036] In conjunction with the second aspect, in one possible implementation, the first master control node includes a first master control device and a second master control device. The global mapping relationship includes at least one first mapping relationship. Each first mapping relationship is used to indicate at least one first logical address managed by the first master control device, the first physical address corresponding to each first logical address, and the first path information. When the first master control device fails, the method further includes: at least one management module updating at least one first mapping relationship, whereby each updated first mapping relationship is used to indicate at least one first logical address managed by the second master control device, the updated first physical address corresponding to each first logical address, and the updated first path information; the second master control device obtaining the updated at least one first mapping relationship from the at least one management module; and the second master control device performing data access based on the updated at least one first mapping relationship.

[0037] Thirdly, this application provides an apparatus comprising: at least one processor for executing a computer program or instructions stored in a memory to perform the method described in the second aspect. Optionally, the apparatus further comprises a memory for storing the computer program or instructions. Optionally, the apparatus further comprises a communication interface through which the processor reads the computer program or instructions stored in the memory.

[0038] In one implementation, the device is a means for implementing the functions of the above-described method in a chip.

[0039] In another implementation, the device is a chip, chip system, or circuit used to implement the functions of the above methods in a chip.

[0040] Fourthly, this application provides a processor, including: an input circuit, an output circuit, and a processing circuit. The processing circuit is used to receive signals through the input circuit and to transmit signals through the output circuit, causing the processor to execute the method described in the second aspect.

[0041] In specific implementation, the processor can be one or more chips, the input circuit can be input pins, the output circuit can be output pins, and the processing circuit can be transistors, gate circuits, flip-flops, and various logic circuits. The input signals received by the input circuit can be received and input via, for example, but not limited to, a communication interface. The signals output by the output circuit can be output to, for example, but not limited to, a communication interface and transmitted by the communication interface. Furthermore, the input circuit and the output circuit can be the same circuit, which is used as both the input and output circuits at different times. This application does not limit the specific implementation of the processor and various circuits.

[0042] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0043] Fifthly, a computing device is provided, including a processor and a memory. The processor is used to read instructions stored in the memory and to receive and send data via a communication interface to execute the method described in the second aspect above.

[0044] Optionally, the processor may be one or more, and the memory may be one or more.

[0045] Optionally, the memory may be integrated with the processor, or the memory may be separated from the processor.

[0046] In the specific implementation process, the memory can be a non-transitory memory, such as read-only memory (ROM), which can be integrated with the processor on the same chip or set on different chips. This application does not limit the type of memory or the way the memory and processor are set.

[0047] Specifically, the data output by the processor can be sent to the communication interface, and the input data received by the processor can come from the communication interface.

[0048] The computing device mentioned in the fifth aspect above can be one or more chips. The processor in the computing device can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. This memory can be integrated into the processor or located outside the processor and exist independently.

[0049] In a sixth aspect, a computing cluster is provided, including at least one computing device, each computing device including a processor and a memory; the processor of the at least one computing device is configured to execute instructions stored in the memory of the at least one computing device, such that the computing device cluster performs the method described in any possible implementation of the second aspect.

[0050] Optionally, the processor can be a general-purpose processor, which can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. This memory can be integrated into the processor or located outside the processor and exist independently.

[0051] In a seventh aspect, a computer-readable storage medium is provided, the computer-readable storage medium including computer program instructions, which, when executed by a cluster of computing devices, are used to perform the method of the second aspect described above.

[0052] Eighthly, a computer program product including instructions is provided, which, when run by a cluster of computing devices, cause the cluster of computing devices to perform the method of the second aspect described above.

[0053] Ninthly, a chip system is provided, comprising a processor and a power supply circuit. The power supply circuit supplies power to the processor, which executes the operation steps corresponding to the method described in the second aspect or any implementation thereof. For brevity, further details are omitted here. The processor can be implemented using a graphics processing unit (GPU), or a data processing unit (DPU), neural network processing unit (NPU), heterogeneous processing unit (XPU), system-on-chip (SoC), offload card, accelerator card, or other computing devices.

[0054] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0055] Figure 1 This is a schematic diagram illustrating an existing SSD system architecture as shown in an embodiment of this application.

[0056] Figure 2 This is a schematic diagram of an SSD system architecture provided in an embodiment of this application.

[0057] Figure 3 This is another schematic diagram of an SSD system architecture provided in an embodiment of this application.

[0058] Figure 4 This is a schematic diagram of a chip structure provided in an embodiment of this application.

[0059] Figure 5 This is a schematic diagram illustrating the mapping relationship between a current NAND flash memory device and a remote NAND flash memory device, as provided in an embodiment of this application.

[0060] Figure 6 This is a schematic diagram of a cloud service system architecture to which this application applies.

[0061] Figure 7 This is a schematic block diagram of the computing device 700 provided in this application.

[0062] Figure 8 This is a schematic block diagram of the computing device 800 provided in this application.

[0063] Figure 9 This is a schematic diagram of the architecture of a computing device cluster provided in this application.

[0064] Figure 10 This is a schematic diagram showing the connection between computing devices 900A and 900B provided in this application via a network. Detailed Implementation

[0065] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0066] To facilitate understanding of the technical solutions provided in the embodiments of this application, the technical terms involved in this application are briefly introduced below. It should be noted that the introduction of technical terms in this application is only for the purpose of helping to understand the technical solutions and should not be construed as limiting the application.

[0067] 1. Erasure coding (EC) Erasure coding works by dividing, encoding, and expanding a piece of data, appending redundant information to the data, and then storing these data fragments in different locations (such as different disks or server nodes). The purpose of this is that when a portion of the data (even a certain proportion of redundant data) is lost or corrupted, we can still use a decoding algorithm to completely recover the original data from the remaining data fragments. Erasure coding is usually described by a simple formula: N+K, where N refers to the number of data blocks (or data fragments) into which the original data is divided, and K refers to the number of parity blocks calculated for these N data blocks. After encoding, a total of N + K data blocks are generated. Any N blocks (which can be data blocks or parity blocks) from these N+K blocks can be combined to recover the complete original data. This means that the system can tolerate the loss or corruption of up to K blocks.

[0068] For example, erasure coding workflow consists of two steps: encoding and decoding. (1) Encoding process (which can also be understood as writing data): ① Segmentation: Divide a large file (such as an object) into N original data chunks of equal size. ② Calculation: Calculate K parity chunks by performing matrix multiplication and other mathematical transformations on these N data chunks using erasure coding algorithms (such as the classic Reed-Solomon code, based on operations on Vandermonde matrices or Cauchy matrices). ③ Distribution: Store the N+K chunks on different disks, nodes, or fault domains. (2) Decoding process (which can also be understood as reading / recovering data): ① Reading: When data needs to be read, if all N data chunks are available, it can be read directly, which is very fast. ② Reconstruction: When some chunks (at most K) are unavailable, the system will read any of the remaining N available chunks (whether data chunks or parity chunks). ③ Decoding: Substitute these blocks and their encoding matrix information into the decoding algorithm, solve the linear equation system, recalculate the lost original data blocks, and return them to the upper layer application.

[0069] As can be seen, erasure coding is a data protection technology that uses mathematical algorithms. It divides the original data and calculates additional check blocks during writing, thus enabling complete recovery even when some data blocks are lost. Its core advantage lies in trading central processing unit (CPU) computing resources for valuable storage space, achieving high reliability with far lower overhead than replication technologies. Therefore, it has become a cornerstone technology of modern large-scale distributed storage systems.

[0070] 2. SSD Typically, a traditional SSD consists of three main components in terms of hardware: the controller module, DRAM cache, and NAND flash memory. Figure 1 This application illustrates a schematic architecture diagram of an existing SSD system. The following section combines... Figure 1 Let me introduce each part separately.

[0071] 2.1 NAND flash memory devices NAND flash memory is the true data storage medium in an SSD, meaning it stores all the data and is typically responsible for persistent data storage, ensuring data integrity even when power is off. Its working principle is as follows: Unlike DRAM, NAND flash memory is a non-volatile storage technology that uses charge stored in floating-gate transistors to represent data ("0" or "1"). NAND flash memory is categorized into several types based on the number of bits stored in each cell, directly determining the cost, speed, and lifespan of the SSD. ① Single-level cell (SLC): Stores 1 bit per cell; fastest speed, longest lifespan, highest cost; currently mainly used in high-end enterprise applications. ② Multi-level cell (MLC): Stores 2 bits per cell; relatively balanced in speed, lifespan, and cost; formerly the mainstream for high-end consumer SSDs. ③ Triple-level cell (TLC): Stores 3 bits per cell; currently the absolute mainstream for consumer SSDs, achieving a good balance between cost, capacity, and performance. ④ Quad-level cell (QLC): Stores 4 bits per cell. The capacity can be made very large and the cost is lower, but the speed and lifespan are also relatively lower, making it suitable for high-capacity read-intensive applications.

[0072] As mentioned earlier, the basic storage unit of a NAND flash memory device is a floating-gate transistor. By controlling the amount of charge in the floating gate, its threshold voltage is changed, thus distinguishing different storage states (i.e., binary data). These units are organized in a specific way into pages (typically 4KB / 8KB / 16KB), blocks (typically composed of hundreds of pages, such as 512KB / 1MB), etc., ultimately forming the entire chip. NAND flash memory devices communicate with the host device through the open NAND flash interface (ONFi), and the data transfer rate continues to improve with the evolution of standards.

[0073] Typically, the chips (dies) in NAND flash memory devices (also known as NAND particles) are the smallest independent functional units cut from silicon wafers. They contain complete memory arrays and basic read / write circuitry, and are where the actual data is stored. NAND flash memory devices are black square chips on a circuit board; they are packaged physical units that can contain one or more chips.

[0074] 2.2 Main Control Equipment The controller can be understood as the brain of the SSD, the most critical factor determining its performance, stability, and lifespan. It's a dedicated microprocessor running complex firmware algorithms, managing and scheduling all data flow. It receives instructions from the CPU and DPU, then directs data read and write operations between the NAND flash memory and the CPU. Its core tasks include: ① Flash Translation Layer (FTL): This is the controller's most crucial function. Through the FTL layer, the controller translates the operating system's logical addresses into physical addresses on the NAND flash memory device. This acts like a simultaneous interpretation, enabling communication between the operating system and the NAND flash memory device. ② Wear Leveling: Each cell in NAND flash memory has a limited write / erase cycle life (e.g., TLC can be erased and written 1000-3000 times). The controller's wear leveling algorithm intelligently allocates data writes, ensuring all cells are used evenly and preventing premature failure due to overuse, thus extending the overall lifespan of the SSD. ③ Garbage Collection: NAND flash memory cannot be directly overwritten; it must be erased before writing. When a file is deleted or modified, the original data is not immediately erased, but marked as "invalid." The controller will find a suitable time in the background to collect the valid data, move it to a new location, and then completely erase the original block to make room for the new data. This process is called garbage collection. ④ ECC Error Correction: With advancements in flash memory technology and increased cell density, bit flips (i.e., "errors") may occur during data storage and retrieval. The controller uses sophisticated error correction coding technology to automatically detect and correct these errors when reading data, ensuring that the read data is completely consistent with the written data.

[0075] The core functional modules of the main control device include: ① Host Interface Controller: Responsible for physical layer and protocol layer communication with the host. Depending on the protocol, it is divided into Serial Advanced Technology Attachment (SATA), Serial Attached SCSI (SAS), or Peripheral Component Interconnect Express (PCIe) (Non-volatile Memory Express, NVMe) controllers. ② NAND Flash Controller (Flash Channels): The main controller connects to NAND flash memory chips through multiple parallel-operating flash channels. Interleaving between channels can significantly improve bandwidth. ③ Embedded Processor Core: Runs complex firmware code, responsible for parsing NVMe instructions, executing scheduling algorithms, handling bad block management, and other high-level logic.

[0076] 2.3 DRAM Cache DRAM cache can be understood as double data rate (DDR) memory chips. It is not standard on all SSDs, but it is crucial for most mainstream and high-performance SSDs. It acts as a high-speed data buffer, storing data mapping tables and data to be processed.

[0077] Its main functions are: ① Storage Mapping Table: The controller needs a huge map, or mapping table, for address translation. This mapping table is a mapping from logical block address (LBA) to physical block address (PBA). By placing this table in the extremely fast DRAM, the controller can instantly find the location of any data, greatly shortening the addressing time. Without DRAM, this table would have to be placed in the much slower NAND flash memory, resulting in long wait times for each lookup and severely impacting performance. ② Data Caching: When writing small amounts of data, the controller first places the data in the fast DRAM, signaling to the computer that the write is complete, and then slowly moves the data from DRAM to NAND flash memory. This acts as a buffer, greatly improving the write speed experienced by the user. During reads, if the data is already in the cache, it can be returned directly, resulting in extremely fast speeds.

[0078] like Figure 1 As shown, this SSD system includes a controller, DRAM, and NAND flash memory. The controller, DRAM, and NAND flash memory are housed in a single module; therefore, failure of any one component necessitates the replacement of the entire SSD. For example, a controller failure would render the entire SSD inoperable, even though the NAND flash memory itself might be functional. The entire SSD becomes unusable simply because the controller and NAND flash memory are soldered together. Typically, NAND flash memory accounts for over 80% of the cost of an SSD, and discarding it would result in significant cost losses. It's clear that in this solution, failure of low-cost components like the controller forces the high-cost NAND flash memory to be scrapped as well, leading to substantial resource waste and cost losses. Therefore, a solid-state drive (SSD) system is needed to reduce hardware failure costs.

[0079] In view of this, this application provides a solid-state drive (SSD) system, which includes at least one master controller node, at least one network switch, and at least one NAND flash memory node. The at least one master controller node can communicate with the at least one network switch via a network protocol, and the at least one network switch can communicate with the at least one NAND flash memory node via a network protocol. That is, in this application, the master controller node and the NAND flash memory node are decoupled and separated, so even if the master controller node fails, it will not affect the NAND flash memory node, thereby reducing hardware failure costs.

[0080] In addition, in this solution, by forming a master control pool from multiple master control devices and a NAND flash memory pool from multiple NAND flash memory devices, the system can dynamically allocate master control resources and NAND resources according to business needs, realize on-demand expansion of storage capacity and elastic scheduling of performance, and significantly improve resource utilization.

[0081] Figure 2 This is a schematic architecture diagram of an SSD system provided in this application. The following is a combination of... Figure 2 This application provides an introduction to the SSD system. For example... Figure 2 As shown, the solid-state drive system includes at least one master control node, at least one network switch, and at least one NAND flash memory node. In this application, each master control node includes at least one master control device, each NAND flash memory node includes at least one NAND flash memory device, and at least one master control node establishes a network connection with at least one NAND flash memory node through at least one network switch, i.e., performs network communication.

[0082] For example, there can be a single network switch. This single network switch can connect all master nodes and all NAND flash memory nodes through its multiple physical ports, achieving full interconnection between any master node and any NAND flash memory node. Exemplarily, either the master node or the NAND flash memory node can be connected to a port of this network switch using a single network cable (e.g., fiber optic cable). Alternatively, if there are multiple network switches, one possible approach is to connect all master nodes and all NAND flash memory nodes using a switch stack; another possible approach is to use a leaf spine architecture. Yet another possible implementation involves a multi-level switching architecture. For example, the master node connects to a first-level switch, and the NAND flash memory node connects to a second-level switch, interconnecting between the two levels, potentially scaling to tens of thousands of nodes. Specifically, the stacking and leaf spine architectures can be understood based on existing publicly available documentation and will not be elaborated further.

[0083] For example, each master node also includes at least one DRAM, which corresponds one-to-one with at least one master device. It can also be understood that both the master device and the DRAM are deployed on the master node.

[0084] For example, the at least one master node is deployed on a compute node, and the at least one NAND flash memory node is deployed on a storage node.

[0085] In this application, the at least one master node is used to communicate with at least one network switch via a network protocol; the at least one network switch is used to communicate with the at least one NAND flash memory node via a network protocol. Figure 2 It can also be seen that in this application, NAND flash memory devices are pooled and become network-accessible resources.

[0086] Generally, a network protocol can be understood as a set of rules, standards, or conventions established for data exchange in a computer network. For example, a network model can be the seven-layer Open Systems Interconnection Reference Model (OSI), or it can be a four-layer, three-layer, etc., with each layer corresponding to a specific protocol. This application does not limit the specific network protocol; the solution provided in this application is applicable to various standard network protocols. For example, the network protocol can be a unified bus (UB) architecture. For example, the network protocol can be compute expresslink (CXL). For example, the network protocol can be Ethernet protocol and InfiniBand (IB) protocol.

[0087] In one possible implementation, the solid-state drive system further includes at least one protocol conversion chip, each chip used to convert network protocols to the ONFi protocol. As mentioned earlier, NAND flash memory devices use the ONFi protocol; therefore, the protocol conversion chip can convert network protocols to the ONFi protocol, thereby enabling communication between the NAND flash memory device and the host device. Alternatively, it can be understood as at least one network switch used to communicate with at least one protocol conversion chip via a network protocol; this at least one protocol conversion chip is used to convert the network protocol to the ONFi protocol; and this at least one protocol conversion chip is used to communicate with at least one NAND flash memory device via the ONFi protocol. For example, at least one protocol conversion chip corresponds one-to-one with at least one NAND flash memory node, where each NAND flash memory node corresponds to one protocol conversion chip. Exemplarily, each NAND flash memory node includes a protocol conversion chip internally (or externally) that can convert network protocols to the ONFi protocol to enable communication with each NAND flash memory device, such as... Figure 3 As shown. For example, each NAND flash memory device in a NAND flash memory node can have its own corresponding protocol conversion chip. In this case, each NAND flash memory device has its own corresponding protocol conversion chip, thereby reducing communication latency.

[0088] In this application, the NAND device accesses the network and achieves end-to-end physical layer data access in accordance with network protocol requirements. The process of establishing the physical layer link and initializing the data link is described below.

[0089] For example, a communication link is established between the master node and the NAND flash memory node via a network cable (e.g., fiber optic cable, copper cable, etc.). Both ends must detect the presence of the other and confirm that the electrical signals are normal (e.g., voltage and clock synchronization) to establish a normal link at the physical layer. For instance, the master node can send an electrical signal, the NAND flash memory node responds, the master node adjusts the voltage / clock, the NAND flash memory node confirms synchronization, and then the two parties can negotiate the data rate to determine the speed. Exemplarily, the master node, NAND flash memory node, and network switch can perform link detection at the physical layer; then, a link can be established based on the physical layer specification, and link parameters can be negotiated using hardware, i.e., an adaptive load balancing algorithm; finally, link initialization is achieved, ensuring that the link has reliable, orderly, and manageable data transmission capabilities. Specifically, the process of establishing a link at the physical layer can be understood by referring to the physical layer handshake process of existing standards, and will not be detailed in this application.

[0090] For example, after establishing a physical link, the data link also needs to be initialized. This can be achieved by establishing a data link layer packet transmission mechanism and enabling link-level reliability features, including packet retry and cyclic redundancy check (CRC) checks, to ensure the link state enters L0 (active) state, meaning the link is fully ready for communication. Specifically, the process of establishing a data link layer can be understood by referring to the existing standard data link layer handshake process, which will not be detailed in this application.

[0091] For example, after the physical and data links are established, the master node needs to identify which NAND devices are available on the network. The master node reads the configuration space of each NAND device to understand who they are, their location, and their respective capabilities, and then allocates them to the system. Alternatively, this can be understood as the at least one master node sending a broadcast request message to at least one network switch. This broadcast request message instructs each NAND flash memory device to report its configuration space information, which is used by the master node to identify and access the NAND flash memory device. The at least one network switch, based on the broadcast request message, obtains the configuration space information of each NAND flash memory device. In other words, in this scheme, after the master node powers on, it can discover remote NAND flash memory devices through network scanning and confirm their identity, thereby establishing a management relationship. Two schemes for discovering NAND flash memory devices are described below.

[0092] In one possible implementation, NAND flash memory devices on the network can be discovered through conventional enumeration. In this case, at least one network switch is used to send a broadcast request message to at least one NAND flash memory node; at least one NAND flash memory node is used to send a broadcast response message to at least one network switch based on the broadcast request message, the broadcast response message carrying the configuration space information of each NAND flash memory device.

[0093] In another possible implementation, the network switch can perform pre-processing by scanning each device on the ports to obtain the configuration space information for each NAND flash memory device. For example, the network switch scans all ports and finds the following information: Port #1: NAND #1, Model XX, Capacity 1TB; Port #2: NAND #2, Model YY, Capacity 2TB; Port #3: NAND #3, Model ZZ, Capacity 512GB. For instance, the network switch can internally create a "virtual NAND flash memory device" containing a table recording information for all real NAND flash memory devices. Therefore, after receiving a broadcast request message from the master node, the network switch can directly send the pre-collected configuration space information for each NAND flash memory device to the master node.

[0094] For example, the configuration space information of a NAND flash memory device may include the following: identification information of the NAND flash memory device, identification information of at least one chip in the NAND flash memory device, and structural information of each chip. The structural information is used to indicate the mapping relationship between the logical ID, plane ID, block ID, and page ID of the logical unit in each chip, as shown in Table 1 below. Figure 4 This is a schematic diagram illustrating the structure of a chip in a NAND flash memory device according to an embodiment of this application, as shown below. Figure 4 As shown, there are two logic units, each corresponding to a chip. Each chip includes multiple planes, each plane includes multiple blocks, and each block includes multiple pages.

[0095] Table 1

[0096] Typically, each NAND flash memory device has standardized configuration space information, which includes a basic configuration header, a capability list, specific NAND device configurations, and vendor-defined extended information. For example, (1) Basic configuration header: includes: device identifier, vendor identifier, device model, configuration space version number, configuration header length, and capability list pointer. (2) Capability list: includes capability identifier, pointer to the next capability, and capability data (e.g., specific capability information). Capability identifier #1 is used to indicate basic NAND capabilities (e.g., core NAND parameters), capability identifier #2 is used to indicate a page structure list (e.g., page / block / plane / logical cell), capability identifier #3 is used to indicate timing parameters (e.g., read / write / erase time), capability identifier #4 is used to indicate network signals (e.g., Internet Protocol (IP), port), and capability identifier #5 is used to indicate extended functions (e.g., temperature control, etc.). (3) Specific configuration of NAND devices: ① Chip information: number of chips and chip identifier list; ② Page structure list: page size, number of pages in each block, number of blocks in each plane, number of planes, logic cell identifier, plane identifier, block identifier, page identifier, etc. Specifically, the understanding and introduction of the configuration space can be understood by referring to the existing published documents, and will not be detailed in this application. In general, the capability list is the key to identifying NAND devices. If a device has the capability identifier in the configuration space information, the master node can determine that the device is a NAND device. For example, when the system starts, all devices can be found by scanning the configuration space. Then, the extended capability list in the configuration space information of each device is checked. The master node assigns an additional local identifier to each NAND flash memory device and creates a mapping relationship between NAND flash memory devices and chip structure information.

[0097] In one possible implementation, the solid-state drive system further includes at least one management module. Each management module stores a global mapping relationship, which includes multiple mapping relationships indicating at least one logical address managed by multiple master devices, the physical address corresponding to each logical address, and path information. The physical address indicates the target NAND flash memory device corresponding to the logical address, the target chip within the target NAND flash memory device, the target logical cell within the target chip, the target plane within the target logical cell, the target block within the target plane, and the target page within the target block. The path information indicates routing information for the network topology from the master device to the physical address; for example, the routing information indicates the target network switch corresponding to the master device, the target NAND flash memory device, and the target chip within the target NAND flash memory device.

[0098] This can also be understood as the global mapping relationship including at least one logical address managed by each of the master control devices, the physical address corresponding to each logical address, and path information. For example, the physical address can be understood as indicating the target NAND flash memory device, the target chip within the target NAND flash memory device, the target logical unit, target plane, target block, and target page within the target chip. For example, the path information is used to indicate the forwarding path of the network switch; for instance, it indicates that data is first sent from the master control device to the target network switch, then exits from the target port of the target switch, and finally reaches the target chip in the target NAND flash memory device. Then, data is accessed in the target logical unit, the target plane within the target logical unit, the target block within the target plane, and the target page within the target block.

[0099] For example, assume there are two master control nodes, namely master control node #1 and master control node #2. Each master control node includes two master control devices. For instance, master control node #1 includes master control device #1 and master control device #2, and master control node #2 includes master control device #3 and master control device #4. For example, mapping relationship #1 indicates the correspondence between the logical address #1 managed by master control device #1, the physical address #1 corresponding to that logical address #1, and the path information #1. For example, mapping relationship #2 indicates the correspondence between the logical address #2 managed by master control device #1, the physical address #2 corresponding to that logical address #2, and the path information #2. For example, mapping relationship #3 indicates the correspondence between the logical address #3 managed by master control device #2, the physical address #3 corresponding to that logical address #3, and the path information #3. For example, mapping relationship #4 indicates the correspondence between the logical address #4 managed by master control device #2, the physical address #4 corresponding to that logical address #4, and the path information #4. For example, mapping relationship #5 is used to indicate the correspondence between logical address #5 managed by master control device #2, physical address #5 corresponding to logical address #5, and path information #5. For example, mapping relationship #6 is used to indicate the correspondence between logical address #6 managed by master control device #3, physical address #6 corresponding to logical address #6, and path information #6. For example, mapping relationship #7 is used to indicate the correspondence between logical address #7 managed by master control device #4, physical address #7 corresponding to logical address #7, and path information #7, and so on. For example, each mapping relationship can be understood with reference to Table 2 below.

[0100] Table 2

[0101] For example, a physical address can be understood as the final physical address of data within a NAND flash memory device (e.g., logical cell / plane / block / page). For example, path information can be understood as network topology routing information from the host device to that physical address (e.g., host device → network switch → NAND flash memory device → chip). That is, the physical address is used for internal addressing within the NAND flash memory device, and the path information is used for network layer routing and forwarding, thereby achieving a complete end-to-end data access path.

[0102] For example, a network switch can store a routing table that indicates the port corresponding to each NAND flash memory device and the port corresponding to the host device, for quickly forwarding data packets to the target NAND flash memory device or the target host device. For instance, this routing table stores: NAND#1 Port #1, NAND #2 Port #2, NAND #3 Port #3; Main control device #1 Port #4, Main control device #2 Port #5, Main control device #3 Port #6.

[0103] For example, suppose the master control device #1 wants to read data. The master control device can obtain the mapping relationship and find that the data is located in logical unit #1, plane #1, block #1, and page #1 of chip #1 in NAND #1. Then, the master control device #1 can send a data packet to network switch #1 (assuming there is only one network switch, and all master control devices communicate with this network switch). The destination of this data packet is NAND #1, and the content of the data packet is to read logical unit #1, plane #1, block #1, and page #1 of chip #1. Network switch #1 receives the packet and can look up the routing table to determine NAND #1. Port #1 is the port from which data packets need to be forwarded, regardless of the content of the data packets. Afterwards, NAND #1 receives the data packets, parses their content, and determines that it needs to read logical unit #1, plane #1, block #1, and page #1 of chip #1. Data can then be read from the corresponding locations, and the returned data will be retrieved.

[0104] In another implementation, the solid-state drive system further includes at least one management module. Each management module stores a global mapping relationship, which includes multiple mapping relationships indicating the correspondence between multiple virtual address information and multiple real address information. The multiple virtual address information indicates at least one logical address managed by each of the multiple master devices, and the physical address of the virtual NAND flash memory device corresponding to each logical address. The multiple real address information indicates the physical address and path information of the real NAND flash memory device corresponding to the physical address of each virtual NAND flash memory device. The physical address indicates the target NAND flash memory device corresponding to the logical address, the target chip in the target NAND flash memory device, the target logical unit in the target chip, the target plane in the target logical unit, the target block in the target plane, and the target page in the target block. The path information indicates the routing information of the network topology from the master device to the physical address.

[0105] This can also be understood as follows: in this implementation, virtual address information is used to indicate the original mapping relationship stored in the master node, while real address information is used to indicate the actual mapping relationship used for data access. In other words, for compatibility with existing technologies and to reduce modification costs, each master node still uses the previous mapping relationship (for example, it can use the existing FTL), but the physical address is not the real physical address and needs to be translated a second time; at this point, another layer of translation can be added: translating the physical address of the local device (which can also be understood as the virtual NAND flash memory device) into the physical address of the real remote device (which can also be understood as the real NAND flash memory device). Figure 5 This application illustrates a schematic diagram of the relationship between a local NAND flash memory device and a remote NAND flash memory device, as shown below. Figure 5 As shown, a mapping relationship can be established between the physical addresses of local NAND flash memory devices and remote NAND flash memory devices. In this case, the global mapping relationship stored in the management module can translate the physical address of the local NAND flash memory device into the physical address of the remote NAND flash memory device. Alternatively, in this application, the controller device can internally map the physical address of the remote NAND flash memory device to achieve standard SSD management. The method of managing the remote NAND flash memory device is consistent with the way the SSD controller device manages the local NAND flash memory device.

[0106] For example, each master control node also stores local mapping relationships, which are subsets of the global mapping relationships. These local mapping relationships are some or all of the master control device-related mapping relationships included in the master control node. In other words, the global mapping relationships include all master control device-related mapping relationships across all master control nodes, while the mapping relationships stored in each master control node may only involve a portion of the mapping relationships. For instance, the mapping relationships stored in a master control node may be all or only some of the master control device-related mapping relationships it includes. For example, when a master control device finds that its locally stored local mapping relationships do not contain the physical address and path information corresponding to a certain logical address, it can request the physical address and path information corresponding to that logical address from the management module and cache it, thus updating its local local mapping relationships. Subsequently, if the logical address is encountered again, it can directly search from the locally cached local mapping relationships, thereby achieving fast data access.

[0107] For example, in this application, a global mapping relationship can be established and maintained through a fabric manager (FM) to record the specific location of each page in the block, plane, logic unit, chip, and NAND flash memory device, and distribute the local mapping relationship in the global mapping relationship to each master device, thereby enabling any master device to find and access any data page on any NAND flash memory device through the network, and at the same time having the ability to reconstruct data after any master device fails.

[0108] The above solution mainly introduces the SSD system provided in this application, as well as the process of establishing the physical link, establishing the data link, discovering the NAND flash memory device by the master node, and mapping the NAND flash memory device. Based on the SSD system architecture provided by the above solution, the following section discusses... Figure 3 This application provides a schematic flowchart of a method 300 for accessing a NAND flash memory device. For a detailed understanding of method 300, please refer to the above description of the SSD system architecture. This section primarily focuses on describing the method flow and steps; specific details can be found above. Figures 2-5 The relevant content will be understood without further explanation.

[0109] This application provides a method 300 that can be applied to a solid-state drive (SSD) system. As previously described, the SSD system includes at least one master controller node, at least one network switch, and at least one NAND flash memory node. Each master controller node includes at least one master controller device, and each NAND flash memory node includes at least one NAND flash memory device. The at least one master controller node establishes a network connection with the at least one NAND flash memory node through the at least one network switch. The method includes: 310, at least one master node, communicating with at least one network switch via network protocols.

[0110] 320, at least one network switch, communicating with at least one NAND flash memory node via a network protocol.

[0111] In one possible implementation, the solid-state drive system further includes at least one protocol conversion chip. In this case, the at least one network switch communicates with the at least one protocol conversion chip via a network protocol. The at least one protocol conversion chip converts the network protocol into an open NAND flash memory interface protocol. The at least one protocol conversion chip communicates with at least one NAND flash memory device via the open NAND flash memory interface protocol.

[0112] In one possible implementation, method 300 further includes: at least one master node sending a broadcast request message to at least one network switch, the broadcast request message instructing each NAND flash memory device to report its respective configuration space information, the configuration space information being used by the master node to identify and access the NAND flash memory device; and at least one network switch obtaining the respective configuration space information of each NAND flash memory device based on the broadcast request message. For example, NAND flash memory devices can be discovered in two ways.

[0113] In one possible implementation, NAND flash memory devices on the network can be discovered through conventional enumeration. In this case, at least one network switch sends a broadcast request message to at least one NAND flash memory node; at least one NAND flash memory node, based on the broadcast request message, sends a broadcast response message to at least one network switch, the broadcast response message carrying the configuration space information of each NAND flash memory device.

[0114] In another possible implementation, the network switch can perform pre-preparatory work by scanning each device on the ports to obtain the configuration space information for each NAND flash memory device. For example, the network switch scans all ports and finds the following information: Port #1: NAND #1, Model XX, Capacity 1TB; Port #2: NAND #2, Model YY, Capacity 2TB; Port #3: NAND #3, Model ZZ, Capacity 512GB. Alternatively, the network switch can internally create a "virtual NAND flash memory device" containing a table recording information for all real NAND flash memory devices. Therefore, after receiving a broadcast request message from the master node, the network switch can directly send the pre-collected configuration space information of each NAND flash memory device to the master node.

[0115] The following example illustrates the complete process of data request and response.

[0116] For example, when master device #1 receives a request from host device #1 to read data at logical address 0x1000, master device #1 queries its local cache mapping to obtain the physical addresses of this logical address pair as: NAND #1, chip #1, logical unit #1, plane #1, block #1, page #1, and obtains the path information: master device #1 → network switch #1 → port #1 → NAND #1 → chip #1 → logical unit #1 → plane #1 → block #1 → page #1. Then, master device #1 can construct a data packet, for example, with the source address being master device #1, the destination address being NAND #1, and carrying a read command, relevant parameters (chip #1, logical unit #1, plane #1, block #1, page #1), and data length (e.g., 16KB). Next, master device #1 sends a request to network switch #1. The network switch queries its routing table to find that the outgoing port corresponding to NAND #1 is port #1. The network switch can then forward the data packet from port #1. For example, protocol conversion chip #1 receives a data packet from port #1, parses the packet to obtain a read command, and retrieves relevant parameters and data length. Protocol conversion chip #1 can convert the network protocol (e.g., NVMe protocol) to the ONFi protocol, transforming the network data packet into an ONFi protocol data packet that the NAND flash memory device can parse, and then send it to NAND flash memory device #1 via the ONFi bus. After receiving the command, NAND flash memory device #1 can perform a read operation at the location indicated by the relevant parameters.

[0117] For example, after completing the data reading, NAND flash memory device #1 can return the read data to protocol conversion chip #1 via the ONFi bus. At this time, the protocol conversion chip can convert the ONFi protocol to a network protocol, packaging the raw data returned by NAND flash memory device #1 into a network data packet. For example, the source address of this network data is NAND flash memory device #1, and the destination address is master device #1. Protocol conversion chip #1 sends the network data packet to network switch #1. Network switch #1 sees that the destination address is master device #1 and, by looking up the routing table, learns that the port corresponding to master device #1 is port #4, so it forwards the network data packet from port #4. Afterwards, master device #1 receives the data packet from port #4, parses it, obtains the data, and returns the data to the upper-layer application, such as the CPU of the host device.

[0118] The NAND flash memory nodes provided in this application can also apply erasure coding technology, thereby improving the reliability of data storage. This can also be understood as NAND flash memory devices being managed as distributed nodes, reducing the impact of NAND device failures. The following mainly introduces the system and method for data storage using EC technology in distributed NAND flash memory devices in this application.

[0119] In one possible implementation, each NAND flash memory node includes multiple NAND flash memory devices. Some of these NAND flash memory devices are used to store at least one data shard of the original data, and the remaining NAND flash memory devices are used to store at least one verification data. The original data consists of multiple data shards, which correspond to the respective NAND flash memory devices. Each verification data is obtained by performing calculations on the multiple data shards.

[0120] In this application, data fragmentation can be understood as the division of the original data into different parts, such as data blocks.

[0121] For example, these multiple data shards correspond to this portion of NAND flash memory devices, which can be understood as multiple data shards being distributed and stored on this portion of NAND flash memory devices. For instance, there are three data shards and three NAND flash memory devices. In this case, two of the three NAND flash memory devices (an example of a portion of NAND flash memory devices) are used to store the three data shards respectively (for example, one of the two NAND flash memory devices stores two of the data shards, and the other NAND flash memory device stores the remaining data shard). The remaining NAND flash memory device can be used to store verification data.

[0122] In this application, the purpose of the check data is to recover the lost data by using the remaining data fragments and the check data through mathematical operations when some data fragments are lost or corrupted. For example, the check data block can be calculated using a simple algorithm based on XOR operations; or, for example, the check data block can be calculated using a complex algorithm based on Vandermonde or Cauchy matrices, and so on. For specific details, please refer to existing publicly available EC technologies; this application will not elaborate further.

[0123] For example, NAND flash node #1 includes four NAND flash devices: NAND flash device #1, NAND flash device #2, NAND flash device #3, and NAND flash device #4. For instance, data #A is divided into three data shards: data shard #A1, data shard #A2, and data shard #A3. For example, block #1 in logical unit #1 of NAND flash device #1 stores data shard #A1; block #1 in logical unit #1 of NAND flash device #2 stores data shard #A2; block #1 in logical unit #1 of NAND flash device #3 stores data shard #A3; and block #1 in logical unit #1 of NAND flash device #4 stores parity data P1 (in this case, these four blocks can also be understood as forming an EC group). For example, if NAND flash memory device #1 fails, data fragment #A2 from NAND flash memory device #2, data fragment #A3 from NAND flash memory device #3, and verification data #P1 from NAND flash memory device #4 can be used to calculate data fragment #A1, thus enabling data recovery. It can be seen that the solution provided in this application can ensure data reliability between different NAND flash memory devices.

[0124] For example, the algorithm and data distribution of each EC group can be recorded through metadata. For instance, EC group #1 includes: data shard #A1 stored in block #1 of logical cell #1 of NAND flash memory device #1; data shard #A2 stored in block #1 of logical cell #1 of NAND flash memory device #2; data shard #A3 stored in block #1 of logical cell #1 of NAND flash memory device #3; and parity data #P1 stored in block #1 of logical cell #1 of NAND flash memory device #4. Subsequently, if a NAND flash memory device #1 is found to be unresponsive, the metadata can be queried to determine the EC group associated with that NAND flash memory device #1 and the stored data shards. For example, a query might typically find that the NAND flash memory device #1 is associated with EC group #1, and that A1 is missing from EC group #1, which can trigger a data recovery mechanism. For example, data fragment #A2 is read from block #1 of logical cell #1 in NAND flash memory device #2, data fragment #A3 is read from block #1 of logical cell #1 in NAND flash memory device #3, and checksum data #P1 is read from block #1 of logical cell #1 in NAND flash memory device #4. The corresponding EC algorithm is then used to recover data fragment #A1. For example, data fragment #A1 can be written to a new, healthy NAND flash memory device, such as NAND flash memory device #5, and the metadata can be updated: the new location of data fragment #A1 is stored in block #1 of logical cell #1 in NAND flash memory device #5.

[0125] In another possible implementation, each NAND flash memory device includes multiple chips, some of which are used to store at least one data shard of the original data, and the remaining chips are used to store at least one verification data. The original data consists of multiple data shards, which correspond to the respective chips, and each verification data is obtained by performing calculations on the multiple data shards.

[0126] For example, NAND flash memory device #5 includes four chips: chip #1, chip #2, chip #3, and chip #4. For instance, data #B is divided into three data shards: data shard #B1, data shard #B2, and data shard #B3. For example, block #2 of logic unit #2 in chip #1 stores data shard #B1, block #2 of logic unit #2 in chip #2 stores data shard #B2, block #2 of logic unit #2 in chip #3 stores data shard #B3, and block #2 of logic unit #2 in chip #4 stores checksum data P2 (in this case, these four blocks can also be understood as forming an EC group). For example, if chip #1 fails, data fragment #B2 from block #2 of logic unit #2 in chip #2, data fragment #B3 from block #2 of logic unit #2 in chip #3, and verification data #P2 from block #2 of logic unit #2 in chip #4 can be used to calculate data fragment #B1, thus enabling data recovery. It can be seen that the solution provided in this application can ensure data reliability between different chips within a NAND flash memory device.

[0127] Furthermore, this application enables the management of distributed NAND flash memory devices. For example, if a master controller fails, it can be replaced, another master controller can be activated, and the FTL table can be synchronized with the other master controller to rebuild the data, thus achieving rapid takeover of business data. For instance, a hot-standby master controller can quickly take over data, reducing the impact of failures.

[0128] The above scheme can also be understood as follows: the first master control node includes a first master control device and a second master control device; the global mapping relationship includes at least one first mapping relationship; each first mapping relationship is used to indicate at least one first logical address managed by the first master control device, the first physical address corresponding to each first logical address, and the first path information; when the first master control device fails, at least one management module is used to update the at least one first mapping relationship; each updated first mapping relationship is used to indicate at least one first logical address managed by the second master control device, the updated first physical address corresponding to each first logical address, and the updated first path information; the second master control device is used to obtain the updated at least one first mapping relationship from at least one management module; the second master control device is used to access data according to the updated at least one first mapping relationship.

[0129] For example, "data access" can be understood as the process of reading, writing, modifying, deleting, or transferring data.

[0130] For example, master node #1 includes two master devices, master device #1 and master device #2. If master device #1, which is currently working, suddenly crashes or becomes damaged, the NAND flash memory devices it was originally responsible for may become temporarily inaccessible, and services may be interrupted. In this scenario, this application proposes that when the system detects that master device #1 is unresponsive, it can be removed from the resource pool, no new tasks will be assigned to it, and it will be marked as faulty. Then, a backup master device #2 is activated, for example, master device #2 is always in a hot standby state (e.g., power is connected, network is connected). At this time, the management module can update the global mapping relationship and instruct the network switch that the NAND flash memory devices originally managed by master device #1 are now taken over by master device #2. At this time, the network switch can update the routing table, that is, update the outgoing port corresponding to the original master device #1 to the outgoing port corresponding to master device #2. Master device #2 can obtain the FTL table stored in the original master device #1 from the management module and load it into its own memory. At this point, master device #2 has the FTL table, which tells it the physical address and path information corresponding to each logical address. It also knows which data groups form EC groups and how the data is distributed. Afterward, it can begin normal service and process read and write requests. If master device #1 fails and some data is still in the cache and hasn't been written to the NAND flash memory, this data can be recalculated using EC technology or recovered from other copies, ultimately successfully writing the data to the NAND flash memory.

[0131] Correspondingly, the method can be understood as follows: at least one management module is used to update at least one first mapping relationship, and each updated first mapping relationship is used to indicate at least one first logical address managed by the second master control device, the updated first physical address corresponding to each first logical address, and the updated first path information; the second master control device is used to obtain the updated at least one first mapping relationship from at least one management module; the second master control device is used to access data according to the updated at least one first mapping relationship.

[0132] Based on the above technical solutions, this application reduces the impact of main control equipment failure on the system by using a backup main control equipment takeover scheme. It also solves the problem of large-scale data loss on NAND flash memory devices after the main control equipment or DRAM is replaced due to failure, reduces data reconstruction time, and improves system reliability.

[0133] For example, the solution provided in this application is used in SSD usage scenarios of a certain scale, including but not limited to data centers such as cloud / Internet / AI / big data centers. For example, it can be applied to distributed storage systems of a certain scale.

[0134] For example, the solution provided in this application can be applied in cloud scenarios (e.g., public cloud, private cloud) or in ordinary scenarios (e.g., single-machine deployment). Figure 6 This is another schematic diagram of a cloud service system architecture to which this application applies, such as Figure 6 As shown, the cloud service system architecture may include: a cloud management platform 610, an internet connection 620, and a client 630. For example... Figure 6 As shown, the cloud management platform 610 is used to manage the infrastructure that provides multiple cloud services. The infrastructure includes multiple cloud data centers, each containing at least one server, and each server containing cloud service resources to provide corresponding cloud services to tenants. For example, the cloud service resources could be cloud databases.

[0135] For example, the method provided in this application can be applied to a cloud service system, which includes a cloud management platform and infrastructure. The cloud management platform is used to manage the infrastructure that provides cloud services (e.g., SSD storage services). For example, the infrastructure includes at least one data center, which is equipped with at least one server. For example, the infrastructure can perform the method 300 described above. For example, interaction with users can be achieved through the cloud management platform.

[0136] For example, both cloud management platforms and infrastructure can be implemented through software or hardware. The implementation of infrastructure will be described below as an example. Similarly, the implementation of a cloud management platform can refer to the implementation of infrastructure. For instance, user interaction can be achieved through a cloud management platform.

[0137] As an example of a software functional unit, the infrastructure can include code running on compute instances. A compute instance can be at least one of a physical host (compute device), virtual machine, container, or other compute device. Furthermore, the aforementioned compute device can be one or more. For example, the infrastructure can include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the application can be distributed within the same region or in different regions. The multiple hosts / virtual machines / containers used to run the code can be distributed within the same availability zone (AZ) or in different AZs, each AZ comprising one or more geographically proximate data centers. Typically, a region can include multiple AZs.

[0138] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same Virtual Private Cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a single region. Communication between two VPCs within the same region, and between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0139] As an example of a hardware functional unit, an infrastructure may include at least one computing device, such as a server. Alternatively, the infrastructure may be implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0140] The infrastructure includes multiple computing devices that can be distributed within the same region or in different regions. Similarly, the infrastructure includes multiple computing devices that can be distributed within the same Availability Zone (AZ) or in different AZs. Likewise, the YY device includes multiple computing devices that can be distributed within the same Virtual Private Cloud (VPC) or in multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0141] It is understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0142] It should also be understood that the ordinal numbers such as "first" and "second" mentioned in this application are used to distinguish multiple objects, and are not used to limit the size, content, order, timing, priority or importance of multiple objects.

[0143] It should also be understood that, in this application, "at least one" means one or more, and "more than one" means two or more. "At least one item" or similar expressions mean one or more items, that is, any combination of these items, including any combination of single items or multiple items. For example, at least one of a, b, or c means: a, b, c, a and b, a and c, b and c, or a and b and c.

[0144] It should also be understood that, in the various embodiments of this application, determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other data.

[0145] It should be noted that the various implementation methods in this application can be reasonably combined according to their internal logic.

[0146] Those skilled in the art will recognize that, based on the units and algorithm steps described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is implemented in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0147] This application can divide a computing device into functional modules based on the above method example. For example, it can divide the device into separate functional modules corresponding to each function, or it can integrate two or more functions into one processing module. The integrated modules can be implemented in hardware or as software functional modules. It should be noted that the module division in this application is illustrative and only represents one logical functional division; other division methods may be used in actual implementation. The following explanation uses the division of functional modules according to each function as an example.

[0148] Figure 7 This is a schematic block diagram of the computing device 700 provided in this application. As shown in the figure, the computing device 700 may include: a transceiver module 710 and a processing module 720.

[0149] For example, in one possible implementation, Figure 7 The computing device 700 shown can be understood as a master node; for example, in another possible implementation, Figure 7 The computing device 700 shown can be understood as a network switch. For example, in another possible implementation, Figure 7 The computing device 700 shown can be understood as a NAND flash memory node. For example, the computing device 700 can also be understood as a protocol conversion chip.

[0150] It should be understood that the computing device 700 here is embodied in the form of a functional unit. The term "unit" here may refer to application-specific integrated circuits (ASICs), electronic circuits, processors (e.g., shared processors, proprietary processors, or group processors) and memory for executing one or more software or firmware programs, integrated logic circuits, and / or other suitable components that support the described functions.

[0151] Each module in this computing device can be implemented in software or hardware. For example, the implementation of the transceiver module 710 will be described below. Similarly, the implementation of other modules can refer to the implementation of the transceiver module 710.

[0152] As an example of a software functional unit, the transceiver module 710 may include code running on a computing instance. The computing instance may include at least one of a physical host (computing device), a virtual machine, or a container. Further, the aforementioned computing instance may be one or more. For example, the transceiver module 710 may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed in the same region or in different regions. Further, the multiple hosts / virtual machines / containers used to run the code may be distributed in the same Availability Zone (AZ) or in different AZs, each AZ including one or more geographically proximate data centers. Typically, a region may include multiple AZs.

[0153] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same VPC or across multiple VPCs. Typically, a VPC is set up within a region. Communication between two VPCs within the same region, as well as between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0154] As an example of a hardware functional unit, the transceiver module 710 may include at least one computing device, such as a server. Alternatively, the transceiver module may be implemented using a CPU, an ASIC, or a PLD. The aforementioned PLD may be implemented using a CPLD, FPGA, GAL, DPU, NPU, SoC, offload card, accelerator card, or any combination thereof.

[0155] The transceiver module 710 includes multiple computing devices that can be distributed within the same region or in different regions. Similarly, the multiple computing devices in this module can be distributed within the same Availability Zone (AZ) or in different AZs. Likewise, the multiple computing devices in this module can be distributed within the same Virtual Private Cloud (VPC) or multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, GALs, DPUs, NPUs, SoCs, offloading cards, and accelerator cards.

[0156] It should be noted that in other embodiments, the transceiver module 710 can be used to execute any step in method 300, and the other modules can also be used to execute any step in method 300. The steps that each module is responsible for implementing can be specified as needed. All functions of the computing device 700 can be realized by implementing different steps in method 300 through each module.

[0157] For example, the computing device 700 has the function of implementing the corresponding steps of the method 300 described above. This function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the functions described above; for example, each module can be replaced by a processor, which respectively executes the transmit / receive operations and related processing operations in each method embodiment. Furthermore, each module can also be a processing circuit.

[0158] It should be pointed out that, Figure 7 The computing device mentioned can be the computing device in the foregoing method embodiments (e.g., a server for providing cloud services), or it can be a chip or chip system corresponding to the computing device, such as a SoC. Each module is a processor, microprocessor, or integrated circuit integrated on the chip. No limitation is made here.

[0159] Figure 8 This is a schematic block diagram of another computing device 800 provided in this application. As shown, the computing device 800 includes: a communication interface 810 and at least one processor 820. The processor 820 is coupled to a memory and is used to execute instructions stored in the memory to send and / or receive signals. Optionally, the computing device 800 also includes a memory 830 for storing instructions. The memory 830 and the processor 820 are connected via a bus 840. For example, the computing device 800 may be a server. It should be understood that this application does not limit the number of processors and memories in the computing device 800.

[0160] It should be understood that the processor 820 and memory 830 described above can be combined into a computing device, with the processor 820 executing the program code stored in the memory 830 to achieve the above functions. In specific implementations, the memory 830 can be integrated into the processor 820 or independent of the processor 820.

[0161] The 840 bus can be a Peripheral Component Interconnect Express (PCIe) bus, an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (Ubus or UB), a Compute Express Link (CXL) bus, a Cache Coherent Interconnect for Accelerators (CCIX) bus, etc. The Unified Bus is also known as the Lingqu Bus. Buses can be divided into address buses, data buses, control buses, etc. For ease of representation, Figure 8The bus 640 may be represented by a single line, but this does not mean that there is only one bus or one type of bus. The bus 640 may include a path for transmitting information between various components of the computing device 800 (e.g., memory 830, processor 820, communication interface 810).

[0162] The memory 830 stores executable program code, and the processor 820 executes this executable program code to implement the functions of the aforementioned modules, thereby implementing the method in this application. That is, the memory 830 stores instructions for executing the above-described method 300. For example, the processor 820 executes the computer program or instructions stored in the memory 830 to implement the various steps in the above-described method 300.

[0163] It should be understood that the computing device 800 according to the embodiments of this application may correspond to the computing device 700 of this application, and may correspond to the corresponding subject executing the method 300 according to the embodiments of this application. The above and other operations and / or functions of each module in the device are respectively for implementing the corresponding process of method 300. For the sake of brevity, they will not be described in detail here.

[0164] The communication interface 810 uses transceiver modules such as, but not limited to, network interface cards and transceivers to enable communication between the computing device 800 and other devices or communication networks.

[0165] This application also provides a chip system including a processor and a power supply circuit. The power supply circuit supplies power to the processor, which executes the operation steps corresponding to method 300. For simplicity, further details are omitted here. The processor can be implemented using a GPU, or it can be implemented using computing devices such as a DPU, NPU, XPU, SoC, offloading card, or accelerator card.

[0166] Figure 9 This is a schematic diagram of a computing device cluster architecture provided in this application. The computing device cluster includes at least one computing device. This computing device can be a server, such as a central server, an edge server, or a local server in a local data center. In some embodiments, the computing device can also be a terminal device such as a desktop computer, a laptop computer, or a smartphone. Figure 9 As shown, the computing device cluster includes at least one computing device 900. The memory 930 of one or more computing devices 900 in the computing device cluster may store the same instructions for performing the actions described in embodiment 300 above.

[0167] In some possible implementations, the memory 930 of one or more computing devices 900 in the computing device cluster may also store partial instructions for performing the actions executed in the method 300 described in the above embodiments. In other words, a combination of one or more computing devices 900 can jointly execute instructions for performing the actions executed by the method 300 described in the above embodiments.

[0168] It should be noted that the memory 930 in different computing devices 900 within the computing device cluster can store different instructions, each used to execute a portion of the functions of the computing device 900. That is, the instructions stored in the memory 930 of different computing devices 900 can implement the functions of one or more of the aforementioned modules.

[0169] Alternatively, the memories 930 in different computing devices 900 within the computing device cluster can store different instructions, each used to execute a portion of the functions of the computing devices corresponding to the aforementioned computing devices 700-800. That is, the instructions stored in the memories 930 of different computing devices 900 can implement the functions of one or more of the aforementioned modules.

[0170] In some possible implementations, one or more computing devices in a computing device cluster can be connected via a network. This network can be a wide area network (WAN) or a local area network (LAN), etc. Figure 10 One possible implementation is shown, such as Figure 10 As shown, the two computing devices 900A and 900B are connected via a network. Specifically, they are connected to the network through the communication interfaces in each computing device.

[0171] It should be understood that Figure 10 The functions of the computing device 900A shown can also be performed by multiple computing devices 900. Similarly, the functions of the computing device 900B can also be performed by multiple computing devices 900. For example, different computing devices can implement the functions of different modules. Figure 10 The connection method between the computing device clusters shown can be considered that, in some scenarios, the method provided in this application needs to use both the master node and the NAND flash memory node at the same time. Therefore, it is considered to delegate the functions implemented by the master node to the computing device 900A.

[0172] In this embodiment, a computer program product containing instructions is also provided. The computer program product may be a software or program product containing instructions capable of running on a computing device cluster or stored on any available medium. When run by the computing device cluster, it causes the computing device cluster to perform the methods provided above, or causes the computing device cluster to implement the functions of the apparatus provided above.

[0173] In this embodiment, a computer-readable storage medium is also provided. This computer-readable storage medium can be any available medium that a computing device can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., a solid-state drive). The computer-readable storage medium includes instructions that, when executed on a computing device, cause the computing device to perform the method described above.

[0174] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

Claims

1. A solid-state drive system, characterized in that, The solid-state drive system includes at least one master controller node, at least one network switch, and at least one NAND flash memory node. Each master controller node includes at least one master controller device, and each NAND flash memory node includes at least one NAND flash memory device. The at least one master controller node establishes a network connection with the at least one NAND flash memory node through the at least one network switch. The at least one master control node is used to communicate with the at least one network switch via a network protocol; The at least one network switch is used to communicate with the at least one NAND flash memory node via the network protocol.

2. The system according to claim 1, characterized in that, The solid-state drive system further includes at least one protocol conversion chip, and the at least one network switch is used to communicate with the at least one NAND flash memory node via the network protocol, including: The at least one network switch is used to communicate with the at least one protocol conversion chip via the network protocol; The at least one protocol conversion chip is used to convert the network protocol into an open NAND flash memory interface protocol; The at least one protocol conversion chip is used to communicate with the at least one NAND flash memory device via the open NAND flash memory interface protocol.

3. The system according to claim 1 or 2, characterized in that, The at least one master node is configured to send a broadcast request message to the at least one network switch. The broadcast request message is configured to instruct each NAND flash memory device to report its respective configuration space information. The configuration space information is used by the master node to identify and access the NAND flash memory device. The at least one network switch is configured to obtain the configuration space information of each NAND flash memory device according to the broadcast request message.

4. The system according to claim 3, characterized in that, The configuration space information includes the identification information of the NAND flash memory device, the identification information of at least one chip in the NAND flash memory device, and the structural information of each chip. The structural information is used to indicate the mapping relationship between the identifiers of logic units, plane identifiers, block identifiers, and page identifiers in each chip.

5. The system according to any one of claims 1 to 4, characterized in that, The solid-state drive system further includes at least one management module, each management module being used to store global mapping relationships. The global mapping relationships include multiple mapping relationships, which are used to indicate at least one logical address managed by each of the multiple master control devices, the physical address corresponding to each logical address, and path information. The physical address is used to indicate the target NAND flash memory device corresponding to the logical address, the target chip in the target NAND flash memory device, the target logical unit in the target chip, the target plane in the target logical unit, the target block in the target plane, and the target page in the target block. The path information is used to indicate routing information of the network topology from the master control device to the physical address.

6. The system according to any one of claims 1 to 4, characterized in that, The solid-state drive system further includes at least one management module. Each management module stores a global mapping relationship, which includes multiple mapping relationships. These multiple mapping relationships indicate the correspondence between multiple virtual address information and multiple real address information. The multiple virtual address information indicates at least one logical address managed by each of the multiple master controllers, and the physical address of the virtual NAND flash memory device corresponding to each logical address. The multiple real address information indicates the physical address and path information of the real NAND flash memory device corresponding to the physical address of each virtual NAND flash memory device. The physical address is used to indicate the target NAND flash memory device corresponding to the logical address, the target chip in the target NAND flash memory device, the target logic unit in the target chip, the target plane in the target logic unit, the target block in the target plane, and the target page in the target block. The path information is used to indicate the routing information of the network topology from the master control device to the physical address.

7. The system according to claim 5 or 6, characterized in that, Each master control node is also used to store local mapping relationships, which are subsets of the global mapping relationships. The local mapping relationships are mapping relationships related to some or all of the master control devices included in the master control node.

8. The system according to any one of claims 1 to 7, characterized in that, Each NAND flash memory node includes multiple NAND flash memory devices. Some of the NAND flash memory devices are used to store at least one data shard of the original data, and the remaining NAND flash memory devices are used to store at least one verification data. The original data is composed of multiple data shards, which correspond to the partial NAND flash memory devices. Each verification data is obtained by performing calculations on the multiple data shards.

9. The system according to any one of claims 1 to 8, characterized in that, Each NAND flash memory device includes multiple chips, some of which are used to store at least one data shard of raw data, and the remaining chips are used to store at least one verification data. The raw data is composed of multiple data shards, which correspond to the partial chips. Each verification data is obtained by performing calculations on the multiple data shards.

10. The system according to any one of claims 5 to 9, characterized in that, The first master control node includes a first master control device and a second master control device. The global mapping relationship includes at least one first mapping relationship. Each first mapping relationship is used to indicate at least one first logical address managed by the first master control device, the first physical address corresponding to each first logical address, and first path information. In the event of a failure of the first master control device... The at least one management module is used to update the at least one first mapping relationship, and each updated first mapping relationship is used to indicate the at least one first logical address managed by the second master control device, the updated first physical address corresponding to each first logical address, and the updated first path information; The second master control device is used to obtain the updated at least one first mapping relationship from the at least one management module; The second master control device is used to access data according to the updated first mapping relationship.

11. A method for accessing a NAND flash memory device, characterized in that, The method is applied to a solid-state drive (SSD) system, which includes at least one master controller node, at least one network switch, and at least one NAND flash memory node. Each master controller node includes at least one master controller device, and each NAND flash memory node includes at least one NAND flash memory device. The at least one master controller node establishes a network connection with the at least one NAND flash memory node through the at least one network switch. The at least one master control node communicates with the at least one network switch via a network protocol; The at least one network switch communicates with the at least one NAND flash memory node via the network protocol.

12. The method according to claim 11, characterized in that, The solid-state drive system further includes at least one protocol conversion chip, and the at least one network switch communicates with the at least one NAND flash memory node via the network protocol, including: The at least one network switch communicates with the at least one protocol conversion chip via the network protocol; The at least one protocol conversion chip converts the network protocol into an open NAND flash memory interface protocol; The at least one protocol conversion chip communicates with the at least one NAND flash memory device through the open NAND flash memory interface protocol.

13. The method according to claim 11 or 12, characterized in that, The method further includes: The at least one master node sends a broadcast request message to the at least one network switch. The broadcast request message is used to instruct each NAND flash memory device to report its own configuration space information. The configuration space information is used by the master node to identify and access the NAND flash memory device. The at least one network switch obtains the configuration space information of each NAND flash memory device according to the broadcast request message.

14. The method according to claim 13, characterized in that, The configuration space information includes the identification information of the NAND flash memory device, the identification information of at least one chip in the NAND flash memory device, and the structural information of each chip. The structural information is used to indicate the mapping relationship between the identifiers of logic units, plane identifiers, block identifiers, and page identifiers in each chip.

15. The method according to any one of claims 11 to 14, characterized in that, The solid-state drive system further includes at least one management module, each management module being used to store global mapping relationships. The global mapping relationships include multiple mapping relationships, which are used to indicate at least one logical address managed by each of the multiple master control devices, the physical address corresponding to each logical address, and path information. The physical address is used to indicate the target NAND flash memory device corresponding to the logical address, the target chip in the target NAND flash memory device, the target logical unit in the target chip, the target plane in the target logical unit, the target block in the target plane, and the target page in the target block. The path information is used to indicate routing information of the network topology from the master control device to the physical address.

16. The method according to any one of claims 11 to 14, characterized in that, The solid-state drive system further includes at least one management module. Each management module stores a global mapping relationship, which includes multiple mapping relationships. These multiple mapping relationships indicate the correspondence between multiple virtual address information and multiple real address information. The multiple virtual address information indicates at least one logical address managed by each of the multiple master controllers, and the physical address of the virtual NAND flash memory device corresponding to each logical address. The multiple real address information indicates the physical address and path information of the real NAND flash memory device corresponding to the physical address of each virtual NAND flash memory device. The physical address is used to indicate the target NAND flash memory device corresponding to the logical address, the target chip in the target NAND flash memory device, the target logic unit in the target chip, the target plane in the target logic unit, the target block in the target plane, and the target page in the target block. The path information is used to indicate the routing information of the network topology from the master control device to the physical address.

17. The method according to claim 15 or 16, characterized in that, Each master control node is also used to store local mapping relationships, which are subsets of the global mapping relationships. The local mapping relationships are mapping relationships related to some or all of the master control devices included in the master control node.

18. The method according to any one of claims 11 to 17, characterized in that, Each NAND flash memory node includes multiple NAND flash memory devices. Some of the NAND flash memory devices are used to store at least one data shard of the original data, and the remaining NAND flash memory devices are used to store at least one verification data. The original data is composed of multiple data shards, which correspond to the partial NAND flash memory devices. Each verification data is obtained by performing calculations on the multiple data shards.

19. The method according to any one of claims 11 to 18, characterized in that, Each NAND flash memory device includes multiple chips, some of which are used to store at least one data shard of raw data, and the remaining chips are used to store at least one verification data. The raw data is composed of multiple data shards, which correspond to the partial chips. Each verification data is obtained by performing calculations on the multiple data shards.

20. The method according to any one of claims 15 to 19, characterized in that, The first master control node includes a first master control device and a second master control device. The global mapping relationship includes at least one first mapping relationship. Each first mapping relationship is used to indicate at least one first logical address managed by the first master control device, a first physical address corresponding to each first logical address, and first path information. When the first master control device fails, the method further includes: The at least one management module updates the at least one first mapping relationship, and each updated first mapping relationship is used to indicate the at least one first logical address managed by the second master control device, the updated first physical address corresponding to each first logical address, and the updated first path information; The second master control device obtains the updated at least one first mapping relationship from the at least one management module; The second master control device accesses data according to the updated first mapping relationship.

21. A computing device, characterized in that, It includes a processor and a memory, the processor being configured to execute a computer program or instructions stored in the memory to cause the computing device to perform the method as described in any one of claims 11 to 20.

22. A computing device cluster, characterized in that, It includes at least one computing device, each computing device including a processor and memory; The processor of the at least one computing device is configured to execute a computer program or instructions stored in the memory of the at least one computing device, so that the cluster of computing devices performs the method as described in any one of claims 11 to 20.

23. A computer program product containing instructions, characterized in that, When the instruction is executed by the computing device cluster, the computing device cluster causes the computing device cluster to perform the method as described in any one of claims 11 to 20.

24. A computer-readable storage medium, characterized in that, Includes a computer program or instructions, which, when executed by a cluster of computing devices, perform the method as described in any one of claims 11 to 20.

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