Inorganic micro light emitting display panel and display device

Abstract

Provided are an inorganic micro light emitting display panel and a display device. The inorganic micro light emitting display panel comprises a substrate, a light emitting element on one side of the substrate, and a driving circuit layer between the substrate and the light emitting element. The driving circuit layer comprises a first conductive layer, a second conductive layer on the side of the first conductive layer away from the substrate, a thin film transistor layer between the first conductive layer and the second conductive layer, a first power transmission structure, and a second power transmission structure. The thin film transistor layer comprises a first type of thin film transistor and a second type of thin film transistor. The first type of thin film transistor comprises a gate and a silicon-containing semiconductor layer; the second type of thin film transistor comprises a gate and an oxide semiconductor layer. The first power transmission structure is electrically connected to a first electrode of the light emitting element, and the second power transmission structure is electrically connected to a second electrode of the light emitting element. The first power transmission structure and the oxide semiconductor layer at least partially overlap in the orthographic projection on the substrate.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to an inorganic micro-light-emitting display panel and display device. Background Technology

[0002] MicroLED (Micro Light Emitting Diode) displays are self-emissive display technologies based on micron-sized inorganic light-emitting diodes. Due to their advantages such as long lifespan and high brightness, they are one of the core directions in display technology development. Traditional MicroLED driving backplanes are mostly based on low-temperature polycrystalline silicon (LTPS) thin-film transistor technology. LTPS thin-film transistors have high electron mobility, but this high mobility leads to significant leakage current, making it unsuitable for low-frequency dynamic refresh displays and resulting in increased display power consumption during low-frequency dynamic refresh. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This application provides an inorganic micro-light-emitting display panel and display device.

[0005] On one hand, this embodiment provides an inorganic micro-light-emitting display panel, including: a substrate, a light-emitting element located on one side of the substrate, and a driving circuit layer located between the substrate and the light-emitting element. The light-emitting element includes a first electrode and a second electrode located on the side closer to the substrate. The driving circuit layer includes: a first conductive layer, a second conductive layer located on the side of the first conductive layer away from the substrate, a thin-film transistor layer located between the first and second conductive layers, a first power transmission structure located at least in the second conductive layer, and a second power transmission structure. The thin-film transistor layer includes at least one first type of thin-film transistor and at least one second type of thin-film transistor. The first type of thin-film transistor includes: a gate, a silicon-containing semiconductor layer, a first electrode, and a second electrode. The second type of thin-film transistor includes: a gate, an oxide semiconductor layer, a first electrode, and a second electrode. The first power transmission structure is electrically connected to the first electrode of the light-emitting element and configured to provide a low-level voltage; the second power transmission structure is electrically connected to the second electrode of the light-emitting element and configured to provide a high-level voltage. The second power transmission structure is disposed in the same layer as the first power transmission structure. The orthographic projection of the first power transmission structure onto the substrate at least partially overlaps with the orthographic projection of the oxide semiconductor layer onto the substrate.

[0006] In some exemplary embodiments, the orthographic projection of the second conductive layer onto the substrate at least partially overlaps with the orthographic projection of the oxide semiconductor layer onto the substrate.

[0007] In some exemplary embodiments, the orthographic projection of the second conductive layer onto the substrate completely covers the orthographic projection of the channel region of the oxide semiconductor layer onto the substrate.

[0008] In some exemplary embodiments, the first conductive layer, the second conductive layer, and the oxide semiconductor layer all have at least partial overlap in their orthogonal projections onto the substrate.

[0009] In some exemplary embodiments, the orthographic projection of the first conductive layer onto the substrate completely covers the orthographic projection of the channel region of the oxide semiconductor layer onto the substrate.

[0010] In some exemplary embodiments, the orthographic projections of the first conductive layer and the second conductive layer on the substrate completely cover the orthographic projection of the oxide semiconductor layer on the substrate.

[0011] In some exemplary embodiments, the orthographic projection of the first power delivery structure onto the substrate at least partially covers the orthographic projection of the channel region of the oxide semiconductor layer onto the substrate.

[0012] In some exemplary embodiments, the orthographic projection of the first power transmission structure onto the substrate completely covers the orthographic projection of the channel region of the oxide semiconductor layer onto the substrate.

[0013] In some exemplary embodiments, the first conductive layer includes: a first shielding structure and a second shielding structure; the orthographic projection of the first shielding structure onto the substrate at least partially overlaps with the orthographic projection of the silicon-containing semiconductor layer onto the substrate; the orthographic projection of the second shielding structure onto the substrate at least partially overlaps with the orthographic projection of the oxide semiconductor layer onto the substrate.

[0014] In some exemplary embodiments, the orthogonal projection of the first shielding structure onto the substrate covers the orthogonal projection of the silicon-containing semiconductor layer onto the substrate; the orthogonal projection of the second shielding structure onto the substrate covers the orthogonal projection of the oxide semiconductor layer onto the substrate.

[0015] In some exemplary embodiments, the area of ​​the second shielding structure projected onto the substrate is not less than the area of ​​the oxide semiconductor layer projected onto the substrate.

[0016] In some exemplary embodiments, the orthographic projection of the second shielding structure onto the substrate at least partially overlaps with the orthographic projection of the first power transmission structure onto the substrate.

[0017] In some exemplary embodiments, the driving circuit layer further includes: a third conductive layer, a fourth conductive layer, and a fifth conductive layer located between the first conductive layer and the second conductive layer; the gate of the first type of thin film transistor is located in the third conductive layer; the gate of the second type of thin film transistor includes a first gate and a second gate, the first gate is located in the fourth conductive layer, and the second gate is located in the fifth conductive layer; the oxide semiconductor layer is disposed between the first gate and the second gate.

[0018] In some exemplary embodiments, the orthogonal projection of the first gate onto the substrate covers the orthogonal projection of the channel region of the oxide semiconductor layer onto the substrate.

[0019] In some exemplary embodiments, the area of ​​the first gate projected onto the substrate is not less than the area of ​​the channel region of the oxide semiconductor layer projected onto the substrate.

[0020] In some exemplary embodiments, the area of ​​the first gate projected onto the substrate is not less than the area of ​​the second gate projected onto the substrate.

[0021] In some exemplary embodiments, the orthographic projection of the second gate onto the substrate is located inside the orthographic projection of the first gate onto the substrate.

[0022] In some exemplary embodiments, the orthographic projection of the second gate onto the substrate completely overlaps with the orthographic projection of the first gate onto the substrate.

[0023] In some exemplary embodiments, at least one planarization layer is disposed between the thin-film transistor layer and the light-emitting element, the at least one planarization layer including a light-absorbing layer.

[0024] In some exemplary embodiments, the light-absorbing layer comprises an organic polymer selected from at least one of carbon black, graphene, carbon nanotubes, and polymer-modified graphene.

[0025] In some exemplary embodiments, the light-absorbing layer comprises black polyimide.

[0026] In some exemplary embodiments, the light-absorbing layer is a double-layer or multi-layer structure.

[0027] In some exemplary embodiments, the light-absorbing layer is a single layer and is located between the oxide semiconductor layer and the second conductive layer.

[0028] In some exemplary embodiments, the light-absorbing layer is a single layer and is located between the second conductive layer and the light-emitting element.

[0029] In some exemplary embodiments, the driving circuit layer further includes a capacitor element, which includes a first capacitor electrode and a second capacitor electrode. The first type of thin-film transistor includes a driving thin-film transistor; the first electrode of the driving thin-film transistor is electrically connected to the second power transmission structure; the gate of the driving thin-film transistor is electrically connected to the first capacitor electrode; and the second electrode of the driving thin-film transistor is electrically connected to the second electrode of the light-emitting element.

[0030] In some exemplary embodiments, both the second power transmission structure and the first power transmission structure are located in the second conductive layer.

[0031] In some exemplary embodiments, the driving circuit layer further includes: a third conductive layer located between the first conductive layer and the second conductive layer, the third conductive layer being located on the side of the silicon-containing semiconductor layer away from the substrate; the first capacitor electrode being located at least in the third conductive layer, and the second capacitor electrode being disposed at least in the same layer as the silicon-containing semiconductor layer.

[0032] In some exemplary embodiments, the first capacitor electrode is located in the third conductive layer; or, the first capacitor electrode includes: a first sub-electrode and a second sub-electrode electrically connected to the first sub-electrode, wherein the first sub-electrode is located in the third conductive layer and the second sub-electrode is located in the first conductive layer.

[0033] In some exemplary embodiments, the driving circuit layer further includes: a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer disposed between the third conductive layer and the second conductive layer and disposed in a direction away from the substrate. The second capacitor electrode includes: a third sub-electrode and a fourth sub-electrode electrically connected to the third sub-electrode, the third sub-electrode being disposed in the same layer as the silicon semiconductor layer, and the fourth sub-electrode being located in the sixth conductive layer.

[0034] In some exemplary embodiments, the second capacitor electrode further includes a fifth sub-electrode electrically connected to the fourth sub-electrode; the fifth sub-electrode is located in the seventh conductive layer.

[0035] In some exemplary embodiments, the second type of thin-film transistor includes: a first control thin-film transistor; the gate of the driving thin-film transistor and the first capacitor electrode are both electrically connected to a first electrode or a second electrode of the first control thin-film transistor.

[0036] In some exemplary embodiments, the driving circuit layer further includes: a data signal line; wherein the first type of thin-film transistor further includes: a data writing thin-film transistor; the first electrode of the data writing thin-film transistor is electrically connected to the data signal line; and the second electrode of the data writing thin-film transistor is electrically connected to the second capacitor electrode.

[0037] In some exemplary embodiments, the second type of thin-film transistor further includes: a second control thin-film transistor, wherein a first electrode of the second control thin-film transistor is electrically connected to a second electrode of the data writing transistor, and a second electrode of the second control thin-film transistor is electrically connected to a second capacitor electrode.

[0038] In some exemplary embodiments, the driving circuit layer further includes: a first reset control line and a first reset signal line; the second type of thin-film transistor includes: a first control thin-film transistor. The first type of thin-film transistor further includes: a first reset thin-film transistor; the gate of the first reset thin-film transistor is electrically connected to the first reset control line; the first terminal of the first reset thin-film transistor is electrically connected to the first reset signal line; the second terminal of the first reset thin-film transistor is electrically connected to the first terminal of the first control thin-film transistor, and the second terminal of the first control thin-film transistor is electrically connected to the gate of the driving thin-film transistor.

[0039] In some exemplary embodiments, the driving circuit layer further includes a light-emitting control signal line. The first type of thin-film transistor further includes a light-emitting control thin-film transistor; the first electrode of the light-emitting control thin-film transistor is electrically connected to the second electrode of the driving transistor; the second electrode of the light-emitting control thin-film transistor is electrically connected to the second electrode of the light-emitting element; and the gate of the light-emitting control thin-film transistor is electrically connected to the light-emitting control signal line.

[0040] In some exemplary embodiments, the first type of thin-film transistor further includes: a third control thin-film transistor, the gate of which is electrically connected to the light-emitting control signal line, and the first or second electrode of which is electrically connected to the second capacitor electrode.

[0041] In some exemplary embodiments, the first power transmission structure includes: a plurality of first power electrodes, a plurality of first power connection lines extending along a first direction, and a plurality of second power connection lines extending along a second direction. The plurality of first power electrodes are connected to the plurality of first power connection lines and the plurality of second power connection lines to form a mesh structure. The orthographic projection of the first power electrodes on the substrate at least partially overlaps with the orthographic projection of the oxide semiconductor layer on the substrate. The first direction and the second direction are parallel to the plane of the substrate, and the first direction and the second direction intersect.

[0042] In some exemplary embodiments, the driving circuit layer further includes: an auxiliary shielding structure located on the side of the first power transmission structure near the thin film transistor layer, the auxiliary shielding structure overlapping the first power transmission structure in the orthographic projection of the substrate, and covering the channel region of the oxide semiconductor layer in the orthographic projection of the substrate.

[0043] In some exemplary embodiments, the auxiliary shielding structure is electrically connected to the first power transmission structure.

[0044] In some exemplary embodiments, the driving circuit layer further includes: an auxiliary shielding structure located on the side of the first power transmission structure near the thin film transistor layer; the union region of the auxiliary shielding structure and the first power transmission structure in the orthographic projection of the substrate covers the orthographic projection of the channel region of the oxide semiconductor layer in the substrate.

[0045] In some exemplary embodiments, the driving circuit layer further includes: a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer disposed between the first conductive layer and the second conductive layer and disposed in a direction away from the substrate. The auxiliary shielding structure is located on the seventh conductive layer, and the first power transmission structure is located on the second conductive layer.

[0046] In some exemplary embodiments, the driving circuit layer further includes an eighth conductive layer located on the side of the second conductive layer away from the substrate, the eighth conductive layer including a first transition electrode and a second transition electrode, the first electrode of the light-emitting element being electrically connected to the first power transmission structure through the first transition electrode, and the second electrode of the light-emitting element being electrically connected to the second power transmission structure through the second transition electrode.

[0047] In some exemplary embodiments, the material of the eighth conductive layer includes a transparent conductive material.

[0048] In some exemplary embodiments, the oxide semiconductor layer is a two-layer or multi-layer stacked structure.

[0049] In some exemplary embodiments, the oxide semiconductor layer is a double-layer stacked structure, with the density of the layer closer to the substrate being lower than that of the layer farther from the substrate.

[0050] In some exemplary embodiments, the oxide semiconductor layer is a double-layer stacked structure, wherein the thickness of the layer closer to the substrate is greater than the thickness of the layer farther from the substrate.

[0051] In some exemplary embodiments, the thickness of the layer closer to the substrate is 1 to 3 times the thickness of the layer farther from the substrate.

[0052] In some exemplary embodiments, the thickness of the layer closer to the substrate is 1.5 to 2 times the thickness of the layer farther from the substrate.

[0053] In some exemplary embodiments, the thickness of the oxide semiconductor layer ranges from 30 nanometers to 60 nanometers.

[0054] In some exemplary embodiments, the thickness of the oxide semiconductor layer ranges from 40 nanometers to 50 nanometers.

[0055] In some exemplary embodiments, the thickness of the silicon-containing semiconductor layer ranges from 30 nanometers to 65 nanometers.

[0056] In some exemplary embodiments, the thickness of the first conductive layer ranges from 45 nanometers to 150 nanometers.

[0057] In some exemplary embodiments, the second conductive layer is a double-layer or multi-layer stacked structure.

[0058] In some exemplary embodiments, the second conductive layer is a titanium Ti, aluminum Al, and titanium Ti stacked structure.

[0059] In some exemplary embodiments, the thickness of the titanium layer ranges from 50 nanometers to 60 nanometers; the thickness of the aluminum layer ranges from 500 nanometers to 700 nanometers.

[0060] On the other hand, this embodiment provides a display device, including the inorganic micro-light-emitting display panel as described above.

[0061] The driving circuit layer of the inorganic micro-light-emitting display panel provided in this embodiment includes two types of thin-film transistors, which can achieve high electron mobility and reduce leakage current during low-frequency display, realize high and low frequency refresh switching, and reduce display power consumption. Moreover, by using the first power transmission structure to shield the oxide semiconductor layer, the oxide semiconductor layer can be prevented from being affected by light for a long time, which can reduce the impact of light on the oxide semiconductor layer and improve the stability of the thin-film transistors.

[0062] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0063] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0064] Figure 1 This is a partial plan view of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 2 This is a partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 3 for Figure 1 An exemplary planar schematic diagram of the first conductive layer; Figure 4 for Figure 1 A partial planar schematic diagram of the first power transmission structure located in the second conductive layer; Figure 5 This disclosure presents at least one embodiment of a schematic diagram showing the orthographic projection relationship between the second shielding structure of the oxide semiconductor layer and the first conductive layer and the first power transmission structure of the second conductive layer; Figure 6 This is another partial planar schematic diagram of the first conductive layer according to at least one embodiment of the present disclosure; Figure 7 This is another partial planar schematic diagram of the first conductive layer according to at least one embodiment of the present disclosure; Figure 8 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 9 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 10 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 11 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 12 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 13 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 14 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 15 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 16This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 17 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 18 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 19 This is another partial planar schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 20 This is another partial planar schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 21 for Figure 20 A partial planar schematic diagram of the first conductive layer in the image; Figure 22 for Figure 20 A partial planar schematic diagram of the first power transmission structure located in the second conductive layer; Figure 23 This is an equivalent circuit diagram of the pixel circuit of the driving circuit layer in at least one embodiment of the present disclosure; Figure 24 for Figure 23 The timing diagram of the pixel circuit shown is shown below. Figure 25 This is another equivalent circuit diagram of the pixel circuit of the driving circuit layer of at least one embodiment of the present disclosure; Figure 26 This is another equivalent circuit diagram of the pixel circuit of the driving circuit layer of at least one embodiment of the present disclosure; Figure 27 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure; Figure 28 This is another cross-sectional structural schematic diagram of a capacitor element according to at least one embodiment of the present disclosure; Figure 29 This is another cross-sectional structural schematic diagram of a capacitor element according to at least one embodiment of the present disclosure; Figure 30 This is another cross-sectional structural schematic diagram of a capacitor element according to at least one embodiment of the present disclosure; Figure 31 This is another cross-sectional structural schematic diagram of a capacitor element according to at least one embodiment of the present disclosure; Figure 32 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0065] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0066] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0067] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0068] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0069] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Joining" can include "electrical connection," which can include situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on "components having some electrical function," as long as they enable the transmission of electrical signals between the connected constituent elements. Examples of "components having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components.

[0070] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0071] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0072] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0073] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0074] In this specification, "approximately" and "about" mean without strictly defined limits, allowing for errors in the process and measurement. In this disclosure, "same" includes values ​​differing by less than 10%, such as values ​​differing by less than 5%.

[0075] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0076] In this specification, "A and B are of the same layer structure" and "A and B are arranged in the same layer" mean that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are at substantially the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. "Same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view. The "shape of A" in this disclosure refers to the shape of A as projected onto the substrate.

[0077] In this specification, a film thickness within the range of A to B means a film thickness greater than or equal to A and less than or equal to B.

[0078] This embodiment provides an inorganic micro-light-emitting display panel and display device, which can help improve the stability of the thin-film transistors in the driving circuit layer of the inorganic micro-light-emitting display panel, support low-frequency display, and improve display stability.

[0079] This embodiment provides an inorganic micro-light-emitting display panel, comprising: a substrate, a light-emitting element located on one side of the substrate, and a driving circuit layer located between the substrate and the light-emitting element. The light-emitting element includes a first electrode and a second electrode located near the substrate. The driving circuit layer includes: a first conductive layer, a second conductive layer, a thin-film transistor layer located between the first and second conductive layers, a first power transmission structure, and a second power transmission structure. The second conductive layer is located on the side of the first conductive layer away from the substrate. The thin-film transistor layer includes: at least one first-type thin-film transistor and at least one second-type thin-film transistor. The first-type thin-film transistor includes: a gate, a silicon-containing semiconductor layer, a first electrode, and a second electrode. The second-type thin-film transistor includes: a gate, an oxide semiconductor layer, a first electrode, and a second electrode. The first power transmission structure is located at least in the second conductive layer and electrically connected to the first electrode of the light-emitting element, and the first power transmission structure is configured to provide a low-level voltage. The second power transmission structure is electrically connected to the second electrode of the light-emitting element, and the second power transmission structure is configured to provide a high-level voltage. The second power transmission structure is disposed in the same layer as the first power transmission structure. The orthographic projection of the first power transmission structure onto the substrate at least partially overlaps with the orthographic projection of the oxide semiconductor layer onto the substrate.

[0080] The driving circuit layer of the inorganic micro-light-emitting display panel provided in this embodiment includes two types of thin-film transistors, which can achieve high electron mobility and reduce leakage current during low-frequency display, realize high and low frequency refresh switching, and reduce display power consumption. Moreover, by using the first power transmission structure to shield the oxide semiconductor layer, the oxide semiconductor layer can be prevented from being affected by light for a long time, which can reduce the impact of light on the oxide semiconductor layer and improve the stability of the thin-film transistors.

[0081] In this example, the light-emitting element is a micro-light-emitting element. The size of a micro-light-emitting element is on the micrometer scale. Micro-light-emitting elements can include micro-light-emitting diodes (MicroLEDs) or mini-LEDs. MicroLEDs are inorganic light-emitting diodes, distinct from organic light-emitting diodes. Taking a square MicroLED as an example, the length can range from 20µm to 40µm; the width can range from 10µm to 30µm. MicroLED technology, namely LED (Light Emitting Diode) miniaturization and matrixing technology, refers to integrating a high-density array of tiny LEDs on a single chip. Each LED can be addressed and individually driven to light up, reducing the pixel distance between adjacent LEDs from millimeters to micrometers, thus improving display quality. MicroLEDs possess self-emissive display characteristics and offer advantages such as all-solid-state operation, long lifespan, high brightness, low power consumption, small size, ultra-high resolution, and applicability to extreme environments such as high temperatures or radiation. The display panel in this example uses micro-light-emitting elements, which can improve the lifespan of the display panel and achieve better display quality.

[0082] In some exemplary embodiments, the orthographic projection of the second conductive layer onto the substrate and the orthographic projection of the oxide semiconductor layer onto the substrate may at least partially overlap. For example, the orthographic projection of the second conductive layer onto the substrate may completely cover the orthographic projection of the channel region of the oxide semiconductor layer onto the substrate. This example utilizes the second conductive layer to shield the oxide semiconductor layer, which can prevent the oxide semiconductor layer from being affected by light for a long time, reduce the impact of light on the channel region of the oxide semiconductor layer, and improve the stability of the thin-film transistor.

[0083] In some exemplary embodiments, the orthographic projection of the first conductive layer onto the substrate completely covers the orthographic projection of the channel region of the oxide semiconductor layer onto the substrate. This example utilizes the first conductive layer to shield the channel region of the oxide semiconductor layer, preventing prolonged exposure to light and reducing the impact of light on the channel region, thereby improving the stability of the thin-film transistor.

[0084] In some exemplary embodiments, the orthographic projections of the first conductive layer, the second conductive layer, and the oxide semiconductor layer onto the substrate all at least partially overlap. In some examples, the orthographic projections of the first conductive layer and the second conductive layer onto the substrate completely cover the orthographic projection of the oxide semiconductor layer onto the substrate. This example utilizes the first and second conductive layers simultaneously to shield the channel region of the oxide semiconductor layer, which can prevent the oxide semiconductor layer from being affected by light for extended periods, reduce the impact of light on the channel region of the oxide semiconductor layer, and improve the stability of the thin-film transistor.

[0085] In some exemplary embodiments, the orthographic projection of the first power transmission structure onto the substrate can at least partially cover the orthographic projection of the channel region of the oxide semiconductor layer onto the substrate. In some examples, the orthographic projection of the first power transmission structure onto the substrate can completely cover the orthographic projection of the channel region of the oxide semiconductor layer onto the substrate. This example utilizes the first power transmission structure to shield the channel region of the oxide semiconductor layer, which can prevent the oxide semiconductor layer from being affected by light for a long time, reduce the impact of light on the channel region of the oxide semiconductor layer, and improve the stability of the thin-film transistor.

[0086] In some exemplary embodiments, the first conductive layer may include: a first shielding structure and a second shielding structure; the orthographic projection of the first shielding structure onto the substrate at least partially overlaps with the orthographic projection of the silicon-containing semiconductor layer onto the substrate; the orthographic projection of the second shielding structure onto the substrate at least partially overlaps with the orthographic projection of the oxide semiconductor layer onto the substrate. For example, the orthographic projection of the first shielding structure onto the substrate may cover the orthographic projection of the silicon-containing semiconductor layer onto the substrate; the orthographic projection of the second shielding structure onto the substrate may cover the orthographic projection of the oxide semiconductor layer onto the substrate. In this example, combining the first conductive layer and the first power transmission structure to shield the oxide semiconductor layer can better shield the oxide semiconductor layer, thereby reducing the influence of light on the oxide semiconductor layer and improving the stability of the second type of thin film transistor; using the first conductive layer to shield the silicon-containing semiconductor layer can avoid the influence of light on the silicon-containing semiconductor layer, which is beneficial for stabilizing the threshold voltage of the first type of thin film transistor, preventing abnormal increases in leakage current, and thus ensuring display stability.

[0087] In some exemplary embodiments, the area of ​​the orthographic projection of the second shielding structure onto the substrate is not less than the area of ​​the orthographic projection of the oxide semiconductor layer onto the substrate. For example, the area of ​​the orthographic projection of the second shielding structure onto the substrate can be larger than the area of ​​the orthographic projection of the oxide semiconductor layer onto the substrate. This helps to ensure the shielding effect of the second shielding structure on the oxide semiconductor layer.

[0088] In some exemplary embodiments, the orthographic projection of the second shielding structure onto the substrate at least partially overlaps with the orthographic projection of the first power transmission structure onto the substrate. This example utilizes the second shielding structure and the first power transmission structure to shield the oxide semiconductor layer from both the top and bottom sides, which can better shield the oxide semiconductor layer, thereby reducing the impact of light on the oxide semiconductor layer and improving the stability of the second type of thin-film transistor.

[0089] In some exemplary embodiments, the driving circuit layer may further include a third conductive layer, a fourth conductive layer, and a fifth conductive layer located between the first conductive layer and the second conductive layer. The gate of the first type of thin-film transistor is located in the third conductive layer; the gate of the second type of thin-film transistor includes a first gate and a second gate, the first gate being located in the fourth conductive layer and the second gate being located in the fifth conductive layer; the oxide semiconductor layer is disposed between the first gate and the second gate. In this example, the second type of thin-film transistor adopts a top-bottom dual-gate design, which can improve carrier mobility and enhance output current, meeting the requirements of high-density, high-resolution display panels.

[0090] In some exemplary embodiments, the orthographic projection of the first gate onto the substrate covers the orthographic projection of the channel region of the oxide semiconductor layer onto the substrate. This example can avoid the occurrence of blind zones at the edges of the channel region that are not modulated by the electric field, which is beneficial to improving the ability to control channel carriers, effectively suppressing short-channel effects, and reducing parasitic capacitance interference, thereby improving the operating stability of the transistor.

[0091] In some exemplary embodiments, the area of ​​the orthographic projection of the first gate onto the substrate is not less than the area of ​​the orthographic projection of the second gate onto the substrate. For example, the area of ​​the orthographic projection of the first gate onto the substrate can be larger than the area of ​​the orthographic projection of the second gate onto the substrate. This example can avoid the occurrence of blind zones at the edges of the channel region that are not controlled by the electric field, which is beneficial to improving the control capability of channel carriers.

[0092] In some exemplary embodiments, the orthographic projection of the second gate onto the substrate can completely overlap with the orthographic projection of the first gate onto the substrate. This example allows for simultaneous modulation of the channel region from both the top and bottom sides, significantly suppressing short-channel effects.

[0093] In some exemplary embodiments, at least one planarization layer may be disposed between the thin-film transistor layer and the light-emitting element, said at least one planarization layer including a light-absorbing layer. In some examples, the light-absorbing layer may include an organic polymer doped with at least one of carbon black, graphene, carbon nanotubes, and polymer-modified graphene. In other examples, the light-absorbing layer may include black polyimide. In some examples, the light-absorbing layer may be a bilayer or multilayer structure. In other examples, the light-absorbing layer may be a single layer; the light-absorbing layer may be located between the oxide semiconductor layer and the second conductive layer, or between the second conductive layer and the light-emitting element. This example, by providing a light-absorbing layer, can absorb external light, thereby better shielding the oxide semiconductor layer, reducing the impact of light on the oxide semiconductor layer, and thus improving the stability of the second type of thin-film transistor.

[0094] In some exemplary embodiments, the driving circuit layer may further include a capacitor element, which includes a first capacitor electrode and a second capacitor electrode. The first type of thin-film transistor includes a driving thin-film transistor; the first electrode of the driving thin-film transistor is electrically connected to the second power transmission structure; the gate of the driving thin-film transistor is electrically connected to the first capacitor electrode; and the second electrode of the driving thin-film transistor is electrically connected to the second electrode of the light-emitting element. For example, the first capacitor electrode may include multiple sub-electrodes located in different film layers, or the second capacitor electrode may include multiple sub-electrodes located in different film layers. This example, by setting a capacitor electrode with multiple sub-electrodes stacked, can multiply the capacitance by increasing the total effective electrode area without changing the area occupied by the capacitor element; or, under the premise of meeting the target capacitance, by stacking multiple sub-electrodes, the area occupied by the capacitor element can be significantly reduced, thereby compressing the overall size of a single sub-pixel, enabling the display panel to achieve a higher pixel density (PPI) and a high-resolution display panel.

[0095] In some exemplary embodiments, the first capacitor electrode is located at least in the third conductive layer, and the second capacitor electrode is disposed at least in the same layer as the silicon-containing semiconductor layer. In this example, the co-location of the second capacitor electrode with the silicon-containing semiconductor layer allows for the simultaneous fabrication of the capacitor element during the transistor fabrication process, which is beneficial for optimizing the process.

[0096] In some exemplary embodiments, the first capacitor electrode may include a first sub-electrode and a second sub-electrode electrically connected to the first sub-electrode, wherein the first sub-electrode is located in the third conductive layer and the second sub-electrode is located in the first conductive layer. The arrangement of the first capacitor electrode in this example can save space and reduce the impact on the layout of other structures.

[0097] In some exemplary embodiments, the driving circuit layer may further include: a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer disposed between the third conductive layer and the second conductive layer and disposed in a direction away from the substrate. The second capacitor electrode may include: a third sub-electrode and a fourth sub-electrode electrically connected to the third sub-electrode, wherein the third sub-electrode is disposed in the same layer as the silicon-containing semiconductor layer, and the fourth sub-electrode is located in the sixth conductive layer. In some examples, the second capacitor electrode may further include: a fifth sub-electrode electrically connected to the fourth sub-electrode; the fifth sub-electrode is located in the seventh conductive layer. The arrangement of the second capacitor electrode in this example can save space and make full use of the space of multiple conductive layers.

[0098] In some exemplary embodiments, the first power transmission structure includes: a plurality of first power electrodes, a plurality of first power connection lines extending along a first direction, and a plurality of second power connection lines extending along a second direction. The plurality of first power electrodes, the plurality of first power connection lines, and the plurality of second power connection lines are connected to form a mesh structure. The orthographic projection of the first power electrodes on the substrate at least partially overlaps with the orthographic projection of the oxide semiconductor layer on the substrate. The first direction and the second direction are parallel to the plane of the substrate and intersect each other. The first power transmission structure in this example is a mesh structure, which can effectively reduce the transmission resistance of low-level voltages, reduce the voltage drop of low-level voltages, reduce power consumption, and effectively improve the uniformity and stability of low-level voltages in the display panel, thereby effectively improving display uniformity and display quality.

[0099] In some exemplary embodiments, the driving circuit layer may further include an auxiliary shielding structure located on the side of the first power transmission structure near the thin-film transistor layer. The overlapping region of the auxiliary shielding structure and the first power transmission structure in the orthographic projection onto the substrate covers the orthographic projection of the oxide semiconductor layer onto the substrate. For example, the auxiliary shielding structure may be electrically connected to the first power transmission structure. This example utilizes the overlapping auxiliary shielding structure and the first power transmission structure to achieve double-layer shielding of the oxide semiconductor layer, further reducing the impact of light on the oxide semiconductor layer and improving the stability of the second type of thin-film transistor.

[0100] In some exemplary embodiments, the driving circuit layer may further include: an auxiliary shielding structure located on the side of the first power transmission structure near the thin-film transistor layer; the union region of the auxiliary shielding structure and the first power transmission structure on the substrate covers the orthogonal projection of the channel region of the oxide semiconductor layer on the substrate. Here, the union region of the auxiliary shielding structure and the first power transmission structure on the substrate refers to the entire combined area covered by the orthogonal projections of the auxiliary shielding structure and the first power transmission structure. This example utilizes the union region of the auxiliary shielding structure and the first power transmission structure to shield the oxide semiconductor layer, ensuring a shielding effect on the oxide semiconductor layer, thereby reducing the impact of light on the oxide semiconductor layer and improving the stability of the second type of thin-film transistor.

[0101] In some exemplary embodiments, the driving circuit layer may further include: a third, fourth, fifth, sixth, and seventh conductive layer disposed between the first and second conductive layers and along a direction away from the substrate; the auxiliary shielding structure is located on the seventh conductive layer, and the first power transmission structure is located on the second conductive layer. This example, by providing the auxiliary shielding structure on a conductive layer close to the first power transmission structure, ensures the combined shielding effect of the auxiliary shielding structure and the first power transmission structure on the oxide semiconductor layer.

[0102] In some exemplary embodiments, the driving circuit layer may further include an eighth conductive layer located on the side of the second conductive layer away from the substrate. The eighth conductive layer includes a first transition electrode and a second transition electrode. The first electrode of the light-emitting element is electrically connected to the first power transmission structure via the first transition electrode, and the second electrode of the light-emitting element is electrically connected to the second power transmission structure via the second transition electrode. In some examples, the material of the eighth conductive layer includes a transparent conductive material. This example, by using a transparent conductive material for the eighth conductive layer, can achieve better eutectic bonding with the light-emitting element, thereby providing high lateral conductivity, reducing local overheating, and improving the lifespan of the light-emitting element.

[0103] In some exemplary embodiments, the oxide semiconductor layer can be a two-layer or multi-layer stacked structure. This example can improve the carrier mobility of transistors, adapting to the display driving requirements of high refresh rates.

[0104] In some exemplary embodiments, the oxide semiconductor layer is a double-layer stacked structure, with the density of the layer closer to the substrate being lower than that of the layer farther from the substrate. The lower-density layer ensures high carrier mobility, while the higher-density layer blocks water and oxygen intrusion, significantly reducing threshold voltage drift under bias stress, thus simultaneously achieving high electrical performance and long-term reliability. Furthermore, employing a double-layer structure with different densities helps reduce leakage paths, effectively lowering off-state leakage current and significantly improving the transistor's current switching ratio, adapting to the low-power driving requirements of display panels.

[0105] In some exemplary embodiments, the oxide semiconductor layer is a double-layer stacked structure, with the thickness of the layer closer to the substrate being greater than the thickness of the layer farther from the substrate. In some examples, the thickness of the layer closer to the substrate is 1 to 3 times the thickness of the layer farther from the substrate. For example, the thickness of the layer closer to the substrate is 1.5 to 2 times the thickness of the layer farther from the substrate. In this example, the layer closer to the substrate ensures efficient transport of channel carriers, while the layer farther from the substrate blocks water and oxygen permeation and suppresses the generation of oxygen vacancy defects, thereby achieving both high mobility and long-term reliability.

[0106] The following examples illustrate the solution of this embodiment.

[0107] Figure 1 This is a partial planar schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. Figure 2 This is a partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. Figure 2 for Figure 1 A partial cross-sectional view along the PP' direction.

[0108] In some examples, such as Figure 1 and Figure 2 As shown, in a direction perpendicular to the display panel, the display panel may include: a substrate 100, and a driving circuit layer and a light-emitting element 41 sequentially disposed on the substrate 100. The driving circuit layer may include: a first conductive layer 21, a second conductive layer 22, and a thin-film transistor layer 23. The thin-film transistor layer 23 may be located between the first conductive layer 21 and the second conductive layer 22, with the second conductive layer 22 located on the side of the first conductive layer 21 away from the substrate 100. The thin-film transistor layer 23 may include first-type thin-film transistors and second-type thin-film transistors. Figure 2 The diagram illustrates a first-type thin-film transistor 31 and a second-type thin-film transistor 32 as examples. The first-type thin-film transistor can be a low-temperature polycrystalline silicon thin-film transistor, and the second-type thin-film transistor can be an oxide thin-film transistor.

[0109] In some examples, such as Figure 2 As shown, a first type of thin-film transistor 31 may include: a gate 313, a silicon semiconductor layer 310, a first electrode 311, and a second electrode 312. The silicon semiconductor layer 310 may include: a channel region 3100, and a first region 3101 and a second region 3102 located on both sides of the channel region 3100. The first electrode 311 of the first type of thin-film transistor 31 may be electrically connected to the first region 3101 of the silicon semiconductor layer 310; the second electrode 312 may be electrically connected to the second region 3102 of the silicon semiconductor layer 310. A second type of thin-film transistor 32 may include: a gate (including a first gate 323a and a second gate 323b), an oxide semiconductor layer 320, a second source electrode 321, and a second drain electrode 322. The oxide semiconductor layer 320 may include: a channel region 3200, and a first region 3201 and a second region 3202 located on both sides of the channel region 3200. The first electrode 321 of the second type of thin film transistor 32 can be electrically connected to the first region 3201 of the oxide semiconductor layer 320; the second electrode 322 can be electrically connected to the second region 3202 of the oxide semiconductor layer 320.

[0110] In some examples, such as Figure 2 As shown, in a direction perpendicular to the display panel, a first inorganic layer 101 is disposed between the first conductive layer 21 and the substrate 100; a second inorganic layer 102 is disposed between the first conductive layer and the thin-film transistor layer 23. The thin-film transistor layer 23 may include: a first semiconductor layer, a third inorganic layer 103, a third conductive layer, a fourth inorganic layer 104, a fourth conductive layer, a fifth inorganic layer 105, a second semiconductor layer, a sixth inorganic layer 106, a fifth conductive layer, a seventh inorganic layer 107, and a sixth conductive layer disposed sequentially along a direction away from the substrate 100. On the side of the sixth conductive layer away from the substrate 100, a first organic layer 111, a seventh conductive layer, a second organic layer 112, a second conductive layer 22, a third organic layer 113, and an eighth conductive layer are disposed sequentially.

[0111] In some examples, the substrate 100 can be a flexible substrate, such as an organic material made of PI (polyimide) or PET (polyethylene terephthalate); or it can be a rigid substrate, such as a glass substrate or a silicon-based substrate.

[0112] In some examples, a first inorganic layer 101 is disposed on a substrate 100. The first inorganic layer 101 may include inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxide (SiOx, x>0), and silicon oxynitride (SiOxNy, x>0, y>0); the first inorganic layer 101 may be a single layer, or it may be two or more layers of silicon nitride, silicon oxide, or silicon oxynitride stacked together. The thickness of the first inorganic layer 101 may be in the range of about 30 nanometers to about 300 nanometers (nm). In some examples, the first inorganic layer 101 may be a single-layer silicon oxide structure, and its thickness may be in the range of about 70 nanometers to about 100 nanometers; exemplaryly, the thickness of the first inorganic layer 101 may be in the range of about 75 nanometers to about 90 nanometers.

[0113] In some examples, the first conductive layer 21 is disposed on the side of the first inorganic layer 101 away from the substrate 100. The material of the first conductive layer 21 may include at least one of the following metals: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), nickel (Ni), tungsten (W), magnesium (Mg), and their alloys or other conductive materials. The thickness of the first conductive layer 21 may be in the range of about 45 nanometers to about 150 nanometers, for example, in the range of about 50 nanometers to about 60 nanometers.

[0114] In some examples, the first conductive layer 21 may include a first shielding structure 211 and a second shielding structure 212. The outline shapes of the first shielding structure 212 and the second shielding structure 212 may be (or approximately) quadrilaterals, pentagons, or other polygons, or may be circular, elliptical, or other irregular shapes or patterns. The outline shapes of the first shielding structure 211 and the second shielding structure 212 may be the same or different. For example, the outline shape of the first shielding structure 211 may be a square, and the outline shape of the second shielding structure 212 may be a rectangle; or, for example, the outline shape of the first shielding structure 211 may be a rectangle, and the outline shape of the second shielding structure 212 may be an ellipse. The first shielding structure 211 may be positioned corresponding to the location of the first type of thin-film transistor 31, and the second shielding structure 212 may be positioned corresponding to the location of the second type of thin-film transistor 32. In some examples, the first shielding structure 211 and the second shielding structure 212 may be an integral structure, physically connected by connecting lines, forming a mesh structure in a plane. In some examples, the first shielding structure 211 and the second shielding structure 212 can be electrically connected to a constant voltage, for example, through a peripheral area or via, to a trace that transmits a constant voltage (which could be a single voltage, an initialization voltage Vint, or a reference voltage Vref). In other examples, the first shielding structure and the second shielding structure can be independent structures with no physical or electrical connection between them.

[0115] Figure 3 for Figure 1 An exemplary planar schematic diagram of the first conductive layer. In some examples, such as... Figure 3 As shown, the first shielding structure 211 and the second shielding structure 212 of the first conductive layer can be an integral structure, and the orthographic projection of this integral structure onto the substrate can be rectangular or square. The integral structure of the first shielding structure 211 and the second shielding structure 212 can be connected to the first connecting line 213 extending along the first direction D1 and the second connecting line 214 extending along the second direction D2. This integral structure, the first connecting line 213 and the second connecting line 214 can be connected to form a mesh structure. The first connecting line 213 or the second connecting line 214 can extend to the peripheral area and be electrically connected to the trace transmitting a certain constant voltage, or it can be electrically connected to the trace transmitting a certain constant voltage at a specific location in the display area through a via.

[0116] In some examples, such as Figure 2 As shown, the first shielding structure 211 is configured to shield the channel region 3100 of the silicon semiconductor layer 310 of the first type of thin film transistor 31, and the second shielding structure 212 is configured to shield the channel region 3200 of the oxide semiconductor layer 320 of the second type of thin film transistor 32. This can avoid or reduce the influence of light on the semiconductor channel region, stabilize the electrical performance of the thin film transistor, and improve the display quality of the display panel. In addition, the first shielding structure 211 can also block the diffusion of impurity ions into the communication region 3100 of the silicon semiconductor layer 310 of the first type of thin film transistor 31, which is beneficial to improving the stability of the first type of thin film transistor.

[0117] In some examples, the second inorganic layer 212 is disposed on the side of the first conductive layer away from the substrate 100. The second inorganic layer 212 may include inorganic insulating materials such as silicon nitride, silicon oxide, titanium oxide, aluminum oxide, and silicon oxynitride; the second inorganic layer 212 may be a single-layer structure, or a stacked structure of two or more layers selected from silicon nitride, silicon oxide, titanium oxide, aluminum oxide, and silicon oxynitride; the thickness of the second inorganic layer 212 may be in the range of about 200 nanometers to about 800 nanometers (nm). For example, the second inorganic layer 212 may be a bilayer structure including a silicon nitride layer and a silicon oxide layer, wherein the thickness of the silicon nitride layer may be in the range of about 40 nanometers to about 70 nanometers, and further in the range of about 50 nanometers to about 60 nanometers; the thickness of the silicon oxide layer may be in the range of about 100 nanometers to about 400 nanometers, and further in the range of about 130 nanometers to about 160 nanometers.

[0118] In some examples, the first semiconductor layer is disposed on the side of the second inorganic layer away from the substrate 100. For example, the first semiconductor layer may be formed of a low-temperature polycrystalline silicon material; the thickness of the first semiconductor layer may be in the range of about 30 nanometers to about 65 nanometers, for example, in the range of about 35 nanometers to about 40 nanometers. The thickness of the silicon-containing semiconductor layer may be in the range of 30 nanometers to 65 nanometers, for example, in the range of about 35 nanometers to about 40 nanometers. The first semiconductor layer may include a conductive region that has been ion-doped and made conductive, and an undoped semiconductor region. The first semiconductor layer may include: a silicon-containing semiconductor layer 310 of a first type of thin-film transistor 31, wherein the silicon-containing semiconductor layer 310 of the first type of thin-film transistor 31 may include: a channel region 3100, and a first region 3101 and a second region 3102 located on both sides of the channel region 3100; wherein the channel region 3100 is an undoped semiconductor region, and the first region 3101 and the second region 3102 are ion-doped conductive regions.

[0119] In some examples, the orthographic projection of the first shielding structure 211 located on the first conductive layer 21 onto the substrate 100 at least partially overlaps with the orthographic projection of the silicon-containing semiconductor layer 310 onto the substrate 100. For example, the orthographic projection of the first shielding structure 211 onto the substrate 100 may cover the orthographic projection of the silicon-containing semiconductor layer 310 onto the substrate 100. For example, the orthographic projection of the first shielding structure 211 onto the substrate 100 may completely cover the orthographic projection of the channel region 3100 of the silicon-containing semiconductor layer 310 onto the substrate 100.

[0120] In some examples, the third inorganic layer 103 is disposed on the side of the first semiconductor layer away from the substrate 100. The third inorganic layer 103 may also be referred to as the first gate insulating layer. The material of the third inorganic layer 103 may include inorganic insulating materials such as silicon nitride, silicon oxide, titanium oxide, aluminum oxide, and silicon oxynitride; the third inorganic layer 103 may be a single-layer structure, or it may be a stacked structure of two or more layers selected from silicon nitride, silicon oxide, titanium oxide, aluminum oxide, and silicon oxynitride; the thickness of the third inorganic layer 103 may be in the range of about 50 nanometers to about 70 nanometers (nm). For example, the third inorganic layer 103 may be a single-layer structure of silicon oxide with a thickness in the range of about 60 nanometers to about 65 nanometers, and further in the range of about 62 nanometers to about 63 nanometers.

[0121] In some examples, the third conductive layer is disposed on the side of the third inorganic layer 103 away from the substrate 100. The material of the third conductive layer can be at least one of the following metals: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), nickel (Ni), tungsten (W), magnesium (Mg), and their alloys or other conductive materials. The thickness of the third conductive layer can be approximately 2 to 6 times the thickness of the first conductive layer; for example, the thickness of the third conductive layer can be in the range of approximately 180 nanometers to approximately 300 nanometers, and more specifically, in the range of approximately 220 nanometers to approximately 280 nanometers.

[0122] In some examples, such as Figure 2 As shown, the third conductive layer may include: the gate 313 of the first type of thin-film transistor 31. The orthographic projection of the gate 313 of the first type of thin-film transistor 31 onto the substrate 100 overlaps with the orthographic projection of the channel region 3100 of the silicon-containing semiconductor layer 310 onto the substrate 100. Specifically, the orthographic projection of the gate 313 of the first type of thin-film transistor 31 onto the substrate 100 and the orthographic projection of the channel region 3100 of the silicon-containing semiconductor layer 310 onto the substrate 100 may coincide.

[0123] In some examples, the fourth inorganic layer 104 is disposed on the side of the third conductive layer away from the substrate 100. The fourth inorganic layer 104 may also be referred to as the second gate insulating layer. The fourth inorganic layer 104 may include inorganic insulating materials such as silicon nitride, silicon oxide, titanium oxide, aluminum oxide, and silicon oxynitride; the fourth inorganic layer 104 may be a single-layer structure, or it may be a stacked structure of two or more layers of silicon nitride, silicon oxide, titanium oxide, aluminum oxide, and silicon oxynitride; the thickness of the fourth inorganic layer 104 may be from about 60 nanometers to about 130 nanometers (nm). For example, the fourth inorganic layer 104 may be a single-layer structure of silicon nitride with a thickness ranging from about 65 nanometers to about 90 nanometers, and further from about 70 nanometers to about 80 nanometers.

[0124] In some examples, the fourth conductive layer is disposed on the side of the fourth inorganic layer 104 away from the substrate 100. The material of the fourth conductive layer can be at least one of the following metals: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), nickel (Ni), tungsten (W), magnesium (Mg), and their alloys or other conductive materials. The thickness of the fourth conductive layer is approximately 2 to 6 times the thickness of the first conductive layer; for example, the thickness of the fourth conductive layer can be in the range of approximately 190 nanometers to approximately 310 nanometers, and more specifically, in the range of approximately 250 nanometers to approximately 280 nanometers.

[0125] In some examples, such as Figure 2As shown, the fourth conductive layer may include: a first gate 323a of the second type of thin-film transistor 32; the orthographic projection of the first gate 323a onto the substrate 100 may at least partially overlap with the orthographic projection of the oxide semiconductor layer 320 of the second type of thin-film transistor 32 onto the substrate 100. For example, the orthographic projection of the first gate 323a onto the substrate 100 may cover the orthographic projection of the channel region 3200 of the oxide semiconductor layer 320 onto the substrate 100. The area of ​​the orthographic projection of the first gate 323a onto the substrate 100 is not less than the area of ​​the orthographic projection of the channel region 3200 of the oxide semiconductor layer 320 onto the substrate 100.

[0126] In some examples, the fifth inorganic layer 105 is disposed on the side of the fourth conductive layer away from the substrate 100. The fifth inorganic layer 105 may also be referred to as the first interlayer dielectric layer. The fifth inorganic layer 105 may include inorganic insulating materials such as silicon nitride, silicon oxide, titanium oxide, aluminum oxide, and silicon oxynitride. The fifth inorganic layer 105 may be a single-layer structure or a stacked structure of two or more layers of silicon nitride, silicon oxide, titanium oxide, aluminum oxide, and silicon oxynitride. The thickness of the fifth inorganic layer 105 may be in the range of about 300 nanometers to about 600 nanometers (nm). For example, the fifth inorganic layer 105 can be a bilayer structure including a silicon nitride layer and a silicon oxide layer (the material order of the bilayer structure is not limited, from bottom to top, it can be a silicon nitride layer and a silicon oxide layer; or it can be a silicon oxide layer and a silicon nitride layer); wherein, the thickness of the silicon nitride layer can be in the range of about 180 nanometers to about 220 nanometers, and further in the range of about 190 nanometers to about 210 nanometers; the thickness of the silicon oxide layer can be in the range of about 190 nanometers to about 250 nanometers, and further in the range of about 200 nanometers to about 230 nanometers.

[0127] In some examples, the second semiconductor layer is disposed on the side of the fifth inorganic layer 105 away from the substrate 100. The second semiconductor layer may be formed of a metal oxide semiconductor material such as indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium zinc oxide (IZO), and the second semiconductor layer includes a conductive region that is conductive by ion doping and a semiconductor region that is not ion doped; the thickness of the second semiconductor layer may be in the range of about 30 nanometers to about 60 nanometers, and more particularly in the range of about 40 nanometers to about 50 nanometers.

[0128] In some examples, such as Figure 2As shown, the second semiconductor layer may include an oxide semiconductor layer 320 of a second type of thin-film transistor 32. The oxide semiconductor layer 320 may include a channel region 3200 and a first region 3201 and a second region 3202 located on either side of the channel region 3200. The channel region 3200 is an undoped semiconductor region, and the first region 3201 and the second region 3202 are ion-doped conductive regions. For example, the thickness of the oxide semiconductor layer 320 may range from 40 nanometers to 50 nanometers, and more specifically, from about 40 nanometers to about 50 nanometers.

[0129] In some examples, the oxide semiconductor layer 320 can be a two-layer or multi-layer stacked structure to improve the carrier mobility of the transistors and adapt to the display driving requirements of high refresh rates.

[0130] In some examples, the oxide semiconductor layer 320 can be a two-layer stacked structure, with the density of the layer closer to the substrate being lower than that of the layer farther from the substrate. The lower-density layer ensures high carrier mobility, while the higher-density layer blocks water and oxygen intrusion, significantly reducing threshold voltage drift under bias stress, thus simultaneously achieving high electrical performance and long-term reliability. Furthermore, using a two-layer structure with different densities helps reduce leakage paths, effectively lowering off-state leakage current and significantly improving the transistor's current switching ratio, adapting to the low-power driving requirements of display panels.

[0131] In some examples, the thickness of the oxide semiconductor layer 320 closest to the substrate is greater than the thickness of the layer furthest from the substrate. In some examples, the thickness of the layer closest to the substrate is 1 to 3 times the thickness of the layer furthest from the substrate. For example, the thickness of the layer closest to the substrate is 1.5 to 2 times the thickness of the layer furthest from the substrate. In this example, the layer closest to the substrate ensures efficient transport of channel carriers, while the layer furthest from the substrate blocks water and oxygen permeation and suppresses the generation of oxygen vacancy defects, thus achieving a balance between high mobility and long-term reliability.

[0132] In some examples, the sixth inorganic layer 106 is disposed on the side of the second semiconductor layer away from the substrate 100. The sixth inorganic layer 106 may also be referred to as the third gate insulating layer. The sixth inorganic layer 106 may include inorganic insulating materials such as silicon nitride, silicon oxide, titanium oxide, aluminum oxide, and silicon oxynitride; the sixth inorganic layer 106 may be a single-layer structure, or it may be a stacked structure of two or more layers of silicon nitride, silicon oxide, titanium oxide, aluminum oxide, and silicon oxynitride; the thickness of the sixth inorganic layer 106 may be from about 100 nanometers to about 200 nanometers (nm). For example, the sixth inorganic layer may be a single-layer structure of silicon oxide with a thickness ranging from about 120 nanometers to about 180 nanometers, and further from about 130 nanometers to about 150 nanometers.

[0133] In some examples, the fifth conductive layer is disposed on the side of the sixth inorganic layer 106 away from the substrate 100. The material of the fifth conductive layer may include at least one of metals selected from Mo, copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), nickel (Ni), tungsten (W), magnesium (Mg), and their alloys or other conductive materials. In some examples, the fifth conductive layer may also include a protective layer, for example, the protective layer material may be titanium nitride (TiN), which can protect the conductive material in the fifth conductive layer from corrosion. The thickness of the fifth conductive layer may be in the range of about 250 nanometers to about 400 nanometers, and more specifically, in the range of about 250 nanometers to about 280 nanometers. In embodiments including a protective layer, the thickness of the protective layer may be in the range of about 30 nanometers to about 45 nanometers.

[0134] In some examples, such as Figure 2As shown, the fifth conductive layer may include: a second gate 323b of the second type thin-film transistor 32; the orthographic projection of the second gate 323b onto the substrate 100 may at least partially overlap with the orthographic projection of the oxide semiconductor layer 320 of the second type thin-film transistor 32 onto the substrate 100. For example, the orthographic projection of the second gate 323b onto the substrate 100 may cover the orthographic projection of the channel region 3200 of the oxide semiconductor layer 320 onto the substrate 100. The area of ​​the orthographic projection of the second gate 323b onto the substrate 100 is not less than the area of ​​the orthographic projection of the channel region 3200 of the oxide semiconductor layer 320 onto the substrate 100. The area of ​​the orthographic projection of the first gate 323a onto the substrate 100 is not less than the area of ​​the orthographic projection of the second gate 323b onto the substrate 100. For example, the orthographic projection of the second gate 323b onto the substrate 100 may be located inside the orthographic projection of the first gate 323a onto the substrate 100. In this example, the second type of thin-film transistor 32 is a dual-gate transistor, with the first gate 323a as the bottom gate and the second gate 323b as the top gate. The oxide semiconductor layer 320 is located between the first gate 323a and the second gate 323b. This example of a dual-gate design for the second type of thin-film transistor 32 can improve carrier mobility and enhance output current. Furthermore, the dual-gate structure allows for simultaneous potential modulation from both the top and bottom sides of the channel region 3200 via the first gate 323a and the second gate 323b, effectively suppressing short-channel effects. Even when the channel is shrunk to the nanometer scale, it maintains a good on / off ratio, meeting the process requirements of high-density, high-resolution panels. Moreover, the dual-gate structure can reduce the electric field strength in the vertical direction, lower the electric field stress on channel carriers, effectively alleviate threshold voltage drift under positive gate thermal stress, and improve the stability of the second type of thin-film transistor during long-term operation.

[0135] In some examples, the seventh inorganic layer 107 is disposed on the side of the fifth conductive layer away from the substrate 100. The seventh inorganic layer 107 can also be referred to as the second interlayer dielectric layer. The material of the seventh inorganic layer 107 may include inorganic insulating materials such as silicon nitride, silicon oxide, titanium oxide, aluminum oxide, and silicon oxynitride; the seventh inorganic layer 107 can be a single-layer structure, or it can be a stacked structure of two or more layers of silicon nitride, silicon oxide, titanium oxide, aluminum oxide, and silicon oxynitride; the thickness of the seventh inorganic layer 107 can be from about 400 nanometers to about 600 nanometers (nm). For example, the seventh inorganic layer 107 can be a bilayer structure including a silicon nitride layer and a silicon oxide layer (the material order of the bilayer structure is not limited, from bottom to top, it can be a silicon nitride layer and a silicon oxide layer; or, in turn, a silicon oxide layer and a silicon nitride layer); wherein, the thickness of the silicon nitride layer can be in the range of about 180 nanometers to about 220 nanometers, and further in the range of about 190 nanometers to about 210 nanometers; the thickness of the silicon oxide layer can be in the range of about 190 nanometers to about 250 nanometers, and further in the range of about 200 nanometers to about 230 nanometers.

[0136] In some examples, such as Figure 2 As shown, the seventh inorganic layer 107 can be provided with multiple vias, such as a first via, a second via, a third via, and a fourth via. The seventh inorganic layer 107, the sixth inorganic layer 106, the fifth inorganic layer 105, the fourth inorganic layer 104, and the third inorganic layer 103 within the first and second vias can be removed, exposing a portion of the surface of the silicon-containing semiconductor layer 310 away from the substrate 100. For example, the first via can expose a portion of the surface of the first region 3101 of the silicon-containing semiconductor layer 310, and the second via can expose a portion of the surface of the second region 3102 of the silicon-containing semiconductor layer 310. The seventh inorganic layer 107 and the sixth inorganic layer 106 within the third and fourth vias can be removed, exposing a portion of the surface of the oxide semiconductor layer 320 away from the substrate 100. For example, the third via can expose a portion of the surface of the first region 3201 of the oxide semiconductor layer 320, and the fourth via can expose a portion of the surface of the second region 3202 of the oxide semiconductor layer 320.

[0137] In some examples, the sixth conductive layer is disposed on the side of the seventh inorganic layer 107 away from the substrate 100. The material of the sixth conductive layer may include at least one of the following metals: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), nickel (Ni), tungsten (W), and magnesium (Mg), or their alloys or other conductive materials. For example, the sixth conductive layer may be a bilayer or multilayer stacked structure, such as a Ti-Mo-Ti stacked structure or a Ti-Al-Ti stacked structure; the thickness of the sixth conductive layer may be in the range of about 500 nanometers to about 800 nanometers. In the Ti-Al-Ti stacked structure embodiment, the thickness of the first metallic Ti layer may be in the range of about 50 nanometers to about 70 nanometers, the thickness of the intermediate Al metal may be in the range of about 500 nanometers to about 700 nanometers, and the thickness of the second metallic Ti layer may be in the range of about 50 nanometers to about 70 nanometers.

[0138] In some examples, such as Figure 2As shown, the sixth conductive layer may include: a first electrode 311 and a second electrode 312 of a first type of thin-film transistor 31, and a first electrode 321 and a second electrode 322 of a second type of thin-film transistor 32. The first electrode 311 of the first type of thin-film transistor 31 may be electrically connected to the first region 3101 of the silicon-containing semiconductor layer 310 through a first via; the second electrode 312 of the first type of thin-film transistor 31 may be electrically connected to the second region 3102 of the silicon-containing semiconductor layer 310 through a second via; the first electrode 321 of the second type of thin-film transistor 32 may be electrically connected to the first region 3201 of the oxide semiconductor layer 320 through a third via; and the second electrode 322 of the second type of thin-film transistor 32 may be electrically connected to the second region 3202 of the oxide semiconductor layer 320 through a fourth via.

[0139] In some examples, the first organic layer 111 is disposed on the side of the sixth conductive layer away from the substrate 100. The first organic layer 111 may include organic insulating materials such as polyimide resin, acrylic resin, phenolic resin, polyamide resin, epoxy resin, and unsaturated polyester resin; the thickness of the first organic layer 111 may be in the range of about 1.1 micrometers to about 3 micrometers, and further, in the range of about 1.2 micrometers to about 1.3 micrometers.

[0140] In some examples, a seventh conductive layer is disposed on the side of the first organic layer 111 away from the substrate 100. The material of the seventh conductive layer may include at least one of the following metals: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), nickel (Ni), tungsten (W), and magnesium (Mg), or their alloys or other conductive materials. For example, the seventh conductive layer is a bilayer or multilayer stacked structure, such as a Ti-Mo-Ti stacked structure or a Ti-Al-Ti stacked structure; the thickness of the seventh conductive layer may be in the range of about 500 nanometers to about 800 nanometers. For example, in a Ti-Al-Ti stacked structure embodiment, the thickness of the first Ti layer may be in the range of about 50 nanometers to about 60 nanometers, the thickness of the intermediate Al metal may be in the range of about 500 nanometers to about 700 nanometers, and the thickness of the second Ti layer may be in the range of about 50 nanometers to about 60 nanometers.

[0141] In some examples, such as Figure 2 As shown, the seventh conductive layer may include a fourth transition electrode 244. The fourth transition electrode 244 can be connected to the second electrode 312 of the first type of thin film transistor 31 located in the sixth conductive layer through a fifth via provided in the first organic layer 111.

[0142] In some examples, the second organic layer 112 is disposed on the side of the seventh conductive layer away from the substrate 100. The second organic layer 112 may include organic insulating materials such as polyimide resin, acrylic resin, phenolic resin, polyamide resin, epoxy resin, and unsaturated polyester resin; the thickness of the second organic layer 112 may be in the range of about 1.2 micrometers to about 2.5 micrometers, and more particularly, may be in the range of about 1.5 micrometers to about 1.8 micrometers.

[0143] In some examples, the second conductive layer 22 is disposed on the side of the second organic layer 112 away from the substrate 100. The material of the second conductive layer 22 may include at least one of the following metals: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), nickel (Ni), tungsten (W), magnesium (Mg), and their alloys or other conductive materials. In some examples, the second conductive layer 22 may be a two-layer or multi-layer stacked structure, such as a Ti-Mo-Ti stacked structure or a Ti-AL-Ti stacked structure; the thickness of the second conductive layer 22 may be in the range of about 500 nanometers to about 800 nanometers. For example, in a Ti-AL-Ti stacked structure embodiment, the thickness of the first metallic Ti layer may be in the range of about 50 nanometers to about 60 nanometers, the thickness of the intermediate Al metal may be in the range of about 500 nanometers to about 700 nanometers, and the thickness of the second metallic Ti layer may be in the range of about 50 nanometers to about 60 nanometers.

[0144] Figure 4 for Figure 1 A partial planar schematic diagram of the first power transmission structure located in the second conductive layer. In some examples, such as... Figure 2 and Figure 4 As shown, the second conductive layer 22 may include a first power transmission structure 25 and a plurality of third transition electrodes 243. The first power transmission structure 25 may be configured to provide a low-level voltage to the first electrode of the light-emitting element. The second conductive layer 22 may also include a second power transmission structure for transmitting a high-level voltage. For example, the second power transmission structure may be electrically connected to the second electrode of the light-emitting element via a thin-film transistor in the thin-film transistor layer.

[0145] In some examples, such as Figure 2 and Figure 4As shown, the third transition electrode 243 can be electrically connected to the fourth transition electrode 244 located in the seventh conductive layer through the sixth via formed in the second planarization layer 112. The first power transmission structure 25 may include: a plurality of first power electrodes 251, a plurality of first power connection lines 252 extending along the first direction D1, and a plurality of second power connection lines 253 extending along the second direction D2. The plurality of first power electrodes 251, the plurality of first power connection lines 252, and the plurality of second power connection lines 253 can be connected to form a mesh structure. The orthographic projection of the first power electrode 251 on the substrate 100 can be approximately rectangular. The minimum length of the first power electrode 251 along the first direction D1 is greater than the linewidth of the first power connection line 252 and the second power connection line 253, and the minimum length of the first power electrode 252 along the second direction D2 is greater than the linewidth of the first power connection line 252 and the second power connection line 253. The first power transmission structure in this example is a mesh structure, which can effectively reduce the transmission resistance of low-level voltage, reduce the voltage drop of low-level voltage, reduce power consumption, and effectively improve the uniformity and stability of low-level voltage in the display panel, thereby effectively improving display uniformity, display quality and display performance.

[0146] In some examples, such as Figure 2 and Figure 4 As shown, the orthographic projection of the first power electrode 251 onto the substrate 100 at least partially overlaps with the orthographic projection of the oxide semiconductor layer 320 onto the substrate 100. For example, the orthographic projection of the first power electrode 251 onto the substrate 100 can completely cover the orthographic projection of the oxide semiconductor layer 320 onto the substrate 100. For example, the orthographic projection of the first power electrode 251 onto the substrate 100 can completely cover the orthographic projection of the channel region 3200 of the oxide semiconductor layer 320 onto the substrate 100. The orthographic projection of the first power electrode 251 onto the substrate 100 at least partially overlaps with the orthographic projection of the second shielding structure 212 located on the first conductive layer 21 onto the substrate 100. For example, the outline pattern of the first power electrode 251 and the outline pattern of the second shielding structure 212 can be at least partially the same; for example, the outline pattern of the first power electrode 251 and the outline pattern of the second shielding structure 212 can be substantially the same. For example, the orthographic projection of the first power electrode 251 onto the substrate 100 can cover the orthographic projection of multiple (e.g., three arranged sequentially along the second direction D2) second shielding structures 212 onto the substrate 100.

[0147] In some examples, the third organic layer 113 is disposed on the side of the second conductive layer 22 away from the substrate 100. The third organic layer 113 may include organic insulating materials such as polyimide resin, acrylic resin, phenolic resin, polyamide resin, epoxy resin, and unsaturated polyester resin; the thickness of the third organic layer 113 may be in the range of about 2.2 micrometers to about 3.3 micrometers, and more particularly, may be in the range of about 2.8 micrometers to about 3.1 micrometers.

[0148] In some examples, such as Figure 1 and Figure 2 As shown, the eighth conductive layer is disposed on the side of the third organic layer 113 away from the substrate 100. The eighth conductive layer may include a first transition electrode 241 and a second transition electrode 242. The first transition electrode 241 can be electrically connected to the first power electrode 251 of the first power transmission structure through a seventh via V7 formed in the third organic layer 113, and the second transition electrode 242 can be electrically connected to the third transition electrode 243 through an eighth via V8 formed in the third organic layer 113. The orthographic projection of the first transition electrode 241 onto the substrate may be located within the orthographic projection range of the first power electrode 251 onto the substrate; the orthographic projection of the second transition electrode 242 onto the substrate may be located within the orthographic projection range of the connected third transition electrode 243 onto the substrate. In some examples, the orthographic projection of the first transition electrode 241 onto the substrate may coincide with the orthographic projection of the first power electrode 251 onto the substrate, and the orthographic projection of the second transition electrode 242 onto the substrate may coincide with the orthographic projection of the connected third transition electrode 243 onto the substrate.

[0149] In some examples, the material of the eighth conductive layer may include at least one of the following metals: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), nickel (Ni), tungsten (W), and magnesium (Mg), or their alloys or other conductive materials. The thickness of the eighth conductive layer may range from about 80 nanometers to about 100 nanometers, and further, from about 85 nanometers to about 95 nanometers. Using a metallic material for the eighth conductive layer in this example can help reduce the resistance voltage drop between the first and second transition electrodes, improve the current injection efficiency of the light-emitting element, and reduce overall power consumption. Furthermore, metallic materials have good mechanical strength and solderability, enabling more reliable welding connections during bonding with the light-emitting element, reducing yield risks such as poor soldering and detachment; they can also quickly dissipate the heat generated during MicroLED operation.

[0150] In some examples, the material of the eighth conductive layer can be a transparent conductive material, such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). Using a transparent conductive material for the eighth conductive layer in this example can meet the electrode conductivity requirements, achieve better eutectic bonding with the light-emitting element (e.g., MicroLED), provide high lateral conductivity, reduce localized overheating, and improve the lifespan of the light-emitting element.

[0151] In some examples, the material of the eighth conductive layer can include metal nanowires, conductive polymers such as poly(3,4-ethylenedioxythiophene) (PEDOT), graphene, and other conductive materials. The material of the eighth conductive layer in this example exhibits high conductivity and excellent flexibility, meeting the needs of miniaturization and flexible MicroLEDs. Taking metal nanowires as an example, metal nanowires do not rely on scarce indium resources, which can reduce material costs and mitigate supply chain risks caused by fluctuations in indium resource prices. Moreover, the networked conductive structure of metal nanowires allows current to diffuse uniformly on the light-emitting side, avoiding problems such as uneven light emission and premature pixel decay caused by excessively high local current density.

[0152] In some examples, such as Figure 2 As shown, the light-emitting element 41 can be a MicroLED. For example, the light-emitting element 41 may include: a light-emitting portion 410, a first electrode 411, and a second electrode 412, wherein the first electrode 411 and the second electrode 412 are located on the side of the light-emitting portion 410 closest to the substrate 100. The first electrode 411 can be a cathode electrode, and the second electrode 412 can be an anode electrode. The first electrode 411 is electrically connected to the first transfer electrode 241, for example, by bonding or soldering; the second electrode 412 is electrically connected to the second transfer electrode 242, for example, by bonding or soldering.

[0153] In some examples, such as Figure 1As shown, the multiple light-emitting elements 41 in the display area may include a first light-emitting element 41a, a second light-emitting element 41b, and a third light-emitting element 41c. The first light-emitting element 41a, the second light-emitting element 41b, and the third light-emitting element 41c can be configured to emit different colors of light. For example, the first light-emitting element 41a can be configured to emit green light, the second light-emitting element 41b can be configured to emit blue light, and the third light-emitting element 41c can be configured to emit red light. The first light-emitting element 41a and the second light-emitting element 41b can be arranged alternately in a row along a first direction D1, and multiple third light-emitting elements 41c can be arranged in a row along the first direction D1. An adjacent first light-emitting element 41a, a second light-emitting element 41b, and a third light-emitting element 41c constitute a pixel unit; within a single pixel unit, the third light-emitting element 41c is located on the same side of the first light-emitting element 41a and the second light-emitting element 41b in the second direction D2. Multiple pixel units can be arranged in an array along the first direction D1 and the second direction D2. The first direction D1 and the second direction D2 are parallel to the plane of the substrate. The first direction D1 intersects the second direction D2. For example, the first direction D1 is perpendicular to the second direction D2.

[0154] In some examples, such as Figure 1 As shown, the second transition electrode 242 and the third transition electrode 243 connected to the three light-emitting elements in a pixel unit are located between two adjacent first power supply electrodes 251 in the first direction D1. In other words, the second transition electrode 242 and the third transition electrode 243 connected to the three light-emitting elements of a pixel unit can be arranged within the grid between two adjacent first power supply electrodes 251 in the first direction D1. The first transition electrode 241 connected to the first light-emitting element 41a in a pixel unit and the first transition electrode 241 connected to the third light-emitting element 41c, as well as the first transition electrode 241 connected to the second light-emitting element 41b in adjacent pixel units, can be connected into a single structure, and the orthographic projection of this single structure onto the substrate is located within the orthographic projection range of the first power supply electrode 251 onto the substrate. The arrangement of the light-emitting elements and the first power transmission structure in this example can make full use of space and facilitates reasonable wiring.

[0155] Figure 5 This disclosure presents a schematic diagram showing the orthographic projection relationship between the oxide semiconductor layer, the second shielding structure of the first conductive layer, and the first power transmission structure of the second conductive layer, representing at least one embodiment. In some examples, such as... Figure 5As shown, the orthographic projection of the channel region 3200 of the oxide semiconductor layer 320 onto the substrate can fall within the orthographic projection range of the second shielding structure 212 onto the substrate, and the orthographic projection of the second shielding structure 212 onto the substrate can fall within the orthographic projection range of the first power connection electrode 251 of the first power transmission structure onto the substrate. The orthographic projection of the first power connection electrode 251 onto the substrate can completely cover the orthographic projection of the second shielding structure 212 onto the substrate. The orthographic projections of the first power connection electrode 251 and the second shielding structure 212 onto the substrate can completely cover the orthographic projection of the channel region 3200 of the oxide semiconductor layer 320 onto the substrate. This example utilizes a first conductive layer (including the second shielding structure) and a second conductive layer (including the first power transmission structure) to shield light from the top and bottom sides of the oxide semiconductor layer, which can further reduce the impact of light on the oxide semiconductor layer and is beneficial to improving the stability of the second type of thin film transistor.

[0156] In other exemplary embodiments, one or more passivation layers may be disposed between the first organic layer 111 and the seventh conductive layer; the passivation layer material may include inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxide (SiOx, x>0), and silicon oxynitride (SiOxNy, x>0, y>0). For example, the passivation layer may be a single-layer silicon nitride structure with a thickness ranging from about 100 nanometers to about 200 nanometers, and further from about 160 nanometers to about 190 nanometers. This example, by providing one or more passivation layers between the first organic layer and the seventh conductive layer, can enhance the insulation effect, prevent local leakage between the conductive layer and the organic film layer, and thus improve structural stability.

[0157] In other exemplary embodiments, one or more passivation layers may be disposed between the second organic layer 112 and the second conductive layer 22; the passivation layer material may include inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxide (SiOx, x>0), and silicon oxynitride (SiOxNy, x>0, y>0). For example, the passivation layer may be a single-layer silicon nitride structure with a thickness ranging from about 100 nanometers to about 200 nanometers, and more particularly from about 160 nanometers to about 190 nanometers. This example, by providing one or more passivation layers between the second organic layer and the second conductive layer, can enhance the insulation effect, prevent local leakage between the conductive layer and the organic film layer, and thus improve structural stability.

[0158] In other exemplary embodiments, one or more passivation layers may be disposed between the second conductive layer 22 and the third organic layer 113; the passivation layer material may include inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxide (SiOx, x>0), and silicon oxynitride (SiOxNy, x>0, y>0). For example, the passivation layer may be a single-layer silicon nitride structure with a thickness ranging from about 100 nanometers to about 200 nanometers, and further from about 140 nanometers to about 160 nanometers. This example, by providing one or more passivation layers between the third organic layer and the second conductive layer, can enhance the insulation effect, prevent local leakage between the conductive layer and the organic film layer, and thus improve structural stability.

[0159] In other exemplary embodiments, one or more passivation layers may be disposed between the eighth conductive layer and the light-emitting element 41; the passivation layer material may include inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxide (SiOx, x>0), and silicon oxynitride (SiOxNy, x>0, y>0). For example, the passivation layer may be a single-layer silicon nitride structure with a thickness ranging from about 100 nanometers to about 200 nanometers, and further from about 140 nanometers to about 160 nanometers. This example, by providing one or more passivation layers between the eighth conductive layer and the light-emitting element, can enhance the insulation effect and reduce the risk of oxidation and corrosion of the conductive layer, thereby extending the service life of the display panel.

[0160] Figure 6 This is another partial planar schematic diagram of the first conductive layer according to at least one embodiment of the present disclosure. In some examples, such as Figure 6 As shown, the first conductive layer may include: a first shielding structure 211 and a second shielding structure 212 separately disposed. The first shielding structure 211 and the second shielding structure 212 may be alternately disposed along a first direction D1, and multiple first shielding structures 211 may be arranged in a row along a second direction D2, and multiple second shielding structures 212 may be arranged in a row along a second direction D2. Multiple first shielding structures 211 and multiple second shielding structures 212 may be connected into a mesh structure by multiple first connecting lines 213 and multiple second connecting lines 214. The orthogonal projection area of ​​the first shielding structure 211 on the substrate may be smaller than the orthogonal projection area of ​​the second shielding structure 212 on the substrate. The first shielding structure and the second shielding structure of the first conductive layer are connected into a mesh structure, which can help improve the uniformity and stability of the signal within the first conductive layer and help reduce the impact on other conductive layers. For further descriptions of the display panel of this example, please refer to the description of the foregoing embodiments, and therefore will not be repeated here.

[0161] Figure 7 This is another partial planar schematic diagram of the first conductive layer according to at least one embodiment of the present disclosure. In some examples, such as Figure 7 As shown, the first conductive layer may include: a first shielding structure 211 and a second shielding structure 212 separately disposed. The first shielding structure 211 and the second shielding structure 212 may be alternately disposed along a first direction D1, and multiple first shielding structures 211 may be arranged in a row along a second direction D2, and multiple second shielding structures 212 may be arranged in a row along a second direction D2. Multiple first shielding structures 211 and multiple second shielding structures 212 may be connected into a mesh structure by multiple first connecting lines 213 and multiple second connecting lines 214. The projected areas of the first shielding structure 211 and the second shielding structure 212 on the substrate may be approximately the same. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0162] Figure 8 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 8 As shown, the inorganic micro-light-emitting display panel may include a first type of thin-film transistor 31 and a second type of thin-film transistor 32. The first type of thin-film transistor 31 has a top-gate structure, and its gate 313 is located on the side of the silicon semiconductor layer 310 away from the substrate 100. The second type of thin-film transistor 32 has a dual-gate structure; the oxide semiconductor layer 320 of the second type of thin-film transistor 32 is located between the first gate 323a and the second gate 323b. The film layer containing the first gate 323a is located on the side of the film layer containing the gate 313 of the first type of thin-film transistor 31 away from the substrate 100. The orthographic projection of the first gate 323a onto the substrate 100 can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100; the orthographic projection of the first gate 323a onto the substrate 100 and the orthographic projection of the second gate 323b onto the substrate 100 can coincide. The orthographic projection of the first shielding structure 211 of the first conductive layer onto the substrate 100 can cover the orthographic projection of the channel region of the silicon semiconductor layer 310 onto the substrate 100; the orthographic projection of the second shielding structure 212 onto the substrate 100 can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and therefore will not be repeated here.

[0163] Figure 9 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 9As shown, the inorganic micro-light-emitting display panel may include a first type of thin-film transistor 31 and a second type of thin-film transistor 32. The first type of thin-film transistor 31 has a top-gate structure, and its gate 313 is located on the side of the silicon semiconductor layer 310 away from the substrate 100. The second type of thin-film transistor 32 has a dual-gate structure; the oxide semiconductor layer 320 of the second type of thin-film transistor 32 is located between the first gate 323a and the second gate 323b. The film layer containing the first gate 323a is located on the side of the film layer containing the gate 313 of the first type of thin-film transistor 31 away from the substrate 100. The orthogonal projection of the first gate 323a onto the substrate 100 can cover the orthogonal projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100; the orthogonal projection of the first gate 323a onto the substrate 100 and the orthogonal projection of the second gate 323b onto the substrate 100 can coincide. The first conductive layer 21 may include a second shielding structure 212. The orthogonal projection of the second shielding structure 212 onto the substrate 100 can cover the orthogonal projection of the channel region of the oxide semiconductor layer 320 of the second type of thin-film transistor 32 onto the substrate 100. In this example, the first conductive layer 21 may omit the provision of the first shielding structure corresponding to the first type of thin-film transistor. This example utilizes the first conductive layer 21 to ensure the light-shielding effect on the second type of thin-film transistor, thereby ensuring the stability of the second type of thin-film transistor. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0164] Figure 10 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 10As shown, the inorganic micro-light-emitting display panel may include a first type of thin-film transistor 31 and a second type of thin-film transistor 32. The first type of thin-film transistor 31 has a top-gate structure, and its gate 313 is located on the side of the silicon semiconductor layer 310 away from the substrate 100. The second type of thin-film transistor 32 has a dual-gate structure; the oxide semiconductor layer 320 of the second type of thin-film transistor 32 is located between the first gate 323a and the second gate 323b. The film layer containing the first gate 323a is located on the side of the film layer containing the gate 313 of the first type of thin-film transistor 31 away from the substrate 100. The orthogonal projection of the first gate 323a onto the substrate 100 can cover the orthogonal projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100; the orthogonal projection of the first gate 323a onto the substrate 100 and the orthogonal projection of the second gate 323b onto the substrate 100 can coincide. The orthographic projection of the first power electrode 251 of the first power transmission structure 25 located in the second conductive layer onto the substrate 100 can cover the orthographic projection of the channel region 3200 of the oxide semiconductor layer 320 onto the substrate 100. In this example, the first power electrode 251 of the first power transmission structure 25 located in the second conductive layer shields the channel region 3200 of the oxide semiconductor layer 320 of the second type of thin film transistor 32 to ensure the stability of the second type of thin film transistor 32. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0165] Figure 11 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 11As shown, the inorganic micro-light-emitting display panel may include a first type of thin-film transistor 31 and a second type of thin-film transistor 32. The first type of thin-film transistor 31 has a top-gate structure, and its gate 313 is located on the side of the silicon semiconductor layer 310 away from the substrate 100. The second type of thin-film transistor 32 has a dual-gate structure; the oxide semiconductor layer 320 of the second type of thin-film transistor 32 is located between the first gate 323a and the second gate 323b. The first gate 323a and the gate 313 of the first type of thin-film transistor 31 are located in the same conductive layer, for example, both in the third conductive layer. The orthographic projection of the first gate 323a onto the substrate 100 may cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100; the orthographic projection of the first gate 323a onto the substrate 100 and the orthographic projection of the second gate 323b onto the substrate 100 may coincide. A fourth inorganic layer 104 is disposed between the second semiconductor layer and the third conductive layer where the oxide semiconductor layer 320 is located. The first conductive layer includes a first shielding structure 211 corresponding to the first type of thin-film transistor 31 and a second shielding structure 212 corresponding to the second type of thin-film transistor 32. The orthographic projection of the first shielding structure 211 onto the substrate 100 covers the orthographic projection of the channel region of the silicon-containing semiconductor layer 310 of the first type of thin-film transistor 31 onto the substrate 100; the orthographic projection of the second shielding structure 212 onto the substrate 100 covers the orthographic projection of the channel region of the oxide semiconductor layer 320 of the second type of thin-film transistor 32 onto the substrate 100. The orthographic projection of the first power electrode 251 of the first power transmission structure 25 located in the second conductive layer onto the substrate 100 covers the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0166] Figure 12 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 12As shown, the inorganic micro-light-emitting display panel may include a first type of thin-film transistor 31 and a second type of thin-film transistor 32. The first type of thin-film transistor 31 has a top-gate structure, and its gate 313 is located on the side of the silicon semiconductor layer 310 away from the substrate 100. The second type of thin-film transistor 32 has a bottom-gate structure; its oxide semiconductor layer 320 is located on the side of the gate 323 away from the substrate 100. The gate 323 of the second type of thin-film transistor 32 may be located in a fourth conductive layer, and the gate 313 of the first type of thin-film transistor 31 may be located in a third conductive layer. The orthographic projection of the gate 323 of the second type of thin-film transistor 32 onto the substrate 100 can completely cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate. The first conductive layer includes a first shielding structure 211 corresponding to the first type of thin-film transistor 31 and a second shielding structure 212 corresponding to the second type of thin-film transistor 32. The orthographic projection of the first shielding structure 211 onto the substrate 100 can cover the orthographic projection of the channel region of the silicon-containing semiconductor layer 310 of the first type of thin-film transistor 31 onto the substrate 100; the orthographic projection of the second shielding structure 212 onto the substrate 100 can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 of the second type of thin-film transistor 32 onto the substrate 100. The orthographic projection of the first power electrode 251 of the first power transmission structure 25 located in the second conductive layer onto the substrate 100 can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0167] Figure 13 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 13As shown, the inorganic micro-light-emitting display panel may include a first type of thin-film transistor 31 and a second type of thin-film transistor 32. The first type of thin-film transistor 31 has a top-gate structure, and its gate 313 is located on the side of the silicon semiconductor layer 310 away from the substrate 100. The second type of thin-film transistor 32 has a bottom-gate structure; its oxide semiconductor layer 320 is located on the side of its gate 323 away from the substrate 100. The gate 323 of the second type of thin-film transistor 32 and the gate 313 of the first type of thin-film transistor 31 may both be located in a third conductive layer. The orthographic projection of the gate 323 of the second type of thin-film transistor 32 onto the substrate 100 may coincide with the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate. The first conductive layer includes a first shielding structure 211 corresponding to the first type of thin-film transistor 31 and a second shielding structure 212 corresponding to the second type of thin-film transistor 32. The orthographic projection of the first shielding structure 211 onto the substrate 100 can cover the orthographic projection of the channel region of the silicon-containing semiconductor layer 310 of the first type of thin-film transistor 31 onto the substrate 100; the orthographic projection of the second shielding structure 212 onto the substrate 100 can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 of the second type of thin-film transistor 32 onto the substrate 100. The orthographic projection of the first power electrode 251 of the first power transmission structure 25 located in the second conductive layer onto the substrate 100 can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0168] Figure 14 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 14As shown, the inorganic micro-light-emitting display panel may include a first type of thin-film transistor 31 and a second type of thin-film transistor 32. The first type of thin-film transistor 31 has a top-gate structure, and its gate 313 is located on the side of the silicon semiconductor layer 310 away from the substrate 100. The second type of thin-film transistor 32 has a bottom-gate structure; its oxide semiconductor layer 320 is located on the side of its gate 323 away from the substrate 100. The gate 323 of the second type of thin-film transistor 32 and the gate 313 of the first type of thin-film transistor 31 may both be located in a third conductive layer. The orthographic projection of the gate 323 of the second type of thin-film transistor 32 onto the substrate 100 can completely cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate. The first conductive layer includes a first shielding structure 211 corresponding to the first type of thin-film transistor 31 and a second shielding structure 212 corresponding to the second type of thin-film transistor 32. The orthographic projection of the first shielding structure 211 onto the substrate 100 can cover the orthographic projection of the channel region of the silicon-containing semiconductor layer 310 of the first type of thin-film transistor 31 onto the substrate 100; the orthographic projection of the second shielding structure 212 onto the substrate 100 can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 of the second type of thin-film transistor 32 onto the substrate 100. The orthographic projection of the first power electrode 251 of the first power transmission structure 25 located in the second conductive layer onto the substrate 100 can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0169] Figure 15 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 15As shown, the inorganic micro-light-emitting display panel may include a first type of thin-film transistor 31 and a second type of thin-film transistor 32. The first type of thin-film transistor 31 has a top-gate structure, and its gate 313 is located on the side of the silicon semiconductor layer 310 away from the substrate 100. The second type of thin-film transistor 32 has a top-gate structure; its oxide semiconductor layer 320 is located on the side of the gate 323 close to the substrate 100. The gate 323 of the second type of thin-film transistor 32 may be located in a fifth conductive layer, and the gate 313 of the first type of thin-film transistor 31 may be located in a third conductive layer. The orthographic projection of the gate 323 of the second type of thin-film transistor 32 onto the substrate 100 may cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate, or the two may overlap. The first conductive layer includes a first shielding structure 211 corresponding to the first type of thin-film transistor 31 and a second shielding structure 212 corresponding to the second type of thin-film transistor 32. The orthographic projection of the first shielding structure 211 onto the substrate 100 can cover the orthographic projection of the channel region of the silicon-containing semiconductor layer 310 of the first type of thin-film transistor 31 onto the substrate 100; the orthographic projection of the second shielding structure 212 onto the substrate 100 can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 of the second type of thin-film transistor 32 onto the substrate 100. The orthographic projection of the first power electrode 251 of the first power transmission structure 25 located in the second conductive layer onto the substrate 100 can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0170] Figure 16 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 16As shown, the inorganic micro-light-emitting display panel may include a first type of thin-film transistor 31 and a second type of thin-film transistor 32. The first type of thin-film transistor 31 has a top-gate structure, and its gate 313 is located on the side of the silicon semiconductor layer 310 away from the substrate 100. The second type of thin-film transistor 32 has a bottom-gate structure; its oxide semiconductor layer 320 is located on the side of its gate 323 away from the substrate 100. The gate 323 of the second type of thin-film transistor 32 and the gate 313 of the first type of thin-film transistor 31 may both be located in a third conductive layer. The first conductive layer includes a first shielding structure 211 corresponding to the first type of thin-film transistor 31 and a second shielding structure 212 corresponding to the second type of thin-film transistor 32. The orthogonal projection of the first shielding structure 211 onto the substrate 100 can cover the orthogonal projection of the channel region of the silicon-containing semiconductor layer 310 of the first type of thin-film transistor 31 onto the substrate 100; the orthogonal projection of the second shielding structure 212 onto the substrate 100 can cover the orthogonal projection of the channel region of the oxide semiconductor layer 320 of the second type of thin-film transistor 32 onto the substrate 100. The orthogonal projection of the first power electrode 251 of the first power transmission structure 25 located in the second conductive layer onto the substrate 100 can cover the orthogonal projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100.

[0171] In some examples, such as Figure 16 As shown, the seventh conductive layer may include a fourth transition electrode 244 and an auxiliary shielding structure 26. The auxiliary shielding structure 26 can be electrically connected to the first power transmission structure 25 located on the second conductive layer through a via formed in the second planarization layer 112. For example, the auxiliary shielding structure 26 can be electrically connected to the first power electrode 251. The overlapping area of ​​the orthographic projections of the auxiliary shielding structure 26 and the first power electrode 251 onto the substrate 100 can at least partially overlap with the orthographic projection of the oxide semiconductor layer 320 onto the substrate, for example, it can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100. This example uses the auxiliary shielding structure and the first power transmission structure to provide double-layer shielding of the channel region of the oxide semiconductor layer from above, and uses the second shielding structure 212 to shield the channel region of the oxide semiconductor layer from below. This can better shield the oxide semiconductor layer, thereby reducing the impact of light on the oxide semiconductor layer and improving the stability of the second type of thin film transistor.

[0172] In some examples, the orthographic projection of the fourth transition electrode 244 onto the substrate can cover the orthographic projection of the channel region of the silicon semiconductor layer 310 onto the substrate. This example utilizes the first shielding structure 211 and the seventh conductive layer to shield the silicon semiconductor layer 310 from both the top and bottom, preventing the influence of light on the silicon semiconductor layer and contributing to the stability of the first type of thin-film transistor's performance. In other examples, the orthographic projection of the third transition electrode located on the second conductive layer onto the substrate can cover the orthographic projection of the channel region of the silicon semiconductor layer onto the substrate.

[0173] In this example, the oxide semiconductor layer is shielded from both the top and bottom by the first and second conductive layers, and combined with the auxiliary shielding structure of the seventh conductive layer to achieve multi-layer light shielding. This multi-layered light shielding helps ensure the stability of the second-type thin-film transistor and improves high refresh rate performance and device lifespan. Similarly, using the first and seventh conductive layers (or the second conductive layer) to shield the silicon-containing semiconductor layer from both the top and bottom helps ensure the stability of the first-type thin-film transistor and improves high refresh rate performance and device lifespan.

[0174] Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0175] Figure 17 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 17As shown, the inorganic micro-light-emitting display panel may include a first type of thin-film transistor 31 and a second type of thin-film transistor 32. The first conductive layer includes a first shielding structure 211 corresponding to the first type of thin-film transistor 31 and a second shielding structure 212 corresponding to the second type of thin-film transistor 32. The orthogonal projection of the first shielding structure 211 onto the substrate 100 can cover the orthogonal projection of the channel region of the silicon-containing semiconductor layer 310 of the first type of thin-film transistor 31 onto the substrate 100; the orthogonal projection of the second shielding structure 212 onto the substrate 100 can cover the orthogonal projection of the channel region of the oxide semiconductor layer 320 of the second type of thin-film transistor 32 onto the substrate 100. The orthogonal projection of the first power electrode 251 of the first power transmission structure 25 located on the second conductive layer onto the substrate 100 can cover the orthogonal projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100. The seventh conductive layer may further include an auxiliary shielding structure 26. The auxiliary shielding structure 26 may not have an electrical connection with the first power transmission structure 25. The overlapping area of ​​the orthographic projections of the auxiliary shielding structure 26 and the first power transmission structure 25 onto the substrate 100 can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100. For example, the orthographic projections of the auxiliary shielding structure 26 and the first power transmission structure 25 onto the substrate 100 can completely overlap and cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100. Similarly, the orthographic projections of the first power electrode 251 of the auxiliary shielding structure 26 and the first power transmission structure 25 onto the substrate can be staggered, and the union of their orthographic projections onto the substrate can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100. This example, by combining the auxiliary shielding structure 26 and the first power transmission structure 25 to provide double-layer shielding for the oxide semiconductor layer 320, facilitates the rational routing of traces within the seventh conductive layer and the second conductive layer, avoids the auxiliary shielding structure and the first power transmission structure affecting the arrangement of other traces, and still ensures shielding of the channel region of the oxide semiconductor layer. In this example, the oxide semiconductor layer is shielded from both the top and bottom by the first and second conductive layers, and combined with the auxiliary shielding structure of the seventh conductive layer to achieve multi-layer light shielding. This helps to ensure the stability of the second type of thin-film transistor and improve high refresh rate performance and device lifespan. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0176] Figure 18 This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 18As shown, the inorganic micro-light-emitting display panel may include a first type of thin-film transistor 31 and a second type of thin-film transistor 32. The first type of thin-film transistor 31 has a top-gate structure, and its gate 313 is located on the side of the silicon semiconductor layer 310 away from the substrate 100. The second type of thin-film transistor 32 has a bottom-gate structure; its oxide semiconductor layer 320 is located on the side of its gate 323 away from the substrate 100. The gate 323 of the second type of thin-film transistor 32 and the gate 313 of the first type of thin-film transistor 31 may both be located in the third conductive layer. The sixth conductive layer, on the side away from the substrate 100, may be sequentially disposed with a second planarization layer 112, a second conductive layer, a third planarization layer 113, and an eighth conductive layer. The third transition electrode 243 located in the second conductive layer can be electrically connected to the second electrode 312 of the first type of thin-film transistor 31 located in the sixth conductive layer through a via formed in the second planarization layer 112. The first conductive layer includes a first shielding structure 211 corresponding to the first type of thin-film transistor 31 and a second shielding structure 212 corresponding to the second type of thin-film transistor 32. The orthographic projection of the first shielding structure 211 onto the substrate 100 can cover the orthographic projection of the channel region of the silicon-containing semiconductor layer 310 of the first type of thin-film transistor 31 onto the substrate 100; the orthographic projection of the second shielding structure 212 onto the substrate 100 can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 of the second type of thin-film transistor 32 onto the substrate 100. The orthographic projection of the first power electrode 251 of the first power transmission structure 25 located on the second conductive layer onto the substrate 100 can cover the orthographic projection of the channel region of the oxide semiconductor layer 320 onto the substrate 100. In this example, the seventh conductive layer and the first organic layer can be omitted. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0177] In some exemplary embodiments, at least one planarization layer (e.g., including a first planarization layer, a second planarization layer, and a third planarization layer) is disposed between the thin-film transistor layer and the light-emitting element of the inorganic micro-light-emitting display panel. This at least one planarization layer may include a light-absorbing layer. In some examples, the light-absorbing layer may include an organic polymer doped with at least one of carbon black, graphene, carbon nanotubes, or polymer-modified graphene. In other examples, the light-absorbing layer may include black polyimide. This example, by providing a light-absorbing layer, can absorb external light, thereby better shielding the oxide semiconductor layer and reducing the impact of light on the oxide semiconductor layer, which is beneficial for improving the stability of the second type of thin-film transistor.

[0178] In some examples, the light-absorbing layer can be a double-layer or multi-layer structure. In other examples, the light-absorbing layer can be a single layer located between the oxide semiconductor layer and the second conductive layer. In still other examples, the light-absorbing layer can be a single layer located between the second conductive layer and the light-emitting element. The double-layer or multi-layer structure of the light-absorbing layer in this example ensures effective absorption of external light, thereby better shielding the oxide semiconductor layer and reducing the impact of light on the oxide semiconductor layer, which is beneficial for improving the stability of the second type of thin-film transistor.

[0179] In the aforementioned exemplary structure of the inorganic micro-light-emitting display panel, the second planarization layer 112 can be a light-absorbing layer; alternatively, the first planarization layer 111 and the second planarization layer 112 can be light-absorbing layers; alternatively, the second planarization layer 112 and the third planarization layer 113 can be light-absorbing layers; or alternatively, the first planarization layer 111, the second planarization layer 112, and the third planarization layer 113 can be light-absorbing layers. This example, by setting a light-absorbing layer and coordinating with the first power transmission structure to shield the oxide semiconductor layer, can reduce the impact of light on the channel region of the oxide semiconductor layer, thereby improving the stability of the second type of thin-film transistor.

[0180] Figure 19 This is another partial planar schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 19 As shown, the orthographic projection of the integrated structure of the first transition electrode 241 connected to the first light-emitting element 41a in a pixel unit, the first transition electrode 241 connected to the third light-emitting element 41c, and the first transition electrode 241 connected to the second light-emitting element 41b in an adjacent pixel unit onto the substrate can be located within the orthographic projection range of the first power supply electrode 251 onto the substrate. The length of the integrated structure of the first transition electrodes 241 connected to the three light-emitting elements along the second direction D2 is less than the length of the first power supply electrode 251 along the second direction D2; for example, one end of this integrated structure along the second direction D2 can be flush with one end of the second transition electrode 242 connected to the third light-emitting element 41c along the second direction D2.

[0181] In other examples, the orthographic projections of the first transition electrode 241 and the first power supply electrode 251 onto the substrate can coincide. This allows the first transition electrode 241 and the first power supply electrode 251 to use the same mask during fabrication, which can simplify the fabrication process.

[0182] In other examples, the orthographic projections of the second transition electrode 242 and the third transition electrode 243 onto the substrate may coincide. During fabrication, the second transition electrode 242 and the third transition electrode 243 may use the same mask to simplify the process.

[0183] Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0184] Figure 20 This is another partial planar schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. Figure 21 for Figure 20 A partial planar schematic diagram of the first conductive layer in the image; Figure 22 for Figure 20 A partial planar schematic diagram of the first power transmission structure located in the second conductive layer.

[0185] In some examples, such as Figures 20 to 22 As shown, the first adapter electrode 241 connected to different light-emitting elements can be independently configured and electrically connected to the first power transmission structure 25 through different vias. The first power transmission structure 25 may include multiple first power electrodes 251, multiple first power connection lines 252 extending along a first direction D1, and multiple second power connection lines 253 extending along a second direction D2. The multiple first power electrodes 251, multiple first power connection lines 252, and multiple second power connection lines 253 can be connected to form a mesh structure. The linewidth of the second power connection line 253 may be greater than the linewidth of the first power connection line 252, and less than the minimum length of the first power electrode 251 along the first direction D1, and less than the minimum length of the first power electrode 251 along the second direction D2.

[0186] In some examples, such as Figure 21 As shown, the first shielding structure 211 and the second shielding structure 212 within the first conductive layer can be connected into a single structure, and the orthographic projection of this single structure onto the substrate can be located within the orthographic projection range of the first power electrode onto the substrate. The single structure of the first shielding structure 211 and the second shielding structure 212 can be connected to a first connecting line 213 extending along the first direction D1 and a second connecting line 214 extending along the second direction D2. This single structure, the first connecting line 213, and the second connecting line 214 can be connected into a mesh structure. The linewidth of the second connecting line 214 can be greater than the linewidth of the first connecting line 213, and less than the minimum length of the single structure of the first shielding structure 211 and the second shielding structure 212 along the first direction D1, and less than the minimum length of the single structure along the second direction D2. The morphology of the shielding structure of the first conductive layer is similar to the morphology of the first power transmission structure of the second conductive layer.

[0187] In some examples, such as Figure 20As shown, the first transition electrode 241 connected to the first light-emitting element 41a in a pixel unit and the first transition electrode 241 connected to the second light-emitting element 41b in the adjacent pixel circuit can be electrically connected to the same first power supply electrode 251; the first transition electrode 241 connected to the third light-emitting element 41c in the pixel unit is electrically connected to another first power supply electrode 251.

[0188] This example reduces the length of the first power electrode along the second direction D2, thereby reducing the footprint of the first power transmission structure while maintaining its signal transmission and shielding effects. Further details regarding the display panel in this example can be found in the description of the foregoing embodiments and will not be repeated here.

[0189] Figure 23 This is an equivalent circuit diagram of the pixel circuit of the driving circuit layer in at least one embodiment of the present disclosure. Figure 24 for Figure 23 The timing diagram of the pixel circuit shown is illustrated. In some examples, such as... Figure 23 As shown, the pixel circuit may include eight transistors (e.g., a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8) and a capacitor C1. The first transistor T1 may also be called a threshold compensation thin-film transistor; the third transistor T3 may also be called a driving thin-film transistor; the eighth transistor T8 may also be called a first control thin-film transistor; the seventh transistor T7 may also be called a second control thin-film transistor; the fifth transistor T5 may also be called a data writing thin-film transistor; the fourth transistor T4 may also be called a first reset thin-film transistor; the second transistor T2 may also be called a light-emitting control thin-film transistor; and the sixth transistor T6 may also be called a third control thin-film transistor. The first type of thin-film transistor may include the first transistor T1 to the sixth transistor T6, and the second type of thin-film transistor may include the seventh transistor T7 and the eighth transistor T8. In other examples, one or more of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be second type thin-film transistors.

[0190] In some examples, such as Figure 23As shown, the gate of the first transistor T1 is electrically connected to the first scan line GL1, the first electrode of the first transistor T1 is electrically connected to the second node N2, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The gate of the second transistor T2 is electrically connected to the light-emitting control signal line EM, the first electrode of the second transistor T2 is electrically connected to the second node N2, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the light-emitting element EL. The gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second power transmission structure VDD, and the second electrode of the third transistor T3 is electrically connected to the second node N2. The gate of the fourth transistor T4 is electrically connected to the first reset control line RST1, the first electrode of the fourth transistor T4 is electrically connected to the first reset signal line INIT1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3. The gate of the fifth transistor T5 is electrically connected to the first scan line GL1, the first electrode of the fifth transistor T5 is electrically connected to the data signal line DL, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4. The gate of the sixth transistor T6 is electrically connected to the light-emitting control signal line EM, the first electrode of the sixth transistor T6 is electrically connected to the reference signal line REF, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the seventh transistor T7 is electrically connected to the third scan line GL3, the first electrode of the seventh transistor T7 is electrically connected to the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected to the second capacitor electrode of capacitor element C1. The first capacitor electrode of capacitor element C1 is electrically connected to the first node N1. The gate of the eighth transistor T8 is electrically connected to the second scan line GL2, the first electrode of the eighth transistor T8 is electrically connected to the third node N3, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1. The first electrode of the light-emitting element EL is electrically connected to the first power line VSS, and the second electrode is electrically connected to the second electrode of the second transistor T2. The first power line VSS and the first power transmission structure can be an integrated structure. The second power transmission structure VDD can be electrically connected to the second electrode of the light-emitting element EL through the third transistor T3 and the second transistor T2. In this example, the light-emitting element EL can be a MicroLED.

[0191] In some examples, the first power delivery structure and the first power line VSS can be configured to transmit a low-level voltage, and the second power delivery structure VDD can be configured to transmit a high-level voltage. The first reset signal line INIT1 can be configured to transmit a constant first initialization voltage Vint1, and the reference signal line REF can be configured to transmit a constant reference voltage Vref.

[0192] In some examples, the first node N1 is the connection node of the gate of the third transistor T3, the first capacitor electrode of the capacitor element C1, and the second electrode of the eighth transistor T8; the second node N2 is the connection node of the second electrode of the third transistor T3, the first electrode of the first transistor T1, and the first electrode of the second transistor T2; the third node N3 is the connection node of the second electrode of the first transistor T1, the first electrode of the eighth transistor T8, and the second electrode of the fourth transistor T4; and the fourth node N4 is the connection node of the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6, and the first electrode of the seventh transistor T7.

[0193] The following reference Figure 24 right Figure 23 The working process of the pixel circuit shown is illustrated with an example.

[0194] In the first stage S1, the first reset control line RST1 transmits a high-level voltage, and the fourth transistor T4 is turned off; the first scan line GL1 transmits a high-level voltage, and both the first transistor T1 and the fifth transistor T5 are turned off; the second scan line GL2 transmits a low-level voltage, and the eighth transistor T8 is turned off; the third scan line GL3 transmits a low-level voltage, and the seventh transistor T7 is turned off; the light emission control signal line EM transmits a high-level voltage, and both the second transistor T2 and the sixth transistor T6 are turned off.

[0195] In the second stage S2 (also known as the reset stage), the first reset control line RST1 transmits a low-level voltage, and the fourth transistor T4 is turned on, writing the first initialization voltage Vint1 provided by the first reset signal line INIT1 into the third node N3. The first scan line GL1 switches from a high-level voltage to a low-level voltage. When the first scan line GL1 transmits a low-level voltage, both the first transistor T1 and the fifth transistor T5 are turned on. The first transistor T1 turns on, causing the second node N2 and the third node N3 to turn on. The fifth transistor T5 turns on, writing the data voltage provided by the data signal line DL into the fourth node N4. The second scan line GL2 switches from a low-level voltage to a high-level voltage. When the second scan line GL2 transmits a high-level voltage, the eighth transistor T8 is turned on, causing the third node N3 to turn on with the first node N1. The first node N1, through the turned-on eighth transistor T8 and the first transistor T1, turns on with the second node N2, causing the first initialization voltage Vint1 to be written into the first node N1 and the second node N2, thus initializing the first node N1 and the second node N2. The third scan line GL3 switches from a low-level voltage to a high-level voltage. When the third scan line GL3 transmits a high-level voltage, the seventh transistor T7 is turned on, connecting the fourth node N4 to the second capacitor electrode of capacitor element C1. This allows the data voltage to be transmitted to the second capacitor electrode of capacitor element C1 through the turned-on fifth transistor T5 and seventh transistor T7. The light emission control signal line EM maintains a high-level voltage transmission, while the second transistor T2 and the sixth transistor T6 are both turned off.

[0196] In the third stage S3 (also known as the data writing stage), the first reset control line RST1 transmits a high-level voltage, and the fourth transistor T4 is off; the first scan line GL1 maintains a low-level voltage, the second scan line GL2 maintains a high-level voltage, and the third scan line GL3 maintains a high-level voltage. The first transistor T1, the fifth transistor T5, the eighth transistor T8, and the seventh transistor T7 remain on. With the first transistor T1 and the eighth transistor T8 on, the first node N1 and the second node N2 are on, allowing the threshold voltage of the third transistor T3 to be written to the first node N1 through the on-state transistors T1 and T8. With the fifth transistor T5 and the seventh transistor T7 on, the data voltage can be transmitted to the capacitor C1 through the fifth transistor T5 and the seventh transistor T7, and the capacitor C1 charges the first node N1, thus connecting the data voltage to the first node N1. The light-emitting control signal line EM maintains a high-level voltage, and the second transistor T2 and the sixth transistor T6 are both off.

[0197] In the fourth stage S4 (also known as the light-emitting stage), the first reset control line RST1 transmits a high-level voltage, and the fourth transistor T4 is turned off. The first scan line GL1 switches to transmit a high-level voltage, and both the first transistor T1 and the fifth transistor T5 are turned off. The second scan line GL2 switches to transmit a low-level voltage, and the eighth transistor T8 is turned off. The third scan line GL3 switches from a high-level voltage to a low-level voltage, and the seventh transistor T7 remains in a conducting state for a period of time before turning off. The light-emitting control signal line EM switches to transmit a low-level voltage, and both the second transistor T2 and the sixth transistor T6 are turned on. In this stage, the third transistor T3 is in a conducting state, and the first node N1 simultaneously records the compensation signals for the data voltage and the threshold voltage. The drive signal output by the third transistor T3 can be provided to the second electrode of the light-emitting element EL through the sixth transistor T6. In this example, the drive signal output by the third transistor T3 is independent of the threshold voltage of the third transistor T3, which can eliminate the influence of the threshold voltage of the third transistor on the drive signal, thereby ensuring uniform display brightness and improving the display effect.

[0198] In this example, the eighth transistor T8 is a type II thin-film transistor, which reduces leakage current and prevents leakage at the first node N1, thereby ensuring a constant voltage at the first node N1 and improving circuit performance.

[0199] In this example, the seventh transistor T7 is a type II thin-film transistor, which can reduce leakage current. In the fourth stage S4, the seventh transistor T7 is turned on for a period of time and then turned off, which can increase the charge stabilization time of the capacitor element and avoid the sudden change of charge on the second capacitor electrode of the capacitor element from affecting the voltage of the first node N1. This is beneficial to maintaining the voltage of the first node N1 constant, thereby ensuring circuit performance.

[0200] The pixel circuit provided in this example can take advantage of the low leakage current of oxide thin film transistors (including the seventh transistor T7 and the eighth transistor T8) to reduce the leakage current of the first node N1, which helps to ensure the constant voltage of the first node N1; and take advantage of the high mobility of low temperature polycrystalline silicon thin film transistors (including the first transistor T1 to the sixth transistor T6) to meet the threshold voltage compensation and current drive requirements, which can further improve the display performance.

[0201] In other examples, the first terminal of the sixth transistor T6 may be electrically connected to the first reset signal line INIT1 or to the second power transmission structure VDD.

[0202] Figure 25 This is another equivalent circuit diagram of the pixel circuit of the driving circuit layer according to at least one embodiment of this disclosure. In some examples, such as Figure 25As shown, the pixel circuit in this example may include nine transistors (including first transistor T1 to ninth transistor T9) and a capacitor C1. The ninth transistor T9 may also be referred to as a second reset thin-film transistor. The first type of thin-film transistors may include: first transistor T1 to sixth transistor T6 and ninth transistor T9; the second type of thin-film transistors may include: seventh transistor T7 and eighth transistor T8.

[0203] In some examples, such as Figure 25 As shown, the gate of the ninth transistor T9 is electrically connected to the second reset control line RST2, the first electrode of the ninth transistor T9 is electrically connected to the second reset signal line INIT2, and the second electrode of the ninth transistor T9 is electrically connected to the second electrode of the light-emitting element EL. The timing of the second reset control line RST2 can be the same as that of the first reset control line RST1. Under the control of the second reset control line RST2, the ninth transistor T9 can initialize the second electrode of the light-emitting element EL using the second initialization voltage Vint2 provided by the second reset signal line INIT2. Further descriptions of the pixel circuit in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0204] Figure 26 This is another equivalent circuit diagram of the pixel circuit of the driving circuit layer according to at least one embodiment of this disclosure. In some examples, such as Figure 26 As shown, the pixel circuit of this example may include seven transistors (including first transistor T1 to sixth transistor T6 and eighth transistor T8) and a capacitor element C1. The first type of thin-film transistor may include first transistor T1 to sixth transistor T6, and the second type of thin-film transistor may include eighth transistor T8. The first capacitor electrode of capacitor element C1 is electrically connected to the first node N1, and the second capacitor electrode is electrically connected to the fourth node N4. The pixel circuit provided in this example can utilize the low leakage current advantage of oxide thin-film transistors (including the eighth transistor T8) to reduce the leakage current of the first node N1, which is beneficial to ensuring a constant voltage at the first node N1; and utilize the high mobility advantage of low-temperature polycrystalline silicon thin-film transistors (including first transistor T1 to sixth transistor T6) to meet the threshold voltage compensation and current drive requirements, which can further improve display performance. Further descriptions of the pixel circuit of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0205] based on Figure 26 The equivalent circuit diagram of the pixel circuit shown is provided. In the cross-sectional view of the aforementioned embodiment, the first type of thin film transistor 31 can be, for example, the second type of thin film transistor T2, and the second type of thin film transistor 32 can be, for example, the eighth type of transistor T8.

[0206] Figure 27This is another partial cross-sectional schematic diagram of an inorganic micro-light-emitting display panel according to at least one embodiment of the present disclosure. In some examples, such as Figure 27 As shown, the capacitor element C1 may include a first capacitor electrode C11 and a second capacitor electrode C12. The first capacitor electrode C11 may include a first sub-electrode C111 and a second sub-electrode C112. The first sub-electrode C111 may be located in the third conductive layer, and the second sub-electrode C112 may be located in the first conductive layer. The first sub-electrode C111 may be electrically connected to the second sub-electrode C112 through vias formed in the third inorganic layer 103 and the second inorganic layer 102. The second capacitor electrode C12 may be located in the first semiconductor layer and disposed in the same layer as the silicon semiconductor layer 310 of the first type of thin film transistor 31. The second capacitor electrode C12 may be electrically connected to the fifth transition electrode 245 located in the sixth conductive layer through vias formed in the third inorganic layer 103, the fourth inorganic layer 104, the fifth inorganic layer 105, the sixth inorganic layer 106, and the seventh inorganic layer 107. The fifth transition electrode 245 may be electrically connected to the sixth transition electrode 246 located in the seventh conductive layer. For example, the second capacitor electrode C12 can be electrically connected to the seventh transistor via the fifth transfer electrode 245 and the sixth transfer electrode 246, or it can be electrically connected to the fifth transistor and the sixth transistor. The orthographic projection of the second capacitor electrode C12 of the capacitor element C1 onto the substrate 100 overlaps with the orthographic projections of the first sub-electrode C111 and the second sub-electrode C112 onto the substrate 100. In this example, by setting the capacitor element to a three-layer stacked structure, the capacitance is increased several times by increasing the total effective electrode area without changing the area occupied by the capacitor element; or, under the premise of meeting the target capacitance, the area occupied by the capacitor element is greatly reduced by stacking multiple sub-electrode plates, thereby compressing the overall size of a single sub-pixel. The remaining descriptions of the display panel of this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0207] Figure 28 This is another cross-sectional structural schematic diagram of a capacitor element according to at least one embodiment of the present disclosure. In some examples, such as Figure 28As shown, the capacitor element may include a first capacitor electrode C11 and a second capacitor electrode C12. The first capacitor electrode C11 may be located, for example, in the third conductive layer. The second capacitor electrode C12 may include a third sub-electrode C121 and a fourth sub-electrode C122 electrically connected to the third sub-electrode C121. The third sub-electrode C121 may be disposed in the same layer as the silicon semiconductor layer, for example, in the first semiconductor layer, and the fourth sub-electrode C122 may be located in the sixth conductive layer. The third sub-electrode C121, the fourth sub-electrode C122, and the first capacitor electrode C11 overlap in their orthogonal projections onto the substrate. The capacitor element in this example uses a three-layer stacked structure, which can save space and reduce the impact on the arrangement of other structures. Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0208] Figure 29 This is another cross-sectional structural schematic diagram of a capacitor element according to at least one embodiment of the present disclosure. In some examples, such as Figure 29 As shown, the capacitor element may include a first capacitor electrode C11 and a second capacitor electrode C12. The first capacitor electrode C11 may include a first sub-electrode C111 and a second sub-electrode C112 electrically connected to the first sub-electrode C111; the first sub-electrode C111 may be located in a third conductive layer, and the second sub-electrode C112 may be located in a first conductive layer. The second capacitor electrode C12 may include a third sub-electrode C121 and a fourth sub-electrode C122 electrically connected to the third sub-electrode C121. The third sub-electrode C121 may be disposed in the same layer as the silicon semiconductor layer, for example, in the first semiconductor layer, and the fourth sub-electrode C122 may be located in a sixth conductive layer. The first sub-electrode C111, the second sub-electrode C112, the third sub-electrode C121, and the fourth sub-electrode C122 all overlap in their orthogonal projections onto the substrate. The capacitor element in this example employs a four-layer stacked structure, which saves space and reduces the impact on the arrangement of other structures. Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0209] Figure 30 This is another cross-sectional structural schematic diagram of a capacitor element according to at least one embodiment of the present disclosure. In some examples, such as Figure 30As shown, the capacitor element may include: a first capacitor electrode C11 and a second capacitor electrode C12. The first capacitor electrode C11 may be located in the third conductive layer. The second capacitor electrode C12 may include: a third sub-electrode C121, a fourth sub-electrode C122 electrically connected to the third sub-electrode C121, and a fifth sub-electrode C123 electrically connected to the fourth sub-electrode C122. The third sub-electrode C121 may be disposed in the same layer as the silicon semiconductor layer, for example, located in the first semiconductor layer; the fourth sub-electrode C122 may be located in the sixth conductive layer; and the fifth sub-electrode C123 may be located in the seventh conductive layer. The first capacitor electrode C11, the third sub-electrode C121, the fourth sub-electrode C122, and the fifth sub-electrode C123 all overlap in their orthogonal projections onto the substrate. The capacitor element in this example uses a four-layer stacked structure, which can save space and reduce the impact on the arrangement of other structures. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0210] Figure 31 This is another cross-sectional structural schematic diagram of a capacitor element according to at least one embodiment of the present disclosure. In some examples, such as Figure 31 As shown, the capacitor element may include: a first capacitor electrode C11 and a second capacitor electrode C12. The first capacitor electrode C11 may include a first sub-electrode C111 and a second sub-electrode C112 electrically connected to the first sub-electrode C111; the first sub-electrode C111 is located in a third conductive layer, and the second sub-electrode C112 is located in a first conductive layer. The second capacitor electrode C12 may include: a third sub-electrode C121, a fourth sub-electrode C122 electrically connected to the third sub-electrode C121, and a fifth sub-electrode C123 electrically connected to the fourth sub-electrode C122. The third sub-electrode C121 may be disposed in the same layer as the silicon semiconductor layer, for example, located in the first semiconductor layer; the fourth sub-electrode C122 may be located in a sixth conductive layer; and the fifth sub-electrode C123 may be located in a seventh conductive layer. The first sub-plate C111, the second sub-plate C112, the third sub-plate C121, the fourth sub-plate C122, and the fifth sub-plate C123 all overlap in their orthographic projections onto the substrate. The five-layer stacked structure of the capacitor element in this example saves space and reduces the impact on the arrangement of other structures. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0211] This example demonstrates how stacking multiple sub-electrodes can multiply the capacitance by increasing the total effective electrode area without changing the area occupied by the capacitor element. Alternatively, while meeting the target capacitance, stacking multiple sub-electrodes can significantly reduce the area occupied by the capacitor element, thereby compressing the overall size of a single sub-pixel and enabling the display panel to achieve a higher pixel density (PPI) and a high-resolution display panel.

[0212] Figure 32 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 32 As shown, this embodiment provides a display device 91, including an inorganic micro-light-emitting display panel 910. In other examples, the display panel included in the display device may be a QLED display panel, a Mini-LED display panel, a liquid crystal display panel (LCD), a plasma display panel, a field emission display panel, an electrowetting display panel, or an electrophoretic display panel, etc.

[0213] In some examples, the display device 91 can be a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, car window glass, shopping mall cabinet, augmented reality (AR) device, virtual reality (VR) device, or other products or components with display functions. However, this embodiment is not limited to this.

[0214] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0215] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. An inorganic micro-luminescent display panel, characterized in that, include: Substrate; A light-emitting element is located on one side of the substrate, and the light-emitting element includes a first electrode and a second electrode located near the side of the substrate. A driving circuit layer is located between the substrate and the light-emitting element; The driving circuit layer includes: First conductive layer; The second conductive layer is located on the side of the first conductive layer away from the substrate. A thin-film transistor layer is located between the first conductive layer and the second conductive layer. The thin-film transistor layer includes at least one first type of thin-film transistor and at least one second type of thin-film transistor. The first type of thin-film transistor includes: a gate, a silicon-containing semiconductor layer, a first electrode, and a second electrode. The second type of thin-film transistor includes: a gate, an oxide semiconductor layer, a first electrode, and a second electrode. A first power transmission structure is located at least in the second conductive layer and electrically connected to the first electrode of the light-emitting element, the first power transmission structure being configured to provide a low-level voltage. The second power transmission structure is electrically connected to the second electrode of the light-emitting element, and the second power transmission structure is configured to provide a high-level voltage; the second power transmission structure is disposed on the same layer as the first power transmission structure. Wherein, the orthographic projection of the first power transmission structure onto the substrate at least partially overlaps with the orthographic projection of the oxide semiconductor layer onto the substrate.

2. The display panel according to claim 1, characterized in that, The orthographic projection of the second conductive layer onto the substrate at least partially overlaps with the orthographic projection of the oxide semiconductor layer onto the substrate.

3. The display panel according to claim 2, characterized in that, The orthographic projection of the second conductive layer onto the substrate completely covers the orthographic projection of the channel region of the oxide semiconductor layer onto the substrate.

4. The display panel according to any one of claims 1 to 3, characterized in that, The first conductive layer, the second conductive layer, and the oxide semiconductor layer all have at least partial overlap in their orthogonal projections onto the substrate.

5. The display panel according to claim 1, characterized in that, The orthographic projection of the first conductive layer onto the substrate completely covers the orthographic projection of the channel region of the oxide semiconductor layer onto the substrate.

6. The display panel according to claim 3 or 5, characterized in that, The orthographic projections of the first conductive layer and the second conductive layer on the substrate completely cover the orthographic projection of the oxide semiconductor layer on the substrate.

7. The display panel according to claim 1, characterized in that, The first power transmission structure, when projected onto the substrate, at least partially covers the projection of the channel region of the oxide semiconductor layer onto the substrate.

8. The display panel according to claim 7, characterized in that, The orthographic projection of the first power transmission structure onto the substrate completely covers the orthographic projection of the channel region of the oxide semiconductor layer onto the substrate.

9. The display panel according to claim 1, characterized in that, The first conductive layer includes: a first shielding structure and a second shielding structure; the orthographic projection of the first shielding structure onto the substrate at least partially overlaps with the orthographic projection of the silicon-containing semiconductor layer onto the substrate; the orthographic projection of the second shielding structure onto the substrate at least partially overlaps with the orthographic projection of the oxide semiconductor layer onto the substrate.

10. The display panel according to claim 9, characterized in that, The first shielding structure's orthogonal projection onto the substrate covers the orthogonal projection of the silicon-containing semiconductor layer onto the substrate; the second shielding structure's orthogonal projection onto the substrate covers the orthogonal projection of the oxide semiconductor layer onto the substrate.

11. The display panel according to claim 9, characterized in that, The area of ​​the second shielding structure projected onto the substrate is not less than the area of ​​the oxide semiconductor layer projected onto the substrate.

12. The display panel according to claim 9, characterized in that, The orthographic projection of the second shielding structure onto the substrate at least partially overlaps with the orthographic projection of the first power transmission structure onto the substrate.

13. The display panel according to claim 1, characterized in that, The driving circuit layer further includes: a third conductive layer, a fourth conductive layer, and a fifth conductive layer located between the first conductive layer and the second conductive layer; The gate of the first type of thin-film transistor is located in the third conductive layer; The gate of the second type of thin-film transistor includes a first gate and a second gate, the first gate being located in the fourth conductive layer and the second gate being located in the fifth conductive layer; The oxide semiconductor layer is disposed between the first gate and the second gate.

14. The display panel according to claim 13, characterized in that, The orthogonal projection of the first gate onto the substrate covers the orthogonal projection of the channel region of the oxide semiconductor layer onto the substrate.

15. The display panel according to claim 13, characterized in that, The area of ​​the first gate as projected onto the substrate is not less than the area of ​​the channel region of the oxide semiconductor layer as projected onto the substrate.

16. The display panel according to claim 13, characterized in that, The area of ​​the first gate as projected onto the substrate is not less than the area of ​​the second gate as projected onto the substrate.

17. The display panel according to claim 13, characterized in that, The orthogonal projection of the second gate onto the substrate is located inside the orthogonal projection of the first gate onto the substrate.

18. The display panel according to claim 13, characterized in that, The orthographic projection of the second gate onto the substrate completely overlaps with the orthographic projection of the first gate onto the substrate.

19. The display panel according to claim 1, characterized in that, At least one planarization layer is disposed between the thin-film transistor layer and the light-emitting element, and the at least one planarization layer includes a light-absorbing layer.

20. The display panel according to claim 19, characterized in that, The light-absorbing layer comprises an organic polymer selected from at least one of doped carbon black, graphene, carbon nanotubes, and polymer-modified graphene.

21. The display panel according to claim 19, characterized in that, The light-absorbing layer comprises black polyimide.

22. The display panel according to any one of claims 19 to 21, characterized in that, The light-absorbing layer has a double-layer or multi-layer structure.

23. The display panel according to any one of claims 19 to 21, characterized in that, The light-absorbing layer is a single layer and is located between the oxide semiconductor layer and the second conductive layer.

24. The display panel according to any one of claims 19 to 21, characterized in that, The light-absorbing layer is a single layer and is located between the second conductive layer and the light-emitting element.

25. The display panel according to claim 1, characterized in that, The driving circuit layer further includes a capacitor element, which includes a first capacitor electrode and a second capacitor electrode. The first type of thin-film transistor includes: a driving thin-film transistor; The first electrode of the driving thin-film transistor is electrically connected to the second power transmission structure. The gate of the driving thin-film transistor is electrically connected to the first capacitor electrode; The second electrode of the driving thin-film transistor is electrically connected to the second electrode of the light-emitting element.

26. The display panel according to claim 25, characterized in that, Both the second power transmission structure and the first power transmission structure are located in the second conductive layer.

27. The display panel according to claim 25, characterized in that, The driving circuit layer further includes: a third conductive layer located between the first conductive layer and the second conductive layer, the third conductive layer being located on the side of the silicon-containing semiconductor layer away from the substrate; the first capacitor electrode being located at least in the third conductive layer, and the second capacitor electrode being disposed at least in the same layer as the silicon-containing semiconductor layer.

28. The display panel according to claim 27, characterized in that, The first capacitor electrode is located in the third conductive layer; or, the first capacitor electrode includes: a first sub-electrode and a second sub-electrode electrically connected to the first sub-electrode, the first sub-electrode being located in the third conductive layer and the second sub-electrode being located in the first conductive layer.

29. The display panel according to claim 28, characterized in that, The driving circuit layer further includes: a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer located between the third conductive layer and the second conductive layer and disposed along a direction away from the substrate; The second capacitor electrode includes a third sub-electrode and a fourth sub-electrode electrically connected to the third sub-electrode. The third sub-electrode is disposed in the same layer as the silicon semiconductor layer, and the fourth sub-electrode is located in the sixth conductive layer.

30. The display panel according to claim 29, characterized in that, The second capacitor electrode further includes a fifth sub-electrode electrically connected to the fourth sub-electrode; the fifth sub-electrode is located in the seventh conductive layer.

31. The display panel according to claim 25, characterized in that, The second type of thin-film transistor includes: a first control thin-film transistor; the gate of the driving thin-film transistor and the first capacitor electrode are both electrically connected to the first electrode or the second electrode of the first control thin-film transistor.

32. The display panel according to claim 31, characterized in that, The driving circuit layer further includes: a data signal line; wherein, the first type of thin film transistor further includes: a data writing thin film transistor; the first electrode of the data writing thin film transistor is electrically connected to the data signal line; the second electrode of the data writing thin film transistor is electrically connected to the second capacitor electrode.

33. The display panel according to claim 32, characterized in that, The second type of thin-film transistor further includes: a second control thin-film transistor, wherein the first electrode of the second control thin-film transistor is electrically connected to the second electrode of the data writing transistor, and the second electrode of the second control thin-film transistor is electrically connected to the second capacitor electrode.

34. The display panel according to claim 25, characterized in that, The driving circuit layer further includes: a first reset control line and a first reset signal line; the second type of thin-film transistor includes: a first control thin-film transistor; The first type of thin-film transistor further includes: a first reset thin-film transistor; the gate of the first reset thin-film transistor is electrically connected to the first reset control line; the first electrode of the first reset thin-film transistor is electrically connected to the first reset signal line; the second electrode of the first reset thin-film transistor is electrically connected to the first electrode of the first control thin-film transistor, and the second electrode of the first control thin-film transistor is electrically connected to the gate of the driving thin-film transistor.

35. The display panel according to claim 25, characterized in that, The driving circuit layer further includes: a light emission control signal line; The first type of thin-film transistor further includes: a light-emitting control thin-film transistor; The first electrode of the light-emitting control thin-film transistor is electrically connected to the second electrode of the driving thin-film transistor; The second electrode of the light-emitting control thin-film transistor is electrically connected to the second electrode of the light-emitting element; The gate of the light-emitting control thin-film transistor is electrically connected to the light-emitting control signal line.

36. The display panel according to claim 35, characterized in that, The first type of thin-film transistor further includes: a third control thin-film transistor, wherein the gate of the third control thin-film transistor is electrically connected to the light-emitting control signal line, and the first electrode or the second electrode of the third control thin-film transistor is electrically connected to the second capacitor electrode.

37. The display panel according to claim 1, characterized in that, The first power transmission structure includes: a plurality of first power electrodes, a plurality of first power connection lines extending along a first direction, and a plurality of second power connection lines extending along a second direction. The plurality of first power electrodes, the plurality of first power connection lines, and the plurality of second power connection lines are connected to form a mesh structure. The orthographic projection of the first power electrodes on the substrate at least partially overlaps with the orthographic projection of the oxide semiconductor layer on the substrate. The first direction and the second direction are parallel to the plane of the substrate, and the first direction and the second direction intersect.

38. The display panel according to claim 1, characterized in that, The driving circuit layer further includes: an auxiliary shielding structure located on the side of the first power transmission structure near the thin film transistor layer, the overlapping area of ​​the auxiliary shielding structure and the first power transmission structure in the orthographic projection of the substrate, and the channel region of the oxide semiconductor layer covering the orthographic projection of the substrate.

39. The display panel according to claim 38, characterized in that, The auxiliary shielding structure is electrically connected to the first power transmission structure.

40. The display panel according to claim 1, characterized in that, The driving circuit layer further includes: an auxiliary shielding structure located on the side of the first power transmission structure near the thin film transistor layer; the union region of the auxiliary shielding structure and the first power transmission structure on the substrate covers the orthogonal projection of the channel region of the oxide semiconductor layer on the substrate.

41. The display panel according to any one of claims 38 to 40, characterized in that, The driving circuit layer further includes: a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer disposed between the first conductive layer and the second conductive layer and along a direction away from the substrate. The auxiliary shielding structure is located in the seventh conductive layer, and the first power transmission structure is located in the second conductive layer.

42. The display panel according to claim 1, characterized in that, The driving circuit layer further includes an eighth conductive layer located on the side of the second conductive layer away from the substrate. The eighth conductive layer includes a first transfer electrode and a second transfer electrode. The first electrode of the light-emitting element is electrically connected to the first power transmission structure through the first transfer electrode, and the second electrode of the light-emitting element is electrically connected to the second power transmission structure through the second transfer electrode.

43. The display panel according to claim 42, characterized in that, The material of the eighth conductive layer includes a transparent conductive material.

44. The display panel according to claim 1, characterized in that, The oxide semiconductor layer has a double-layer or multi-layer stacked structure.

45. The display panel according to claim 44, characterized in that, The oxide semiconductor layer has a double-layer stacked structure, and the density of the layer closer to the substrate is lower than that of the layer farther away from the substrate.

46. ​​The display panel according to claim 44, characterized in that, The oxide semiconductor layer has a double-layer stacked structure, with the layer closer to the substrate having a greater thickness than the layer farther from the substrate.

47. The display panel according to claim 46, characterized in that, The thickness of the layer closest to the substrate is 1 to 3 times the thickness of the layer furthest from the substrate.

48. The display panel according to claim 47, characterized in that, The thickness of the layer closest to the substrate is 1.5 to 2 times the thickness of the layer furthest from the substrate.

49. The display panel according to claim 1, characterized in that, The thickness of the oxide semiconductor layer ranges from 30 nanometers to 60 nanometers.

50. The display panel according to claim 49, characterized in that, The thickness of the oxide semiconductor layer ranges from 30 nanometers to 60 nanometers.

51. The display panel according to claim 1, characterized in that, The thickness of the silicon-containing semiconductor layer ranges from 30 nanometers to 65 nanometers.

52. The display panel according to claim 1, characterized in that, The thickness of the first conductive layer ranges from 45 nanometers to 150 nanometers.

53. The display panel according to claim 1, characterized in that, The second conductive layer is a double-layer or multi-layer stacked structure.

54. The display panel according to claim 53, characterized in that, The second conductive layer is a stacked structure of titanium (Ti), aluminum (Al), and titanium (Ti).

55. The display panel according to claim 54, characterized in that, The thickness of the titanium layer ranges from 50 nanometers to 60 nanometers; the thickness of the aluminum layer ranges from 500 nanometers to 700 nanometers.

56. A display device, characterized in that, Including the inorganic micro-luminescent display panel as described in any one of claims 1 to 55.

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