Method and apparatus for signaling displacement component block size at each level of detail

Abstract

According to one aspect of the disclosure, a method of decoding by a decoder is provided. For each hierarchical subdivision level of a plurality of hierarchical subdivision levels, the following operations can be performed. The method can include decoding, by a processor, a first syntax element to determine a sub-block size associated with the hierarchical subdivision level. The method can include determining, by the processor, a number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size. The method can include decoding, by the processor, the hierarchical subdivision level based on the number of sub-blocks.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. Provisional Application No. 63 / 625,180, filed January 25, 2024, entitled “DISPLACEMENT COMPONENT BLOCK SIZESIGNALING PER LOD,” the entire contents of which are incorporated herein by reference. Background Technology

[0002] Embodiments of this disclosure relate to dynamic mesh encoding and decoding.

[0003] A mesh consists of a set of vertices, edges, and faces that define the shape or topology of a polyhedral object. These faces typically include triangles. Each vertex in three-dimensional (3D) space is associated with a geometric location, as well as connectivity and attributes (e.g., color, reflectivity, intensity, classification, etc.) or mapping and texture information. To effectively compress dynamic mesh data, the mesh's geometry can be compressed first, and then the corresponding connectivity, attributes, and / or mappings can be compressed based on the geometry using dynamic mesh coding techniques (e.g., versatile dynamic mesh coding (V-DMC)). Summary of the Invention

[0004] According to one aspect of this disclosure, a method for decoding by a decoder is provided. For each of a plurality of hierarchical subdivision levels, the following operations may be performed: The method may include decoding a first syntax element by a processor to determine the sub-block size associated with the hierarchical subdivision level. The method may include determining the number of sub-blocks associated with the hierarchical subdivision level by the processor based on the sub-block size. The method may include decoding the hierarchical subdivision level by the processor based on the number of sub-blocks.

[0005] According to another aspect of this disclosure, a decoder is provided. The decoder may include a processor and a memory storing instructions. The memory stores instructions that, when executed by the processor, cause the processor to perform the following operations for each of a plurality of hierarchical subdivision levels: The memory stores instructions that, when executed by the processor, cause the processor to decode a first syntax element to determine a sub-block size associated with the hierarchical subdivision level; the memory stores instructions that, when executed by the processor, cause the processor to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size; and the memory stores instructions that, when executed by the processor, cause the processor to decode the hierarchical subdivision level based on the number of sub-blocks.

[0006] According to another aspect of this disclosure, an apparatus for decoding is provided. The apparatus for decoding may include a processor and a memory storing instructions. The memory stores instructions that, when executed by the processor, cause the processor to perform the following operations for each of a plurality of hierarchical subdivision levels: The memory stores instructions that, when executed by the processor, cause the processor to decode a first syntax element to determine a sub-block size associated with the hierarchical subdivision level; the memory stores instructions that, when executed by the processor, cause the processor to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size; and the memory stores instructions that, when executed by the processor, cause the processor to decode the hierarchical subdivision level based on the number of sub-blocks.

[0007] According to another aspect of this disclosure, a non-transitory computer-readable medium is provided that stores instructions for a processor of a decoder. When executed by the decoder's processor, the instructions cause the decoder's processor to perform the following operations for each of a plurality of hierarchical subdivision levels. When executed by the decoder's processor, the instructions cause the decoder's processor to decode a first syntax element to determine a sub-block size associated with the hierarchical subdivision level. When executed by the decoder's processor, the instructions cause the decoder's processor to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size. While being executed by the decoder's processor, the instructions cause the decoder's processor to decode the hierarchical subdivision level based on the number of sub-blocks.

[0008] According to one aspect of this disclosure, a method for encoding by an encoder is provided. For each of a plurality of hierarchical subdivision levels, the following operations may be performed: The method may include encoding a first syntax element by a processor to indicate the size of a sub-block associated with the hierarchical subdivision level. The method may include determining, by the processor, the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size. The method may include encoding the hierarchical subdivision level by the processor based on the number of sub-blocks.

[0009] According to another aspect of this disclosure, an encoder is provided. The encoder may include a processor and a memory storing instructions. The memory stores instructions that, when executed by the processor, cause the processor to perform the following operations for each of a plurality of hierarchical subdivision levels. The memory stores instructions that, when executed by the processor, cause the processor to encode a first syntax element to indicate a sub-block size associated with the hierarchical subdivision level. The memory stores instructions that, when executed by the processor, cause the processor to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size. The memory stores instructions that, when executed by the processor, cause the processor to encode the hierarchical subdivision level based on the number of sub-blocks.

[0010] According to another aspect of this disclosure, an apparatus for encoding is provided. The apparatus for encoding may include a processor and a memory storing instructions. The memory stores instructions that, when executed by the processor, cause the processor to perform the following operations for each of a plurality of hierarchical subdivision levels. The memory stores instructions that, when executed by the processor, cause the processor to encode a first syntax element to indicate a sub-block size associated with the hierarchical subdivision level. The memory stores instructions that, when executed by the processor, cause the processor to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size. The memory stores instructions that, when executed by the processor, cause the processor to encode the hierarchical subdivision level based on the number of sub-blocks.

[0011] According to another aspect of this disclosure, a non-transitory computer-readable medium is provided, storing instructions for a processor of an encoder. When executed by the encoder's processor, the instructions cause the encoder's processor to perform the following operations for each of a plurality of subdivision levels. When executed by the encoder's processor, the instructions cause the encoder's processor to encode a first syntax element to determine a sub-block size associated with the subdivision level. When executed by the encoder's processor, the instructions cause the encoder's processor to determine the number of sub-blocks associated with the subdivision level based on the sub-block size. When executed by the encoder's processor, the instructions cause the encoder's processor to encode the subdivision level based on the number of sub-blocks.

[0012] According to another aspect of this disclosure, a non-transitory computer-readable medium for storing a bitstream is provided. The bitstream can be generated using one or more of the operations described herein.

[0013] These illustrative embodiments are mentioned not to limit or restrict this disclosure, but to provide examples to aid in understanding it. Further embodiments are described in the detailed description, and further description is provided therein. Attached Figure Description

[0014] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0015] Figure 1 A block diagram of an exemplary encoding system according to some embodiments of the present disclosure is shown.

[0016] Figure 2 A block diagram of an exemplary decoding system according to some embodiments of the present disclosure is shown.

[0017] Figure 3Some embodiments according to this disclosure are shown. Figure 1 A detailed block diagram of an exemplary encoder in an encoding system.

[0018] Figure 4 Some embodiments according to this disclosure are shown. Figure 2 A detailed block diagram of an exemplary decoder in a decoding system.

[0019] Figure 5 A diagram illustrating a grid data structure according to some embodiments of the present disclosure is shown.

[0020] Figure 6 A diagram of a mesh having four vertices and three triangular faces according to some embodiments of the present disclosure is shown.

[0021] Figure 7 A connectivity diagram of a mesh having four vertices and three triangular faces is shown according to some embodiments of the present disclosure.

[0022] Figure 8 A data structure diagram of a parameterized mesh according to some embodiments of the present disclosure is shown.

[0023] Figure 9 A diagram of a mesh having four vertices, three triangular faces, and corresponding attribute mappings according to some embodiments of the present disclosure is shown.

[0024] Figure 10 A diagram showing mesh face orientation based on vertex index order according to some embodiments of the present disclosure is illustrated.

[0025] Figure 11 A block diagram of a geometry encoding process implemented by an encoder according to some embodiments of the present disclosure is shown.

[0026] Figures 12A-12C The present disclosure illustrates a mesh subdivision and mesh displacement approximation process implemented by an encoder according to some embodiments of the present disclosure.

[0027] Figure 13 A diagram showing the decomposition of displacement components in a local coordinate system according to some embodiments of the present disclosure is illustrated.

[0028] Figure 14 Detailed diagrams of a parametric mesh encoding process according to some embodiments of the present disclosure are shown.

[0029] Figure 15 An exemplary decoding process according to some embodiments of this disclosure is shown.

[0030] Figure 16 A flowchart illustrating an exemplary method for video decoding according to some embodiments of the present disclosure is shown.

[0031] Figure 17 A flowchart illustrating an exemplary method of video encoding according to some embodiments of the present disclosure is shown.

[0032] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0033] While some configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0034] It should be noted that when the specification refers to "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," or "certain embodiments," it indicates that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment must include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0035] Generally, terms can be understood, at least in part, from their usage in context. For example, the term "one or more," as used herein, can be used, at least in part, to describe any feature, structure, or characteristic in a singular sense, or a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a" or "the" can be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0036] Various aspects of a dynamic mesh coding / decoding system will now be described with reference to various apparatuses and methods. These apparatuses and methods will be described in the following detailed description and illustrated in the accompanying drawings by various modules, components, circuits, steps, operations, processes, algorithms, etc. (collectively, "elements"). These elements can be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether these elements are implemented as hardware, firmware, or software depends on the specific application and design constraints imposed on the overall system. The techniques described herein can be used in a variety of dynamic mesh coding / decoding applications. As described herein, dynamic mesh coding / decoding involves both encoding and decoding dynamic meshes.

[0037] V-DMC is widely used in virtual reality / augmented reality (VR / AR), telecommunications, autonomous vehicles, and other applications in entertainment and industrial settings, such as game asset management, spatial media, architectural design modeling, and structural analysis. The Moving Picture Experts Group (MPEG) has released the first draft of the V-DMC international standard community, and the Alliance for Open Media (AOM) is also developing a mesh codec standard.

[0038] However, the existing V-DMC standard is not well-suited for a wide range of dynamic mesh inputs across many different applications. For example, in addition to the representation of levels (or coefficients in some cases), other information used in V-DMC (e.g., parameters) can also be encoded as syntax elements in the bitstream. Since V-DMC organizes the set of points into different levels by dividing it into different segments (e.g., sequences, slices, etc.) associated with different attributes (e.g., geometric information, attribute information, etc.), the parameter set is also arranged at different levels (e.g., sequence level, attribute level, slice level, etc.), for example, in different headers. Furthermore, parsing some syntax elements in V-DMC may require multiple condition checks, which further increases the complexity of organizing and parsing the representation of syntax elements.

[0039] To improve the flexibility and versatility of dynamic mesh coding and decoding, this disclosure provides various novel schemes for the representation and organization of syntax elements that are compatible with any suitable V-DMC standard, including but not limited to the Alliance for Open Media (AOM) Volumetric Visual Media (VVM) standard and the MPEG V-DMC standard.

[0040] Figure 1 A block diagram of an exemplary encoding system 100 according to some embodiments of the present disclosure is shown. Figure 2 A block diagram of an exemplary decoding system 200 according to some embodiments of the present disclosure is shown. Each system 100 or 200 can be applied to or integrated into a variety of systems and devices capable of data processing, such as computers and wireless communication devices. For example, system 100 or 200 can be all or part of a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with data processing capabilities. Figure 1 and Figure 2As shown, system 100 or 200 may include processor 102, memory 104, and interface 106. These components are shown as being connected to each other via a bus, but other connection types are also permitted. It should be understood that system 100 or 200 may include any other suitable components for performing the functions described herein.

[0041] Processor 102 may include a microprocessor, such as a graphics processing unit (GPU), image signal processor (ISP), central processing unit (CPU), digital signal processor (DSP), tensor processing unit (TPU), vision processing unit (VPU), neural processing unit (NPU), synergistic processing unit (SPU), physics processing unit (PPU), microcontroller unit (MCU), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), state machine, gated logic, discrete hardware circuitry, and other suitable hardware configured to perform the various functions described throughout this disclosure. Figure 1 and Figure 2 Only one processor is shown, but it should be understood that multiple processors may be included. Processor 102 may be a hardware device having one or more processing cores. Processor 102 can execute software. Software should be interpreted broadly to mean instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, application programs, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc., regardless of whether it is referred to as software, firmware, middleware, microcode, hardware description languages, or others. Software may include computer instructions written in interpreted languages, compiled languages, or machine code. Other technologies used to indicate hardware are also permitted under the broad category of software.

[0042] Memory 104 can broadly include both memory (also known as main / system memory) and storage devices (also known as auxiliary memory). For example, memory 104 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferro-electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage devices, hard disk drive (HDD) (e.g., disk storage devices or other magnetic storage devices), flash memory drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 102. More broadly, memory 104 can be embodied in any computer-readable medium (such as non-transitory computer-readable media). Although in Figure 1 and Figure 2 Only one memory is shown, but it should be understood that multiple memories may be included.

[0043] Interface 106 can broadly include data interfaces and communication interfaces, the communication interface being configured to receive and transmit signals during the reception and transmission of information with other external network elements. For example, interface 106 may include input / output (I / O) devices and wired or wireless transceivers. Although in Figure 1 and Figure 2 Only one memory is shown, but it should be understood that it may include multiple interfaces.

[0044] Processor 102, memory 104, and interface 106 may be implemented in various forms within system 100 or 200 for performing dynamic mesh encoding / decoding functions. In some embodiments, processor 102, memory 104, and interface 106 of system 100 or 200 are implemented (e.g., integrated) on one or more system-on-chip (SoCs). In one example, processor 102, memory 104, and interface 106 may be integrated on an application processor (AP) SoC that handles application processing within an operating system (OS) environment, including running dynamic mesh encoding and decoding applications. In another example, processor 102, memory 104, and interface 106 may be integrated on a dedicated processor chip for dynamic mesh encoding / decoding, such as a GPU or ISP chip dedicated to graphics processing in a real-time operating system (RTOS).

[0045] like Figure 1 As shown, in the encoding system 100, the processor 102 may include one or more modules, such as the encoder 101. Although Figure 1 Encoder 101 is shown within a processor 102; however, it should be understood that encoder 101 may include one or more submodules that may be implemented on different processors, either close to or far from each other. Encoder 101 (and any corresponding submodules or subunits) may be a hardware unit (e.g., a portion of an integrated circuit) of processor 102, designed for use with other components or software units implemented by processor 102 by executing at least a portion of a program (i.e., instructions). The instructions of the program may be stored on a computer-readable medium such as memory 104, and when executed by processor 102, may perform processes having one or more functions related to dynamic lattice coding, such as voxelization, transformation, quantization, arithmetic coding, etc., as described in detail below.

[0046] Similarly, such as Figure 2 As shown, in the decoding system 200, the processor 102 may include one or more modules, such as the decoder 201. Although Figure 2Decoder 201 is shown within a processor 102; however, it should be understood that decoder 201 may include one or more submodules that may be implemented on different processors, either close to or far from each other. Decoder 201 (and any corresponding submodules or subunits) may be a hardware unit of processor 102 (e.g., a portion of an integrated circuit) designed for use with other components or software units implemented by processor 102 by executing at least a portion of a program (i.e., instructions). The instructions of the program may be stored on a computer-readable medium such as memory 104, and when executed by processor 102, it may perform processes having one or more functions related to dynamic mesh decoding, such as arithmetic decoding, inverse quantization, inverse transform, reconstruction, synthesis, etc., as described in detail below.

[0047] Figure 3 Some embodiments according to this disclosure are shown. Figure 1 A detailed block diagram of an exemplary encoder 101 in the encoding system 100. (See attached diagram.) Figure 3 As shown, encoder 101 may include: coordinate transformation module 302, voxelization module 304, geometric analysis module 306, and arithmetic encoding module 308, which together are configured to encode the positions associated with points on the dynamic mesh into a geometric bitstream (i.e., geometric encoding). Figure 3 As shown, encoder 101 may further include a color transformation module 310, an attribute transformation module 312, a quantization module 314, and an arithmetic encoding module 316, which together are configured to encode attributes associated with vertices or faces of the dynamic mesh into an attribute bitstream (i.e., attribute encoding). It should be understood that... Figure 3 Each element shown is presented independently to represent a distinct feature function within the dynamic mesh encoder, and does not imply that each component is formed by a separate hardware or software configuration unit. That is, for ease of illustration, each included element is listed as an element; at least two elements can be combined to form a single element, or an element can be divided into multiple elements to perform its function. It should also be understood that some elements are not essential for performing the functions described in this disclosure, but may be optional elements used to improve performance. It should also be understood that these elements can be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether these elements are implemented as hardware, firmware, or software depends on the specific application and design constraints imposed on the encoder 101. It should also be further understood that... Figure 3 The modules shown are for illustrative purposes only, and in some examples, different modules may be included in encoder 101 for dynamic mesh encoding.

[0048] like Figure 3As shown, the geometric positions and properties associated with the vertices and faces of a mesh can be encoded individually. The mesh's geometric information can be a set of vertices, the positions of which are... of, , where K is the number of vertices in the mesh, and the attribute is , Where D is the number of attributes for each vertex. In some embodiments, attribute encoding depends on the decoded geometric information. Therefore, the positions of the mesh vertices can be encoded first. Since geometric positions can be represented by floating-point numbers in the original coordinate system, coordinate transformation module 302 and voxelization module 304 can be configured to perform coordinate transformation, followed by voxelization for quantization and removal of duplicate vertices. The process of position quantization, duplicate vertex removal, and attribute assignment to the remaining vertices is called voxelization. The voxelized mesh can be represented, for example, using a list structure in a lossless manner. Geometric analysis module 306 can be configured to perform geometric analysis using, for example, a predictive vertex position encoding scheme. Arithmetic encoding module 308 can be configured to arithmetically encode the resulting structure from geometric analysis module 306 into the geometric bitstream.

[0049] In some embodiments, the geometry analysis module 306 is configured to perform geometry analysis using a predictive vertex position encoding scheme. Under the predictive vertex position encoding scheme, the geometric information (x, y, z) of a location can be represented by the defined predictive vertex position encoding structure. Since mesh vertices can be duplicated, multiple mesh vertices can be mapped to the same sub-cube of size 1 (i.e., the same voxel). To handle this, for each sub-cube of size 1, the corresponding properties of the voxels are averaged.

[0050] Return to reference Figure 3 Regarding attribute encoding, optionally, the color transformation module 310 can be configured to convert the red / green / blue (RGB) color attribute of each point to a YCbCr color attribute when the attribute includes color. The attribute transformation module 312 can be configured to perform attribute transformations based on results from the geometry analysis module 306 (e.g., using a predictive vertex position scheme), including but not limited to hybrid video coding. Optionally, the quantization module 314 can be configured to quantize the transformation coefficients of the attributes from the attribute transformation module 312 to generate a quantization level of the attribute associated with each point to reduce dynamic range. The arithmetic encoding module 316 can be configured to arithmetically encode the resulting transformation coefficients or their quantization levels of the attributes associated with each grid vertex into the attribute bitstream.

[0051] Figure 4 Some embodiments according to this disclosure are shown. Figure 2 A detailed block diagram of an exemplary decoder 201 in the decoding system 200. (See attached diagram.) Figure 4 As shown, decoder 201 may include an arithmetic decoding module 402, a geometry synthesis module 404, a reconstruction module 406, and a coordinate inverse transformation module 408, which together are configured to decode the positions associated with the vertices of the dynamic mesh from the geometry bitstream (i.e., geometry decoding). Figure 4 As shown, the decoder 201 may further include an arithmetic decoding module 410, an inverse quantization module 412, an inverse attribute transformation module 414, and an inverse color transformation module 416, which together are configured to decode attributes associated with vertices or faces of the dynamic mesh from the attribute bitstream (i.e., attribute decoding). It should be understood that... Figure 4 Each element shown is presented independently to represent a distinct feature function within the dynamic mesh decoder, and does not imply that each component is formed by a separate hardware or software configuration unit. That is, for ease of illustration, each included element is listed as an element; at least two elements can be combined to form a single element, or an element can be divided into multiple elements to perform its function. It should also be understood that some elements are not essential for performing the functions described in this disclosure, but may be optional elements used to improve performance. It should also be understood that these elements can be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether these elements are implemented as hardware, firmware, or software depends on the specific application and design constraints imposed on the decoder 201. It should also be further understood that... Figure 4 The modules shown are for illustrative purposes only, and in some examples, different modules may be included in decoder 201 for dynamic mesh decoding.

[0052] When an encoded dynamic mesh bitstream (e.g., a geometry bitstream or an attribute bitstream) is input from a dynamic mesh encoder (e.g., encoder 101), the input bitstream can be decoded by decoder 201 in a process reversed from that of the dynamic mesh encoder. Therefore, for ease of description, the decoding details described above regarding encoding can be skipped. Arithmetic decoding modules 402 and 410 can be configured to decode the geometry bitstream and the attribute bitstream, respectively, to obtain various information encoded into the bitstream. For example, arithmetic decoding module 410 can decode the attribute bitstream to obtain attribute information associated with each vertex or face, such as the quantization level or coefficient of the attribute associated with each vertex or face. Optionally, dequantization module 412 can be configured to dequantize the quantization level of the attribute associated with each vertex or face to obtain the coefficient of the attribute associated with each vertex or face. In addition to attribute information, arithmetic decoding module 410 can parse the bitstream to obtain various other information (e.g., in the form of syntax elements), such as syntax elements indicating the attribute encoding order followed by the vertex list, connectivity information, and mapping information of the dynamic mesh encoding.

[0053] The inverse attribute transformation module 414 can be configured to perform inverse attribute transformations, such as an inverse mapping from a 2D texture image to a 3D mesh model, to transform data from the projection domain (e.g., the texture image) back to the attribute domain (e.g., brightness and / or chromaticity information of color attributes). Optionally, the inverse color transformation module 416 can be configured to convert YCbCr color attributes to RGB color attributes.

[0054] Regarding geometric decoding, the geometric synthesis module 404, reconstruction module 406, and coordinate inverse transformation module 408 of decoder 201 can be configured to perform the inverse operations of the geometric analysis module 306, voxelization module 304, and coordinate transformation module 302 of encoder 101, respectively.

[0055] Consistent with the scope of this disclosure, encoder 101 and decoder 201 may be configured to employ various novel schemes of syntax element representation and organization as disclosed herein to improve the flexibility and versatility of dynamic mesh encoding and decoding.

[0056] exist Figure 5 The example shown in the grid data structure 500 depicts the geometric information of a grid frame. Figure 6 Figure 600 shows a mesh having four vertices and three triangular faces according to some embodiments of the present disclosure. Figure 7 A connectivity diagram 700 of a mesh having four vertices and three triangular faces is shown according to some embodiments of the present disclosure.

[0057] refer to Figure 6 One example of a surface is represented by a mesh with a color attribute per vertex, four vertices, and three faces. The location in space is described by X, Y, Z coordinates and the color attributes red (R), green (G), and blue (B) for each vertex. For example... Figure 6 As shown, each face is defined by the indices of the three vertices that form a triangle. Figure 7 The diagram shows the connectivity of these features.

[0058] Figure 8 A data structure diagram 800 of a parameterized mesh according to some embodiments of the present disclosure is shown. Figure 9 Figure 900 illustrates a mesh with four vertices and three triangular faces, and the corresponding attribute mapping, according to some embodiments of the present disclosure.

[0059] Figure 9 The image depicts an example of a surface, consisting of four vertices and three faces, with property mapping properties (e.g., Figure 8The grid representation is used. The position of each vertex in space is described by X, Y, and Z coordinates. (U, V) represent the attribute coordinates in the 2D texture vertex map. Each face is defined by three pairs of vertex indices, the texture vertex coordinates that form a triangle in 3D space, and the triangle in the 2D texture map.

[0060] Figure 10 A diagram illustrating a mesh face orientation 1000 based on vertex index order according to some embodiments of this disclosure is shown. Reference Figure 10 The orientation of a face is determined using a right-handed coordinate system. A face consists of three vertices belonging to three edges, and the three vertex indices describe each face. A manifold mesh is a mesh in which one edge belongs to at most two different faces, such as... Figure 10 As shown on the left. On the other hand, a non-manifold mesh is one where an edge belongs to two or more meshes, such as... Figure 10 As shown on the right.

[0061] Some existing technologies employ a two-stage coding process to encode geometric information. First, the geometry is extracted to create a base mesh encoded using a general geometric coding method (e.g., an "edgebreaker"). Then, the base mesh is subdivided layer by layer, and the differences between the subdivision points and approximations of the original mesh are stored as geometric displacement components. These displacement components are then packed into a two-dimensional (2D) image and encoded using lossless video coding. The following section combines... Figure 11 A high-level diagram describing the two-stage geometric coding process 1100.

[0062] refer to Figure 11 The encoder can receive static or dynamic meshes from video, images, frames, scenes, etc. At 1102, the encoder can perform preprocessing to generate a base mesh geometry and mesh displacement. The base mesh geometry may include an extracted base mesh with fewer points than the initially received static or dynamic mesh. The extracted base mesh can be input to a mesh encoder 1104, which implements, for example, an edgebreaker encoding process. The mesh encoder can perform geometric encoding on the extracted base mesh. On the other hand, the mesh displacement can be input to a displacement packing component 1106. The displacement packing component 1106 can perform the operation of packing displacement coefficients into a 2D image, as will be described below. Figures 12A-12C As described, displacement packing information can be input to a displacement-specific video encoder 1108, such as an HEVC component. The mesh encoder 1104 and the video encoder 1108 can input their respective information to a multiplexer (MUX) 1110, which encodes the information into a bitstream.

[0063] Figures 12A-12C Mesh subdivision and mesh displacement approximation processes 1200, 1225, 1250, implemented by the displacement packing component of an encoder according to some embodiments of the present disclosure, are illustrated. Figure 13 A diagram showing the displacement component decomposition 1300 in a local coordinate system according to some embodiments of the present disclosure is illustrated. Figures 12A-12C The process is illustrated for one face in the base mesh.

[0064] refer to Figure 12A PB1, PB2 and PB3 represent the basic grid points. Figure 12B In the code, PS1, PS2, and PS3 represent subdivision points. PSD1, PSD2, and PSD3 represent subdivision displacement points, such as... Figure 12C As shown. The subdivision point PS1 can be calculated as the midpoint between points PB1 and PB2. This process can then be repeated recursively. (Reference) Figure 12C and Figure 13 Each vector of PS1 and PSD1 is described as having three components in the directions of normal, tangent, and double tangent, which are further mapped to a color plane (e.g., the Y, U, and V components in the YUV 444 color space).

[0065] Figure 14 Detailed diagrams of a parametric mesh encoding process 1400 according to some embodiments of the present disclosure are shown. Reference Figure 14 The base mesh frame is quantized by quantization component 1402 and encoded using static mesh encoder 1404. This process is independent of the type of mesh encoding scheme used to compress the base mesh.

[0066] Mesh displacement can be input to the displacement update component 1408, which updates the displacement based on information received from the static mesh decoder 1406. For example, this information can be related to the extracted base mesh. Once updated, the mesh displacement can be input to the wavelet transform component 1410. For example, the mesh displacement can be processed using a layered wavelet transform (or other type of transform) that recursively applies thinning layers to the reconstructed base mesh. The wavelet transform coefficients are then quantized by the wavelet coefficient quantization component 1412. The image packing component 1414 can then pack the quantized wavelet transform coefficients into a 2D image / video compressed using a conventional image / video encoder 1416.

[0067] The reconstructed version of the wavelet transform coefficients can be generated by the image unpacking component 1418, which applies image unpacking. The wavelet coefficient inverse quantization component 1420 performs inverse quantization on the reconstructed wavelet coefficient image / video generated during the image / video decoding process. The inverse wavelet transform is then applied to the reconstructed wavelet by the inverse wavelet transform component 1422 to calculate the reconstructed displacement. The reconstructed wavelet transform coefficients, along with the inverse quantization of the base grid from the base grid inverse quantization component 1436, are input to the reconstructed grid component 1424. Once the grid is reconstructed, it can be input to the attribute transfer component 1426 along with a pre-built attribute map. Once the attributes are transferred to the reconstructed grid, the attribute image filling component 1428 applies image filling along with the attribute transfer to the reconstructed grid. Color space conversion 1430 performs color space conversion on the attribute map. The attribute video encoding component 1432 then encodes the attribute map. The encoded attribute map, patch information, and the geometrically encoded base grid can be input to the multiplexer 1434 for input to the bitstream.

[0068] Wavelet transform coefficients are calculated in floating-point format and can be positive and / or negative. In the prior art, the coefficients are first converted to positive values ​​using expression (1) and mapped to a given positioning depth to generate a 2D image.

[0069] c'(i) = 2^[bit_depth-1] + [c(i) 2^bit_depth] / [c_max - c_min] (1), Where c'(i) is the integerized displacement coefficient value, c(i) is the current displacement coefficient, c_max is the maximum displacement coefficient value, c_min is the minimum displacement coefficient value, and bit_depth is a value that defines the fixed number of layers used for image encoding.

[0070] The displacement components are transformed using a lifting transform, and their corresponding values ​​are quantized according to the value of `vmc_transform_lifting_quantization_parameters[ltpIndex][i]`, where `ltpIndex` defines the application level (e.g., 0-sequence; 1-frame; 2-patch), and `i` represents the corresponding displacement component (x, y, z for the canonical coordinate system, n, t, bt for the local coordinate system). Examples of syntax elements used to encode the displacement components are shown in Table 1 below. Examples of sequence-level, frame-level, and patch-level syntax elements are shown in Tables 2, 3, and 4 below, respectively.

[0071]

[0072] Table 1: Examples of Syntax Elements for Encoding Displacement Components To encode displacement components using some arithmetic coding techniques, the transformed displacement components are grouped into coding blocks of size subblockSize = 1<<dh_log2_subblock_size_minus6 according to the values of the syntax elements, at different levels of detail.

[0073] Subsequently, each block can be encoded using a separate context model. When all the values in a block are equal to zero, a special flag can be used to indicate that the block is occupied. For example, when dpdu_nz_subBlock [ tileID ][patchIdx ][ k ][ block ] is equal to 1, the block is occupied, and when it is equal to 0, all the block values are equal to zero and no encoding is required. In some techniques, for level 0 (e.g., the first LoD) and level 1 (e.g., the second LoD), the block size is evaluated to be equal to the size of the level-of-details (LoDs) coefficient. The subblockSize is used to encode all levels of detail greater than 2.

[0074] A drawback of this method is that it does not allow zero block sizes for lower levels of detail (e.g., level 0 and level 1).

[0075] To overcome these and other challenges, the present disclosure provides an exemplary technique where the block size is derived based on the number of subdivisions for each level of detail (LoD) rather than through explicit signaling of the block size. In this way, variable block lengths per LoD are supported, and block sizes other than 2^(6+x) are allowed.

[0076] For example, the block size can be determined from the dh_log2_subblock_size_minus6 syntax element, which can be signaled for each LoD (hierarchical subdivision level). The decoder can determine the subblock size (subblockSize[level]) as the sum of the value of the dh_log2_subblock_size_minus6 syntax element plus 6. In doing so, the block size and the number of subblocks can be different for each LoD.

[0077] To determine the number of vertices in a LoD (vertCount[level]), the decoder decodes the diu_vertex_count_lod syntax element. Using the number of vertices and the subblock size, the decoder determines the number of subblocks in the LoD (numSubblock[level]) by calculating vertCount[level] / subblockSize[level]. The block size (levelBlockSize[level]) can be equal to subblockSize[level], for example, levelBlockSize[level] = subblockSize[level].

[0078] In existing techniques, the encoding method for each coefficient can remain the same, for example, using diu_coeff_abs_level_gt0, diu_coeff_abs_level_gt1, diu_coeff_sign, and diu_coeff_abs_level_rem. Entropy encoding starts from the first vertex and ends at the last vertex, propagating the context. Examples of syntax element signaling used in this technique are shown in Tables 2 and 3 below.

[0079]

[0080] Table 2: First Examples of Syntax Elements

[0081] Table 3: Second example of syntax elements As shown in Table 3, `subblockCountPerLevel` represents the number of subblocks in the LoD at index i. In some implementations, when the value of the `dpdu_nz_subBlock[tileID][patchIdx][k][block]` syntax element is equal to 1, the subblock has at least one non-zero coefficient in the k-th displacement component; on the other hand, when the value of the `dpdu_nz_subBlock[tileID][patchIdx][k][block]` syntax element is equal to 0, the subblock is not occupied. The `dpdu_coeff_gt0[tileID][patchIdx][k][v]` syntax element indicates that the coefficient value is greater than 0. The `dpdu_coeff_sign[tileID][patchIdx][k][v]` syntax element indicates that the coefficient value is negative. The `dpdu_coeff_gt1[tileID][patchIdx][k][v]` syntax element indicates that the coefficient value is greater than 1. The `dpdu_coeff_rem[tileID][patchIdx][k]` syntax element indicates the remaining value of the coefficient.

[0082] Examples of shift component syntax elements that can be encoded using the techniques disclosed herein are shown in Table 4 below.

[0083]

[0084] Table 4: Examples of displacement component syntax elements Referring to Table 4, when the value of the syntax element `dpdu_nz_subBlock[tileID][patchIdx][k][block]` is equal to 1, the subblock has at least one non-zero coefficient; conversely, when the value of the syntax element `dpdu_nz_subBlock[tileID][patchIdx][k][block]` is equal to 0, the subblock is not occupied. The syntax element `dpdu_coeff_gt0[tileID][patchIdx][k][v]` indicates that the coefficient value is greater than 0. The syntax element `dpdu_coeff_sign[tileID][patchIdx][k][v]` indicates that the coefficient value is negative. The syntax element `dpdu_coeff_gt1[tileID][patchIdx][k][v]` indicates that the coefficient value is greater than 1. The syntax element `dpdu_coeff_rem[tileID][patchIdx][k]` indicates the remaining value of the coefficient.

[0085] For cases where the last block is partially occupied, the last vertex in the block is calculated as the minimum of min(vBlockStart[level][block] + levelBlockSize[level], totalVertCount). MaxDimension is derived as 1 or 3 by the dsps_single_dimension_flag syntax element encoded in the sequence parameter set. For example, the decoder can determine MaxDimension as MaxDimension = dsps_single_dimension_flag? 1:3. vStart[level], vBlockStart[level][block], and vBlockEnd[level][block] are vertex indices indicating the first vertex of the level, the first vertex in the sub-block, and the last vertex in the sub-block, respectively. An exemplary decoding process 1500 using the above technique is described in... Figure 15 As shown in the image.

[0086] Figure 16A flowchart illustrating an exemplary method 1600 of decoding by a decoder according to some embodiments of the present disclosure is shown. Method 1600 may be performed by an apparatus (e.g., decoder 201 of decoding system 200 or any other suitable decoding system). Method 1600 may include operations 1602-1610 as described below. It should be understood that some operations may be optional (indicated by dashed lines), and some operations may be performed simultaneously or in different ways. Figure 16 The execution sequence is shown.

[0087] refer to Figure 16 Operations 1602-1612 can be performed for each of the multiple hierarchical subdivision levels. In some implementations, the multiple hierarchical subdivision levels may include multiple different LoDs.

[0088] At 1602, the device can decode the first syntax element to determine the subblock size associated with the hierarchical subdivision level. In some embodiments, the first syntax element may include the dh_log2_subblock_size_minus6 syntax element. In some embodiments, to decode the first syntax element to determine the subblock size associated with the hierarchical subdivision level, the device can determine the subblock size by summing the value of the dh_log2_subblock_size_minus6 syntax element by adding six. For example, refer to... Figure 2 According to Table 3, the decoder 201 can determine the subblock size (subblockSize[level]) as the sum of the value of the dh_log2_subblock_size_minus6 syntax element and 6.

[0089] At 1604, the device can decode the second syntax element to determine the number of vertices associated with the hierarchical subdivision level. In some implementations, the second syntax element may include the `diu_vertex_count_lod` syntax element. For example, refer to... Figure 2 According to Table 3, decoder 201 can determine the number of vertices in a level by decoding the diu_vertex_count_lod syntax element.

[0090] At 1606, the device can determine the number of sub-blocks associated with a subdivision level based on the sub-block size. In some embodiments, to determine the number of sub-blocks associated with a subdivision level based on the sub-block size, the device can determine the number of sub-blocks associated with a subdivision level based on the number of vertices and the sub-block size. For example, refer to... Figure 2According to Table 3, using the number of vertices and the subblock size, the decoder 201 can determine the number of subblocks (numSubblock[level]) of the LoD by calculating vertCount[level] / subblockSize[level].

[0091] At 1608, the device can determine multiple displacement components associated with the hierarchical subdivision level based on the number of sub-blocks. (Reference) Figure 2 According to Table 4, decoder 201 can determine multiple displacement coefficients of a level by decoding one or more of, for example, dpdu_nz_subBlock, diu_coeff_abs_level_gt0, diu_coeff_abs_level_gt1, diu_coeff_sign, and diu_coeff_abs_level_rem. For example, when the value of the dpdu_nz_subBlock[tileID][patchIdx][k][block] syntax element is equal to 1, the sub-block has at least one non-zero coefficient; on the other hand, when the value of the dpdu_nz_subBlock[tileID][patchIdx][k][block] syntax element is equal to 0, the sub-block is not occupied. The dpdu_coeff_gt0[tileID][patchIdx][k][v] syntax element indicates that the coefficient value is greater than 0. The dpdu_coeff_sign[tileID][patchIdx][k][v] syntax element indicates that the coefficient value is negative. dpdu_coeff_gt1[tileID][patchIdx][k][v] Syntax element indicates that the value of the coefficient is greater than 1. dpdu_coeff_rem[tileID][patchIdx][k] Syntax element indicates the remaining value of the coefficient.

[0092] At 1610, the device can decode the subdivision hierarchy based on the number of sub-blocks. In some embodiments, to decode the subdivision hierarchy based on the number of sub-blocks, the device can decode the subdivision hierarchy based on multiple displacement components. For example, refer to... Figure 2 According to Table 4, decoder 201 can decode the hierarchical subdivision level by determining the displacement component based on the sub-block size.

[0093] Figure 17A flowchart illustrating an exemplary method 1700 of encoding by an encoder according to some embodiments of the present disclosure is shown. Method 1700 can be performed by encoder 101 of encoding system 100 or any other suitable encoding system. Method 1700 may include operations 1702-1710 as described below. It should be understood that some operations may be optional (indicated by dashed lines), and some operations may be performed simultaneously or in different ways. Figure 17 The execution sequence is shown.

[0094] refer to Figure 17 Operations 1702-1712 can be performed for each of the multiple hierarchical subdivision levels. In some implementations, the multiple hierarchical subdivision levels may include multiple different LoDs.

[0095] At 1702, the device can encode a first syntax element to indicate the subblock size associated with the hierarchical subdivision level. In some embodiments, the first syntax element may include a dh_log2_subblock_size_minus6 syntax element. In some embodiments, to encode the first syntax element to indicate the subblock size associated with the hierarchical subdivision level, the device can determine the subblock size by summing the value of the dh_log2_subblock_size_minus6 syntax element by adding six. For example, refer to... Figure 1 According to Table 3, encoder 101 can determine the subblock size (subblockSize[level]) as the value of the dh_log2_subblock_size_minus6 syntax element plus 6.

[0096] At 1704, the device can encode a second syntax element to indicate the number of vertices associated with a hierarchical subdivision level. In some implementations, the second syntax element may include a `diu_vertex_count_lod` syntax element. For example, refer to... Figure 1 According to Table 3, encoder 101 can determine the number of vertices in a level by encoding the diu_vertex_count_lod syntax element.

[0097] At 1706, the device can determine the number of sub-blocks associated with a hierarchical subdivision level based on the sub-block size. In some embodiments, to determine the number of sub-blocks associated with a hierarchical subdivision level based on the sub-block size, the device can determine the number of sub-blocks based on the number of vertices and the sub-block size. For example, refer to... Figure 1According to Table 3, using the number of vertices and the subblock size, encoder 101 can determine the number of subblocks (numSubblock[level]) of the LoD by calculating vertCount[level] / subblockSize[level].

[0098] At 1708, the device can determine multiple displacement components associated with the hierarchical subdivision level based on the number of sub-blocks. (Reference) Figure 1 According to Table 4, encoder 101 can determine multiple displacement coefficients of a level by encoding one or more of, for example, dpdu_nz_subBlock, diu_coeff_abs_level_gt0, diu_coeff_abs_level_gt1, diu_coeff_sign, and diu_coeff_abs_level_rem. For example, when the value of the dpdu_nz_subBlock[tileID][patchIdx][k][block] syntax element is equal to 1, the sub-block has at least one non-zero coefficient; on the other hand, when the value of the dpdu_nz_subBlock[tileID][patchIdx][k][block] syntax element is equal to 0, the sub-block is not occupied. The dpdu_coeff_gt0[tileID][patchIdx][k][v] syntax element indicates that the coefficient value is greater than 0. The dpdu_coeff_sign[tileID][patchIdx][k][v] syntax element indicates that the coefficient value is negative. dpdu_coeff_gt1[tileID][patchIdx][k][v] Syntax element indicates that the value of the coefficient is greater than 1. dpdu_coeff_rem[tileID][patchIdx][k] Syntax element indicates the remaining value of the coefficient.

[0099] At 1710, the device can encode the subdivision level based on the number of sub-blocks. In some embodiments, in order to encode the subdivision level based on the number of sub-blocks, the device can encode the subdivision level based on multiple displacement components. For example, refer to... Figure 1 According to Table 4, encoder 101 can encode the hierarchical subdivision level by determining the displacement component based on the sub-block size.

[0100] In all respects of this disclosure, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored as instructions on a non-transitory computer-readable medium. Computer-readable media include computer storage media. Storage media can be processors (such as...) Figure 1 and Figure 2The processor 102 in the computer can access any available medium. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, HDDs (such as disk storage devices or other magnetic storage devices), flash drives, SSDs, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system (such as a mobile device or computer). As used herein, disks and optical discs include CDs, laser discs, optical discs, digital video discs (DVDs), and floppy disks, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0101] According to one aspect of this disclosure, a method for decoding by a decoder is provided. For each of a plurality of hierarchical subdivision levels, the following operations may be performed: The method may include decoding a first syntax element by a processor to determine the sub-block size associated with the hierarchical subdivision level. The method may include determining the number of sub-blocks associated with the hierarchical subdivision level by the processor based on the sub-block size. The method may include decoding the hierarchical subdivision level by the processor based on the number of sub-blocks.

[0102] In some implementations, multiple hierarchical subdivisions may include multiple different LoDs.

[0103] In some implementations, the method may include having the processor determine multiple displacement components associated with the hierarchical subdivision level based on the number of sub-blocks. In some implementations, decoding the hierarchical subdivision level by the processor based on the number of sub-blocks may include decoding the hierarchical subdivision level by the processor based on multiple displacement components.

[0104] In some implementations, the first syntax element may include the dh_log2_subblock_size_minus6 syntax element.

[0105] In some implementations, the processor decoding the first syntax element to determine the subblock size associated with the hierarchical subdivision level may include the processor determining the subblock size by summing the value of the dh_log2_subblock_size_minus6 syntax element by six.

[0106] In some implementations, the method may include having the processor decode a second syntax element to determine the number of vertices associated with the hierarchical subdivision level. In some implementations, determining the number of sub-blocks associated with the hierarchical subdivision level by the processor based on the sub-block size may include determining the number of sub-blocks associated with the hierarchical subdivision level by the processor based on the number of vertices and the sub-block size.

[0107] In some implementations, the second syntax element may include the diu_vertex_count_lod syntax element.

[0108] According to another aspect of this disclosure, a decoder is provided. The decoder may include a processor and a memory storing instructions. The memory stores instructions that, when executed by the processor, cause the processor to perform the following operations for each of a plurality of hierarchical subdivision levels: The memory stores instructions that, when executed by the processor, cause the processor to decode a first syntax element to determine a sub-block size associated with the hierarchical subdivision level; the memory stores instructions that, when executed by the processor, cause the processor to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size; and the memory stores instructions that, when executed by the processor, cause the processor to decode the hierarchical subdivision level based on the number of sub-blocks.

[0109] In some implementations, multiple hierarchical subdivisions may include multiple different LoDs.

[0110] In some embodiments, the memory stores instructions that, when executed by a processor, cause the processor to determine multiple displacement components associated with a subdivision level based on the number of subblocks. In some embodiments, to decode the subdivision level based on the number of subblocks, the memory stores instructions that, when executed by a processor, cause the processor to decode the subdivision level based on multiple displacement components.

[0111] In some implementations, the first syntax element may include the dh_log2_subblock_size_minus6 syntax element.

[0112] In some implementations, in order to decode the first syntax element to determine the subblock size associated with the hierarchical subdivision level, the memory stores instructions that, when executed by the processor, enable the processor to determine the subblock size by summing the value of the dh_log2_subblock_size_minus6 syntax element by 6.

[0113] In some implementations, the memory stores instructions that, when executed by a processor, cause the processor to decode a second syntax element to determine the number of vertices associated with the hierarchical subdivision level. In some implementations, to determine the number of sub-blocks associated with a hierarchical subdivision level based on sub-block size, the memory stores instructions that, when executed by a processor, cause the processor to determine the number of sub-blocks associated with a hierarchical subdivision level based on the number of vertices and the sub-block size.

[0114] In some implementations, the second syntax element may include the diu_vertex_count_lod syntax element.

[0115] According to another aspect of this disclosure, an apparatus for decoding is provided. The apparatus for decoding may include a processor and a memory storing instructions. The memory stores instructions that, when executed by the processor, cause the processor to perform the following operations for each of a plurality of hierarchical subdivision levels: The memory stores instructions that, when executed by the processor, cause the processor to decode a first syntax element to determine a sub-block size associated with the hierarchical subdivision level. The memory stores instructions that, when executed by the processor, cause the processor to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size. The memory stores instructions that, when executed by the processor, cause the processor to decode the hierarchical subdivision level based on the number of sub-blocks.

[0116] According to another aspect of this disclosure, a non-transitory computer-readable medium is provided that stores instructions for a processor of a decoder. When executed by the decoder's processor, the instructions cause the decoder's processor to perform the following operations for each of a plurality of hierarchical subdivision levels. When executed by the decoder's processor, the instructions cause the decoder's processor to decode a first syntax element to determine a sub-block size associated with the hierarchical subdivision level. When executed by the decoder's processor, the instructions cause the decoder's processor to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size. When executed by the decoder's processor, the instructions cause the decoder's processor to decode the hierarchical subdivision level based on the number of sub-blocks.

[0117] In some implementations, multiple hierarchical subdivisions may include multiple different LoDs.

[0118] In some embodiments, when executed by the decoder's processor, the instructions may cause the decoder's processor to determine multiple displacement components associated with the subdivision level based on the number of subblocks. In some embodiments, in order to decode the subdivision level based on the number of subblocks, the instructions, when executed by the decoder's processor, may cause the decoder's processor to decode the subdivision level based on multiple displacement components.

[0119] In some implementations, the first syntax element may include the dh_log2_subblock_size_minus6 syntax element.

[0120] In some implementations, in order to decode the first syntax element to determine the subblock size associated with the hierarchical subdivision level, the instruction, when executed by the decoder's processor, may cause the decoder's processor to determine the subblock size by summing the value of the dh_log2_subblock_size_minus6 syntax element by 6.

[0121] In some implementations, when executed by the decoder's processor, the instructions may cause the decoder's processor to decode a second syntax element to determine the number of vertices associated with the hierarchical subdivision level. In some implementations, in order to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size, the instructions, when executed by the decoder's processor, may cause the decoder's processor to determine the number of sub-blocks associated with the hierarchical subdivision level based on the number of vertices and the sub-block size.

[0122] In some implementations, the second syntax element may include the diu_vertex_count_lod syntax element.

[0123] According to one aspect of this disclosure, a method for encoding by an encoder is provided. For each of a plurality of hierarchical subdivision levels, the following operations may be performed: The method may include encoding a first syntax element by a processor to indicate the size of a sub-block associated with the hierarchical subdivision level. The method may include determining, by the processor, the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size. The method may include encoding the hierarchical subdivision level by the processor based on the number of sub-blocks.

[0124] In some implementations, multiple hierarchical subdivision levels may include sequence level, frame level, and patch level.

[0125] In some implementations, the method may include having the processor determine multiple displacement components associated with the hierarchical subdivision level based on the number of sub-blocks. In some implementations, encoding the hierarchical subdivision level by the processor based on the number of sub-blocks may include encoding the hierarchical subdivision level by the processor based on multiple displacement components.

[0126] In some implementations, the first syntax element may include the dh_log2_subblock_size_minus6 syntax element.

[0127] In some implementations, encoding the first syntax element by the processor to indicate the subblock size associated with the hierarchical subdivision level may include: the processor determining the subblock size by summing the value of the dh_log2_subblock_size_minus6 syntax element by 6.

[0128] In some implementations, the method may include encoding a second syntax element by a processor to indicate the number of vertices associated with the hierarchical subdivision level. In some implementations, determining the number of sub-blocks associated with the hierarchical subdivision level by the processor based on the sub-block size may include determining the number of sub-blocks associated with the hierarchical subdivision level by the processor based on the number of vertices and the sub-block size.

[0129] In some implementations, the second syntax element may include the diu_vertex_count_lod syntax element.

[0130] According to another aspect of this disclosure, an encoder is provided. The encoder may include a processor and a memory storing instructions. The memory stores instructions that, when executed by the processor, cause the processor to perform the following operations for each of a plurality of hierarchical subdivision levels. The memory stores instructions that, when executed by the processor, cause the processor to encode a first syntax element to indicate a sub-block size associated with the hierarchical subdivision level. The memory stores instructions that, when executed by the processor, cause the processor to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size. The memory stores instructions that, when executed by the processor, cause the processor to encode the hierarchical subdivision level based on the number of sub-blocks.

[0131] In some implementations, multiple hierarchical subdivision levels can include sequence level, frame level, and patch level.

[0132] In some embodiments, the memory stores instructions that, when executed by a processor, cause the processor to determine multiple displacement components associated with a subdivision level based on the number of subblocks. In some embodiments, to encode the subdivision level based on the number of subblocks, the memory stores instructions that, when executed by a processor, cause the processor to encode the subdivision level based on multiple displacement components.

[0133] In some implementations, the first syntax element may include the dh_log2_subblock_size_minus6 syntax element.

[0134] In some implementations, in order to encode the first syntax element to indicate the subblock size associated with the hierarchical subdivision level, the memory stores instructions that, when executed by the processor, enable the processor to determine the subblock size by summing the value of the dh_log2_subblock_size_minus6 syntax element by 6.

[0135] In some implementations, the memory stores instructions that, when executed by a processor, cause the processor to encode a second syntax element to indicate the number of vertices associated with a subdivision level. In some implementations, to determine the number of sub-blocks associated with a subdivision level based on sub-block size, the memory stores instructions that, when executed by a processor, cause the processor to determine the number of sub-blocks associated with a subdivision level based on the number of vertices and the sub-block size.

[0136] In some implementations, the second syntax element may include the diu_vertex_count_lod syntax element.

[0137] According to another aspect of this disclosure, an apparatus for encoding is provided. The apparatus for encoding may include a processor and a memory storing instructions. The memory stores instructions that, when executed by the processor, cause the processor to perform the following operations for each of a plurality of hierarchical subdivision levels. The memory stores instructions that, when executed by the processor, cause the processor to encode a first syntax element to indicate a sub-block size associated with the hierarchical subdivision level. The memory stores instructions that, when executed by the processor, cause the processor to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size. The memory stores instructions that, when executed by the processor, cause the processor to encode the hierarchical subdivision level based on the number of sub-blocks.

[0138] According to another aspect of this disclosure, a non-transitory computer-readable medium is provided, storing instructions for a processor of an encoder. When executed by the encoder's processor, the instructions cause the encoder's processor to perform the following operations for each of a plurality of subdivision levels. When executed by the encoder's processor, the instructions cause the encoder's processor to encode a first syntax element to determine a sub-block size associated with the subdivision level. When executed by the encoder's processor, the instructions cause the encoder's processor to determine the number of sub-blocks associated with the subdivision level based on the sub-block size. When executed by the encoder's processor, the instructions cause the encoder's processor to encode the subdivision level based on the number of sub-blocks.

[0139] In some implementations, multiple hierarchical subdivision levels can include sequence level, frame level, and patch level.

[0140] In some embodiments, when executed by the encoder's processor, the instructions may cause the encoder's processor to determine multiple displacement components associated with the subdivision level based on the number of sub-blocks. In some embodiments, in order to encode the subdivision level based on the number of sub-blocks, the instructions, when executed by the encoder's processor, may cause the encoder's processor to encode the subdivision level based on multiple displacement components.

[0141] In some implementations, the first syntax element may include the dh_log2_subblock_size_minus6 syntax element.

[0142] In some implementations, in order to encode the first syntax element to indicate the subblock size associated with the hierarchical subdivision level, the instruction, when executed by the encoder's processor, may cause the encoder's processor to determine the subblock size by summing the value of the dh_log2_subblock_size_minus6 syntax element plus 6.

[0143] In some implementations, when executed by the encoder's processor, the instructions may cause the encoder's processor to encode a second syntax element to indicate the number of vertices associated with the hierarchical subdivision level. In some implementations, to determine the number of sub-blocks associated with the hierarchical subdivision level based on sub-block size, the instructions, when executed by the encoder's processor, may cause the encoder's processor to determine the number of sub-blocks associated with the hierarchical subdivision level based on the number of vertices and the sub-block size.

[0144] In some implementations, the second syntax element may include the diu_vertex_count_lod syntax element.

[0145] According to another aspect of this disclosure, a non-transitory computer-readable medium for storing a bitstream is provided. The bitstream can be generated using one or more of the operations described herein.

[0146] The description of the above embodiments will reveal the general nature of this disclosure, enabling those skilled in the art to readily modify and / or adapt such embodiments for various applications without departing from the general concept of this disclosure, without excessive experimentation. Therefore, based on the teachings and guidance presented herein, such modifications and adaptations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for descriptive purposes and not for limitation, and therefore the terminology or terminology of this specification will be interpreted by those skilled in the art based on the teachings and guidance.

[0147] The embodiments of this disclosure have been described above with the aid of functional building blocks that illustrate the implementation of specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries may be defined, provided that the specified functions and their relationships can be properly performed.

[0148] The summary and abstract may set forth one or more, but not all, exemplary embodiments of this disclosure as contemplated by the inventors, and are therefore not intended to limit this disclosure and the appended claims in any way.

[0149] Various functional blocks, modules, and steps have been disclosed above. The arrangements provided are illustrative and not limiting. Therefore, functional blocks, modules, and steps can be rearranged or combined in ways different from the examples provided above. Similarly, some embodiments include only a subset of functional blocks, modules, and steps, and any such subset is permitted.

[0150] The breadth and scope of this disclosure should not be limited by any of the foregoing exemplary embodiments, but should be defined solely by the appended claims and their equivalents.

Claims

1. A method for decoding by a decoder, comprising: For each of the multiple hierarchical subdivision levels The processor decodes the first syntax element to determine the size of the sub-blocks associated with the hierarchical subdivision level; The processor determines the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size; as well as The processor decodes the hierarchical subdivision level based on the number of sub-blocks.

2. The method according to claim 1, wherein, The multiple hierarchical subdivisions include multiple different levels of detail.

3. The method according to claim 1, further comprising: The processor determines multiple displacement components associated with the hierarchical subdivision level based on the number of sub-blocks. The decoding of the hierarchical subdivision level by the processor based on the number of sub-blocks includes: The processor decodes the hierarchical subdivision levels based on the multiple displacement components.

4. The method according to claim 1, wherein, The first syntax element includes the dh_log2_subblock_size_minus6 syntax element.

5. The method according to claim 4, wherein, Decoding the first syntax element by the processor to determine the size of the sub-block associated with the hierarchical subdivision level includes: The processor determines the subblock size by summing the values ​​of the dh_log2_subblock_size_minus6 syntax element by 6.

6. The method according to claim 1, further comprising: The processor decodes the second syntax element to determine the number of vertices associated with the hierarchical subdivision level. The process by which the processor determines the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size includes: The processor determines the number of sub-blocks associated with the hierarchical subdivision level based on the number of vertices and the sub-block size.

7. The method according to claim 6, wherein, The second syntax element includes the diu_vertex_count_lod syntax element.

8. A decoder, comprising: processor; as well as The memory stores instructions that, when executed by the processor, cause the processor to: For each of the multiple hierarchical subdivision levels Decode the first syntax element to determine the size of the sub-blocks associated with the hierarchical subdivision level; The number of sub-blocks associated with the hierarchical subdivision level is determined based on the sub-block size; as well as The hierarchical subdivision level is decoded based on the number of sub-blocks.

9. The decoder according to claim 8, wherein, The multiple hierarchical subdivisions include multiple different levels of detail.

10. The decoder according to claim 8, wherein, The memory stores instructions, which, when executed by the processor, cause the processor to: Based on the number of sub-blocks, multiple displacement components associated with the hierarchical subdivision level are determined. In order to decode the hierarchical subdivision levels based on the number of sub-blocks, the memory stores instructions that, when executed by the processor, cause the processor to: The hierarchical subdivision level is decoded based on the multiple displacement components.

11. The decoder according to claim 8, wherein, The first syntax element includes the dh_log2_subblock_size_minus6 syntax element.

12. The decoder according to claim 11, wherein, In order to decode the first syntax element to determine the size of the sub-block associated with the hierarchical subdivision level, the memory stores instructions that, when executed by the processor, cause the processor to: The subblock size is determined by summing the values ​​of the dh_log2_subblock_size_minus6 syntax element by 6.

13. The decoder according to claim 8, wherein, The memory stores instructions, which, when executed by the processor, cause the processor to: Decode the second syntax element to determine the number of vertices associated with the said hierarchical subdivision level. In order to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size, the memory stores instructions that, when executed by the processor, cause the processor to: The number of sub-blocks associated with the hierarchical subdivision level is determined based on the number of vertices and the sub-block size.

14. The decoder according to claim 13, wherein, The second syntax element includes the diu_vertex_count_lod syntax element.

15. An apparatus for decoding, comprising: processor; as well as The memory stores instructions that, when executed by the processor, cause the processor to: For each of the multiple hierarchical subdivision levels Decode the first syntax element to determine the size of the sub-blocks associated with the hierarchical subdivision level; The number of sub-blocks associated with the hierarchical subdivision level is determined based on the sub-block size; as well as The hierarchical subdivision level is decoded based on the number of sub-blocks.

16. A non-transitory computer-readable medium storing instructions, said instructions causing the processor of the decoder, when executed by a processor of a decoder, to: For each of the multiple hierarchical subdivision levels Decode the first syntax element to determine the size of the sub-blocks associated with the hierarchical subdivision level; The number of sub-blocks associated with the hierarchical subdivision level is determined based on the sub-block size; as well as The hierarchical subdivision level is decoded based on the number of sub-blocks.

17. The non-transitory computer-readable medium according to claim 16, wherein, The multiple hierarchical subdivisions include multiple different levels of detail.

18. The non-transitory computer-readable medium according to claim 16, wherein, When the instruction is executed by the decoder's processor, the decoder's processor: Based on the number of sub-blocks, multiple displacement components associated with the hierarchical subdivision level are determined. In order to decode the hierarchical subdivision levels based on the number of sub-blocks, the instructions, when executed by the decoder's processor, cause the decoder's processor to: The hierarchical subdivision level is decoded based on the multiple displacement components.

19. The non-transitory computer-readable medium according to claim 16, wherein, The first syntax element includes the dh_log2_subblock_size_minus6 syntax element.

20. The non-transitory computer-readable medium according to claim 19, wherein, In order to decode the first syntax element to determine the size of the sub-block associated with the hierarchical subdivision level, the instructions, when executed by the decoder's processor, cause the decoder's processor to: The subblock size is determined by summing the values ​​of the dh_log2_subblock_size_minus6 syntax element by 6.

21. The non-transitory computer-readable medium according to claim 16, wherein, When the instruction is executed by the decoder's processor, the decoder's processor: Decode the second syntax element to determine the number of vertices associated with the said hierarchical subdivision level. In order to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size, the instruction, when executed by the decoder's processor, causes the decoder's processor to: The number of sub-blocks associated with the hierarchical subdivision level is determined based on the number of vertices and the sub-block size.

22. The non-transitory computer-readable medium according to claim 21, wherein, The second syntax element includes the diu_vertex_count_lod syntax element.

23. A method for encoding by an encoder, comprising: For each of the multiple hierarchical subdivision levels The processor encodes the first syntax element to indicate the size of the sub-blocks associated with the hierarchical subdivision level; The processor determines the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size; as well as The processor encodes the hierarchical subdivision levels based on the number of sub-blocks.

24. The method according to claim 23, wherein, The multiple hierarchical subdivisions include multiple different levels of detail.

25. The method of claim 23, further comprising: The processor determines multiple displacement components associated with the hierarchical subdivision level based on the number of sub-blocks. The encoding of the hierarchical subdivision level by the processor based on the number of sub-blocks includes: The processor encodes the hierarchical subdivision levels based on the plurality of displacement components.

26. The method according to claim 23, wherein, The first syntax element includes the dh_log2_subblock_size_minus6 syntax element.

27. The method according to claim 26, wherein, The processor encodes the first syntax element to indicate the size of the sub-block associated with the hierarchical subdivision level, including: The processor determines the subblock size by summing the values ​​of the dh_log2_subblock_size_minus6 syntax element by 6.

28. The method of claim 23, further comprising: The processor encodes the second syntax element to determine the number of vertices associated with the hierarchical subdivision level. The process by which the processor determines the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size includes: The processor determines the number of sub-blocks associated with the hierarchical subdivision level based on the number of vertices and the sub-block size.

29. The method according to claim 28, wherein, The second syntax element includes the diu_vertex_count_lod syntax element.

30. An encoder, comprising: processor; as well as The memory stores instructions that, when executed by the processor, cause the processor to: For each of the multiple hierarchical subdivision levels The first syntax element is encoded to indicate the size of the sub-blocks associated with the hierarchical subdivision level; The number of sub-blocks associated with the hierarchical subdivision level is determined based on the sub-block size; as well as The hierarchical subdivision level is encoded based on the number of sub-blocks.

31. The encoder according to claim 30, wherein, The multiple hierarchical subdivisions include multiple different levels of detail.

32. The encoder according to claim 30, wherein, The memory stores instructions, which, when executed by the processor, cause the processor to: Based on the number of sub-blocks, multiple displacement components associated with the hierarchical subdivision level are determined. In order to encode the hierarchical subdivision levels based on the number of sub-blocks, the memory stores instructions that, when executed by the processor, cause the processor to: The hierarchical subdivision level is encoded based on the multiple displacement components.

33. The encoder according to claim 30, wherein, The first syntax element includes the dh_log2_subblock_size_minus6 syntax element.

34. The encoder according to claim 33, wherein, In order to encode the first syntax element to indicate the size of the sub-block associated with the hierarchical subdivision level, the memory stores instructions that, when executed by the processor, cause the processor to: The subblock size is determined by summing the values ​​of the dh_log2_subblock_size_minus6 syntax element by 6.

35. The encoder according to claim 30, wherein, The memory stores instructions, which, when executed by the processor, cause the processor to: The second syntax element is encoded to indicate the number of vertices associated with the hierarchical subdivision level. In order to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size, the memory stores instructions that, when executed by the processor, cause the processor to: The number of sub-blocks associated with the hierarchical subdivision level is determined based on the number of vertices and the sub-block size.

36. The encoder according to claim 35, wherein, The second syntax element includes the diu_vertex_count_lod syntax element.

37. An apparatus for encoding, comprising: processor; as well as The memory stores instructions that, when executed by the processor, cause the processor to: For each of the multiple hierarchical subdivision levels The first syntax element is encoded to indicate the size of the sub-blocks associated with the hierarchical subdivision level; The number of sub-blocks associated with the hierarchical subdivision level is determined based on the sub-block size; as well as The hierarchical subdivision level is encoded based on the number of sub-blocks.

38. A non-transitory computer-readable medium storing instructions that, when executed by a processor of an encoder, cause the processor of the encoder to: For each of the multiple hierarchical subdivision levels The first syntax element is encoded to indicate the size of the sub-blocks associated with the hierarchical subdivision level; The number of sub-blocks associated with the hierarchical subdivision level is determined based on the sub-block size; and The hierarchical subdivision level is encoded based on the number of sub-blocks.

39. The non-transitory computer-readable medium according to claim 38, wherein, The multiple hierarchical subdivisions include multiple different levels of detail.

40. The non-transitory computer-readable medium according to claim 38, wherein, When the instruction is executed by the encoder's processor, the encoder's processor: Based on the number of sub-blocks, multiple displacement components associated with the hierarchical subdivision level are determined. In order to encode the hierarchical subdivision levels based on the number of sub-blocks, the instructions, when executed by the encoder's processor, cause the encoder's processor to: The hierarchical subdivision level is encoded based on the multiple displacement components.

41. The non-transitory computer-readable medium according to claim 38, wherein, The first syntax element includes the dh_log2_subblock_size_minus6 syntax element.

42. The non-transitory computer-readable medium according to claim 41, wherein, In order to encode the first syntax element to indicate the size of the sub-block associated with the hierarchical subdivision level, the instruction, when executed by the encoder's processor, causes the encoder's processor to: The subblock size is determined by summing the values ​​of the dh_log2_subblock_size_minus6 syntax element by 6.

43. The non-transitory computer-readable medium according to claim 38, wherein, When the instruction is executed by the encoder's processor, the encoder's processor: The second syntax element is encoded to indicate the number of vertices associated with the hierarchical subdivision level. In order to determine the number of sub-blocks associated with the hierarchical subdivision level based on the sub-block size, the instruction, when executed by the encoder's processor, causes the encoder's processor to: The number of sub-blocks associated with the hierarchical subdivision level is determined based on the number of vertices and the sub-block size.

44. The non-transitory computer-readable medium according to claim 43, wherein, The second syntax element includes the diu_vertex_count_lod syntax element.

45. A non-transitory computer-readable medium for storing a bitstream generated based on at least one of claims 23 to 29.

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