Chip memory data fault-tolerant processing method and system

Abstract

The application relates to the technical field of data processing, and discloses a chip memory data fault-tolerant processing method and system. The method comprises the following steps: performing space-time alignment on error events, memory access instruction stream segments and system state parameters of a chip to obtain error characteristic sequences of the chip; performing dependence relationship mining on the error characteristic sequences, and constructing a soft error prediction framework of the chip; performing dynamic risk marking on the memory access instruction stream segments, and performing resource collaborative pre-allocation on the marked instructions to obtain a fault-tolerant scheduling strategy set of the chip; performing redirection testing on the fault-tolerant scheduling strategy set to obtain fault-tolerant scheduling tracks and resource occupation portraits of the chip; performing compilation binding on the fault-tolerant scheduling strategy set to obtain endogenous safe memory access microinstructions of the chip; and performing incremental learning on the soft error prediction framework to obtain a fault-tolerant strategy library of the chip. The application can improve the efficiency of chip memory data fault-tolerant processing.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a method and system for fault-tolerant processing of chip memory data. Background Technology

[0002] Current chip memory data fault tolerance technologies mostly employ preset, fixed strategies. These technologies cannot accurately align error events, memory access instruction stream segments, and system state parameters generated during chip operation, making it difficult to generate error feature sequences that truly reflect the abnormal patterns of chip operation. Existing technologies lack multi-granularity analytical dimensions when mining error correlations, and the constructed predictive frameworks can only cover a limited number of error types. They cannot comprehensively perceive and predict the complex and ever-changing chip operating states, resulting in insufficient accuracy in fault tolerance processing and difficulty in effectively reducing the probability of chip memory data errors.

[0003] The generation and verification stages of existing chip memory fault-tolerant scheduling strategies are disconnected. Before actual deployment, these strategies lack in-depth adaptation testing with the trusted execution environment and memory address remapping mechanism, making it impossible to accurately obtain the fault-tolerant scheduling trajectory and resource consumption profile during strategy execution. Furthermore, existing technologies lack incremental optimization mechanisms based on execution feedback and emerging error events, preventing dynamic iterative updates to the fault-tolerant strategy library. Faced with constantly emerging new error modes during chip operation, it is difficult to quickly generate appropriate response strategies, resulting in insufficient timeliness and flexibility in chip memory fault tolerance processing, thus hindering the overall performance of the chip. Summary of the Invention

[0004] This invention provides a chip memory data fault tolerance processing method and system to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides a chip memory data fault tolerance processing method, comprising: S1. Perform spatiotemporal alignment on the chip's error events, memory access instruction stream segments, and system status parameters to obtain the chip's error feature sequence; S2. Perform dependency mining on the error feature sequence, and construct a soft error prediction framework for the chip based on the mined dependency features; S3. Based on the soft error prediction framework, the memory access instruction stream segments are dynamically risk-marked, and the marked instructions are pre-allocated resources collaboratively to obtain the fault-tolerant scheduling strategy set of the chip. S4. Based on the trusted execution environment and memory address remapping mechanism in the chip, a redirection test is performed on the fault-tolerant scheduling strategy set to obtain the fault-tolerant scheduling trajectory and resource consumption profile of the chip. S5. Based on the fault-tolerant scheduling trajectory and the resource occupancy profile, compile and bind the fault-tolerant scheduling strategy set to obtain the chip's intrinsic safe memory access microinstructions. S6. Based on the execution feedback of the intrinsically safe memory access microinstruction and the newly generated error events, the soft error prediction framework is incrementally learned to obtain the fault tolerance strategy library of the chip.

[0006] In a preferred embodiment, the step of spatiotemporally aligning the chip's error events, memory access instruction stream segments, and system state parameters to obtain the chip's error feature sequence includes: The chip's error events are intercepted, and the precise clock cycle of the error events is recorded to obtain the chip's event timestamp; Based on the event timestamp, the memory access instruction stream of the chip is synchronously captured to obtain the instruction stream segment of the chip; The system status parameters of the chip are synchronously acquired, and the acquired parameters are bound to the system clock to obtain a snapshot of the chip's system status. Logically associate and bind the instruction stream segment and the system state snapshot to obtain the error feature sequence of the chip.

[0007] In a preferred embodiment, the step of performing dependency mining on the error feature sequence and constructing a soft error prediction framework for the chip based on the mined dependency features includes: By performing directional reasoning on the causes and consequences of the error feature sequence, the causal relationship of the chip can be obtained; The timing, instruction, and system dimensions of the causal relationship are concurrently traversed to obtain the multi-granularity dependency features of the chip; The multi-granularity dependency features are formally transformed, and the rule confidence of the chip is optimized by combining continuous feedback to obtain the causal rule library of the chip. The chip's framework prototype is constructed using a long-term knowledge memory based on the aforementioned causal relationships, a real-time perception based on a multi-scale feature parsing engine, and a reasoning and decision-making core based on the aforementioned causal rule base. The framework prototype is functionally encapsulated to obtain the soft error prediction framework for the chip.

[0008] In a preferred embodiment, the concurrent traversal of the temporal, instruction, and system dimensions in the causal relationship to obtain the multi-granularity dependency features of the chip includes: Based on the error event timestamps in the error feature sequence, the occurrence interval of the error events is periodically detected to obtain the quasi-periodic oscillation mode characteristics of the chip. Based on the instruction sequence before the error event in the error feature sequence, the instruction opcode and address sequence in the causal relationship are extracted to obtain the key instruction sequence pattern features of the chip. Based on the system state parameters and error events in the error feature sequence, a nonlinear analysis is performed on the correlation between the state parameters and the probability of error occurrence in the causal relationship to obtain the state parameter modulation characteristics of the chip. The quasi-periodic oscillation mode features, the key instruction sequence mode features, and the state parameter modulation features are spliced ​​together to obtain the multi-granularity spatiotemporal dependence features of the chip.

[0009] In a preferred embodiment, the step of dynamically marking the memory access instruction stream segments based on the soft error prediction framework and performing resource co-allocation on the marked instructions to obtain the chip's fault-tolerant scheduling strategy set includes: Based on the causal rule base in the soft error prediction framework, multi-level risk rule matching is performed on the memory access instruction stream segment, and the successfully matched instructions are marked as instructions with different risk level labels to obtain the instruction stream of the chip; Instruction clusters are aggregated from the high-risk-level tagged instructions in the instruction stream to obtain risk-homogeneous instruction clusters of the chip; The redundant execution paths, memory protection bandwidth, and error correction processing time slots required by the risk-related instruction clusters are collaboratively planned to obtain the resource pre-allocation sequence of the chip; By weaving the semantic features of the risk-related instruction clusters with the resource planning information in the resource pre-allocation sequence using strategy logic, the fault-tolerant scheduling strategy set of the chip is obtained.

[0010] In a preferred embodiment, the step of performing redirection tests on the fault-tolerant scheduling strategy set based on the trusted execution environment and memory address remapping mechanism in the chip to obtain the fault-tolerant scheduling trajectory and resource usage profile of the chip includes: Based on the memory address remapping mechanism in the chip, a remapping test area isolated from the main memory space is created in the trusted execution environment of the chip, and a mapping relationship is established between the remapping test area and the memory addresses involved in the fault-tolerant scheduling strategy set to construct the isolated verification environment of the chip. Within the remapping test area, the fault-tolerant scheduling strategy set is logically reconstructed to obtain the test execution logic of the chip; The test execution logic is isolated and driven, and the instruction execution path, address access sequence and resource operation events during the operation are monitored and recorded to obtain the chip's original scheduling behavior log; The operation chain is restored from the original scheduling behavior log to obtain the fault-tolerant scheduling trajectory of the chip; The memory bandwidth, protected area capacity, and processing latency of the isolated verification environment are continuously collected to obtain the resource consumption record of the chip; The resource consumption records are reduced by feature reduction to obtain a resource usage profile of the chip.

[0011] In a preferred embodiment, the step of compiling and binding the fault-tolerant scheduling policy set based on the fault-tolerant scheduling trajectory and the resource occupancy profile to obtain the chip's intrinsically safe memory access microinstructions includes: The fault-tolerant scheduling trajectory is semantically parsed to obtain the policy operation semantic flow of the chip; Dependency analysis is performed on the resource usage profile to obtain the strategy resource binding list for the chip; Using the policy operation semantic flow as content and the policy resource binding list as constraints, the fault-tolerant scheduling policy set is encoded with micro-opcodes to obtain the policy micro-opcode sequence of the chip; Based on the strategy micro-opcode sequence, the opcode and address information of the original memory access instructions in the chip are semantically reorganized to obtain the intermediate instruction format of the chip; The intermediate instruction format is encoded and encapsulated to obtain the chip's intrinsically secure memory access microinstructions.

[0012] In a preferred embodiment, the incremental learning of the soft error prediction framework based on the execution feedback of the intrinsically safe memory access microinstructions and emerging error events to obtain the chip's fault tolerance strategy library includes: The execution process of the intrinsically secure memory access microinstruction is periodically monitored to obtain the policy execution feedback record of the chip; The newly generated error events of the intrinsically safe memory access microinstruction are captured in real time to obtain the newly generated error feature sequence of the chip; Based on the policy execution feedback record, the effectiveness of the fault-tolerant scheduling policy set is evaluated to obtain the effectiveness evaluation result of the chip; Based on the newly generated error feature sequence and the effectiveness evaluation results, the causal rule base in the soft error prediction framework is optimized by rule matching to obtain the updated causal rule base of the chip. Based on the updated causal rule base, the memory access instruction stream fragments and the chip's historical policies are reconstructed to obtain the chip's fault tolerance policy base.

[0013] In a preferred embodiment, the calculation formula for updating the causal rule base is: , in ; In the formula, Update the confidence level in the causal rule base. The original confidence level of the causal rule base is given. This is the dynamic adjustment amount of the confidence level in the causal rule base. The time interval for rule updates. The preset time decay constant, The preset learning rate, The preset weight parameters, The policy execution feedback in the policy execution feedback record. The number of times the rule is matched in the newly generated error event.

[0014] To address the above problems, the present invention also provides a chip memory data fault-tolerant processing system, the system comprising: The feature spatiotemporal alignment module is used to perform spatiotemporal alignment on the chip's error events, memory access instruction stream segments, and system status parameters to obtain the chip's error feature sequence. The dependency feature modeling module is used to mine the dependency relationships of the error feature sequence and construct a soft error prediction framework for the chip based on the mined dependency features. The risk scheduling marking module is used to dynamically mark the memory access instruction stream segments based on the soft error prediction framework, and to perform resource collaborative pre-allocation on the marked instructions to obtain the fault-tolerant scheduling strategy set of the chip. The redirection profiling module is used to perform redirection tests on the fault-tolerant scheduling strategy set based on the trusted execution environment and memory address remapping mechanism in the chip, so as to obtain the fault-tolerant scheduling trajectory and resource consumption profile of the chip. The compilation and binding generation module is used to compile and bind the fault-tolerant scheduling strategy set based on the fault-tolerant scheduling trajectory and the resource occupancy profile to obtain the chip's intrinsic safe memory access microinstructions; The incremental learning iteration module is used to incrementally learn the soft error prediction framework based on the execution feedback of the intrinsically safe memory access microinstruction and emerging error events, so as to obtain the fault tolerance strategy library of the chip.

[0015] Compared with the prior art, the present invention has the following beneficial effects: 1. This technology achieves precise spatiotemporal alignment of chip error events, memory access instruction stream segments, and system status parameters, thereby forming an error feature sequence that truly reflects the abnormal patterns of chip operation. Based on a soft error prediction framework built upon multi-granularity dependency feature mining, it can improve the comprehensiveness and accuracy of soft error prediction. The fault-tolerant scheduling strategy set generated by dynamic risk marking and resource collaborative pre-allocation can provide targeted protection for the safe execution of memory access instructions and enhance the stability of chip memory data processing.

[0016] 2. This technology conducts redirection tests based on a trusted execution environment and memory address remapping mechanism, which can accurately obtain fault-tolerant scheduling trajectories and resource usage profiles. The intrinsically safe memory access microinstructions generated by the compilation and binding operations based on this can enhance the intrinsic protection capability of chip memory data. Combined with the incremental learning carried out by the execution feedback of intrinsically safe memory access microinstructions and new error events, it can realize the continuous optimization of the soft error prediction framework and the dynamic improvement of the fault tolerance strategy library, improve the timeliness and adaptability of chip memory fault tolerance processing, and ensure the stable performance of the overall chip. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a chip memory data fault tolerance processing method according to an embodiment of the present invention; Figure 2 This is a functional block diagram of a chip memory data fault-tolerant processing system provided in an embodiment of the present invention; The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0019] This application provides a chip memory data fault tolerance processing method. The execution subject of this chip memory data fault tolerance processing method includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application embodiment: a server, a terminal, etc. In other words, the chip memory data fault tolerance processing method can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster. The server can be an independent server or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms.

[0020] Reference Figure 1 The diagram shown is a flowchart illustrating a chip memory data fault tolerance processing method according to an embodiment of the present invention. In this embodiment, the chip memory data fault tolerance processing method includes: S1. Perform spatiotemporal alignment on the chip's error events, memory access instruction stream segments, and system status parameters to obtain the chip's error feature sequence; In this embodiment of the invention, the step of performing spatiotemporal alignment of the chip's error events, memory access instruction stream segments, and system state parameters to obtain the chip's error feature sequence includes: The chip's error events are intercepted, and the precise clock cycle of the error events is recorded to obtain the chip's event timestamp; Based on the event timestamp, the memory access instruction stream of the chip is synchronously captured to obtain the instruction stream segment of the chip; The system status parameters of the chip are synchronously acquired, and the acquired parameters are bound to the system clock to obtain a snapshot of the chip's system status. Logically associate and bind the instruction stream segment and the system state snapshot to obtain the error feature sequence of the chip.

[0021] The built-in error monitoring unit of the chip is enabled. This unit operates in continuous mode and monitors three types of core abnormal signals during memory read and write processes in real time. The trigger criteria for the data verification failure signal is that the CRC checksum calculated from the memory stored data is inconsistent with the preset checksum. The trigger criteria for the address access out-of-bounds signal is that the instruction target address exceeds the preset legal address range of the chip's memory. The trigger criteria for the bus response timeout signal is that no response feedback is received after more than 10 clock cycles since the memory controller issued the instruction. At the moment any abnormal signal is triggered, the current value of the high-precision system clock module inside the chip is retrieved synchronously. The minimum clock tick of this system clock module is set to 1 nanosecond to record the precise clock cycle of the error event and obtain the event timestamp of the chip.

[0022] Using the clock cycle node corresponding to the acquired event timestamp as a reference point, a range of 100 consecutive clock cycles is traced forward and extended backward to a range of 100 consecutive clock cycles, thus determining a fixed acquisition range of 200 consecutive clock cycles. The start and end clock cycles of this acquisition range are clearly marked. Through the instruction capture interface directly connected to the chip's memory controller instruction output, all memory access instructions issued by the memory controller are extracted within this acquisition range, clock cycle by clock cycle. Instruction information includes operation type, target memory address, and instruction execution identifier. The operation type is specifically divided into three categories: read operation, write operation, and erase operation. The instruction execution identifier is specifically divided into three categories: pending execution, executing, and completed. All extracted instructions are then systematically integrated in order of clock cycle sequence to obtain the chip's instruction stream segment.

[0023] The chip uses a preset status parameter acquisition port, which is configured with independent acquisition channels for four parameters: core operating voltage, chip surface temperature, real-time memory occupancy, and bus data transfer rate. Synchronous acquisition is carried out within the acquisition interval of 200 consecutive clock cycles, which is the same as the acquisition instruction stream segment. The sampling frequency of the four parameters is consistent with the system clock cycle, that is, a full parameter acquisition is completed once per clock cycle. The core operating voltage acquisition range covers the chip's preset normal operating range of 0.8V-1.2V. The chip surface temperature is acquired by a built-in thermistor with an acquisition accuracy of 0.1℃. The real-time memory occupancy is obtained by statistically analyzing the ratio of the currently allocated memory space to the total memory space. The bus data transfer rate is obtained by statistically analyzing the amount of binary data transmitted on the bus in each clock cycle. After each parameter acquisition is completed, the parameter type, parameter value, and corresponding clock cycle value are immediately associated and bound to form a three-dimensional data set with a one-to-one correspondence. After integrating all three-dimensional data sets, a system status snapshot of the chip is obtained.

[0024] Using the clock cycle value as a unified and unique reference, each instruction in the instruction stream segment is traversed, and the clock cycle value corresponding to each instruction is extracted. The three-dimensional data set with the same clock cycle value is retrieved in the system state snapshot. The four retrieved system state parameter data are matched and bound with the corresponding instructions to establish a one-to-one correspondence between a single instruction operation and the corresponding system state. Then, all the bound instruction data and state parameter data are arranged in order from clock cycle to clock cycle. The arranged dataset completely contains the instruction information and system state information within 200 clock cycles before and after the error event, thus obtaining the error feature sequence of the chip.

[0025] The beneficial effects are as follows: by accurately capturing chip error events and recording the corresponding precise clock cycles, the precise anchoring of the error event occurrence time can be achieved. Based on this time anchor, the memory access instruction stream is captured synchronously, and system status parameters are collected and bound to the system clock. This enables a precise correspondence between the error event, the memory access instruction stream fragment, and the system status parameters in the time dimension. Furthermore, by logically associating and binding the instruction stream fragment and the system status snapshot, an error feature sequence that truly reflects the abnormal operation pattern of the chip can be formed. This provides accurate and reliable data support for subsequent error dependency mining and the construction of a soft error prediction framework, thereby improving the overall accuracy and effectiveness of chip memory data fault tolerance processing.

[0026] S2. Perform dependency mining on the error feature sequence, and construct a soft error prediction framework for the chip based on the mined dependency features; In this embodiment of the invention, the step of performing dependency mining on the error feature sequence and constructing a soft error prediction framework for the chip based on the mined dependency features includes: By performing directional reasoning on the causes and consequences of the error feature sequence, the causal relationship of the chip can be obtained; The timing, instruction, and system dimensions of the causal relationship are concurrently traversed to obtain the multi-granularity dependency features of the chip; The multi-granularity dependency features are formally transformed, and the rule confidence of the chip is optimized by combining continuous feedback to obtain the causal rule library of the chip. The chip's framework prototype is constructed using a long-term knowledge memory based on the aforementioned causal relationships, a real-time perception based on a multi-scale feature parsing engine, and a reasoning and decision-making core based on the aforementioned causal rule base. The framework prototype is functionally encapsulated to obtain the soft error prediction framework for the chip.

[0027] The concurrent traversal of the temporal, instruction, and system dimensions in the causal relationship to obtain the multi-granularity dependency features of the chip includes: Based on the error event timestamps in the error feature sequence, the occurrence interval of the error events is periodically detected to obtain the quasi-periodic oscillation mode characteristics of the chip. Based on the instruction sequence before the error event in the error feature sequence, the instruction opcode and address sequence in the causal relationship are extracted to obtain the key instruction sequence pattern features of the chip. Based on the system state parameters and error events in the error feature sequence, a nonlinear analysis is performed on the correlation between the state parameters and the probability of error occurrence in the causal relationship to obtain the state parameter modulation characteristics of the chip. The quasi-periodic oscillation mode features, the key instruction sequence mode features, and the state parameter modulation features are spliced ​​together to obtain the multi-granularity spatiotemporal dependence features of the chip.

[0028] The generated chip error feature sequence is retrieved, and the clock cycle corresponding to the error event is used as the core anchor point to trace the instruction operations and system state parameter changes within a fixed interval before and after the clock cycle. The instruction execution order and state parameter fluctuations before the error event are clarified, and the subsequent instruction anomalies and state parameter offsets caused by the error event are defined. By directionally sorting out the triggering and triggered relationships between error events and instructions and parameters, the causal relationship of the chip is obtained.

[0029] Based on causal relationships, concurrent traversal operations are simultaneously initiated in the timing, instruction, and system dimensions. In the timing dimension, the time intervals between multiple occurrences of error events are statistically analyzed to identify recurring patterns. In the instruction dimension, a fixed number of consecutive instructions before the error event occur are extracted, and the opcode combinations and address access patterns of the instructions are summarized. In the system dimension, the numerical distribution range of system state parameters at the time of the error event is analyzed to clarify the correspondence between parameter values ​​and error occurrence. The traversal results of the three dimensions are integrated to obtain the multi-granularity dependency features of the chip.

[0030] Using a preset feature description specification, multi-granularity dependent features are converted into rule entries with a fixed field structure. Each rule entry includes triggering conditions, feature content, and association results. At the same time, information on the success or failure of rule matching is collected during subsequent strategy execution. The confidence of each rule is adjusted based on the ratio of the actual number of rule matches to the total number of calls. Rules with confidence below a preset threshold are removed, and newly discovered effective rules are added to optimize the library structure, thus obtaining the causal rule library of the chip.

[0031] The causal relationship is used as the long-term knowledge memory of the framework to store historical correlation information between chip error events and instructions and state parameters. The multi-scale feature parsing engine is used as the real-time perception module of the framework to extract features from the real-time input instruction stream and state parameters. The causal rule base is used as the reasoning and decision-making core of the framework to match corresponding rules based on the real-time extracted features. These three parts are combined in the logical order of perception, memory and reasoning to build the framework prototype of the chip.

[0032] The functional interfaces of each component module of the framework prototype are defined, the data transmission format and calling logic between modules are clarified, and the input and output parameters of the framework are standardized and encapsulated. The input parameters are set as the chip's real-time instruction stream and system status parameters, and the output parameters are set as the soft error prediction results. After completing all encapsulation operations, the soft error prediction framework of the chip is obtained.

[0033] The generated chip error feature sequence is retrieved, and the event timestamps corresponding to all error events in the sequence are extracted. The timestamps are arranged in chronological order, and the time interval between two adjacent error event timestamps is calculated. A time interval fluctuation threshold is set, and time intervals with fluctuation amplitude within the threshold range are classified into the same period category. The number of time intervals in the same period category is counted, and the occurrence period attribute of the error event is determined based on the proportion of the number of occurrences, thus obtaining the quasi-periodic oscillation mode characteristics of the chip.

[0034] Extract a fixed number of consecutive memory access instructions preceding each error event in the error feature sequence, extract the opcode and target memory address information for each instruction, arrange the opcode and address information according to the order of instruction execution, count the frequency of opcode combinations, define the address access range corresponding to high-frequency opcode combinations, and associate and bind high-frequency opcode combinations with the corresponding address access ranges to obtain the key instruction sequence pattern features of the chip.

[0035] Retrieve all system state parameter data and corresponding error event records from the error feature sequence, divide the system state parameter value ranges, count the number of error events occurring in each value range, calculate the ratio of the number of error events occurring in each value range to the total number of parameter acquisitions in that range, and analyze the correspondence between changes in parameter value ranges and changes in the error occurrence ratio to obtain the state parameter modulation characteristics of the chip.

[0036] The generated quasi-periodic oscillation mode features, key instruction sequence mode features, and state parameter modulation features are structurally integrated in the order of time sequence dimension, instruction dimension, and system dimension, retaining the complete information of each feature and the corresponding dimension identifier, forming a unified dataset containing features of the three dimensions, thus obtaining the multi-granularity spatiotemporal dependency features of the chip.

[0037] The beneficial effects are as follows: by mining the dependency relationships of error feature sequences and constructing a soft error prediction framework, it is possible to accurately identify the causal relationships between error events and memory access instructions and system state parameters. By combining concurrent traversal of time series, instructions, and systems to extract and integrate corresponding features, a comprehensive and multi-granular dependency feature set that fits the actual operation of the chip can be formed. The causal rule library obtained through formal transformation and rule confidence optimization has higher reliability and adaptability. The soft error prediction framework built and encapsulated based on causal relationships, multi-scale feature parsing engine, and causal rule library can achieve accurate perception and scientific prediction of chip soft errors, providing solid and effective theoretical and data support for the generation of subsequent dynamic risk marking and fault-tolerant scheduling strategies, and improving the overall accuracy and stability of chip memory data fault tolerance processing.

[0038] S3. Based on the soft error prediction framework, the memory access instruction stream segments are dynamically risk-marked, and the marked instructions are pre-allocated resources collaboratively to obtain the fault-tolerant scheduling strategy set of the chip. In this embodiment of the invention, the step of dynamically marking the memory access instruction stream segments based on the soft error prediction framework and performing resource coordinating pre-allocation on the marked instructions to obtain the chip's fault-tolerant scheduling strategy set includes: Based on the causal rule base in the soft error prediction framework, multi-level risk rule matching is performed on the memory access instruction stream segment, and the successfully matched instructions are marked as instructions with different risk level labels to obtain the instruction stream of the chip; Instruction clusters are aggregated from the high-risk-level tagged instructions in the instruction stream to obtain risk-homogeneous instruction clusters of the chip; The redundant execution paths, memory protection bandwidth, and error correction processing time slots required by the risk-related instruction clusters are collaboratively planned to obtain the resource pre-allocation sequence of the chip; By weaving the semantic features of the risk-related instruction clusters with the resource planning information in the resource pre-allocation sequence using strategy logic, the fault-tolerant scheduling strategy set of the chip is obtained.

[0039] The causal rule base in the constructed chip soft error prediction framework is retrieved, and all rule entries containing the correspondence between error triggering conditions and risk levels are extracted. Each instruction in the memory access instruction stream segment is compared with the rule entries to determine whether the instruction meets the rule triggering conditions. Instructions that meet different rule triggering conditions are marked with three preset risk level labels: high, medium, and low. After completing the marking operation of all instructions, the instruction stream of the chip is obtained.

[0040] Extract all instructions marked with high-risk level tags from the instruction stream, classify them according to the opcode type and target memory address segment, group instructions with the same opcode type and target memory address segment in the same preset range into the same set, and verify the execution timing correlation of instructions within the set to ensure that there is a direct or indirect execution dependency relationship between instructions within the set. After completing the classification and integration, the risk homogeneous instruction cluster of the chip is obtained.

[0041] For the instruction execution requirements of each instruction cluster with the same risk, two independent redundant execution paths are planned to avoid the risk of single-path failure. The corresponding memory protection bandwidth is allocated according to the data transmission scale of the instruction cluster, and the bandwidth allocation meets the requirement of the maximum data transmission rate of the instruction cluster. Then, independent error correction processing time slots are divided according to the execution order of instructions within the instruction cluster. The duration of each time slot matches the execution cycle of the corresponding instruction. The planning information of all redundant execution paths, memory protection bandwidth and error correction processing time slots is organized by instruction cluster to obtain the resource pre-allocation sequence of the chip.

[0042] Semantic features are extracted from each risk-related instruction cluster. These features cover the instruction's operation type, execution logic, and error avoidance requirements. The semantic features are then associated with the resource planning information of the corresponding instruction cluster in the resource pre-allocation sequence. This clarifies the redundant path selection, bandwidth usage standard, and time slot allocation scheme for each instruction execution. Finally, all associated information is sorted according to the policy execution priority to form a structured set of policy entries, resulting in the chip's fault-tolerant scheduling policy set.

[0043] The beneficial effects are as follows: by performing multi-level risk rule matching and marking instruction risk levels based on the causal rule base in the soft error prediction framework, it is possible to accurately distinguish instructions with different risk levels in memory access instruction stream segments. By aggregating high-risk instructions from the same source, centralized management of risky instructions can be achieved. By carrying out collaborative planning of redundant execution paths, memory protection bandwidth, and error correction processing time slots for risky instruction clusters from the same source, the rationality and sufficiency of resource allocation can be ensured, avoiding resource waste or insufficient resources. By weaving the semantic features of instruction clusters and resource planning information into policy logic, a set of fault-tolerant scheduling policies with clear execution logic and resource constraints can be formed, providing accurate and feasible execution basis for fault-tolerant processing of chip memory data, and improving the fault-tolerant response efficiency and overall security of chip memory operation.

[0044] S4. Based on the trusted execution environment and memory address remapping mechanism in the chip, a redirection test is performed on the fault-tolerant scheduling strategy set to obtain the fault-tolerant scheduling trajectory and resource consumption profile of the chip. In this embodiment of the invention, the step of performing redirection tests on the fault-tolerant scheduling strategy set based on the trusted execution environment and memory address remapping mechanism in the chip to obtain the fault-tolerant scheduling trajectory and resource usage profile of the chip includes: Based on the memory address remapping mechanism in the chip, a remapping test area isolated from the main memory space is created in the trusted execution environment of the chip, and a mapping relationship is established between the remapping test area and the memory addresses involved in the fault-tolerant scheduling strategy set to construct the isolated verification environment of the chip. Within the remapping test area, the fault-tolerant scheduling strategy set is logically reconstructed to obtain the test execution logic of the chip; The test execution logic is isolated and driven, and the instruction execution path, address access sequence and resource operation events during the operation are monitored and recorded to obtain the chip's original scheduling behavior log; The operation chain is restored from the original scheduling behavior log to obtain the fault-tolerant scheduling trajectory of the chip; The memory bandwidth, protected area capacity, and processing latency of the isolated verification environment are continuously collected to obtain the resource consumption record of the chip; The resource consumption records are reduced by feature reduction to obtain a resource usage profile of the chip.

[0045] The chip's memory address remapping mechanism is enabled. Within the pre-defined trusted execution environment of the chip, a physical storage area that does not overlap with the main memory space address range is designated as the remapping test area. All target memory addresses involved in the fault-tolerant scheduling strategy set are extracted. A unique mapping address corresponding to each target memory address is assigned within the remapping test area. A one-to-one correspondence between the target memory address and the mapping address is established. The mapping relationship is then permanently stored, and the isolated verification environment of the chip is constructed.

[0046] Within the constructed remapping test area, all policy entries in the fault-tolerant scheduling policy set are retrieved, and all target memory addresses involved in the policy entries are replaced with the corresponding mapping addresses. The instruction execution logic, resource call order, and risk handling rules in the policy entries remain unchanged. All the replaced policy entries are sorted according to their execution priority to form an ordered logical execution sequence, thus obtaining the test execution logic of the chip.

[0047] The chip's built-in isolation driver module is activated. This module only allocates running resources to the remapped test area and does not interact with the main memory space. Under the control of the isolation driver module, the test execution logic runs. At the same time, the chip's operation monitoring unit is activated. This unit records the instruction execution path switching nodes, address access sequence change information, and resource operation event types during the test execution logic operation cycle by clock cycle. All recorded information is integrated in chronological order to obtain the chip's original scheduling behavior log.

[0048] The generated original scheduling behavior logs are retrieved, and the log content is parsed line by line in the order of clock cycles. The initiation time, execution path selection, address access process and resource interaction details of each instruction are restored. The triggering dependencies and execution order between instructions are sorted out to form a complete and continuous strategy execution operation chain, and the fault-tolerant scheduling trajectory of the chip is obtained.

[0049] The chip's resource monitoring unit is enabled to continuously collect three core resource data in the isolated verification environment throughout the entire test execution logic process. The memory bandwidth data is the real-time bandwidth usage value, the protected area capacity data is the ratio of used storage capacity to total capacity, and the processing latency data is the time from the initiation of each instruction to its completion. The three data are correlated and integrated according to the collection time to obtain the chip's resource consumption record.

[0050] The resource consumption records are classified and processed to remove redundant data collected repeatedly. The numerical variation patterns of three data points—memory bandwidth, protection area capacity, and processing latency—are extracted at different test stages. These variation patterns are then associated with the corresponding strategy execution stages to form a structured data set that covers the correspondence between resource consumption characteristics and strategy execution stages, thus obtaining a resource occupancy profile of the chip.

[0051] The beneficial effects are as follows: By constructing an isolated verification environment based on the chip's trusted execution environment and memory address remapping mechanism, the fault-tolerant scheduling strategy set and the main memory space can be physically isolated, avoiding interference with the normal operation of the chip during the testing process. The fault-tolerant scheduling strategy set can be logically reconstructed within the remapping test area to form execution logic adapted to the test scenario, ensuring the feasibility and accuracy of the test process. Isolating and driving the test execution logic and monitoring and recording relevant running information can completely retain key data during the strategy execution process. By restoring the operation chain from the original scheduling behavior log, a clear and complete fault-tolerant scheduling trajectory can be obtained. Continuously collecting resource data from the isolated verification environment and performing feature reduction can form an intuitive and accurate resource occupancy profile. The scheduling trajectory and resource occupancy profile obtained during the overall testing process can serve as the core basis for subsequent compilation and binding operations, improving the adaptability and reliability of the chip's memory fault-tolerant processing strategy.

[0052] S5. Based on the fault-tolerant scheduling trajectory and the resource occupancy profile, compile and bind the fault-tolerant scheduling strategy set to obtain the chip's intrinsic safe memory access microinstructions. In this embodiment of the invention, the step of compiling and binding the fault-tolerant scheduling strategy set based on the fault-tolerant scheduling trajectory and the resource occupancy profile to obtain the chip's intrinsically secure memory access microinstructions includes: The fault-tolerant scheduling trajectory is semantically parsed to obtain the policy operation semantic flow of the chip; Dependency analysis is performed on the resource usage profile to obtain the strategy resource binding list for the chip; Using the policy operation semantic flow as content and the policy resource binding list as constraints, the fault-tolerant scheduling policy set is encoded with micro-opcodes to obtain the policy micro-opcode sequence of the chip; Based on the strategy micro-opcode sequence, the opcode and address information of the original memory access instructions in the chip are semantically reorganized to obtain the intermediate instruction format of the chip; The intermediate instruction format is encoded and encapsulated to obtain the chip's intrinsically secure memory access microinstructions.

[0053] The generated chip fault-tolerant scheduling trajectory is retrieved, and the instruction execution order, resource call logic, error handling actions, and path switching nodes contained in the trajectory are extracted. These contents are structured and sorted out to clarify the semantic actions and execution logic corresponding to each strategy step, forming a set of semantic information arranged in the execution sequence, thus obtaining the strategy operation semantic flow of the chip.

[0054] Retrieve the generated chip resource usage profile, analyze the correspondence between the three types of resource consumption data (memory bandwidth, protected area capacity, and processing latency) in the profile and the policy execution steps, determine the resource requirement type and usage threshold for each policy step, associate the policy entries with the corresponding resource configuration information one by one, form a corresponding document containing policy execution steps and resource constraints, and obtain the policy resource binding list of the chip.

[0055] Each semantic action in the policy operation semantic flow is used as the encoding content, and the resource constraints in the policy resource binding list are used as the encoding basis. Referring to the chip's preset micro-operation code encoding specification, a unique corresponding micro-operation code is assigned to each semantic action. During the encoding process, it is ensured that the resource occupancy parameters do not exceed the threshold range set in the binding list. All encoded micro-operation codes are arranged according to the semantic execution order to obtain the chip's policy micro-operation code sequence.

[0056] The original memory access instructions of the chip are retrieved, and the original opcode information in the original instructions is replaced based on the policy micro-opcode sequence. At the same time, the memory address information in the instructions is adjusted according to the policy resource binding list to adapt to the address mapping relationship and resource allocation scheme of the remapping test area, while keeping the instruction execution logic and error handling function unchanged, thus obtaining the intermediate instruction format of the chip.

[0057] The intermediate instruction format is standardized and encapsulated by adding instruction check bits, resource binding identifiers and execution priority tags. The encapsulated instruction format conforms to the instruction reading specifications of the chip execution unit and can be directly recognized and executed by the chip. After completing all encapsulation operations, the chip's intrinsic secure memory access microinstructions are obtained.

[0058] The beneficial effects are as follows: by performing semantic structure analysis on the fault-tolerant scheduling trajectory to obtain the policy operation semantic flow, the core logic and action direction of policy execution can be accurately extracted; by performing dependency analysis on the resource occupancy profile to obtain the policy resource binding list, the resource requirements and constraint boundaries in the policy execution process can be clearly defined; by using the policy operation semantic flow as content and the policy resource binding list as constraints to encode the fault-tolerant scheduling policy set with micro-opcodes, the policy can be transformed into a chip-recognizable encoding form; by semantically recombining the original memory access instructions based on the policy micro-opcode sequence to obtain the intermediate instruction format, the instructions can be adapted to the execution requirements of the fault-tolerant policy; and by encoding and encapsulating the intermediate instruction format to obtain the intrinsically safe memory access micro-instructions, the executable instructions with intrinsic protection capabilities can be generated, providing a direct execution basis for chip memory data fault tolerance processing and improving the security and stability of chip memory access.

[0059] S6. Based on the execution feedback of the intrinsically safe memory access microinstruction and the newly generated error events, the soft error prediction framework is incrementally learned to obtain the fault tolerance strategy library of the chip.

[0060] In this embodiment of the invention, the incremental learning of the soft error prediction framework based on the execution feedback of the intrinsically safe memory access microinstruction and emerging error events to obtain the fault tolerance strategy library of the chip includes: The execution process of the intrinsically secure memory access microinstruction is periodically monitored to obtain the policy execution feedback record of the chip; The newly generated error events of the intrinsically safe memory access microinstruction are captured in real time to obtain the newly generated error feature sequence of the chip; Based on the policy execution feedback record, the effectiveness of the fault-tolerant scheduling policy set is evaluated to obtain the effectiveness evaluation result of the chip; Based on the newly generated error feature sequence and the effectiveness evaluation results, the causal rule base in the soft error prediction framework is optimized by rule matching to obtain the updated causal rule base of the chip. Based on the updated causal rule base, the memory access instruction stream fragments and the chip's historical policies are reconstructed to obtain the chip's fault tolerance policy base.

[0061] The calculation formula for updating the causal rule base is as follows: , in ; In the formula, Update the confidence level in the causal rule base. The original confidence level of the causal rule base is given. This is the dynamic adjustment amount of the confidence level in the causal rule base. The time interval for rule updates. The preset time decay constant, The preset learning rate, The preset weight parameters, The policy execution feedback in the policy execution feedback record. The number of times the rule is matched in the newly generated error event.

[0062] The chip's built-in instruction execution monitoring unit is enabled. This unit continuously monitors the execution process of the intrinsically safe memory access microinstructions according to the chip's minimum operating clock cycle. The monitoring content covers the instruction's start time, execution progress, resource usage compliance, and error avoidance effectiveness. All monitoring data is continuously recorded in chronological order to obtain the chip's strategy execution feedback record.

[0063] The chip's error event capture unit is enabled. This unit monitors new abnormal signals that occur during the execution of the intrinsic safe memory access microinstruction in real time. When an abnormal signal is triggered, the clock cycle of the error, the corresponding instruction content, and the system status parameters are recorded immediately. All the recorded new error-related information is arranged in chronological order to obtain the chip's new error feature sequence.

[0064] Retrieve the generated strategy execution feedback records, set the effectiveness judgment criteria for strategy execution, and the criteria include three core indicators: error avoidance success rate, resource consumption control compliance rate, and instruction execution completion rate. Compare the actual data in the feedback records with the judgment criteria item by item, and classify the effectiveness level of the strategy according to the comparison results to obtain the effectiveness evaluation result of the chip.

[0065] The generated new error feature sequence and effectiveness evaluation results are retrieved. The error types in the new error feature sequence are matched with the existing rules in the causal rule base within the soft error prediction framework. Rules that are determined to be efficient in the effectiveness evaluation results are retained. New rules corresponding to new errors are added. The triggering conditions of inefficient rules are adjusted to complete the optimization of the causal rule base and obtain the updated causal rule base of the chip.

[0066] The generated updated causal rule base is retrieved and used as the core basis for policy reconstruction. Combined with the feature information of memory access instruction stream segments and the content of effectiveness evaluation in the chip's historical policies, fault-tolerant policies adapted to different error types are generated according to the new rule logic. All generated policies are classified and integrated to obtain the fault-tolerant policy library of the chip.

[0067] The original confidence level of the causal rule base is the initial confidence level value set for each rule in the causal rule base within the soft error prediction framework.

[0068] The update confidence level of the causal rule base is the confidence level value of each rule after the causal rule base is optimized.

[0069] The dynamic adjustment of confidence in the causal rule base is a confidence adjustment value calculated by combining policy execution feedback and newly generated error events.

[0070] The rule update interval is the time difference between two rule matching optimization operations performed on the causal rule base.

[0071] The preset time decay constant is a fixed value that is pre-set to measure the degree to which confidence decays over time.

[0072] The preset learning rate is a fixed value set in advance to control the range of confidence adjustment.

[0073] The preset weight parameters are fixed values ​​that are pre-set to balance the impact of policy execution feedback and emerging error events on confidence adjustment.

[0074] The policy execution feedback in the policy execution feedback record is the feedback information obtained from monitoring the execution process of the intrinsically safe memory access microinstruction.

[0075] The number of rule matches in a newborn error event is the number of rule matches counted within the newborn error feature sequence obtained from the real-time capture of the newborn error event of the intrinsically safe memory access microinstruction.

[0076] The purpose of this content is to optimize the rule matching of the causal rule base in the soft error prediction framework. By combining the number of rule matches between the policy execution feedback in the policy execution feedback record and the newly generated error feature sequence, the confidence of each rule in the causal rule base is adjusted. This makes the adjusted causal rule base more accurately adaptable to the actual needs of chip memory data fault tolerance processing, improves the prediction accuracy of the soft error prediction framework, and provides a reliable basis for subsequent reconstruction of fault tolerance strategies based on the updated causal rule base. Ultimately, a more adaptable fault tolerance strategy library for the chip is obtained.

[0077] The beneficial effects are as follows: by periodically monitoring the execution process of intrinsically safe memory access microinstructions and obtaining policy execution feedback records, the actual execution effectiveness of the policies can be grasped in real time. New error events can be captured in real time and new error feature sequences can be generated, which can promptly discover new error patterns that occur during chip operation. Based on the feedback records, the effectiveness of the fault-tolerant scheduling policy set can be evaluated, and the effectiveness level of the policies can be accurately determined. By combining the new error feature sequences and effectiveness evaluation results, the causal rule base in the soft error prediction framework can be matched and optimized, enabling dynamic iterative updates of the rule base and continuously improving the prediction accuracy of the framework. Based on the updated causal rule base, the memory access instruction stream fragments and historical policies can be reconstructed to generate a more adaptable fault-tolerant policy library, providing continuously optimized policy support for chip memory data fault tolerance processing and improving the timeliness and stability of the chip's overall fault tolerance capability.

[0078] like Figure 2 The diagram shown is a functional block diagram of a chip memory data fault-tolerant processing system provided in an embodiment of the present invention.

[0079] The chip memory data fault-tolerant processing system 100 described in this invention can be installed in an electronic device. Depending on the functions implemented, the chip memory data fault-tolerant processing system 100 may include a feature spatiotemporal alignment module 101, a dependent feature modeling module 102, a risk scheduling and marking module 103, a redirection profiling module 104, a compilation and binding generation module 105, and an incremental learning iteration module 106. The modules described in this invention can also be referred to as units, which are a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, stored in the memory of the electronic device.

[0080] In this embodiment, the functions of each module / unit are as follows: The feature spatiotemporal alignment module 101 is used to perform spatiotemporal alignment on the chip's error events, memory access instruction stream segments, and system status parameters to obtain the chip's error feature sequence. The dependency feature modeling module 102 is used to mine the dependency relationship of the error feature sequence and construct the soft error prediction framework of the chip based on the mined dependency features. The risk scheduling marking module 103 is used to dynamically mark the memory access instruction stream segments based on the soft error prediction framework, and to perform resource collaborative pre-allocation on the marked instructions to obtain the fault-tolerant scheduling strategy set of the chip. The redirection profiling module 104 is used to perform redirection tests on the fault-tolerant scheduling strategy set based on the trusted execution environment and memory address remapping mechanism in the chip, so as to obtain the fault-tolerant scheduling trajectory and resource usage profile of the chip. The compilation and binding generation module 105 is used to compile and bind the fault-tolerant scheduling strategy set based on the fault-tolerant scheduling trajectory and the resource occupancy profile to obtain the chip's intrinsic safe memory access microinstructions. The incremental learning iteration module 106 is used to perform incremental learning on the soft error prediction framework based on the execution feedback of the intrinsically safe memory access microinstruction and the newly generated error events, so as to obtain the fault tolerance strategy library of the chip.

[0081] In the several embodiments provided by this invention, it should be understood that the disclosed methods and systems can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.

[0082] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0083] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0084] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0085] This application embodiment can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence is the theory, method, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for fault-tolerant processing of chip memory data, characterized in that, The method includes: S1. Perform spatiotemporal alignment on the chip's error events, memory access instruction stream segments, and system status parameters to obtain the chip's error feature sequence; S2. Perform dependency mining on the error feature sequence, and construct a soft error prediction framework for the chip based on the mined dependency features; S3. Based on the soft error prediction framework, the memory access instruction stream segments are dynamically risk-marked, and the marked instructions are pre-allocated resources collaboratively to obtain the fault-tolerant scheduling strategy set of the chip. S4. Based on the trusted execution environment and memory address remapping mechanism in the chip, a redirection test is performed on the fault-tolerant scheduling strategy set to obtain the fault-tolerant scheduling trajectory and resource consumption profile of the chip. S5. Based on the fault-tolerant scheduling trajectory and the resource occupancy profile, compile and bind the fault-tolerant scheduling strategy set to obtain the chip's intrinsic safe memory access microinstructions. S6. Based on the execution feedback of the intrinsically safe memory access microinstruction and the newly generated error events, the soft error prediction framework is incrementally learned to obtain the fault tolerance strategy library of the chip.

2. The chip memory data fault tolerance processing method as described in claim 1, characterized in that, The process of spatiotemporally aligning the chip's error events, memory access instruction stream fragments, and system state parameters to obtain the chip's error feature sequence includes: The chip's error events are intercepted, and the precise clock cycle of the error events is recorded to obtain the chip's event timestamp; Based on the event timestamp, the memory access instruction stream of the chip is synchronously captured to obtain the instruction stream segment of the chip; The system status parameters of the chip are synchronously acquired, and the acquired parameters are bound to the system clock to obtain a snapshot of the chip's system status. Logically associate and bind the instruction stream segment and the system state snapshot to obtain the error feature sequence of the chip.

3. The chip memory data fault tolerance processing method as described in claim 1, characterized in that, The step of performing dependency mining on the error feature sequence and constructing a soft error prediction framework for the chip based on the mined dependency features includes: By performing directional reasoning on the causes and consequences of the error feature sequence, the causal relationship of the chip can be obtained; The timing, instruction, and system dimensions of the causal relationship are concurrently traversed to obtain the multi-granularity dependency features of the chip; The multi-granularity dependency features are formally transformed, and the rule confidence of the chip is optimized by combining continuous feedback to obtain the causal rule library of the chip. The chip's framework prototype is constructed using a long-term knowledge memory based on the aforementioned causal relationships, a real-time perception based on a multi-scale feature parsing engine, and a reasoning and decision-making core based on the aforementioned causal rule base. The framework prototype is functionally encapsulated to obtain the soft error prediction framework for the chip.

4. The chip memory data fault tolerance processing method as described in claim 3, characterized in that, The concurrent traversal of the temporal, instruction, and system dimensions in the causal relationship to obtain the multi-granularity dependency features of the chip includes: Based on the error event timestamps in the error feature sequence, the occurrence interval of the error events is periodically detected to obtain the quasi-periodic oscillation mode characteristics of the chip. Based on the instruction sequence before the error event in the error feature sequence, the instruction opcode and address sequence in the causal relationship are extracted to obtain the key instruction sequence pattern features of the chip. Based on the system state parameters and error events in the error feature sequence, a nonlinear analysis is performed on the correlation between the state parameters and the probability of error occurrence in the causal relationship to obtain the state parameter modulation characteristics of the chip. The quasi-periodic oscillation mode features, the key instruction sequence mode features, and the state parameter modulation features are spliced ​​together to obtain the multi-granularity spatiotemporal dependence features of the chip.

5. The chip memory data fault tolerance processing method as described in claim 1, characterized in that, Based on the soft error prediction framework, the memory access instruction stream segments are dynamically risk-marked, and resource coordinating pre-allocation is performed on the marked instructions to obtain the chip's fault-tolerant scheduling strategy set, including: Based on the causal rule base in the soft error prediction framework, multi-level risk rule matching is performed on the memory access instruction stream segment, and the successfully matched instructions are marked as instructions with different risk level labels to obtain the instruction stream of the chip; Instruction clusters are aggregated from the high-risk-level tagged instructions in the instruction stream to obtain risk-homogeneous instruction clusters of the chip; The redundant execution paths, memory protection bandwidth, and error correction processing time slots required by the risk-related instruction clusters are collaboratively planned to obtain the resource pre-allocation sequence of the chip; By weaving the semantic features of the risk-related instruction clusters with the resource planning information in the resource pre-allocation sequence using strategy logic, the fault-tolerant scheduling strategy set of the chip is obtained.

6. The chip memory data fault tolerance processing method as described in claim 1, characterized in that, The method of performing redirection tests on the fault-tolerant scheduling strategy set based on the trusted execution environment and memory address remapping mechanism in the chip, to obtain the fault-tolerant scheduling trajectory and resource usage profile of the chip, including: Based on the memory address remapping mechanism in the chip, a remapping test area isolated from the main memory space is created in the trusted execution environment of the chip, and a mapping relationship is established between the remapping test area and the memory addresses involved in the fault-tolerant scheduling strategy set to construct the isolated verification environment of the chip. Within the remapping test area, the fault-tolerant scheduling strategy set is logically reconstructed to obtain the test execution logic of the chip; The test execution logic is isolated and driven, and the instruction execution path, address access sequence and resource operation events during the operation are monitored and recorded to obtain the chip's original scheduling behavior log; The operation chain is restored from the original scheduling behavior log to obtain the fault-tolerant scheduling trajectory of the chip; The memory bandwidth, protected area capacity, and processing latency of the isolated verification environment are continuously collected to obtain the resource consumption record of the chip; The resource consumption records are reduced by feature reduction to obtain a resource usage profile of the chip.

7. The chip memory data fault tolerance processing method as described in claim 1, characterized in that, The process of compiling and binding the fault-tolerant scheduling strategy set based on the fault-tolerant scheduling trajectory and the resource occupancy profile to obtain the chip's intrinsically safe memory access microinstructions includes: The fault-tolerant scheduling trajectory is semantically parsed to obtain the policy operation semantic flow of the chip; Dependency analysis is performed on the resource usage profile to obtain the strategy resource binding list for the chip; Using the policy operation semantic flow as content and the policy resource binding list as constraints, the fault-tolerant scheduling policy set is encoded with micro-opcodes to obtain the policy micro-opcode sequence of the chip; Based on the strategy micro-opcode sequence, the opcode and address information of the original memory access instructions in the chip are semantically reorganized to obtain the intermediate instruction format of the chip; The intermediate instruction format is encoded and encapsulated to obtain the chip's intrinsically secure memory access microinstructions.

8. The chip memory data fault tolerance processing method as described in claim 1, characterized in that, The soft error prediction framework is incrementally learned based on the execution feedback and emerging error events of the intrinsically safe memory access microinstructions to obtain the chip's fault tolerance strategy library, including: The execution process of the intrinsically secure memory access microinstruction is periodically monitored to obtain the policy execution feedback record of the chip; The newly generated error events of the intrinsically safe memory access microinstruction are captured in real time to obtain the newly generated error feature sequence of the chip; Based on the policy execution feedback record, the effectiveness of the fault-tolerant scheduling policy set is evaluated to obtain the effectiveness evaluation result of the chip; Based on the newly generated error feature sequence and the effectiveness evaluation results, the causal rule base in the soft error prediction framework is optimized by rule matching to obtain the updated causal rule base of the chip. Based on the updated causal rule base, the memory access instruction stream fragments and the chip's historical policies are reconstructed to obtain the chip's fault tolerance policy base.

9. The chip memory data fault-tolerant processing method as described in claim 8, characterized in that, The calculation formula for updating the causal rule base is as follows: ， in ; In the formula, Update the confidence level in the causal rule base. The original confidence level of the causal rule base is given. This is the dynamic adjustment amount of the confidence level in the causal rule base. The time interval for rule updates. The preset time decay constant, The preset learning rate, The preset weight parameters, The policy execution feedback in the policy execution feedback record. The number of times the rule is matched in the newly generated error event.

10. A chip memory data fault-tolerant processing system, characterized in that, The system for implementing the chip memory data fault-tolerant processing method according to claim 1 includes: The feature spatiotemporal alignment module is used to perform spatiotemporal alignment on the chip's error events, memory access instruction stream segments, and system status parameters to obtain the chip's error feature sequence. The dependency feature modeling module is used to mine the dependency relationships of the error feature sequence and construct a soft error prediction framework for the chip based on the mined dependency features. The risk scheduling marking module is used to dynamically mark the memory access instruction stream segments based on the soft error prediction framework, and to perform resource collaborative pre-allocation on the marked instructions to obtain the fault-tolerant scheduling strategy set of the chip. The redirection profiling module is used to perform redirection tests on the fault-tolerant scheduling strategy set based on the trusted execution environment and memory address remapping mechanism in the chip, so as to obtain the fault-tolerant scheduling trajectory and resource consumption profile of the chip. The compilation and binding generation module is used to compile and bind the fault-tolerant scheduling strategy set based on the fault-tolerant scheduling trajectory and the resource occupancy profile to obtain the chip's intrinsic safe memory access microinstructions; The incremental learning iteration module is used to incrementally learn the soft error prediction framework based on the execution feedback of the intrinsically safe memory access microinstruction and emerging error events, so as to obtain the fault tolerance strategy library of the chip.

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