FPGA-based LVDS communication system and communication method

Abstract

The application discloses an FPGA-based LVDS communication system, wherein a data sending unit and a data receiving unit of the FPGA-based LVDS communication system are connected through 4-way LVDS link signal lines, and through configuration of a control primitive and a corresponding communication protocol, fast transmission of various data between a mainboard FPGA and a daughterboard FPGA is realized. The bidirectional transmission rate between the mainboard FPGA and the daughterboard FPGA of the communication system can reach 3.2 Gbps, the error code rate is less than 1x10 ‑14 , and the one-way data delay is less than 100 ns, which fully meets the communication requirements of 50Mbps-5Gbps interconnection between boards. The communication system supports modular design, and when software development is carried out, the details of the underlying LVDS protocol do not need to be concerned, the development cost of interconnection between boards of a multi-slot plug-in card type hardware system can be effectively reduced, and the development speed of the multi-slot plug-in card type hardware system is improved.

Description

Technical Field

[0001] This invention relates to FPGA communication technology, and in particular to a system and method for communication between a motherboard FPGA and a daughterboard FPGA in a multi-slot plug-in card system using LVDS. Background Technology

[0002] In multi-slot plug-in card hardware systems, a modular architecture consisting of a motherboard, backplane, and multiple functional daughterboards is commonly used, and this is widely applied in telecommunications equipment, test and measurement instruments, and industrial computing platforms. To achieve data interaction and device control between the motherboard and its daughterboards, the industry has developed several mature inter-board communication interfaces. These interfaces differ significantly in their applicable scenarios, bandwidth, cost, and design complexity. Among them, PCIe, SRIO, AURORA, and Ethernet are high-speed serial interfaces with ultra-large transmission bandwidth, capable of meeting the needs of ultra-high bit rate data transmission. However, these interfaces have complex hardware designs, large protocol stacks, and high material and R&D costs. Using these interfaces in medium-bandwidth applications (100Mbps-5Gbps) would result in resource redundancy and cost waste. SPI, IIC, and GPIO are low-speed general-purpose interfaces with fewer hardware pins and simpler circuit implementation, but their transmission bandwidth is generally below 50Mbps. They are only suitable for simple control command interactions and cannot support high-speed data streams, making them unsuitable for medium-to-high-speed transmission scenarios. Therefore, how to design a low-cost communication system with a transmission rate of 100Mbps-5Gbps is a technical issue that many hardware manufacturers are generally concerned about.

[0003] Low-voltage differential signaling (LVDS) interfaces have become the preferred solution for medium-bandwidth inter-board communication due to their advantages of low power consumption, low bit error rate, low transmission latency, and strong anti-interference capability. Taking the Xilinx Spartan-7 series of low-cost FPGAs as an example, the single-channel LVDS interface can achieve a speed of 950Mb / s-1250Mb / s. Through multi-channel bonding, the total bandwidth can be extended to within 5Gbps, perfectly covering the aforementioned medium-bandwidth range. At the same time, the hardware cost is far lower than that of high-end high-speed interfaces such as PCIe, making it extremely valuable for applications.

[0004] Invention patent CN202211033710.5 discloses an FPGA-based LVDS high-speed communication system and method. This system consists of an LVDS circuit and a corresponding FPGA program module, used to achieve high-speed communication between FPGA chips. The LVDS circuit uses a combination of one pair of clock differential lines and multiple pairs of data differential lines. Both the clock and data differential lines adopt the LVDS level standard, running serialized high-speed signals on the differential lines to improve data transmission speed. While this solution can improve data transmission rate, it cannot adapt to the diverse data communication needs between the motherboard and various daughterboards in multi-slot plug-in card systems. For communication scenarios between different functional daughterboard FPGAs and the motherboard FPGA, specific adaptation and modification of the underlying LVDS communication protocol are required, resulting in high hardware and software design costs and long development cycles. Based on these problems, there is an urgent need to optimize and improve the existing LVDS communication system and method between FPGAs in multi-slot plug-in card systems. Summary of the Invention

[0005] To address the aforementioned issues, this invention provides a system and method for communication between the motherboard FPGA and the daughterboard FPGA in a multi-slot plug-in card system using LVDS, thus solving the technical challenges of high hardware and software design costs, long design cycles, and insufficient communication bandwidth in existing multi-slot plug-in card devices for inter-board communication.

[0006] An FPGA-based LVDS communication system includes a first FPGA chip and a second FPGA chip. Both the first and second FPGA chips have a data transmission unit and a data reception unit. The data transmission unit of the first FPGA chip and the data reception unit of the second FPGA chip are connected via an LVDS data transmission bus. The data transmission unit of the second FPGA chip and the data reception unit of the first FPGA chip are also connected via an LVDS data transmission bus. The LVDS data transmission bus includes four LVDS link signal lines, one LVDS clock signal line, and one GPIO control interface signal line. The LVDS link signal lines are used for data transmission, the LVDS clock signal line provides the LVDS data transmission clock signal, and the GPIO control interface signal line sends a feedback signal to the data transmission unit after the four LVDS link signal lines are ready for data transmission. The data transmission unit and the corresponding data reception unit communicate via the LVDS data transmission bus to transmit control primitives, data packets, and command packets to achieve the transmission of service data streams between the first and second FPGAs.

[0007] Preferably, the data transmission unit includes a primitive generation module, a command packet generation module, a data transmission FIFO module, a data processing module, a data transmission control module, and a data parallel-to-serial conversion module. The primitive generation module generates control primitives for the communication protocol and sends them to the data transmission control module. The data transmission FIFO module stores downlink FIFO data and sends it to the data processing module. The data processing module converts the data to be transmitted into data packets of a specified format and sends them to the data transmission control module. The command packet generation module reads command parameters from the upper-layer application software in the local register and converts them into command packets of a specified format, sending them to the data transmission control module. The data transmission control module sends control primitives, data packets, and command packets to the data parallel-to-serial conversion module according to priority. The data parallel-to-serial conversion module converts the control primitives, data packets, and command packets into four serial data streams and sends them to the data receiving unit via LVDS link signal lines.

[0008] Preferably, the data receiving unit includes a data serial-to-parallel conversion module, a data receiving control module, a data packet parsing module, a command packet parsing module, and a data receiving FIFO module. The data serial-to-parallel conversion module is used to convert the received four-channel serial data into parallel data. The data receiving control module is used to send the received data packets and command packets to the corresponding data packet parsing module or command packet parsing module. The data packet parsing module is used to parse the data packets into raw transmission data and send them to the data receiving FIFO module for storage. The command packet parsing module is used to parse the received command packets, access the local registers according to the content of the command packets, and generate corresponding response command packets.

[0009] Preferably, the data parallel-to-serial conversion module is used to convert 32-bit parallel data into 4 channels of 8-bit serial data, and the data serial-to-parallel conversion module is used to convert 4 channels of 8-bit serial data into 32-bit parallel data. The data parallel-to-serial conversion module and the data serial-to-parallel conversion module are connected through 4 LVDS link signal lines.

[0010] Preferably, both the command packet generation module and the command packet parsing module are connected to the AXI-Lite interface.

[0011] Preferably, the data sending unit further includes a flow control module, which has a credit value. The flow control module is connected to the data sending control module. The credit value is decremented by 1 for each data packet sent by the data sending control module. When the credit value is 0, the data sending control module stops sending data packets.

[0012] This invention also discloses a communication method using the above-mentioned FPGA-based LVDS communication system, which includes the following steps: In the initial state, the data sending unit sends training primitives to the corresponding data receiving unit to perform bit-alignment and byte-alignment training on the four LVDS link signal lines. After the data receiving unit completes the training, it sends a feedback signal indicating that the training is complete to the data sending unit through the GPIO control interface signal line, indicating that the data transmission of the four LVDS link signal lines is ready. After the data transmission of the LVDS link signal lines is ready, the data sending unit and the corresponding data receiving unit transmit control primitives, data packets, and command packets through the LVDS data transmission bus to realize the transmission of service data streams between the motherboard FPGA and the daughterboard FPGA. During the data transmission process, the priority of the command packet is higher than that of the data packet.

[0013] Preferably, when the first FPGA chip sends a request command to the second FPGA chip, the data sending unit of the first FPGA chip sends the request command packet to the data receiving unit of the second FPGA chip through four LVDS link signal lines. The data receiving unit parses and executes the request command packet, generates a corresponding response command packet, and then sends the response command packet to the data receiving unit of the first FPGA chip through the data sending unit of the second FPGA chip.

[0014] Preferably, during the process of the first FPGA chip sending data packets to the second FPGA chip, the data sending unit of the first FPGA chip sets a credit value. The credit value of the first FPGA chip is decremented by 1 for each data packet sent. When the credit value is 0, the data sending unit stops sending data packets.

[0015] Preferably, when the second FPGA chip data receiving unit receives a data packet, the second FPGA chip data receiving unit sends a request signal to the second FPGA chip data sending unit. The second FPGA chip data sending unit generates a reception confirmation primitive and sends it to the first FPGA chip data receiving unit. After receiving the reception confirmation primitive, the first FPGA chip data receiving unit increments its credit value by 1.

[0016] The above technical solution has the following beneficial effects: The data transmission unit and data reception unit of this FPGA-based LVDS communication system are connected through four LVDS link signal lines. By configuring control primitives and corresponding communication protocols, it enables rapid data transmission between the motherboard FPGA and the daughterboard FPGA, effectively meeting the communication requirements of multi-slot plug-in card systems. The bidirectional transmission rate between the motherboard FPGA and the daughterboard FPGA of this communication system can reach 3.2Gbps, with a bit error rate of less than 1×10⁻⁶.-14 The one-way data latency is less than 100ns, fully meeting the communication requirements for inter-board interconnection in the 50Mbps-5Gbps range. This communication system supports modular design, eliminating the need to focus on the underlying LVDS protocol details during software development. This effectively reduces the development cost of inter-board interconnection in multi-slot plug-in hardware systems, making software development more convenient and significantly accelerating the development speed of such systems. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the physical layer connection structure according to an embodiment of the present invention.

[0018] Figure 2 This is a logic block diagram of the FPGA chip in an embodiment of the present invention.

[0019] Figure 3 This is a logic block diagram showing the communication connection between two FPGA chips in an embodiment of the present invention.

[0020] Figure 4 This is a diagram defining the transmission packet format according to an embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of the data packet sending and receiving process according to an embodiment of the present invention.

[0022] Figure 6 This is a schematic diagram of the command packet sending and receiving process according to an embodiment of the present invention. Detailed Implementation

[0023] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0024] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make the invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of the invention. However, those skilled in the art will recognize that the technical solutions of the invention can be practiced by omitting one or more of the specific details, or other methods, components, apparatus, steps, etc. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring aspects of the invention, and the invention will be further described in detail below with reference to embodiments.

[0025] like Figure 1As shown, this invention discloses an FPGA-based LVDS communication system. This communication method is mainly applied to multi-slot plug-in card hardware systems. This type of hardware system adopts a modular architecture consisting of a motherboard, a backplane, and multiple functional daughterboards. Both the motherboard and daughterboards are equipped with FPGA chips. The LVDS communication method of this invention is mainly used for communication between the two FPGA chips on the motherboard and daughterboards. For ease of description, it is assumed that the motherboard has a first FPGA chip and the daughterboard has a second FPGA chip. The first and second FPGA chips have the same logical architecture. Both the first and second FPGA chips have data transmission and data reception units. The data transmission unit of the first FPGA chip and the data reception unit of the second FPGA chip are connected via an LVDS data transmission bus, and the data transmission unit of the second FPGA chip and the data reception unit of the first FPGA chip are also connected via an LVDS data transmission bus. Both LVDS data transmission buses include four LVDS link signal lines, one LVDS clock signal line, and one GPIO control interface signal line. The aforementioned LVDS link signal lines, LVDS clock signal lines, and GPIO control interface signal lines all utilize the pin resources of the FPGA chips.

[0026] When the first FPGA chip communicates with the second FPGA chip, the data sending unit and the corresponding data receiving unit transmit control primitives, data packets, and command packets through a 4-channel LVDS data transmission bus to realize the transmission of service data streams between the motherboard FPGA and the daughterboard FPGA. The aforementioned service data stream refers to the valid user data exchanged between the motherboard FPGA and the daughterboard FPGA, including but not limited to acquired data, configuration parameters, and status information. During communication, the 4-channel LVDS link signal lines are used for data transmission, the LVDS clock signal line provides the LVDS data transmission clock signal, and the GPIO control interface signal lines send feedback signals to the data sending unit after the 4-channel LVDS link signal lines are ready for data transmission.

[0027] like Figure 2 As shown, this is the logic architecture of an FPGA chip. The first FPGA chip and the second FPGA chip have the same logic architecture, which includes a data transmission unit and a data reception unit.

[0028] The data transmission unit includes a primitive generation module, a command packet generation module, a data transmission FIFO module, a data processing module, a data transmission control module, and a data parallel-to-serial conversion module. The primitive generation module generates control primitives for the communication protocol and sends them to the data transmission control module. These control primitives are used to implement communication between the two FPGA chips. Commonly generated control primitives include training primitives, idle primitives, receive acknowledgment primitives, interrupt primitives, flow control reset primitives, and link reset primitives.

[0029] The data transmission FIFO module stores downlink FIFO data and sends it to the data processing module. Connected to the downlink data bus, the data transmission FIFO module receives data to be transmitted and stores it in the data transmission FIFO module. The data processing module converts the data to be transmitted into data packets of a specified format and sends them to the data transmission control module. The command packet generation module reads command parameters from the upper-layer application software in the local register and converts them into command packets of a specified format, sending them to the data transmission control module. This upper-layer application software can be software deployed on the local FPGA or control software of a remote system. During data transmission, the data transmission control module sends control primitives, data packets, and command packets to the data parallel-to-serial conversion module according to priority. The data parallel-to-serial conversion module converts the control primitives, data packets, and command packets into four channels of serial data and sends them to the data receiving unit via the LVDS link signal lines.

[0030] like Figure 4 As shown in the illustration, a specific embodiment of the present invention defines the formats of data packets and command packets. Both data packets and command packets consist of three parts: a frame header, data, and a checksum. The frame header is 4 bytes long, where the DATA_TYPE field is used to distinguish the packet type, the DATA_TAG field is used to add a marker for the command / response packet, and the DATA_LEN field indicates the byte length of the packet. CRC checksum data is appended to the end of each packet. During communication, data packets are used to transmit data streams between communication nodes, while command packets transmit control commands. Command packets are divided into four types: write command, read command, write response, and read response. Command packets have higher priority than data packets during communication.

[0031] The data receiving unit includes a data serial-to-parallel conversion module, a data receiving control module, a data packet parsing module, a command packet parsing module, and a data receiving FIFO module. The data serial-to-parallel conversion module is connected to the corresponding data parallel-to-serial conversion module of the data transmitting unit. The data serial-to-parallel conversion module converts the received four channels of serial data into parallel data. In one specific embodiment, the data parallel-to-serial conversion module converts 32-bit parallel data into four channels of 8-bit serial data, and the data serial-to-parallel conversion module converts four channels of 8-bit serial data into 32-bit parallel data. The data serial-to-parallel conversion modules are connected to each other via four LVDS link signal lines.

[0032] The data receiving control module sends received data packets and command packets to the corresponding data packet parsing module or command packet parsing module according to the type of the transmission packet. The type of data packet and command packet can be determined from the packet header. The data packet parsing module parses the received data packets into raw transmission data and sends it to the data receiving FIFO module for storage. The command packet parsing module parses command packets, accesses local registers according to the content of the command packets, and generates corresponding response command packets.

[0033] Both the command packet generation module and the command packet parsing module are connected to the AXI-Lite interface, enabling indirect access to remote registers. During communication, the command packet generation module receives commands from the upper-layer application software via the AXI-Lite interface and converts the command parameters in the local registers into a request command packet of a specified format, which is then sent to the corresponding data receiving unit. The command packet parsing module of the data receiving unit parses the command packet, accesses the parameters in the local registers based on the parsed command, and generates a corresponding response command packet. Using this method, the upper-layer application software can transparently access both remote and local registers for data reception and transmission. This eliminates the need for upper-layer application software development to concern itself with the details of the underlying LVDS protocol, making software development for multi-slot plug-in card hardware systems more convenient and effectively improving development speed.

[0034] The present invention also discloses a communication method for the above-mentioned communication system. The following description further illustrates the communication method of the present invention using the communication between the first FPGA chip and the second FPGA chip as an example.

[0035] In the initial state upon system power-on or reset, bit-alignment and byte-alignment training are first performed on the two LVDS data transmission buses. Taking the LVDS data transmission bus between the first FPGA chip's data transmitting unit and the second FPGA chip's data receiving unit as an example, the primitive generation module of the first FPGA chip generates training primitives and sends them to the data receiving unit of the second FPGA chip, enabling bit-alignment and byte-alignment training on the four LVDS link signal lines. When the data receiving unit completes the training and correctly parses the training code, it pulls high the voltage of the GPIO control interface signal line to send a training completion feedback signal to the data transmitting unit. This indicates that data transmission on the four LVDS link signal lines between the first and second FPGA chip data transmitting units is ready. The LVDS data transmission buses between the second and first FPGA chip data transmitting units undergo alignment training in the same manner. This process requires 10 user clock cycles to complete, and the training process will cause a one-way data transmission delay of approximately 100ns.

[0036] Once the LVDS link signal lines have completed training and data transmission is ready, the data sending unit and the corresponding data receiving unit can transmit control primitives, data packets, and command packets through the LVDS data transmission bus to realize the transmission of business data streams between the two FPGA chips.

[0037] When the LVDS data transmission bus is in an idle state, the data sending unit sends an idle primitive to the corresponding data receiving unit through the LVDS link signal line. In this embodiment, the idle primitive is defined as 32'hbcbcbcbc.

[0038] When the first FPGA chip's data transmission FIFO module detects that there is data to be transmitted, the LVDS link signal line enters the data packet transmission state. The first FPGA chip's data processing module reads the data according to its length and converts it into... Figure 4 The data packet, in the specified format, is then converted from 32-bit data to four 8-bit serial data streams by a data parallel-to-serial conversion module and sent to the data serial-to-parallel conversion module of the second FPGA chip. The data serial-to-parallel conversion module then converts the data packet into 32-bit parallel data and sends it to the data receiving control module. The data receiving control module determines the packet is a data packet based on the header information and sends it to the data packet parsing module. The data packet parsing module parses the data packet, performs CRC verification, and converts it back into raw data. The raw data is then sent to the data receiving FIFO module for storage and uploaded via the uplink data bus.

[0039] If an error occurs during data packet parsing (such as failing CRC check), the data transmission unit of the second FPGA chip sends an interrupt primitive to the data receiving unit of the first FPGA chip. At this point, data transmission should be stopped, and the interrupt primitive information should be sent to the upper-layer application software. In this embodiment, the interrupt primitive is defined as 32'hbcdcxxxx, and the lower 16 bits of the interrupt primitive are a predefined interrupt vector.

[0040] To prevent data loss due to data overflow during data transmission, this invention controls data transmission by setting a credit value. As a specific implementation, a flow control module can be set in the data transmission unit of the FPGA chip. This flow control module sets a credit value, which is typically the same as the maximum data packet size that the data receiving FIFO module in the second FPGA chip's data receiving unit can store. Each time the first FPGA chip's data transmission unit sends a data packet, its credit value is decremented by 1. When the credit value reaches 0, the data transmission unit stops sending data packets.

[0041] In response, each time the second FPGA chip data receiving unit receives a data packet, the second FPGA chip data receiving unit sends a request signal to the second FPGA chip data sending unit. The second FPGA chip data sending unit generates a reception confirmation primitive and sends it to the first FPGA chip data receiving unit. After receiving the reception confirmation primitive, the first FPGA chip data receiving unit increments its credit value by 1.

[0042] Its specific communication method is as follows Figure 5 As shown, the first FPGA chip is defined as A, and the second FPGA chip as B. The credit value of the data transmission unit of the first FPGA chip is set to 2. When the data transmission unit of the first FPGA chip sends a data packet, the credit value is decremented by 1. When the credit value is 0, transmission is paused. After the data receiving FIFO module of the data receiving unit of the second FPGA chip stores a data packet, the data transmission unit of the second FPGA chip sends a reception confirmation primitive to the data receiving unit of the first FPGA chip. When the data receiving unit of the first FPGA chip receives the reception confirmation primitive, the credit value in its flow control module is incremented by 1. In this embodiment, the reception confirmation primitive is defined as 32'hbcbcbc00.

[0043] As another embodiment of the present invention, when the first FPGA chip has a request command that needs to be sent to the second FPGA chip, such as Figure 6 As shown, the first FPGA chip is defined as A, and the second FPGA chip as B. The command packet generation module of the first FPGA chip receives commands from the upper-layer application software, stores them in its local register, and then processes the command parameters in the local register according to... Figure 4 The command is converted into a request command packet (CMD) of a specified format and sent to the data receiving unit of the second FPGA chip. The second FPGA chip's command packet parsing module parses the command packet and accesses its local registers according to the content of the command packet to generate a corresponding response command packet. The second FPGA chip's command packet generation module generates a response command packet (RP) of a specified format and sends it to the data receiving unit of the first FPGA chip. The first FPGA chip's command packet parsing module then parses the response command packet and stores the execution result of the response packet in its local registers for access and reading by the upper-layer application software.

[0044] To aid understanding, let's take the example of the first FPGA chip writing a 1 to the 0x1000 register of the second FPGA chip to further describe the communication process. First, the upper-layer application software writes the operation content to the command packet generation module of the first FPGA chip via the AXI-Lite interface. The command packet generation module of the first FPGA chip converts the information into a command packet of a specified format and sends it to the second FPGA chip. The command packet parsing module of the second FPGA chip parses the command packet and, based on its content, performs the write operation via the AXI-Lite interface, generating a corresponding command response packet. The command response packet is then sent from the second FPGA chip to the first FPGA chip, which parses it, saves the access result in its local register, and waits for the upper-layer application software to read it.

[0045] This FPGA-based LVDS communication system connects its data transmission and reception units via four LVDS link signal lines. By configuring control primitives and corresponding communication protocols, it enables rapid data transmission between the motherboard FPGA and the daughterboard FPGA, effectively meeting the communication requirements of multi-slot plug-in card systems. The bidirectional transmission rate between the motherboard FPGA and the daughterboard FPGA in this communication system can reach 3.2 Gbps, with a bit error rate of less than 1 × 10⁻⁶. -14 The one-way data latency is less than 100ns, fully meeting the communication requirements for inter-board interconnection in the 50Mbps-5Gbps range. This communication system supports modular design, eliminating the need to focus on the underlying LVDS protocol details during software development. This effectively reduces the development cost of inter-board interconnection in multi-slot plug-in hardware systems, making software development more convenient and significantly accelerating the development speed of such systems.

[0046] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An FPGA-based LVDS communication system comprising a first FPGA chip and a second FPGA chip, characterized in that: Both the first and second FPGA chips are equipped with data transmission units and data receiving units. The data transmission unit of the first FPGA chip and the data receiving unit of the second FPGA chip are connected via an LVDS data transmission bus, and the data transmission unit of the second FPGA chip and the data receiving unit of the first FPGA chip are also connected via an LVDS data transmission bus. The LVDS data transmission bus includes four LVDS link signal lines, one LVDS clock signal line, and one GPIO control interface signal line. The LVDS link signal lines are used for data transmission, the LVDS clock signal line is used to provide the LVDS data transmission clock signal, and the GPIO control interface signal line sends a feedback signal to the data transmission unit after the data transmission of the four LVDS link signal lines is ready. The data transmission unit and the corresponding data receiving unit transmit control primitives, data packets, and command packets via the LVDS data transmission bus to realize the transmission of business data streams between the first and second FPGAs.

2. The FPGA-based LVDS communication system of claim 1, wherein, The data transmission unit includes a primitive generation module, a command packet generation module, a data transmission FIFO module, a data processing module, a data transmission control module, and a data parallel-to-serial conversion module. The primitive generation module generates control primitives for the communication protocol and sends them to the data transmission control module. The data transmission FIFO module stores downlink FIFO data and sends it to the data processing module. The data processing module converts the data to be transmitted into data packets of a specified format and sends them to the data transmission control module. The command packet generation module reads command parameters from the upper-layer application software in the local register and converts them into command packets of a specified format, sending them to the data transmission control module. The data transmission control module sends control primitives, data packets, and command packets to the data parallel-to-serial conversion module according to priority. The data parallel-to-serial conversion module converts the control primitives, data packets, and command packets into four serial data streams and sends them to the data receiving unit via LVDS link signal lines.

3. The FPGA-based LVDS communication system of claim 2, wherein, The data receiving unit includes a data serial-to-parallel conversion module, a data receiving control module, a data packet parsing module, a command packet parsing module, and a data receiving FIFO module. The data serial-to-parallel conversion module is used to convert the received four-channel serial data into parallel data. The data receiving control module is used to send the received data packets and command packets to the corresponding data packet parsing module or command packet parsing module. The data packet parsing module is used to parse the data packets into raw transmission data and send them to the data receiving FIFO module for storage. The command packet parsing module is used to parse the received command packets, access the local registers according to the content of the command packets, and generate corresponding response command packets.

4. The FPGA-based LVDS communication system of claim 3, wherein, The data parallel-to-serial conversion module is used to convert 32-bit parallel data into 4 channels of 8-bit serial data, and the data serial-to-parallel conversion module is used to convert 4 channels of 8-bit serial data into 32-bit parallel data. The data parallel-to-serial conversion module and the data serial-to-parallel conversion module are connected through 4 LVDS link signal lines.

5. The FPGA-based LVDS communication system of claim 4, wherein, Both the command package generation module and the command package parsing module are connected to the AXI-Lite interface.

6. The FPGA-based LVDS communication system of claim 4, wherein, The data transmission unit further includes a flow control module, which has a credit value. The flow control module is connected to the data transmission control module. The credit value is decremented by 1 for each data packet sent by the data transmission control module. When the credit value is 0, the data transmission control module stops sending data packets.

7. A communication method of the FPGA-based LVDS communication system according to claim 1, characterized in that, It includes the following steps: In the initial state, the data sending unit sends training primitives to the corresponding data receiving unit, enabling the four LVDS link signal lines to perform bit alignment and byte alignment training. After completing the training, the data receiving unit sends a feedback signal indicating that the training is complete to the data sending unit through the GPIO control interface signal line, indicating that the four LVDS link signal lines are ready for data transmission. After the LVDS link signal line data transmission is ready, the data sending unit and the corresponding data receiving unit transmit control primitives, data packets, and command packets through the LVDS data transmission bus to realize the transmission of business data stream between the motherboard FPGA and the daughterboard FPGA; During data transmission, the command packet has a higher priority than the data packet.

8. The communication method of the FPGA-based LVDS communication system according to claim 7, wherein, When the first FPGA chip sends a request command to the second FPGA chip, the data transmission unit of the first FPGA chip sends the request command packet to the data receiving unit of the second FPGA chip through four LVDS link signal lines. The data receiving unit parses and executes the request command packet and generates a corresponding response command packet. The response command packet is then sent to the data receiving unit of the first FPGA chip through the data transmission unit of the second FPGA chip.

9. The communication method of the FPGA-based LVDS communication system according to claim 7, wherein, During the process of the first FPGA chip sending data packets to the second FPGA chip, the data sending unit of the first FPGA chip sets a credit value. Each time the data sending unit of the first FPGA chip sends a data packet, its credit value is decremented by 1. When the credit value is 0, the data sending unit stops sending data packets.

10. The communication method of the FPGA-based LVDS communication system according to claim 9, wherein, When the second FPGA chip data receiving unit receives a data packet, it sends a request signal to the second FPGA chip data sending unit. The second FPGA chip data sending unit generates a reception confirmation primitive and sends it to the first FPGA chip data receiving unit. After receiving the reception confirmation primitive, the first FPGA chip data receiving unit increments its credit value by 1.

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