A high-precision single-ended read circuit based on voltage-controlled magnetic anisotropy magnetic memory

Abstract

This invention discloses a high-precision single-ended read circuit based on a voltage-controlled magnetic anisotropic magnetic memory (VMI). The circuit includes a master-slave RFSE read sensing circuit, a finely adjustable voltage divider circuit, and a read control signal generation circuit. The master-slave RFSE read sensing circuit comprises two independent RFSE read sensing circuits, enabling alternating read operations during the reset and sensing phases. The finely adjustable voltage divider circuit fine-tunes the bit line voltage within a ±10% range of the voltage divider resistor to compensate for process variations and voltage drift. The read control signal generation circuit generates an adjustable asynchronous read control signal through a read delay chain structure. The memory cell being read consists of a magnetic tunnel junction (MTJ) and a memory access transistor. This circuit innovatively introduces a finely adjustable voltage divider circuit, eliminating the need for a traditional reference cell and effectively resisting PVT fluctuations. High-speed, high-precision asynchronous reading is achieved through the master-slave RFSE read sensing circuit and the read control signal generation circuit.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and in particular relates to a high-precision no-reference single-ended read circuit based on a voltage-controlled magnetic anisotropic random access memory. Background Technology

[0002] With the rapid development of new computing architectures and storage technologies, traditional storage solutions face numerous limitations in speed, area, and power consumption in dedicated computing systems, driving innovation in novel memories and readout circuits. Against this backdrop, random computation and its hardware implementation platform, the Ising machine system, have become a research hotspot. The Ising machine is a dedicated computing device designed based on the Ising model principle. It can efficiently solve combinatorial optimization problems that traditional computers struggle with, exhibiting significantly higher computing speed and energy efficiency than traditional architectures for specific tasks. However, such systems rely on arrays composed of a large number of p-bits to perform probabilistic computations, placing extremely high demands on the read / write speed and accuracy of storage units. Therefore, a storage and readout scheme capable of supporting high-speed, high-precision p-bit random access is urgently needed.

[0003] Voltage-controlled magnetic anisotropic magnetic random access memory (VCMA-MRAM) is an emerging type of non-volatile memory. It is based on the magnetic anisotropy of the free layer in a voltage-regulated magnetic tunnel junction (MTJ) and achieves information writing by changing the direction of the easy magnetization axis of the free layer's magnetic moment.

[0004] Using VCMA-MRAM as the storage medium to implement the Ising machine enables a deep physical-level integration of storage and computation. VCMA-MRAM significantly reduces power consumption by controlling magnetization switching via voltage rather than current. Its spin units naturally correspond to the spin states of the Ising model, allowing direct use in constructing large-scale Ising arrays. Furthermore, its non-volatile nature ensures that the computational state is maintained even after power loss, supporting instantaneous wake-up and low standby power consumption. Its voltage control mechanism also facilitates integration with CMOS processes, enabling the development of high-density, large-scale integrated dedicated computing chips, providing a promising technical path for building practical, low-power Ising machine hardware platforms.

[0005] Referenceless single-ended read circuits for memory offer significant performance advantages due to their simplified circuit design and operation, enabling fast and efficient data reading, which is crucial for applications requiring instant access to stored data. Referenceless single-ended read circuits reduce circuit complexity, power consumption, and read speed by minimizing the required reference signal. However, when applied to emerging memories such as VCMA-MRAM, reliability issues such as bit-line voltage sensitivity and significant impact from process variations still exist, limiting their application in high-precision scenarios. Therefore, designing a referenceless single-ended read circuit that combines high speed and high precision has become a key technical challenge supporting the application of VCMA-MRAM in Ising machines. Summary of the Invention

[0006] Technical Problem: The purpose of this invention is to provide a high-precision single-ended read circuit based on voltage-controlled magnetic anisotropic magnetic memory to solve the technical problems of insufficient read speed and low accuracy when VCMA-MRAM is used in Ising machines, and to provide a high-speed and high-precision data reading solution for the reading of probability bit (p-bit) array data in Ising machines based on VCMA-MRAM.

[0007] Technical solution: To solve the above technical problems, the present invention provides a high-precision single-ended read circuit based on a voltage-controlled magnetic anisotropic magnetic memory, including an adjustable voltage divider circuit, a master-slave RFSE read sensing circuit, and a read control signal generation circuit. The adjustable voltage divider circuit is controlled by a voltage divider enable signal and a 4-bit fine-tuning control signal to form a path with the memory cell and generate an accurate and stable voltage divider on the bit line. The master-slave RFSE read sensing circuit is controlled by a reset signal and a sensing signal, senses the voltage on the bit line and amplifies the output of the read result; The read control signal generation circuit generates appropriate reset and sensing signals based on the clock signal and pulse width selection signal.

[0008] The adjustable voltage divider circuit consists of five resistors (a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor) and five NMOS switches (a first NMOS switch, a second NMOS switch, a third NMOS switch, a fourth NMOS switch, and a fifth NMOS switch). The five resistors are connected in series with the first NMOS switch, and the gate of the first NMOS switch is connected to the voltage divider enable signal. The first resistor is the main voltage divider resistor, and the other four resistors are adjustment resistors. Each of the four adjustment resistors is connected in parallel with an NMOS switch to control whether the adjustment resistor is connected. The gates of the four NMOS switches are connected to the corresponding bits of a 4-bit adjustment control signal, and the switching on and off of the switches is controlled by the logic level of the adjustment control signal.

[0009] The master-slave RFSE read sensing circuit consists of two RFSE read sensing circuits, an AND gate AND2_1, and an OR gate OR2_1. The inputs of the two RFSE read sensing circuits are connected to the same bit line for reading data. The output of the first RFSE read sensing circuit is connected to the input of the OR gate for direct data reading in single RFSE read mode. The output of the second RFSE read sensing circuit is connected to the input of the AND gate for high-speed data reading in master-slave RFSE read mode. The other input of the AND gate is connected to the mode selection signal for reading mode switching. The output of the AND gate is connected to the input of the OR gate, and the output signal of the OR gate is the sensing result OUT.

[0010] The read control signal generation circuit is composed of a read delay chain and a combinational logic circuit. The read delay chain consists of multiple delay units. The input signal is the clock signal CLK. Each delay unit outputs a delay signal. The combinational logic circuit generates reset signals and sensing signals with different pulse widths, which are output through AND gates respectively.

[0011] The RFSE reading sensing circuit consists of a voltage-current sensing circuit, a current-voltage latching circuit, and a two-stage latching circuit. The voltage-current sensing circuit consists of four PMOS transistors and two NMOS transistors connected together, with the gate of the twenty-second NMOS transistor connected to the bit line. A current mirror structure is used, consisting of the gates of the twentieth and seventh PMOS transistors connected together. The current mirror is connected to the next stage circuit through the eighth PMOS transmission transistor. The sixth PMOS transistor is used for reset. The gates of the eighth PMOS transistor and the twenty-first NMOS transistor are connected to the sensing signal. The circuit converts voltage into current and performs preliminary amplification of the input current. The current-voltage latch circuit consists of three PMOS transistors and four NMOS transistors. The tenth PMOS transistor, fourteenth PMOS transistor, eleventh NMOS transistor, and fifteenth NMOS transistor form the latch unit, which is used to latch data. The gates of the ninth PMOS transistor and the thirteenth NMOS transistor are connected to the reset enable signal, which is responsible for initializing the latch to the preset level before reading begins. The gate of the twelfth NMOS transistor is connected to a low level, and its drain is connected to the input terminal of the latch unit. Its drain potential changes with the current magnitude. By sensing the current magnitude, the data latched by the latch unit is changed, thereby realizing the secondary amplification of the input current signal and latching the voltage signal. The two-stage latch circuit is composed of two NMOS transistors and two PMOS transistors connected together. The sixteenth PMOS transistor, the seventeenth PMOS transistor, the eighteenth NMOS transistor, and the nineteenth NMOS transistor constitute the two-stage latch circuit, stably read out the signal, and transmit the signal to the next stage as the output stage.

[0012] The memory cell consists of a voltage-controlled magnetic anisotropic tunnel junction and a memory access transistor. The voltage-controlled magnetic anisotropic tunnel junction has voltage-controlled magnetic anisotropy. During data reading, a read voltage lower than the MTJ flip voltage is applied between the bit line and the source line. The resistance difference of the MTJ in the parallel and antiparallel states generates different voltage division signals on the bit line, which are then distinguished by the subsequent read sensing circuit. During data writing, a write voltage pulse is sent to the selected memory cell through the write drive circuit. The VCMA effect is used to achieve controllable flipping of the magnetization state, completing the voltage-driven writing of data.

[0013] The voltage-controlled magnetic anisotropic random access memory high-precision referenceless single-ended read circuit has operating modes including single RFSE data read mode, master-slave RFSE data read mode, and data write mode.

[0014] The single RFSE data readout mode includes three stages: reset, sensing, and latching. Reset phase: The read control signal generation circuit generates a reset signal; the fine-tunable voltage divider circuit is adjusted to the appropriate voltage divider level, and the DIV signal is enabled; the Mode signal is set to "0", so that the master and slave RFSE read sensing circuit is in single RFSE data read mode, its voltage-current sensing circuit does not work, and the current-voltage latch circuit and the secondary latch circuit pre-store data. Sensing Phase: The read control signal generation circuit generates a sensing signal; the memory access transistor of the memory cell is turned on, forming a current path with the finely adjustable voltage divider circuit, and forming a voltage divider on the bit line; after receiving the sensing signal, the master-slave RFSE read sensing circuit is turned on, and the bit line voltage drives its voltage-current sensing circuit to generate current. The current enters the current-voltage latch circuit through the current mirror. The latch circuit senses the magnitude of the current and thus flips or holds the pre-stored data to realize data reading. Latching stage: The fine-tunable voltage divider circuit is turned off, the master-slave RFSE reading sensing circuit stably reads the signal and latches the data, and the read control signal generation circuit is turned off.

[0015] The master-slave RFSE data readout mode includes three stages: reset, sensing, and latching. Reset Phase: The read control signal generation circuit generates a reset signal; the adjustable voltage divider circuit is adjusted to the appropriate voltage divider level, and the DIV signal is enabled; the storage unit and the adjustable voltage divider circuit form a voltage divider on the bit line; the Mode signal is set to "1", which puts the master-slave RFSE read sensing circuit into master-slave RFSE data read mode. Its first RFSE read sensing circuit is turned off. During this phase, the system is reset and pre-stored. The second RFSE read sensing circuit is turned on. At the beginning of data reading, an invalid bit is read out, and during continuous reading, a valid bit is read out. Sensing Phase: The read control signal generation circuit generates a sensing signal; the adjustable voltage divider circuit is adjusted to the appropriate voltage divider level and connected to the bit line; the storage unit and the adjustable voltage divider circuit form a voltage divider on the bit line; the first RFSE reading sensing circuit of the master-slave RFSE reading sensing circuit turns on after receiving the sensing signal and reads one bit of valid data; the second RFSE reading sensing circuit turns off and resets after receiving the sensing signal. Latching phase: The adjustable voltage divider circuit is not working. The current-voltage latching circuit and the secondary latching circuit of the master-slave RFSE read sensing circuit stably read the signal and latch the data. The read control signal generation circuit is not working. In the next cycle, the first and second RFSE read sensing circuits exchange working states and repeat in this way.

[0016] In the data writing mode, the adjustable voltage divider circuit, the master-slave RFSE read sensing circuit, and the read control signal generation circuit are not working. Appropriate write voltage pulses are applied to the storage unit to realize data writing.

[0017] Beneficial effects: The high-precision single-ended read circuit based on voltage-controlled magnetic anisotropic magnetic memory of the present invention has the following advantages: (1) The high-precision referenceless single-ended read circuit based on voltage-controlled magnetic anisotropic random access memory studied in this invention has the advantage of high speed. In traditional dual-ended read schemes, the memory cell and the reference cell need to construct a symmetrical read path. The parasitic capacitance on this path needs to be charged and discharged during each read, becoming the main source of latency. The referenceless single-ended read circuit of this invention eliminates the reference cell and avoids the capacitor charging and discharging process, thus significantly reducing read latency. At the same time, the two RFSE read sensing units integrated in the circuit adopt a master-slave alternating working mode, so that the reset and sensing stages overlap in timing, eliminating the waiting gap inherent in single-channel read circuits, and nearly doubling the effective data read volume that can be completed in a single clock cycle.

[0018] (2) The high-precision referenceless single-ended read circuit based on voltage-controlled magnetic anisotropic random access memory studied in this invention has the advantage of high precision. This advantage stems from its highly customized design, specifically achieved through two core mechanisms: adjustable voltage divider resistors and adjustable read delay. The adjustable voltage divider resistor mechanism enables the circuit to dynamically compensate for the drift of bit line voltage caused by process deviations or environmental factors, ensuring that the voltage signal of the sensing node is always in the optimal discrimination range; the adjustable read delay mechanism allows for fine optimization of the timing window of the reset and sensing stages according to the actual process angle and working conditions, to adapt to the response characteristics of different memory cells, thereby capturing stable data signals under various operating conditions. After 1000 Monte Carlo simulations, the design still maintains a read accuracy of 99.9% under process fluctuations, fully demonstrating its excellent precision. Attached Figure Description

[0019] Figure 1 This is a structural block diagram of a high-precision single-ended read circuit based on a voltage-controlled magnetic anisotropic magnetic memory according to the present invention; Figure 2 This is a diagram showing the relationship between the voltage-controlled magnetic anisotropic tunnel junction state and the voltage across its terminals. Figure 3 This is a schematic diagram of the parallel and antiparallel states of a magnetic tunnel junction and a schematic diagram of the memory cell structure; Figure 4 This is a schematic diagram of the working waveform of the high-precision referenceless single-ended read circuit of the present invention; Figure 5 This is a schematic diagram of the adjustable resistance range of the adjustable voltage divider circuit of the present invention; Figure 6 This is a schematic diagram of the adjustable timing range of the read control signal generation circuit of the present invention under the process corners SS, TT, and FF. Figure 7 The high-precision referenceless single-ended read circuit of this invention achieves reading accuracy in 1000 Monte Carlo simulations at 0℃, 25℃, and 85℃. Figure 8 This is a comparison chart of the amount of data read by the high-precision referenceless single-ended read circuit of the present invention in master-slave RFSE data readout mode and that of the traditional read circuit; The diagram includes: a finely adjustable voltage divider circuit 1, a master-slave RFSE read sensing circuit 2, and a read control signal generation circuit 3; a voltage-current sensing circuit 21, a current-voltage latch circuit 22, and a two-stage latch circuit 23; bit line BL, read enable signal REN, sensing signal SEN, reset signal RST, voltage divider enable signal DIV, finely adjustable voltage divider circuit fine-tuning control signal RTrim<3:0>, clock signal Clk, pulse width selection signal WCh<3:0>, and mode selection signal Mode; first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5, first NMOS transistor M1, second NMOS transistor M2, and third NMOS transistor M3; NMOS transistor M3, fourth NMOS transistor M4, fifth NMOS transistor M5, sixth PMOS transistor M6, seventh PMOS transistor M7, eighth PMOS transistor M8, ninth PMOS transistor M9, tenth PMOS transistor M10, eleventh NMOS transistor M11, twelfth NMOS transistor M12, thirteenth NMOS transistor M13, fourteenth PMOS transistor M14, fifteenth NMOS transistor M15, sixteenth PMOS transistor M16, seventeenth NMOS transistor M17, eighteenth PMOS transistor M18, nineteenth NMOS transistor M19, twentieth NMOS transistor M20, twenty-first NMOS transistor M21, twenty-second PMOS transistor M22. Detailed Implementation

[0020] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides a high-precision, reference-free, single-ended read circuit based on a voltage-controlled magnetic anisotropic random access memory.

[0021] A block diagram of a high-precision single-ended read circuit based on a voltage-controlled magnetic anisotropic magnetic memory of the present invention is shown below. Figure 1 As shown, it includes an adjustable voltage divider circuit 1, a master-slave RFSE read sensing circuit 2, and a read control signal generation circuit 3.

[0022] The adjustable voltage divider circuit 1 is composed of 5 resistors and 5 NMOS transistors connected together. Figure 1(Top left) Five resistors are connected in series with one NMOS switch, which acts as the main enable switch for the voltage divider circuit. Its gate is connected to the voltage divider enable signal DIV. One resistor is the main voltage divider resistor, used to form the bit line voltage divider. The other four resistors are trimmer resistors, used to fine-tune the bit line voltage. Each of the four trimmer resistors is connected in parallel with an NMOS switch to control whether the trimmer resistors are connected. The gates of the four NMOS switches are connected to the corresponding bits of a 4-bit trimmer control signal. The on / off state of the corresponding switches is controlled by the logic level (RTrim<3:0>) of the control signal. By configuring the trimmer control signal with different binary codes, the total equivalent resistance value of the circuit can be changed, thereby fine-tuning the bit line voltage divider.

[0023] The master-slave RFSE read sensing circuit 2 consists of two RFSE read sensing circuits, one AND gate and one OR gate. Figure 1 (Right) The control signals of the two RFSE read sensing circuits are inverted accordingly. The RFSE read sensing circuit is composed of 9 PMOS transistors and 8 NMOS transistors connected together. Figure 1 The left and middle sections are used to sense and amplify the bit line voltage and read out the data. The two RFSE reading sensing circuits are in parallel, with their inputs connected to the same BL. The other end of the BL is connected to the storage unit. The output of the first RFSE reading sensing circuit is directly connected to the input of an OR gate for direct data reading in single RFSE readout mode. The output of the second RFSE reading sensing circuit is connected to the input of an AND gate for high-speed data reading in master-slave RFSE readout mode. The other input of the AND gate is connected to the mode selection signal (Mode) for reading mode switching. The output of the AND gate is connected to the input of an OR gate, and the output signal of the OR gate is the sensing result OUT.

[0024] The RFSE reading sensing circuit consists of three parts: a voltage-current sensing circuit 21, a current-voltage latch circuit 22, and a secondary latch circuit 23. The voltage-current sensing circuit 21 is composed of four PMOS transistors and two NMOS transistors connected together, with the gate of the 22nd NMOS transistor M22 connected to bit line BL. It employs a current mirror structure, consisting of the 20th PMOS transistor M20 and the 7th PMOS transistor M7 connected together, changing the output current according to the input current signal. The current mirror output is connected to the current-voltage latch circuit 23 via a transmission 8th PMOS transistor M8. The 6th PMOS transistor M6 is used to reset the current mirror gate voltage. The gates of the 8th PMOS transistor M8 and the 21st NMOS transistor M21 are connected to the sensing signal SEN. The circuit converts voltage into current and performs preliminary amplification of the input current. The current-voltage latch circuit 22 is composed of three PMOS transistors and four NMOS transistors connected together, with the 10th PMOS transistor M10, the 14th PMOS transistor M14, the 11th NMOS transistor M11, and the 22nd NMOS transistor M22 connected together. The fifteenth NMOS transistor M15 forms a latch unit for latching data; the gates of the ninth PMOS transistor M9 and the thirteenth NMOS transistor M13 are connected to the reset enable signal RST, which is responsible for initializing the latch to a preset level before reading begins, and is used to reset the latched data; the gate of the twelfth NMOS transistor M12 is connected to a low level, and its drain is connected to the input terminal of the latch unit. Its drain potential changes with the magnitude of the current. By sensing the magnitude of the current, it changes the data latched by the latch unit or maintains the original state, thereby realizing the secondary amplification of the input current signal and latching the voltage signal; the secondary latch circuit 23 is composed of two NMOS transistors and two PMOS transistors connected together. Among them, the sixteenth PMOS transistor M16, the seventeenth PMOS transistor M17, the eighteenth NMOS transistor M18, and the nineteenth NMOS transistor M19 form a secondary latch circuit, which stably reads out the signal and serves as the output stage to transmit the signal backward.

[0025] The read control signal generation circuit 3 is composed of a read delay chain and a combinational logic circuit. Figure 1 (Lower left), where the read delay chain consists of multiple delay units. The input signal is the clock signal CLK, which is used as the first delay reference signal. After passing through several delay units, the signal delayed by one-third of a clock cycle is used as the second delay reference signal. Each delay unit outputs a delay signal, which is used to generate control signals SEN and RST with different pulse widths through combinational logic circuits with the two reference signals.

[0026] VCMA-MRAM, as a novel type of non-volatile memory, uses voltage-controlled magnetic anisotropic tunnel junctions as its working cells. The relationship between the state of the magnetic tunnel junction and the voltage across it is shown in the figure below. Figure 2 As shown. The magnetoresistive state is related to the applied voltage V. in With voltage pulse width t bRegarding the applied voltage, when it reaches the magnitude of the switching voltage, the applied voltage itself does not directly set the state, but rather controls the pulse duration t. b This allows for precise triggering of magnetization reversal. At each "flip window" time point, the energy provided by the voltage pulse, combined with the VCMA effect, precisely overcomes the energy barrier for magnetization reversal, achieving magnetic state reversal. The relationship between device state and voltage is determined through time-domain selection using pulse width modulation. With a suitable voltage amplitude, the target magnetoresistive state can be non-volatilely written to (or switched) by precisely controlling the voltage pulse duration. During the data readout phase, the voltage across the magnetic tunnel junction must be kept below the flip voltage to prevent erroneous flipping during the readout phase.

[0027] The present invention provides a storage unit based on a voltage-controlled magnetic anisotropic random access memory, such as... Figure 3 As shown in (a), a 1T1M memory cell is formed by a voltage-controlled magnetic anisotropic magnetic tunnel junction (VCMA-MTJ) and a memory access transistor. The VCMA-MTJ has voltage-controlled magnetic anisotropy and consists of a fixed layer, a free layer, and a non-magnetic oxide isolation layer made of magnetic dielectric. The relative magnetization directions of the fixed layer and the free layer of the MTJ determine the state of the MTJ. The two states of the MTJ in the memory cell are antiparallel AP and parallel P, respectively. When the direction of the free layer of the MTJ is parallel to the fixed layer, the magnetoresistance of the MTJ is R. P , representing logic "0"; when the magnetization direction of the free layer is antiparallel to that of the fixed layer, the magnetic reluctance is R. AP , representing logic "1"; the storage unit structure is as follows Figure 3 As shown in (b). During data reading, a read voltage lower than its flip voltage is applied between the bit line BL and the source line SL. A current path is formed by the conduction of the memory access transistor. Different voltage divider signals are generated on the bit line BL by utilizing the resistance difference of MTJ in the parallel P state and antiparallel AP state, and are distinguished by the subsequent read sensing circuit. During data writing, a voltage pulse with a specific polarity is applied to the word line WL, bit line BL and source line SL of the selected memory cell through the write drive circuit. This pulse forms a vertical voltage higher than its flip threshold at both ends of MTJ. The effective magnetic anisotropy of the free layer is changed by utilizing the VCMA effect, thereby realizing the controllable flip of the magnetization state and completing the voltage-driven writing of data.

[0028] Figure 4The diagram illustrates the operating waveforms of the high-precision referenceless single-ended read circuit of this invention. Based on a voltage-controlled magnetic anisotropic random access memory, the high-precision referenceless single-ended read circuit operates in data read mode and remains off in data write mode. The data read modes include a single RFSE data read mode and a master-slave RFSE data read mode, which are achieved through the combined operation of an adjustable voltage divider circuit 1, a master-slave RFSE read sensing circuit 2, and a read control signal generation circuit 3.

[0029] Furthermore, in single RFSE data readout mode, the sensing signal SEN is set to high level, the voltage divider control signal DIV is consistent with the sensing signal SEN, the word line control signal WL is periodically turned on with the clock signal CLK, and the read control signal generation circuit 3 generates the reset signal RST and the sensing signal SEN; the adjustable voltage divider circuit 1 is adjusted to a suitable voltage divider level so that the BL voltage is within a recognizable read window; the master-slave RFSE read sensing circuit 2 is adjusted to single RFSE data readout mode. The storage unit and the voltage divider unit form a readout path and generate a voltage divider on the bit line, which is then converted into a sensing current by the voltage-current sensing circuit. The current-voltage latch circuit and the secondary latch circuit perform data holding or flipping and latching operations according to the magnitude of the sensing current, thus reading out the data of the storage unit and realizing data readout. The high-precision referenceless single-ended readout circuit single RFSE data readout mode readout stage is divided into: reset stage, sensing stage and latching stage. The specific operation of single RFSE data readout mode is as follows: The reset phase works as follows: the read control signal generation circuit 3 generates a reset signal RST; the adjustable voltage divider circuit 1 is controlled by the fine-tuning control signal and adjusted to a suitable voltage divider level; the DIV signal is enabled, and the voltage divider circuit precharges the bit line BL voltage; the Mode signal is set to "0", making the master-slave RFSE read sensing circuit 2 in single RFSE data readout mode; the reset signal RST is high, the sixth PMOS transistor M6 is turned on, pulling the gate voltage SENSE_N of the twentieth PMOS transistor M20 and the seventh PMOS transistor M7 high; the thirteenth NMOS transistor M13 is turned on; the ninth PMOS transistor M9 is turned off, pulling the potential of point Q in the latch low; the pre-stored data is "0", and the output data OUT is "0". After the above operations are completed, RST drops to low, the sixth PMOS transistor M6 and the twelfth NMOS transistor M12 are turned off, the ninth transistor M9 is turned on, the reset phase ends, and the sensing phase begins.

[0030] The sensing phase works as follows: The read control signal generation circuit 3 generates the sensing signal SEN; when WL is high, the read transistor, i.e., the 22nd NMOS transistor M22, is turned on. The adjustable voltage divider circuit 1's voltage divider enable signal DIV is high, turning on the first NMOS transistor M1. The voltage divider circuit and the storage cell form a current path and generate a voltage divider on BL. The voltage divider resistor value is finely adjusted to ensure the voltage on BL is within a reasonable range, guaranteeing that the voltage across MTJ is less than the MTJ state switching voltage. When MTJ is in a high-resistance state, the 22nd NMOS transistor M22 is turned on; when MTJ is in a low-resistance state, the 22nd NMOS transistor M22 is turned off. When the sensing signal SEN is high, the gated 21st NMOS transistor M21 and the 8th PMOS transistor M8 are turned on, putting the current mirror into operation. When MTJ is in a high-impedance state, i.e., when the 22nd NMOS transistor M22 is turned on, a sensing current path is formed. A large current is generated at the input of the current mirror, and there is a tendency for the same current to be generated at the output. However, since the 12th NMOS transistor M12 is pulled down to a low-level bias state, the current that can pass through is very small. The large current driven by the current mirror causes the drain-source voltage of the 12th NMOS transistor M12 to increase rapidly, thereby raising the Q-point potential and flipping the latch state. The data latched at Q-point changes from "0" to "1", and the output data of the master-slave RFSE reading sensing circuit 2 changes from "0" to "1". When MTJ is in a low-impedance state, i.e., when the 22nd NMOS transistor M22 is turned off, there is no current path. The input current of the current mirror is extremely small, and the output current is extremely small. It will not affect the drain-source voltage of the 12th NMOS transistor M12, which is in a low-level bias state. The Q-point potential remains unchanged, the data latched at Q-point remains "0", and the output data of the master-slave RFSE reading sensing circuit 2 remains "0".

[0031] The latching stage works as follows: the read control signal generation circuit 3 is turned off, the adjustable voltage divider circuit 1 is turned off, and the current-voltage latching circuit 22 and the secondary latching circuit 23 of the master-slave RFSE read sensing circuit 2 stably read out the signal and latch the data; at this time, the output data of the master-slave RFSE read sensing circuit 2 is the stored data of MTJ, and the output result is the read result.

[0032] Furthermore, in the master-slave RFSE data readout mode, the sensing signal SEN is set to a high level, the voltage divider control signal DIV is consistent with the sensing signal SEN, the word line control signal WL is periodically turned on with the clock signal CLK, and the read control signal generation circuit 3 generates the reset signal RST and the sensing signal SEN; the fine-tunable voltage divider circuit 1 is adjusted to a suitable voltage divider level so that the BL voltage is within a recognizable readout window; the master-slave RFSE read sensing circuit 2 is adjusted to the master-slave RFSE data readout mode, and the two RFSE read sensing circuits are in the sensing and latching stages respectively in the same phase, realizing the reading of two bits of data within one cycle. The storage unit and the voltage divider unit form a readout path and generate a voltage divider on the bit line, which is then converted into a sensing current by the voltage-current sensing circuit. The current-voltage latching circuit and the secondary latching circuit complete the data holding or flipping and latching operation according to the magnitude of the sensing current, and read out the data of the storage unit, realizing data readout. The high-precision referenceless single-ended read circuit master-slave RFSE data readout mode readout stage is divided into: reset stage, sensing stage and latching stage. The specific operation of the master-slave RFSE data read mode is as follows: The reset phase works as follows: the read control signal generation circuit 3 generates a reset signal RST; the adjustable voltage divider circuit 1 is controlled by the fine-tuning control signal and adjusted to a suitable voltage divider level; the DIV signal is enabled, and the voltage divider circuit is connected to the bit line BL; the memory access transistor of the memory cell is turned on, the memory cell is connected to the bit line BL, forming a current path with the adjustable voltage divider circuit 2, and forming a voltage divider on the bit line BL; the Mode signal is set to "1", so that the master-slave RFSE read sensing circuit 2 is in the master-slave RFSE data read mode, its first RFSE read sensing circuit is in the off state, and resets and pre-stores data in this stage; the second RFSE read sensing circuit is in the on state, reading an invalid bit at the beginning of data reading, and reading a valid bit during continuous reading; in the next working cycle, the working states of the first and second RFSE read sensing circuits are interchanged.

[0033] The sensing phase works as follows: the read control signal generation circuit 3 generates a sensing signal SEN; the fine-tunable voltage divider circuit 1 is controlled by the fine-tuning control signal and adjusted to a suitable voltage divider level, the DIV signal is enabled, and the voltage divider circuit is connected to the bit line BL; the memory access transistor of the memory cell is turned on, the memory cell is connected to the bit line BL, forming a current path with the fine-tunable voltage divider circuit 2, and forming a voltage divider on the bit line BL; the first RFSE reading sensing circuit of the master-slave RFSE reading sensing circuit 2 turns on after receiving the sensing signal SEN and reads one bit of valid data, and the second RFSE reading sensing circuit turns off and resets after receiving the sensing signal SEN; in the next working cycle, the working states of the first and second RFSE reading sensing circuits are interchanged.

[0034] The latching phase works as follows: the adjustable voltage divider circuit 1 is not working; the current-voltage latching circuit 22 and the secondary latching circuit 23 of the master-slave RFSE reading sensing circuit 2 stably read the signal and latch the data; and the read control signal generation circuit 3 is not working.

[0035] Furthermore, in data writing mode, the adjustable voltage divider circuit 1, the master-slave RFSE read sensing circuit 2, and the read control signal generation circuit 3 are not working, and an appropriate write voltage is applied to the storage unit to realize data writing.

[0036] Figure 5 This diagram illustrates the adjustable voltage divider circuit of the present invention, showing its adjustable resistance range. Ideally, this circuit can achieve a voltage divider resistor value adjustment of ±10% of the nominal value required by the circuit. In actual circuits, due to process variations and transistor voltage division, the simulated value of the actual adjustable voltage divider circuit deviates from the theoretical value; similarly, the actual voltage division value on line BL in the current path deviates from the theoretical value due to process variations and transistor voltage division. Both of these deviations can be offset by fine-tuning the voltage divider resistor value of the adjustable voltage divider circuit.

[0037] Figure 6 The diagram illustrates the adjustable timing range of the read control signal generation circuit of the present invention at process corners SS, TT, and FF. For the TT process corner, the read control signal generation circuit generates an equivalent read delay of 1.5ns to 6ns, with 16 adjustable levels. Figure 7 The high-precision referenceless single-ended read circuit of the present invention demonstrates the reading accuracy of 1000 Monte Carlo simulations at 0℃, 25℃, and 75℃. It can achieve a reading accuracy of up to 99.9% at 25℃, but the reading accuracy decreases to varying degrees at low and high temperatures. Figure 8 The diagram shows a comparison of the data read volume of the high-precision referenceless single-ended read circuit of the present invention in master-slave RFSE data read mode with that of a conventional read circuit. The present invention can read two bits of data consecutively in one read cycle in master-slave RFSE data read mode, thereby improving the data read speed.

[0038] Furthermore, this invention employs an HL 28nm CMOS process and a 70nm MTJ design, and evaluates the impact of process variations on circuit performance using the Monte Carlo (MC) method, while also considering the statistical distribution of overall and local transistor parameters. According to simulation results, when the supply voltage is 0.9V and the TMR is 170%, the readout accuracy can reach 99.9% at 25°C.

[0039] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A high-precision single-ended read circuit based on a voltage-controlled magnetic anisotropic magnetic memory, characterized in that, It includes a finely adjustable voltage divider circuit (1), a master-slave RFSE read sensing circuit (2), and a read control signal generation circuit (3); The adjustable voltage divider circuit (1) is controlled by a voltage divider enable signal (DIV) and a 4-bit fine-tuning control signal (RTrim<3:0>) to form a path with the memory cell and generate an accurate and stable voltage divider on the bit line (BL). The master-slave RFSE read sensing circuit (2) is controlled by the reset signal (RST) and the sensing signal (SEN), senses the voltage on the bit line (BL) and amplifies the output of the read result; The read control signal generation circuit (3) generates a suitable reset signal (RST) and sensing signal (SEN) based on the clock signal (Clk) and the pulse width selection signal (WCh<3:0>).

2. The high-precision single-ended read circuit based on a voltage-controlled magnetic anisotropic magnetic memory according to claim 1, characterized in that, The adjustable voltage divider circuit (1) consists of five resistors (R1, R2, R3, R4, R5) and five NMOS switches (M1, M2, M3, M4, M5). The five resistors are connected in series with the first NMOS switch (M1), and the gate of the first NMOS switch (M1) is connected to the voltage divider enable signal (DIV). The first resistor (R1) is the main voltage divider resistor, and the other four resistors are fine-tuning resistors. Each of the four fine-tuning resistors is connected in parallel with an NMOS switch to control whether the fine-tuning resistor is connected. The gates of the four NMOS switches are connected to the corresponding bits of the 4-bit fine-tuning control signal (RTrim<3:0>), and the switching on and off of the switches is controlled by the logic level of the fine-tuning control signal.

3. The high-precision single-ended read circuit based on a voltage-controlled magnetic anisotropic magnetic memory according to claim 1, characterized in that, The master-slave RFSE read sensing circuit (2) consists of two RFSE read sensing circuits, an AND gate AND2_1, and an OR gate OR2_1. The input terminals of the two RFSE read sensing circuits are connected to the same bit line (BL) for reading data. The output terminal of the first RFSE read sensing circuit is connected to the input terminal of the OR gate for directly reading data in single RFSE read mode. The output of the second RFSE reading sensing circuit is connected to the input of an AND gate for high-speed data reading in master-slave RFSE readout mode; the other input of the AND gate is connected to the mode selection signal (Mode) for reading mode switching; the output of the AND gate is connected to the input of an OR gate, and the output signal of the OR gate is the sensing result OUT.

4. The high-precision single-ended read circuit based on a voltage-controlled magnetic anisotropic magnetic memory according to claim 1, characterized in that, The read control signal generation circuit (3) is composed of a read delay chain and a combinational logic circuit. The read delay chain is composed of multiple delay units. The input signal is the clock signal CLK. Each delay unit outputs a delay signal. The combinational logic circuit generates reset signals (RST) and sensing signals (SEN) with different pulse widths, which are output through AND gates respectively.

5. A high-precision single-ended read circuit based on a voltage-controlled magnetic anisotropic magnetic memory according to claim 3, characterized in that, The RFSE reading sensing circuit consists of a voltage-current sensing circuit (21), a current-voltage latch circuit (22), and a two-stage latch circuit (23); The voltage-current sensing circuit (21) is composed of four PMOS transistors and two NMOS transistors connected together. The gate of the twenty-second NMOS transistor (M22) is connected to the bit line (BL). A current mirror structure is adopted, which is composed of the gates of the twentieth PMOS transistor (M20) and the seventh PMOS transistor (M7) connected together. The current mirror is connected to the next stage circuit through the eighth PMOS transmission transistor (M8). The sixth PMOS transistor (M6) is used for reset. The gates of the eighth PMOS transistor (M8) and the twenty-first NMOS transistor (M21) are connected to the sensing signal (SEN). The circuit converts voltage into current and amplifies the input current initially. The current-voltage latch circuit (22) is composed of three PMOS transistors and four NMOS transistors connected together. The tenth PMOS transistor (M10), the fourteenth PMOS transistor (M14), the eleventh NMOS transistor (M11), and the fifteenth NMOS transistor (M15) constitute the latch unit for latching data. The gates of the ninth PMOS transistor (M9) and the thirteenth NMOS transistor (M13) are connected to the reset enable signal (RST), which is responsible for initializing the latch to the preset level before the reading begins. The gate of the twelfth NMOS transistor (M12) is connected to a low level, and its drain is connected to the input terminal of the latch unit. Its drain potential changes with the magnitude of the current. By sensing the magnitude of the current, the data latched by the latch unit is changed, thereby realizing the secondary amplification of the input current signal and latching the voltage signal. The secondary latch circuit (23) is composed of two NMOS transistors and two PMOS transistors connected together. The sixteenth PMOS transistor (M16), the seventeenth PMOS transistor (M17), the eighteenth NMOS transistor (M18), and the nineteenth NMOS transistor (M19) constitute the secondary latch circuit, stably read out the signal and transmit the signal to the next stage as the output stage.

6. A high-precision single-ended read circuit based on a voltage-controlled magnetic anisotropic magnetic memory according to claim 1, characterized in that, The memory cell consists of a voltage-controlled magnetic anisotropic magnetic tunnel junction (VCMA-MTJ) and a memory access transistor. The VCMA-MTJ has voltage-controlled magnetic anisotropy. During data reading, a read voltage lower than the MTJ flip voltage is applied between the bit line (BL) and the source line (SL). The resistance difference of the MTJ in the parallel (P) state and the antiparallel (AP) state generates different voltage division signals on the bit line (BL), which are then distinguished by the subsequent read sensing circuit. During data writing, a write voltage pulse is sent to the selected memory cell through the write drive circuit. The VCMA effect is used to achieve controllable flipping of the magnetization state, completing the voltage-driven writing of data.

7. A high-precision single-ended read circuit based on a voltage-controlled magnetic anisotropic magnetic memory according to claim 1, characterized in that, The voltage-controlled magnetic anisotropic random access memory high-precision referenceless single-ended read circuit has operating modes including single RFSE data read mode, master-slave RFSE data read mode, and data write mode.

8. A high-precision single-ended read circuit based on a voltage-controlled magnetic anisotropic magnetic memory according to claim 7, characterized in that, The single RFSE data readout mode includes three stages: reset, sensing, and latching. Reset phase: The read control signal generation circuit (3) generates a reset signal (RST); the adjustable voltage divider circuit (1) is adjusted to the appropriate voltage divider level, and the DIV signal is enabled; the Mode signal is set to "0", so that the master-slave RFSE reading sensing circuit (2) is in single RFSE data reading mode, its voltage-current sensing circuit (21) does not work, and the current-voltage latch circuit (22) and the secondary latch circuit (23) pre-store data; Sensing stage: The read control signal generation circuit (3) generates a sensing signal (SEN); the memory access transistor of the memory cell is turned on, forming a current path with the finely adjustable voltage divider circuit (1), and forming a voltage divider on the bit line (BL); the master-slave RFSE read sensing circuit (2) is turned on after receiving the sensing signal (SEN), and the bit line voltage drives its voltage-current sensing circuit (21) to generate current. The current enters the current-voltage latch circuit (12) through the current mirror. The latch circuit senses the magnitude of the current and flips or holds the pre-stored data to realize data reading. Latching stage: The adjustable voltage divider circuit (1) is turned off, the master-slave RFSE reading sensing circuit (2) stably reads out the signal and latches the data, and the read control signal generation circuit (3) is turned off.

9. A high-precision single-ended read circuit based on a voltage-controlled magnetic anisotropic magnetic memory according to claim 7, characterized in that, The master-slave RFSE data readout mode includes three stages: reset, sensing, and latching. Reset phase: The read control signal generation circuit (3) generates a reset signal (RST); the adjustable voltage divider circuit (1) is adjusted to the appropriate voltage divider level, and the DIV signal is enabled; the storage unit and the adjustable voltage divider circuit (1) form a voltage divider on the bit line (BL); the Mode signal is set to "1", so that the master-slave RFSE read sensing circuit (2) is in the master-slave RFSE data read mode, its first RFSE read sensing circuit is turned off, and the data is reset and pre-stored in this phase. The second RFSE read sensing circuit is turned on, and an invalid bit is read at the beginning of data reading, and a valid bit is read during continuous reading. Sensing stage: The read control signal generation circuit (3) generates a sensing signal (SEN); the adjustable voltage divider circuit (1) is adjusted to the appropriate voltage divider level and connected to the bit line (BL); the storage unit and the adjustable voltage divider circuit (1) form a voltage divider on the bit line (BL); the first RFSE reading sensing circuit of the master-slave RFSE reading sensing circuit (2) turns on after receiving the sensing signal (SEN) and reads out one bit of valid data, and the second RFSE reading sensing circuit turns off and resets after receiving the sensing signal (SEN); Latching stage: The adjustable voltage divider circuit (1) is not working. The current-voltage latching circuit (22) and the secondary latching circuit (23) of the master-slave RFSE read sensing circuit (2) stably read out the signal and latch the data. The read control signal generation circuit (3) is not working. In the next cycle, the first and second RFSE read sensing circuits exchange working states and repeat in this way.

10. A high-precision single-ended read circuit based on a voltage-controlled magnetic anisotropic magnetic memory according to claim 7, characterized in that, In the data writing mode, the adjustable voltage divider circuit (1), the master-slave RFSE read sensing circuit (2) and the read control signal generation circuit (3) are not working, and an appropriate write voltage pulse is applied to the storage unit to realize data writing.

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