A magnetic coupling isolation type IGBT driving system

Abstract

The application discloses a kind of magnetic coupling isolation type IGBT driving systems, comprising: primary low-voltage side module, for connecting external microcontroller;Secondary side high-voltage side module, for connecting functional semiconductor device, secondary side high-voltage side module is connected with primary low-voltage side module by isolation band module communication, the secondary side high-voltage side module includes adjustable power supply unit, anti-interference unit, adaptive drive unit and collaborative protection unit, the adjustable power supply unit includes the power input end of anti-interference unit, adaptive drive unit, collaborative protection unit is connected respectively, the independent reverse fault feedback channel of " collaborative protection unit to isolation band module again to primary low-voltage side module " is constructed in the application, for the differentiated transmission and identification of different types of fault signals Special hardware foundation is provided, the limitation that only single high-low level fault signal can be transmitted in prior art is completely broken, so that primary microcontroller can obtain enough information to distinguish specific fault type.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a magnetically isolated IGBT drive system. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs), as power semiconductor devices that combine the advantages of MOSFETs (low drive power, fast switching speed) and bipolar transistors (high current carrying capacity, low saturation voltage), are the core power switching devices in power electronic devices. Because IGBTs have large gate parasitic capacitance and high turn-on threshold voltage, they cannot be directly driven by microcontrollers (MCUs); at the same time, there is a potential difference between the low-voltage control system and the high-voltage power system, requiring electrical isolation to ensure safety.

[0003] Currently, mainstream isolated IGBT driver chips typically integrate signal isolation transmission, gate drive, and multiple protection functions, including desaturation (DESAT) detection protection, undervoltage lockout (UVLO) protection, active Miller clamp protection, and soft shutdown protection. When the chip detects an abnormality in the IGBT or its own operating state, it immediately shuts off the IGBT drive output and sends a fault signal to the MCU through a fault feedback channel. However, existing isolated IGBT driver chips have the following drawbacks: The existing system's fault feedback channel can only transmit a single high / low level signal. When any fault occurs on the secondary side, the primary-side MCU can only determine that the system is abnormal, but cannot distinguish the specific fault type. This prevents the MCU from taking targeted measures: for a fatal IGBT short-circuit fault, the system's main power supply must be immediately cut off and the system shut down for maintenance; for a non-fatal undervoltage fault, it is only necessary to wait for the voltage to recover and then automatically restart. A single fault signal significantly reduces the system's fault handling efficiency, prolongs fault recovery time, and may even lead to the escalation of the fault due to improper handling, causing serious economic losses and safety accidents. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies that cannot distinguish specific fault types, this invention provides a magnetically isolated IGBT drive system, comprising: The primary-side low-voltage module is used to connect to an external microcontroller; The secondary high-voltage side module is used to connect functional semiconductor devices. It is communicatively connected to the primary low-voltage side module via an isolation strip module. The secondary high-voltage side module includes an adjustable power supply unit, an anti-interference unit, an adaptive drive unit, and a cooperative protection unit. The adjustable power supply unit includes power input terminals connected to the anti-interference unit, the adaptive drive unit, and the cooperative protection unit, respectively. The primary low-voltage side module is connected to the first input terminal of the anti-interference unit via the isolation strip module. The output terminal of the anti-interference unit is connected to the input terminal of the adaptive drive unit. The first output terminal of the adaptive drive unit is connected to the control electrode of the power semiconductor device. The second output terminal of the adaptive drive unit is connected to the first input terminal of the cooperative protection unit. The first output terminal of the cooperative protection unit is connected to the second input terminal of the anti-interference unit. The second output terminal of the cooperative protection unit is connected to the primary low-voltage side module via the isolation strip module.

[0005] Optionally, the primary low-voltage side module includes an isolation transmission unit and an isolation status monitoring and receiving unit, and the secondary high-voltage side module includes an isolation transmission and receiving unit and an isolation status monitoring and transmitting unit. The input terminal of the isolation transmission and receiving unit is connected to an external microcontroller, and the output terminal of the isolation transmission and receiving unit is connected to the first input terminal of the anti-interference unit. The isolation transmission and receiving unit is connected to the isolation transmission and receiving unit through an isolation strip module. The input terminal of the isolation status monitoring and transmitting unit is connected to the second output terminal of the collaborative protection unit, and the output terminal of the isolation status monitoring and receiving unit is connected to an external microcontroller. The isolation status monitoring and transmitting unit and the isolation status monitoring and receiving unit are connected through an isolation strip module.

[0006] Optionally, the isolation strip module includes a first magnetic coupling transformer and a second magnetic coupling transformer. The output of the isolation transmission transmitting unit is connected to the primary side of the first magnetic coupling transformer, the secondary side of the first magnetic coupling transformer is connected to the input of the isolation transmission receiving unit, the output of the isolation status monitoring transmitting unit is connected to the primary side of the second magnetic coupling transformer, and the secondary side of the second magnetic coupling transformer is connected to the input of the isolation status monitoring receiving unit.

[0007] Optionally, the anti-interference unit includes a filter circuit and an RS flip-flop shaping circuit; the input terminal of the filter circuit serves as the first input terminal of the anti-interference unit, the output terminal of the filter circuit is connected to the input terminal of the RS flip-flop shaping circuit, the output terminal of the RS flip-flop shaping circuit serves as the output terminal of the anti-interference unit, and the control terminal of the RS flip-flop shaping circuit serves as the second input terminal of the anti-interference unit and is connected to the first output terminal of the cooperative protection unit.

[0008] Optionally, the adaptive driving unit includes a high-side driving circuit and a low-side driving circuit; the input terminal of the high-side driving circuit and the input terminal of the low-side driving circuit are connected to the output terminal of the anti-interference unit, the output terminal of the high-side driving circuit and the output terminal of the low-side driving circuit are connected to the control electrode of the power semiconductor device, and the control terminals of the high-side driving circuit and the low-side driving circuit are both connected to the first input terminal of the cooperative protection unit.

[0009] Optionally, the cooperative protection unit includes a desaturation protection circuit, an overcurrent protection circuit, an overtemperature protection circuit, an undervoltage protection circuit, and a soft shutdown control circuit; the input terminal of the desaturation protection circuit is connected to the power electrode of the power semiconductor device; the input terminal of the overcurrent protection circuit is connected to the power electrode of the power semiconductor device; the output terminal of the desaturation protection circuit is connected to the first input terminal of the soft shutdown control circuit; the output terminal of the overcurrent protection circuit is connected to the second input terminal of the soft shutdown control circuit; the output terminal of the overtemperature protection circuit is connected to the third input terminal of the soft shutdown control circuit; the output terminal of the undervoltage protection circuit is connected to the fourth input terminal of the soft shutdown control circuit; the first output terminal of the soft shutdown control circuit is connected to the second input terminal of the anti-interference unit; and the second output terminal of the soft shutdown control circuit is connected to the input terminal of the isolation state monitoring and transmitting unit.

[0010] Optionally, the adjustable power supply unit includes a bandgap reference source circuit and a multi-channel adjustable LDO circuit; the output terminal of the bandgap reference source circuit is connected to the input terminal of the multi-channel adjustable LDO circuit, and the multiple output terminals of the multi-channel adjustable LDO circuit are respectively connected to the power input terminals of the anti-interference unit, the adaptive drive unit, and the cooperative protection unit.

[0011] Optionally, the isolation status monitoring and sending unit includes a fault reporting module, the input of which is connected to the second output of the collaborative protection unit, and the output of which is connected to the primary side of the second magnetic coupling transformer.

[0012] Optionally, the isolated transmission transmitting unit integrates a refresh module circuit, and the isolated transmission receiving unit integrates a detection circuit; the input terminal of the refresh module circuit is connected to an external microcontroller, and the output terminal of the refresh module circuit is connected to the primary side of the first magnetic coupling transformer; the input terminal of the detection circuit is connected to the secondary side of the first magnetic coupling transformer, and the output terminal of the detection circuit is connected to the first input terminal of the anti-interference unit.

[0013] Optionally, the desaturation protection circuit is composed of a constant current source charging module, a blanking time control circuit, a high voltage detection diode interface, a voltage comparator, and a fault latch trigger connected in sequence; the input terminal of the blanking time control circuit is connected to the output terminal of the adaptive drive unit.

[0014] The beneficial effects of this invention are as follows: This application provides a dedicated hardware foundation for the differentiated transmission and identification of different types of fault signals by constructing an independent reverse fault feedback channel from the "cooperative protection unit to the isolation strip module and then to the primary low-voltage side module". This completely breaks the limitation of the existing technology that can only transmit a single high- or low-level fault signal, enabling the primary-side microcontroller to obtain sufficient information to distinguish the specific fault type and thus take targeted handling measures. For fatal IGBT short-circuit faults, the main power supply can be cut off immediately, and for non-fatal undervoltage faults, the system can wait for the voltage to recover and then automatically restart. This greatly improves the efficiency of system fault handling and avoids the expansion of faults and safety accidents caused by improper handling. Attached Figure Description

[0015] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0016] Figure 1 These are system framework diagrams from some embodiments; Figure 2 These are system flowcharts for some embodiments; Figure 3 These are frame diagrams of the isolation strip module in some embodiments; Figure 4 These are framework diagrams of the isolation strip module in some embodiments; Figure 5 This is a detection circuit diagram in a series of embodiments; Figure 6 This is a filter circuit diagram in a series of embodiments; Figure 7 This is a high-side drive circuit diagram in one embodiment; Figure 8 This is a low-side drive circuit diagram in a series of embodiments; Figure 9 This is a desaturation protection diagram in a series of embodiments; Figure 10 This is a fault error diagram from a series of embodiments; Figure 11 This is a circuit diagram of the working monitoring circuit in a series of embodiments; Figure 12 This is a bandgap reference diagram in a series of embodiments. Detailed Implementation

[0017] The following will clearly and completely describe the concept, specific structure, and technical effects of the present invention in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this invention can be combined interactively without contradicting each other.

[0018] like Figure 1 As shown, this invention provides a magnetically isolated IGBT drive system, comprising: a primary-side low-voltage module for connecting to an external microcontroller; and a secondary-side high-voltage module for connecting to a functional semiconductor device. The secondary-side high-voltage module is communicatively connected to the primary-side low-voltage module via an isolation strip module. The secondary-side high-voltage module includes an adjustable power supply unit, an anti-interference unit, an adaptive drive unit, and a cooperative protection unit. The adjustable power supply unit includes power input terminals respectively connected to the anti-interference unit, the adaptive drive unit, and the cooperative protection unit. The primary-side low-voltage module is connected to the first input terminal of the anti-interference unit via the isolation strip module. The output terminal of the anti-interference unit is connected to the input terminal of the adaptive drive unit. The first output terminal of the adaptive drive unit is connected to the control electrode of the power semiconductor device. The second output terminal of the adaptive drive unit is connected to the first input terminal of the cooperative protection unit. The first output terminal of the cooperative protection unit is connected to the second input terminal of the anti-interference unit. The second output terminal of the cooperative protection unit is connected to the primary-side low-voltage module via the isolation strip module.

[0019] Specifically, this magnetically coupled isolated IGBT drive system adopts a three-level architecture design, consisting of a primary-side low-voltage module, an isolation strip module, and a secondary-side high-voltage module. The primary-side low-voltage module operates in the low-voltage control domain, receiving input pulse signals from the external microcontroller, performing preliminary logic integration and error output, and feeding back system status information to the microcontroller. The secondary-side high-voltage module operates in the high-voltage power domain, directly generating high-current signals to drive external insulated-gate bipolar transistors (IGBTs). The isolation transmission unit provides a kilovolt-level electrical isolation barrier, ensuring high-speed, bidirectional, reliable cross-domain transmission of the forward drive signal and the reverse state feedback signal, directly driving the power semiconductor device to turn on and off and detecting its operating status. The isolation strip module is located between the primary and secondary sides, achieving electrical isolation between them, and simultaneously completing bidirectional communication transmission of the forward drive control signal and the reverse state feedback signal.

[0020] The secondary high-voltage side module integrates four core functional units: an adjustable power supply unit, an anti-interference unit, an adaptive drive unit, and a collaborative protection unit. The adjustable power supply unit, acting as the secondary-side power management module, connects to the power input terminals of the anti-interference unit, adaptive drive unit, and collaborative protection unit, providing a stable operating power supply to these three units. The primary low-voltage side module connects to the first input terminal of the anti-interference unit via an isolation strip module, transmitting the received microcontroller drive control signals to the anti-interference unit. The output terminal of the anti-interference unit connects to the input terminal of the adaptive drive unit, sending the processed drive signals to the adaptive drive unit.

[0021] The adaptive drive unit has two output terminals. The first output terminal is connected to the control electrode of the power semiconductor device and is used to output drive signals to control the switching action of the power semiconductor device. The second output terminal is connected to the first input terminal of the cooperative protection unit and is used to feed back the real-time drive status information of the power semiconductor device to the cooperative protection unit. The cooperative protection unit has two output terminals. The first output terminal is connected to the second input terminal of the anti-interference unit and sends a control signal to the anti-interference unit when a fault is detected. The second output terminal is connected to the primary-side low-voltage side module through the isolation strip module to feed back the fault status information to the primary-side microcontroller.

[0022] This application constructs an independent reverse fault feedback channel from the "cooperative protection unit to the isolation strip module and then to the primary-side low-voltage module," providing a dedicated hardware foundation for the differentiated transmission and identification of different types of fault signals. This completely breaks the limitation of existing technologies that can only transmit single high- and low-level fault signals, enabling the primary-side microcontroller to acquire sufficient information to distinguish specific fault types and take targeted measures—for fatal IGBT short-circuit faults, the main power supply can be immediately cut off; for non-fatal undervoltage faults, the system can automatically restart after voltage recovery, significantly improving system fault handling efficiency and preventing fault escalation and safety accidents caused by improper handling. An adjustable power supply unit provides independent power to the secondary-side anti-interference unit, adaptive drive unit, and cooperative protection unit. The power supply voltage of each module can be flexibly adjusted according to the operating characteristics of different functional modules and the driving requirements of different IGBT models, eliminating the need for a uniform fixed voltage power supply. This significantly improves the system's adaptability to diverse power devices and application scenarios, overcoming the shortcomings of insufficient versatility in existing systems. On the one hand, the integrated anti-interference unit preprocesses the transmitted drive signal, effectively filtering out common-mode and differential-mode interference in high-voltage, strong electromagnetic environments. On the other hand, through the direct connection design of "cooperative protection unit → anti-interference unit," rapid local signal control under fault conditions is achieved. When the system malfunctions, the erroneous drive signal can be directly blocked on the secondary side without primary-side processing, avoiding damage to power devices caused by IGBT erroneous turn-on or turn-off. Adopting an adaptive drive unit design, the drive parameters can be dynamically adjusted according to the actual switching state of the IGBT, breaking through the limitation of fixed output capability of existing drive units. While ensuring reliable IGBT switching, it minimizes switching losses and electromagnetic interference, improving system operating efficiency and avoiding electromagnetic interference to surrounding electronic equipment. A local closed-loop protection path of "adaptive drive unit → cooperative protection unit → anti-interference unit" is constructed, making the protection function, drive function, and signal processing function an organic whole. When a fault is detected, the protection signal can directly act on the drive link to achieve local emergency shutdown, significantly shortening the fault response time, effectively preventing the expansion of the fault range, and significantly improving the reliability and stability of the system.

[0023] In some embodiments, the primary low-voltage side module includes an isolation transmission transmitting unit and an isolation status monitoring receiving unit, and the secondary high-voltage side module includes an isolation transmission receiving unit and an isolation status monitoring transmitting unit. The input terminal of the isolation transmission transmitting unit is connected to an external microcontroller, and the output terminal of the isolation transmission receiving unit is connected to the first input terminal of the anti-interference unit. The isolation transmission transmitting unit is connected to the isolation transmission receiving unit through an isolation strip module. The input terminal of the isolation status monitoring transmitting unit is connected to the second output terminal of the collaborative protection unit, and the output terminal of the isolation status monitoring receiving unit is connected to an external microcontroller. The isolation status monitoring transmitting unit and the isolation status monitoring receiving unit are connected through an isolation strip module.

[0024] Specifically, the primary-side low-voltage module integrates two functional modules: an isolation transmission unit and an isolation status monitoring and receiving unit. The secondary-side high-voltage module also integrates corresponding isolation transmission and receiving units. The input of the isolation transmission unit is connected to an external microcontroller to receive drive control signals output by the microcontroller. The isolation transmission unit connects to the isolation transmission receiving unit via an isolation strip module, processing the received drive control signals and transmitting them to the isolation transmission receiving unit. The output of the isolation transmission receiving unit connects to the first input of an anti-interference unit, sending the received drive control signals to the anti-interference unit.

[0025] The input terminal of the isolation status monitoring transmitting unit is connected to the second output terminal of the collaborative protection unit to receive the fault status signal output by the collaborative protection unit; the isolation status monitoring transmitting unit is connected to the isolation status monitoring receiving unit through the isolation band module, and transmits the received fault status signal to the isolation status monitoring receiving unit through the isolation band module after processing; the output terminal of the isolation status monitoring receiving unit is connected to an external microcontroller to feed back the received fault status signal to the microcontroller.

[0026] In some embodiments, the isolation strip module includes a first magnetic coupling transformer and a second magnetic coupling transformer. The output terminal of the isolation transmission transmitting unit is connected to the primary side of the first magnetic coupling transformer, the secondary side of the first magnetic coupling transformer is connected to the input terminal of the isolation transmission receiving unit, the output terminal of the isolation status monitoring transmitting unit is connected to the primary side of the second magnetic coupling transformer, and the secondary side of the second magnetic coupling transformer is connected to the input terminal of the isolation status monitoring receiving unit.

[0027] Figure 3This paper illustrates a magnetically coupled isolation topology based on microtransformers (a first magnetically coupled transformer and a second magnetically coupled transformer) in an isolated transmission unit. It replaces the traditional optocoupler structure by cascading a transmitter pulse modulation circuit, an on-chip microtransformer, and a receiver demodulation and restoration circuit. When the input logic control signal undergoes a level transition, the transmitter pulse modulation circuit converts the rising or falling edge of the signal into a pair of complementary differential narrow pulse currents and injects them into the primary coil of the microtransformer. Utilizing the principle of high-frequency magnetic field coupling, a differential voltage pulse is induced on the physically isolated secondary coil. The subsequent receiver demodulation circuit, through low-noise amplification and hysteresis determination, restores the pulse signal back to the original switching logic. Since the magnetically coupled isolator only generates transient pulse transmission at signal edges, if the input signal maintains a single DC high or low level for a long period, the level state of the secondary latch is easily erroneously flipped due to internal parasitic leakage current or strong electromagnetic noise interference, thus seriously threatening the reliability of the overall drive architecture. To solve this state failure problem under long-term fixed-level operation, this embodiment of the invention integrates a periodic state maintenance refresh module in the isolated transmission unit.

[0028] Specifically, the isolation module contains two independent dedicated magnetic coupling isolation devices: a first magnetic coupling transformer (forward signal transmission magnetic coupling transformer) and a second magnetic coupling transformer (reverse state feedback magnetic coupling transformer). The first magnetic coupling transformer, defined as a forward signal transmission magnetic coupling transformer, is specifically used to transmit drive control signals from the primary low-voltage side to the secondary high-voltage side. Its primary winding is connected to the output of the isolation transmission transmitting unit, receiving the modulated drive control signal output by the isolation transmission transmitting unit and converting this electrical signal into an alternating magnetic field. The secondary winding of the first magnetic coupling transformer is connected to the input of the isolation transmission receiving unit, using the principle of electromagnetic induction to restore the alternating magnetic field to the corresponding electrical signal, which is then transmitted to the isolation transmission receiving unit. The second magnetic coupling transformer, defined as a reverse state feedback magnetic coupling transformer, is specifically used to transmit fault state feedback signals from the secondary high-voltage side to the primary low-voltage side. The primary winding of the first magnetic coupling transformer is connected to the output of the isolation status monitoring transmitting unit, receiving the modulated fault status signal output by the isolation status monitoring transmitting unit and converting the electrical signal into an alternating magnetic field. The secondary winding of the second magnetic coupling transformer is connected to the input of the isolation status monitoring receiving unit, using the principle of electromagnetic induction to restore the alternating magnetic field to the corresponding electrical signal, which is then transmitted to the isolation status monitoring receiving unit. The first and second magnetic coupling transformers are two independent physical devices, each undertaking a dedicated signal transmission task in a single direction, without crossing over or interfering with each other. The two independent magnetic coupling transformers are responsible for the dedicated transmission of the forward drive signal and the reverse status signal, respectively, achieving physical isolation of the signal channels and completely eliminating crosstalk between signals.

[0029] In some embodiments, the anti-interference unit includes a filter circuit and an RS flip-flop shaping circuit; the input terminal of the filter circuit serves as the first input terminal of the anti-interference unit, the output terminal of the filter circuit is connected to the input terminal of the RS flip-flop shaping circuit, the output terminal of the RS flip-flop shaping circuit serves as the output terminal of the anti-interference unit, and the control terminal of the RS flip-flop shaping circuit serves as the second input terminal of the anti-interference unit and is connected to the first output terminal of the cooperative protection unit.

[0030] Specifically, the anti-interference unit consists of two cascaded parts: a filter circuit and an RS flip-flop shaping circuit. The filter circuit adopts a symmetrical structure design to synchronously filter the two differential signals output from the isolated transmission and reception unit, effectively filtering out common-mode interference and differential-mode interference under high-voltage and strong electromagnetic environments. The RS flip-flop shaping circuit further shapes and latches the filtered signal, eliminating glitches and spikes in the signal, preventing IGBT malfunctions, and significantly improving the anti-interference capability and operational stability of the drive system.

[0031] Figure 6 The transistor-level circuit diagram of the low-pass filter circuit in the anti-interference unit is shown. In high-voltage, high-power power electronic applications, the main power transistor generates a sharp voltage jump during switching. This high dv / dt induces a large common-mode transient interference current between the isolation dielectric, resulting in a small amount of ultra-narrow common-mode glitches in the demodulated pulse signal. To completely eliminate these glitches and prevent their propagation downstream, the anti-interference unit employs a deeply optimized low-pass filter topology. (Refer to...) Figure 6 As shown, all inverters, NAND gates, NOR gates, and the core Schmitt trigger within this filter circuit abandon traditional standard units, instead employing a cascaded structure composed of PMOS and NMOS transistors with specific channel parameters connected in series or parallel. In the RC delay stage and multi-stage shaping chain, the channel lengths of specific NMOS and PMOS transistors are intentionally increased to form long-channel transistors with large gate parasitic capacitances. Utilizing the inherent channel resistance of the long-channel transistors and the interaction with the output resistance of the preceding stage transistors, an equivalent low-pass filter time constant is constructed within the chip, thus replacing the bulky on-chip polysilicon resistors. Furthermore, the critical Schmitt gate circuit is reconstructed into a custom hysteresis network consisting of six tightly cascaded MOS transistors. By using internal positive feedback transistors to dynamically clamp the pull-up and pull-down paths, the threshold voltage difference between positive and negative inversions is artificially widened, forming a broad voltage hysteresis window. When ultra-narrow glitches introduced by interference enter the filter circuit, due to the capacitor charging and discharging delay effect of the long-channel transistor and the wide hysteresis range of the Schmitt trigger, the glitches cannot cause the level flip of the subsequent cascaded MOS gate circuit. Thus, efficient low-pass physical filtering is achieved at the hardware level, ensuring the absolute purity of the control signals sent to the subsequent driver stage.

[0032] In some embodiments, the adaptive driving unit includes a high-side driving circuit and a low-side driving circuit; the input terminal of the high-side driving circuit and the input terminal of the low-side driving circuit are connected to the output terminal of the anti-interference unit, the output terminal of the high-side driving circuit and the output terminal of the low-side driving circuit are connected to the control electrode of the power semiconductor device, and the control terminals of the high-side driving circuit and the low-side driving circuit are both connected to the first input terminal of the cooperative protection unit.

[0033] Specifically, the high-side drive circuit is used to generate the IGBT turn-on drive signal, and the low-side drive circuit is used to generate the IGBT turn-off drive signal; both the high-side drive circuit and the low-side drive circuit adopt a multi-stage push-pull structure and can adaptively adjust the magnitude of the drive current according to the frequency and amplitude of the input signal.

[0034] Figure 7 An exemplary schematic diagram of the high-side drive circuit in an adaptive drive unit is shown. To balance switching losses and electromagnetic interference spikes during the switching process of high-power devices, the overall drive architecture employs an adaptive gate drive design. (Refer to...) Figure 7 As shown, this adaptive high-side drive circuit mainly consists of a multi-stage parallel matrix of large-size power PMOS transistors, a pre-drive stage, and a gate voltage dynamic monitoring feedback branch. Its core working principle is to dynamically adjust the charging current injected into the gate based on the different stages of the external power device's gate voltage. In the initial turn-on phase, when the forward drive signal transitions from low to high, the pre-drive stage controls the adaptive logic to simultaneously turn on multiple sets of parallel power PMOS transistors, injecting charge into the gate of the external power device with a large transient charging current. This forces the gate-source voltage to rise rapidly to near the threshold voltage, minimizing the turn-on dead time. When the gate voltage monitoring feedback network detects that the power device's gate voltage has entered the Miller plateau region, the internal adaptive control logic quickly turns off several sets of power PMOS transistors, reducing the current intensity of the charging branch. This slows down the current rise rate and voltage change rate during the Miller plateau period, suppresses transient voltage spikes caused by the diode reverse recovery current, and reduces system electromagnetic interference. Once the Miller plateau region is safely crossed, the control logic re-enables all power PMOS transistors, rapidly pulling the gate voltage up to the secondary-side positive power rail to ensure full saturation of the power devices and reduce on-state voltage drop. The entire graded charging and adaptive adjustment process is entirely controlled by... Figure 7 The transistor network shown in the diagram works automatically with the level shifting structure.

[0035] Figure 8 An exemplary schematic diagram of the low-side drive circuit in an adaptive drive unit is shown. (Refer to...) Figure 8As shown, the low-side drive circuit mainly consists of a parallel network of large-size power NMOS transistors, a hard-turn-off path, and a cooperative protection soft-turn-off path. Under normal fault-free turn-off conditions, the positive pulse control signal transitions to a low level, enabling the hard-turn-off path of the low-side drive circuit. This turns on the large-size power NMOS transistor with extremely low on-resistance, rapidly extracting and discharging the charge on the gate of the external power device to the negative power rail on the secondary side, achieving rapid turn-off of the power device and minimizing turn-off losses. However, when the cooperative protection unit detects a serious fault such as overcurrent or short circuit in the external power system, if the hard-turn-off path is still used to forcibly and quickly cut off the large current, the huge parasitic inductance in the main power circuit will cause extremely severe induced voltage spikes, which can easily break down the power device. To avoid this devastating overvoltage damage, the low-side drive circuit will adaptively switch to the soft-turn-off protection mode. At this time, the internal control logic forcibly locks the large-size NMOS transistor in the hard-turn-off path and turns on the dedicated soft-turn-off NMOS transistor with high internal resistance and long channel characteristics. The weak discharge of this dedicated NMOS transistor causes the gate voltage of the power device to decrease linearly at a very slow slope, allowing the main circuit current to decay smoothly. This enables safe and stable desaturation shutdown protection, avoiding transient overvoltage breakdown.

[0036] Furthermore, such as Figure 7As shown, the high-side drive circuit includes a first bias circuit, a first current mirror, a second current mirror, a third current mirror, a first push-pull output stage, a second push-pull output stage, and a first level conversion circuit; the first bias circuit includes a first diode D1, a second diode D2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first current source IB1, a second current source IB2, a third current source IB3, a first MOSFET M1 (PMOS type), a second MOSFET M2 (PMOS type), a third MOSFET M3 (PMOS type), a fourth MOSFET M4 (NMOS type), a fifth MOSFET M5 (PMOS type), and a sixth MOSFET M6. (PMOS type), seventh MOSFET M7 (PMOS type), eighth MOSFET M8 (NMOS type), ninth MOSFET M9 (NMOS type), tenth MOSFET M10 (NMOS type), eleventh MOSFET M11 (NMOS type), twelfth MOSFET M12 (NMOS type), thirteenth MOSFET M13 (NMOS type), fourteenth MOSFET M14 (PMOS type), fifteenth MOSFET M15 (PMOS type), sixteenth MOSFET M16 (PMOS type), seventeenth MOSFET M17 (NMOS type), eighteenth MOSFET M18 (NMOS type), nineteenth MOSFET M19 (PMOS type); the first diode D1 The cathode of the first MOSFET M1 is connected to the drain, and the anode is connected to the lower end of the first resistor R1 and the input terminal of the first current source IB1. The source of the first MOSFET M1 is connected to the power supply VDD, and the gate and drain are shorted. The upper end of the first resistor R1 is connected to the drain of the first MOSFET M1, and the node serves as the first bias voltage VB1. The cathode of the second diode D2 is connected to the power supply VDD, and the anode is connected to the node of the first bias voltage VB1. The upper end of the third resistor R3 is connected to the power supply VDD, and the lower end is connected to the source of the second MOSFET M2. The gate of the second MOSFET M2 is connected to the first bias voltage VB1, and the drain is connected to the source of the third MOSFET M3. The gate of the third MOSFET M3 is connected to the second bias voltage VB2, and the drain is connected to the input terminal of the second current source IB2. The output of current source IB2 is grounded to VSS; the left end of the second resistor R2 is connected to the output of the third current source IB3, and the right end is connected to the gate of the fourth MOSFET M4. The input of the third current source IB3 is connected to the power supply VDD; the source of the fourth MOSFET M4 is grounded to VSS, and the drain is connected to the connection node between the drain of the second MOSFET M2 and the source of the third MOSFET M3. This node is the second bias voltage VB2; the upper end of the fourth resistor R4 is connected to the power supply VDD, and the lower end is connected to the source of the fifth MOSFET M5; the gate and drain of the fifth MOSFET M5 are shorted, and the gate is connected to the gates of the sixth MOSFET M6 and the seventh MOSFET M7; the source of the sixth MOSFET M6 is connected to the power supply VDD, and the drain is connected to the source of the seventh MOSFET M7.The drain of the seventh MOSFET M7 is connected to the drain of the ninth MOSFET M9, and simultaneously connected to the gate of the fourteenth MOSFET M14; the lower end of the fifth resistor R5 is grounded to VSS, and the upper end is connected to the source of the eighth MOSFET M8; the gate and drain of the eighth MOSFET M8 are shorted, and the gate is also connected to the gate of the ninth MOSFET M9; the source of the ninth MOSFET M9 is grounded to VSS; the gates of the tenth MOSFET M10 and the twelfth MOSFET M12 are both connected to the first bias voltage VB1, and their sources are both grounded to VSS; the gates of the eleventh MOSFET M11 and the thirteenth MOSFET M13 are both connected to the second bias voltage VB2, and their sources are both grounded to VSS; the drain of the tenth MOSFET M10 is connected to the drain of the eleventh MOSFET M11, and the drain of the twelfth MOSFET M12 is connected to the drain of the thirteenth MOSFET M14. The drains of S-MOSFET M13 are connected; the source of the fourteenth MOSFET M14 is connected to power supply VDD, and its drain serves as the first drive voltage node GS1; the source of the fifteenth MOSFET M15 is connected to power supply VDD, and its drain is connected to the upper end of the sixth resistor R6; the lower end of the sixth resistor R6 is connected to the gate of the sixteenth MOSFET M16; the source of the sixteenth MOSFET M16 is connected to power supply VDD, and its drain serves as the second drive voltage GS2; the gate of the seventeenth MOSFET M17 is connected to the first bias voltage VB1, its source is grounded VSS, and its drain is connected to the second drive voltage GS2; the gate of the eighteenth MOSFET M18 is connected to the second bias voltage VB2, its source is grounded VSS, and its drain is connected to the second drive voltage GS2; the source of the nineteenth MOSFET M19 is connected to power supply VDD, and its drain is connected to the second drive voltage GS2.

[0037] The high-side driving circuit further includes a first output stage circuit, which includes the twentieth MOSFET M20 (PMOS type), the twenty-first MOSFET M21 (NMOS type), the twenty-second MOSFET M22 (PMOS type), the twenty-third MOSFET M23 (NMOS type), the twenty-fourth MOSFET M24 (PMOS type), the twenty-fifth MOSFET M25 (NMOS type), the twenty-sixth MOSFET M26 (PMOS type), and the twenty-seventh MOSFET M27 (NMOS type). The source of the twentieth MOSFET M20 is connected to the power supply VD, the gate is connected to the input signal A, and the drain is connected to the drain of the twenty-first MOSFET M21. The source of the twenty-first MOSFET M21 is grounded to VSS, and the gate is connected to the first driving voltage GS1. The source of the twenty-second MOSFET M22 is connected to the power supply VD, and the gate is connected to the first driving voltage GS1. The source of the 23rd MOSFET M23 is connected to the input signal A, and its drain is connected to the drain of the 24th MOSFET M24. The source of the 24th MOSFET M24 is connected to the power supply VD, its gate is connected to the input signal A, and its drain is connected to the drain of the 25th MOSFET M25. The source of the 25th MOSFET M25 is connected to the power supply VSS, and its gate is connected to the first drive voltage GS1. The source of the 26th MOSFET M26 is connected to the power supply VD, its gate is connected to the input signal A, and its drain is connected to the drain of the 27th MOSFET M27. The source of the 27th MOSFET M27 is connected to the power supply VSS, and its gate is connected to the second drive voltage GS2. The drains of the 20th MOSFET M20, the 22nd MOSFET M22, the 24th MOSFET M24, and the 26th MOSFET M26 are connected together to form the high-side drive output signal YN.

[0038] like Figure 8As shown, the low-side drive circuit includes a second bias circuit, a fourth current mirror, a fifth current mirror, a sixth current mirror, a third push-pull output stage, a fourth push-pull output stage, and a second level conversion circuit; the second bias circuit includes a third diode D3, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a fourth current source IB4, a fifth current source IB5, a twenty-eighth MOSFET M28 (NMOS type), a twenty-ninth MOSFET M29 (PMOS type), a thirtieth MOSFET M30 (NMOS type), a thirty-first MOSFET M31 (PMOS type), a thirty-second MOSFET M32 (NMOS type), and a thirty-third MOSFET M30 (NMOS type). S-MOSFET M33 (PMOS type), 34th MOSFET M34 (NMOS type), 35th MOSFET M35 (PMOS type), 36th MOSFET M36 (NMOS type), 37th MOSFET M37 (NMOS type), 38th MOSFET M38 (PMOS type), 39th MOSFET M39 (NMOS type), 40th MOSFET M40 (PMOS type), 41st MOSFET M41 (NMOS type), 42nd MOSFET M42 (PMOS type), 43rd MOSFET M43 (NMOS type), 44th MOSFET M44 (PMOS type), 45th MOSFET M45 (NMOS type), 46th MOSFET M38 (PMOS type), 4 ... The transistors are: S-type M46 (PMOS), 47th MOS transistor M47 (NMOS), 48th MOS transistor M48 (PMOS), 49th MOS transistor M49 (NMOS), 50th MOS transistor M50 (PMOS), 51st MOS transistor M51 (NMOS), 52nd MOS transistor M52 (PMOS), 53rd MOS transistor M53 (NMOS), 54th MOS transistor M54 (PMOS), and 55th MOS transistor M55 (NMOS). The anode of the third diode D3 is grounded to VSS, and the cathode is connected to the left end of the seventh resistor R7. The right end of the seventh resistor R7 is connected to the gate of the 28th MOS transistor M28. The source of transistor M28 is grounded to VSS, and its drain is connected to the gate of the 30th MOSFET M30 and the gate of the 32nd MOSFET M32; the source of the 29th MOSFET M29 is connected to the power supply VDD, its gate is connected to the output terminal of the fourth current source IB4, and its drain is connected to the upper end of the eighth resistor R8; the lower end of the eighth resistor R8 is connected to the upper end of the ninth resistor R9 and the gate of the 31st MOSFET M31; the lower end of the ninth resistor R9 is connected to the drain of the 30th MOSFET M30; the source of the 30th MOSFET M30 is grounded to VSS; the source of the 31st MOSFET M31 is connected to the power supply VDD, and its drain is connected to the drain of the 32nd MOSFET M32 and the gate of the 33rd MOSFET M33; the source of the 32nd MOSFET M32 is grounded to VSS.The source of the 33rd MOSFET M33 is connected to the power supply VDD, and its drain is connected to the drain of the 34th MOSFET M34 and the gate of the 35th MOSFET M35. The source of the 34th MOSFET M34 is connected to the upper end of the 10th resistor R10, and the lower end of the 10th resistor R10 is grounded to VSS. The gate of the 34th MOSFET M34 is connected to the gate of the 32nd MOSFET M32. The source of the 35th MOSFET M35 is connected to the power supply VDD, and its drain serves as the first drive voltage node, also connected to the drain of the 36th MOSFET M36. The source of the 36th MOSFET M36 is connected to the upper end of the 11th resistor R11, and the lower end of the 11th resistor R11 is grounded to VSS. SS, the gate of the 36th MOSFET M36 is connected to the gate of the 34th MOSFET M34; the source of the 38th MOSFET M38 is connected to the power supply VDD, and its gate is connected to the gate of the 35th MOSFET M35. Its drain serves as the second drive voltage node, and is simultaneously connected to the drains of the 37th MOSFET M37 and the 39th MOSFET M39; the sources of the 37th MOSFET M37 and the 39th MOSFET M39 are connected to the upper end of the 12th resistor R12, and the lower end of the 12th resistor R12 is grounded to VSS. The gates of the 37th MOSFET M37 and the 39th MOSFET M39 are connected to the gate of the 34th MOSFET M34.

[0039] The low-side drive circuit further includes a second output stage circuit and a third output stage circuit. The second output stage circuit includes a 40th MOS transistor M40 (PMOS type), a 41st MOS transistor M41 (NMOS type), a 42nd MOS transistor M42 (PMOS type), a 43rd MOS transistor M43 (NMOS type), a 44th MOS transistor M44 (PMOS type), a 45th MOS transistor M45 (NMOS type), a 46th MOS transistor M46 (PMOS type), and a 47th MOS transistor M47 (NMOS type). The sources of the 40th MOS transistor M40, 42nd MOS transistor M42, 44th MOS transistor M44, and 46th MOS transistor M46 are commonly connected to the first drive voltage node, their gates are commonly connected to the first input signal A1, and their drains are commonly connected to serve as the first low-side drive output signal Y1. The drains of the 41st MOS transistor M41, 43rd MOS transistor M43, 45th MOS transistor M45, and 47th MOS transistor M47 are commonly connected to the first low-side drive output signal Y1, and their sources are commonly grounded to VSS and the third drive voltage GS3.

[0040] The third output stage circuit is identical in structure to the second output stage circuit, including eight MOS transistors from the forty-eighth MOS transistor M48 (PMOS type) to the fifty-fifth MOS transistor M55 (NMOS type). The sources of the upper transistors are connected to the second driving voltage node, the gates are connected to the second input signal A2, and the drains are connected to the second low-side driving output signal Y2. The drains of the lower transistors are connected to the second low-side driving output signal Y2, and the sources are grounded to VSS and the fourth driving voltage GS4.

[0041] In some embodiments, the cooperative protection unit includes a desaturation protection circuit, an overcurrent protection circuit, an overtemperature protection circuit, an undervoltage protection circuit, and a soft shutdown control circuit; the input terminal of the desaturation protection circuit is connected to the power electrode of the power semiconductor device; the input terminal of the overcurrent protection circuit is connected to the power electrode of the power semiconductor device; the output terminal of the desaturation protection circuit is connected to the first input terminal of the soft shutdown control circuit; the output terminal of the overcurrent protection circuit is connected to the second input terminal of the soft shutdown control circuit; the output terminal of the overtemperature protection circuit is connected to the third input terminal of the soft shutdown control circuit; the output terminal of the undervoltage protection circuit is connected to the fourth input terminal of the soft shutdown control circuit; the first output terminal of the soft shutdown control circuit is connected to the second input terminal of the anti-interference unit; and the second output terminal of the soft shutdown control circuit is connected to the input terminal of the isolation state monitoring and transmitting unit.

[0042] Specifically, the desaturation protection circuit monitors the collector-emitter voltage of the IGBT in real time, and can quickly respond and trigger the protection mechanism when the IGBT experiences a desaturation fault; the overcurrent protection circuit monitors the collector current of the IGBT, and promptly shuts down the IGBT when the current exceeds a set threshold; the overtemperature protection circuit monitors the junction temperature of the chip to prevent damage due to overheating; the undervoltage protection circuit monitors the supply voltage of each module on the secondary side, and triggers protection when the supply voltage is lower than the normal operating range to prevent abnormal module operation; the soft shutdown circuit slowly shuts down the IGBT at a controllable rate when various faults occur, effectively suppressing voltage spikes and electromagnetic interference generated during the shutdown process, and preventing damage to the IGBT due to overvoltage. These protection circuits work together to achieve comprehensive protection for the IGBT and the driver chip.

[0043] Figure 9 The cascaded structure diagram of the desaturation protection circuit in the collaborative protection unit is shown. The desaturation protection circuit is a critical boundary for achieving high-reliability closed-loop safety monitoring in the entire drive architecture. (Refer to...) Figure 9As shown, the desaturation protection circuit consists of a precision constant current source charging module, blanking time control logic, an external high-voltage detection diode interface, a voltage comparator, and a fault latch trigger cascaded together. This circuit utilizes the physical characteristic that an external power device exits its saturation conduction region and its collector-emitter voltage spikes abnormally when a short-circuit overcurrent occurs. During the initial transient of the power device's turn-on, before its collector-emitter voltage has fully decreased, the blanking time control logic generates a positive blanking pulse with a fixed pulse width to prevent malfunction of the protection circuit. This pulse turns on the pull-down NMOS transistor inside the detection node, forcibly clamping the voltage of the detection node to the secondary side ground level. After the blanking time ends, the internal pull-down NMOS transistor turns off, and the precision constant current source begins charging the detection node. Under normal saturation conduction conditions, the collector-emitter voltage is extremely low. The current in the detection node flows to the collector of the power device through the externally connected high-voltage isolation diode, clamping the voltage of the detection node to a lower value. Since this voltage is lower than the reference threshold voltage at the inverting input of the voltage comparator, the comparator output remains low. Once an external short-circuit fault occurs, the device current surges and exits the saturation region, causing the collector-emitter voltage to spike rapidly. This results in the external high-voltage isolation diode being reverse-biased and the current from the internal precision constant current source rapidly charging the parasitic capacitance of the detection node and the external blanking capacitor. Consequently, the voltage at the detection node exceeds the reference threshold of the voltage comparator within a very short time. The voltage comparator output immediately flips to a high level, triggering the subsequent fault latch trigger, which instantaneously generates a short-circuit fault protection signal and simultaneously sends it to the adaptive driver stage to activate the aforementioned soft-shutdown path.

[0044] In some embodiments, the adjustable power supply unit includes a bandgap reference source circuit and a multi-channel adjustable LDO circuit; the output terminal of the bandgap reference source circuit is connected to the input terminal of the multi-channel adjustable LDO circuit, and the multiple output terminals of the multi-channel adjustable LDO circuit are respectively connected to the power input terminals of the anti-interference unit, the adaptive drive unit, and the cooperative protection unit.

[0045] Specifically, the bandgap reference source circuit is used to generate a high-precision, low-temperature-drift reference voltage, providing a stable voltage reference for the entire secondary-side system. The multi-channel adjustable LDO circuit, based on the reference voltage generated by the bandgap reference source, can output multiple stable supply voltages of different voltage levels to power the anti-interference unit, adaptive drive unit, cooperative protection unit, and isolation status monitoring unit, respectively. Furthermore, it can flexibly adjust the output voltage according to the driving requirements of different IGBT models, improving the compatibility of the drive system with different IGBT devices.

[0046] In some embodiments, the isolation status monitoring and sending unit includes a fault reporting module, the input of which is connected to the second output of the cooperative protection unit, and the output of which is connected to the primary side of the second magnetic coupling transformer.

[0047] Specifically, the isolation status monitoring and transmitting unit integrates a fault reporting module. The input of the fault reporting module is connected to the second output of the collaborative protection unit to receive the fault signal output by the collaborative protection unit; the output of the fault reporting module is connected to the primary side of the second magnetic coupling transformer to transmit the encoded fault signal to the second magnetic coupling transformer.

[0048] Figure 10 This diagram illustrates a fault reporting circuit for multi-fault coding in an isolated state monitoring unit. Traditional isolated drive topologies typically transmit a single binary level signal to the primary side via a dedicated reverse channel for state monitoring. Upon receiving the error signal, the primary-side microcontroller can only detect an anomaly on the secondary side, but cannot distinguish between a secondary-side undervoltage supply fault and a severe power device short-circuit desaturation fault, preventing the system from making targeted differentiated protection decisions. To improve the reliability and precision of fault diagnosis from an overall architecture perspective, this embodiment introduces a hardware-level pulse width encoding and frequency division logic mechanism in the isolated state monitoring unit. This mechanism requires no additional pins or physical channels, directly utilizing the existing reverse feedback channel to perform real-time dynamic pulse stream modulation on the feedback signal at the hardware level. If a short-circuit desaturation fault occurs, the reverse channel is controlled to send a fixed narrow pulse signal sequence with a frequency of 100kHz; if secondary-side undervoltage lockout protection occurs, the reverse channel is controlled to send a fixed wide pulse signal sequence with a frequency of 10kHz. Primary-side microcontrollers can accurately determine the specific fault type by measuring the period or width of the pulse. (Refer to...) Figure 10As shown, to achieve dynamic encoding fusion of multiple faults at the hardware level, the fault reporting circuit underwent a key modification in its topology. Specifically, a custom two-input AND gate was added cascaded after the output of the original fifth D flip-flop. The first input of the two-input AND gate is directly connected to the Q output of the fifth D flip-flop to obtain the latched overall fault enable state. The second input is connected to the secondary pulse characteristic control signal line generated by the internal encoding generator. The output of the two-input AND gate serves as the final fault reporting encoding output port of the isolation state monitoring unit, which is directly connected to the transmitting input pin of the reverse isolation transmission unit. During normal, fault-free operation, the Q output of the fifth D flip-flop remains low. Regardless of how the pulse characteristic control signal on the second input flips, the output port of the newly added AND gate is always clamped to a fixed invalid low-level state, and there is no pulse output from the reverse channel. However, once a short-circuit fault or undervoltage fault is triggered on the secondary side, the fifth D flip-flop is set, and its Q output flips to a high level, putting the newly added AND gate in a logic-allowed state for the second input. At this point, the output level of the final fault error code output port will depend entirely on the waveform on the pulse characteristic control signal line. If the current fault is a short circuit, the internal encoding logic causes the pulse characteristic control signal line to generate a narrow pulse clock of 100kHz, which is perfectly transmitted to the inverting isolation channel through an AND gate; if the current fault is an undervoltage fault, the pulse characteristic control signal line switches to a wide pulse clock of 10kHz and outputs it through an AND gate. This design successfully achieves dynamic encoding output for multiple faults in a single channel.

[0049] When different types of faults occur, the fault reporting module encodes the received corresponding fault signals and converts them into pulse signal sequences with different identifiable characteristics, such as pulse signals with different frequencies, pulse widths, or duty cycles. The encoded pulse signal sequences are transmitted to the isolation status monitoring receiving unit on the primary side through the second magnetic coupling transformer. The primary-side microcontroller can accurately distinguish the specific fault type by identifying the characteristic parameters of the pulse signal sequences.

[0050] In some embodiments, the isolated transmission transmitting unit integrates a refresh module circuit, and the isolated transmission receiving unit integrates a detection circuit; the input terminal of the refresh module circuit is connected to an external microcontroller, and the output terminal of the refresh module circuit is connected to the primary side of the first magnetic coupling transformer; the input terminal of the detection circuit is connected to the secondary side of the first magnetic coupling transformer, and the output terminal of the detection circuit is connected to the first input terminal of the anti-interference unit.

[0051] Specifically, the refresh module circuit is used to periodically refresh the transmitted digital signal to prevent loss or misjudgment of the DC signal during long-term transmission; the detection circuit is used to demodulate the modulated signal transmitted by the magnetic coupling transformer to recover the original digital control signal.

[0052] Furthermore, such as Figure 4As shown, the refresh module circuit includes a sixth current source, a thirteenth resistor R13, a first capacitor C1, a fifty-sixth MOSFET M56 (PMOS type), a fifty-seventh MOSFET M57 (PMOS type), a fifty-eighth MOSFET M58 (PMOS type), a fifty-ninth MOSFET M59 (PMOS type), a sixtieth MOSFET M60 (PMOS type), a sixty-first MOSFET M61 (NMOS type), a sixty-second MOSFET M62 (PMOS type), a sixty-third MOSFET M63 (NMOS type), a sixty-fourth MOSFET M64 (PMOS type), a sixty-fifth MOSFET M65 (NMOS type), and a sixty-sixth MOSFET... M66 (NMOS type), 67th MOS transistor M67 (NMOS type), 68th MOS transistor M68 (NMOS type), 69th MOS transistor M69 (NMOS type), first Schmitt trigger, first inverter, second inverter, first D flip-flop DFF1, second D flip-flop DFF2, first NOR gate, second NOR gate, first delay unit, second delay unit, first AND gate, first XOR gate, and second XOR gate; the sixth current source is composed of 13th resistor R13 and 56th MOS transistor M56 and 57th MOS transistor M57, one end of 13th resistor R13 is grounded, and the other end is connected to the drain of 56th MOS transistor M56. The source of the 56th MOSFET M56 is connected to the power supply VCC, and its gate is connected to the gate of the 57th MOSFET M57. The source of the 57th MOSFET M57 is connected to the power supply VCC, and its drain is connected to the source of the 58th MOSFET M58 and the source of the 59th MOSFET M59. The gate and drain of the 59th MOSFET M59 are shorted, and its gate is also connected to the gate of the 58th MOSFET M58, forming a PMOS current mirror. The drain of the 58th MOSFET M58 is connected to the drain of the 59th MOSFET M59, and is also connected to the upper end of the first capacitor C1 and the input of the first Schmitt trigger. The lower end of the first capacitor C1 is grounded. The output of the first Schmitt trigger... The first inverter's output is connected to the input of the second inverter; the output of the second inverter is connected to the gates of the 60th MOSFET M60 and the 61st MOSFET M61; the source of the 60th MOSFET M60 is connected to the power supply VCC, and the source of the 61st MOSFET M61 is grounded. The drains of the two transistors are connected together and then connected to the clock input of the first D flip-flop DFF1; the two inputs of the first XOR gate are connected to the fault-free input signal DIN_NOFLT and the original input signal DIN, respectively, and the output of the first XOR gate is connected to the clock input of the second D flip-flop DFF2; the D input of the first D flip-flop DFF1 is connected to the power supply VCC, and the R input is connected to the output of the first NOR gate; one input of the first NOR gate is connected to the enable signal D_EN, and the other input is connected to the output of the first delay unit; the input of the first delay unit is connected to the Q input of the first D flip-flop DFF1; the Q input of the first D flip-flop DFF1 is connected to one input of the first AND gate;The D terminal of the second D flip-flop DFF2 is connected to the power supply VCC, and the R terminal is connected to the output of the second NOR gate. One input of the second NOR gate is connected to the enable signal D_EN, and the other input is connected to the output of the second delay unit. The input of the second delay unit is connected to the Q terminal of the second D flip-flop DFF2. The Q terminal of the second D flip-flop DFF2 is connected to the input of the first inverter, and the output of the first inverter is connected to the other input of the first AND gate. The output of the first AND gate is connected to one input of the second XOR gate, and the other input of the second XOR gate is connected to the original input signal DIN. The output of the second XOR gate is the mixed refresh signal DIN_MIX. The cascaded MOSFETs M62 to M69 form an output drive network to complete the enhancement, shaping, and output drive of the refresh signal.

[0053] like Figure 5As shown, the detection circuit includes a seventh current source IB7, a fourteenth resistor R14, a second capacitor C2, a first comparator, a third D flip-flop DFF3, and seventieth MOSFETs M70 (PMOS type), M71 (PMOS type), M72 (PMOS type), M73 (PMOS type), M74 (PMOS type), M75 (NMOS type), M76 (NMOS type), M77 (NMOS type), M78 (PMOS type), and M79 (PMOS type). The 80th MOS transistor (M80, NMOS type), the 81st MOS transistor (M81, PMOS type), the 82nd MOS transistor (M82, NMOS type), the 83rd MOS transistor (M83, NMOS type), the 84th MOS transistor (M84, NMOS type), the 85th MOS transistor (M85, NMOS type), and the 86th MOS transistor (M86, NMOS type) are connected to the source of the 70th MOS transistor (M70) and the 71st MOS transistor (M71), respectively. Their sources are connected to the power supply VCC, their gates are connected to the reset signal RST, and their drains are connected to the set node SET. The set node SET is also connected to the clock input of the third D flip-flop DFF3 and the input of the differential amplifier stage. The 72nd MOS transistor... The sources of S-MOSFETs M72, M73 (73rd), and M74 (74th) are connected to the power supply VCC, and their gates are interconnected to form a PMOS current mirror load. MOSFETs M75 (75th) and M76 (76th) are a differential input pair, with their drains connected to the current mirror outputs respectively, and their sources connected to the drain of MOSFET M77 (77th). The source of MOSFET M77 is grounded to VSS, and its gate is connected to the differential bias voltage. One end of resistor R14 is grounded to VSS, and the other end is connected to the drain and gate of MOSFET M78 (78th). The source of MOSFET M78 is connected to the power supply VCC, and its gate is simultaneously connected to the gate of MOSFET M79 (79th), forming a PMOS... Bias current mirror; the source of the 79th MOSFET M79 is connected to the power supply VCC, and the drain is connected to the upper end of the second capacitor C2, the drain of the 80th MOSFET M80, and the inverting input of the first comparator; the lower end of the second capacitor C2 and the source of the 80th MOSFET M80 are grounded to VSS, and the gate of the 80th MOSFET M80 is connected to the output of the differential amplifier stage; the non-inverting input of the first comparator is connected to the reference voltage Vref, and the output is connected to the input of the third D flip-flop DFF3; the reset terminal of the third D flip-flop DFF3 is connected to the reset signal RST, and the output is connected to the output driver stage; the 81st MOSFET M81 is an output pull-up transistor, with its source connected to the power supply VCC and its gate connected to the output of the third D flip-flop DFF3;MOSFETs M82 (82nd) ​​to M86 (86th) are connected in parallel to form a pull-down output array. Their drains are connected together as the detector output signal DOUT, their sources are grounded to VSS, and their gates are connected together to the output terminal of the third D flip-flop DFF3.

[0054] correspond Figure 3 The magnetically isolated topology shown is as follows: Figure 4 The transistor-level circuit diagram of the refresh module is shown. The ideal current source and standard digital logic gates commonly used in traditional designs exhibit significant uncertainties in actual circuit construction and multi-process angle simulation. To improve the overall reliability of the architecture, this embodiment of the invention replaces and improves them with a full MOS transistor configuration. Specifically, the constant current charging branch in this refresh circuit abandons the ideal current source and instead adopts a precision proportional mirror current source structure composed of a bias PMOS transistor, a first mirror PMOS transistor, and a second mirror PMOS transistor. The drain of the bias PMOS transistor is connected to a fixed reference bias current, its gate and drain are shorted at the active node, and its source is connected to the low-voltage power supply rail on the secondary side. The gates of both the first and second mirror PMOS transistors are connected to the gate of the bias PMOS transistor, and their sources are both connected to the low-voltage power supply rail. By precisely adjusting the channel width-to-length ratio of each transistor in the design, a stable charging current is injected into the timing core capacitor. Furthermore, all traditional standard logic gates within the refresh module have been replaced with custom-designed complementary MOS transistor structures composed of cascaded complementary transistors. For example, the inverter is composed of a PMOS transistor and an NMOS transistor connected in series, with their gates shorted as inputs and their drains shorted as outputs. The NAND and NOR gates are also constructed using specific parallel and series MOS transistor networks. This fully MOS-based transistor-level design eliminates substrate current injection caused by high-speed switching of the digital standard cell library. By fine-tuning the geometry of the custom MOS transistors, precise control of the refresh pulse delay window and edge slope is achieved, ensuring absolute stability of the status refresh signal under DC conditions.

[0055] Figure 5The transistor-level circuit diagram of the detection circuit used to recover weak pulse signals is further shown. To ensure that the weak differential spike pulse induced by the secondary coil of the micro-transformer can still be stably captured when subjected to transient common-mode interference introduced by high-voltage switching, the detection stage has been reconstructed and optimized at the transistor level. Specifically, the tail current sources and active loads of the front-stage differential amplifier and the rear-stage hysteresis comparator are all replaced by a precision low-voltage active current mirror network composed of multiple NMOS transistors. The gates of the NMOS transistors in the low-voltage active current mirror network are interconnected, and the sources are grounded. By strictly matching the channel parameters of each NMOS transistor in the design, the common-mode rejection ratio of the differential amplifier stage is significantly improved, effectively preventing the common-mode interference coupled through the transformer parasitic capacitance under high-voltage switching transients from being converted into differential error codes. At the same time, all logic gates in the digital shaping stage, cascaded delay chain, and pulse latch used to latch the final level at the back end of the detection module are replaced by a custom-made complementary MOS transistor network composed of specific transistors cascaded one by one, instead of standard gate cells. This custom transistor-level design not only reduces the transient switching power consumption spikes of the detector module when dealing with high-frequency pulses of hundreds of megahertz, but also significantly reduces the jitter of transmission delay. This allows the cascaded complementary MOS pair to still achieve stable demodulation and latching of the signal, even when the amplitude of the sensed pulse is attenuated to a certain extent due to process deviations.

[0056] In some embodiments, the desaturation protection circuit is composed of a constant current source charging module, a blanking time control circuit, a high voltage detection diode interface, a voltage comparator, and a fault latch trigger connected in sequence; the input terminal of the blanking time control circuit is connected to the output terminal of the adaptive drive unit.

[0057] Specifically, the desaturation protection circuit adopts a cascaded architecture design, consisting of a precision constant current source charging module, a blanking time control circuit, a high-voltage detection diode interface, a voltage comparator, and a fault latch trigger connected in sequence. The output of the precision constant current source charging module is connected to the high-voltage detection diode interface, providing a constant charging current to the detection node. The high-voltage detection diode interface is used to connect an external high-voltage detection diode, enabling connection to the power electrode of the power semiconductor device. The input of the voltage comparator is connected to the detection node, used to compare the voltage at the detection node with a reference voltage. The input of the fault latch trigger is connected to the output of the voltage comparator, used to latch the fault state. The input of the blanking time control circuit is connected to the output of the adaptive drive unit, receiving the drive signal output by the adaptive drive unit. The output of the blanking time control circuit is connected to the detection node, generating a fixed-width blanking pulse at the initial turn-on stage of the power semiconductor device, clamping the voltage at the detection node to a low level to prevent false triggering of the protection due to the power electrode voltage of the power semiconductor device not completely decreasing at the moment of turn-on.

[0058] likeFigure 1 , Figure 2 As shown, the forward drive signal flows from the primary-side input logic control stage. The pulse width modulation (PWM) signal generated by the external microcontroller is input to the primary-side low-voltage module. The primary-side low-voltage module integrates a primary-side undervoltage lockout (UVLO) protection circuit. After verification by the primary-side UVLO protection circuit, the signal is transmitted to the secondary-side high-voltage module through the forward channel of the isolation transmission unit. The raw signal received by the secondary-side high-voltage module first enters the filtering circuit of the anti-interference unit to filter out high-frequency common-mode glitches introduced by complex strong electromagnetic interference on the transmission path. Then, the clean control pulse is sent to the control terminal of the adaptive drive unit, which outputs drive current through its internal high-side drive circuit and low-side drive circuit, thereby controlling the on and off of the external power devices. The reverse feedback path involves the collaborative protection unit monitoring the desaturation state of external power devices in real time. Upon detecting a short-circuit fault, the collaborative protection unit directly cascades to the adaptive drive unit to trigger an emergency shutdown. Simultaneously, it transmits the short-circuit fault signal to the isolation state monitoring and transmission unit. This unit is also connected to the output of the secondary-side undervoltage lockout protection circuit to acquire the abnormal power supply status of the secondary side in real time. The isolation state monitoring and transmission unit performs pulse width and frequency characteristic encoding modulation on the aforementioned multiple fault signals at the hardware level. The modulated single pulse stream is then safely transmitted back to the status monitoring and error output stage of the primary-side control chip via the reverse channel of the isolation band module, ultimately reporting to the external microcontroller, thus realizing a fully closed-loop protection and monitoring path. To ensure the robust operation of the digital logic and high-frequency analog modules within the primary and secondary sides, an external basic support network consisting of a bandgap reference circuit and a low-dropout linear regulator (LDO) circuit is cascaded within the overall architecture. This network converts the variable external power supply into a highly stable on-chip low-voltage power rail.

[0059] Figure 11 The transistor-level clock processing topology of the chip operation monitoring circuit in the isolation state monitoring unit (isolation state monitoring transmitting unit and isolation state monitoring receiving unit) is shown. In order to ensure the frequency stability and pulse width accuracy of the above-mentioned 100kHz and 10kHz pulse streams, and to avoid frequency drift caused by process deviations, drastic fluctuations in power supply voltage, and changes in ambient temperature during chip manufacturing, which could lead to misjudgments by the primary-side microcontroller, a precise hardware time base division network must be established.

[0060] Reference Figure 11 As shown, the chip's operational monitoring circuit includes a clock signal input, a multi-bit digital counter module, and a first D flip-flop for latching the monitoring state. To perfectly adapt to and generate a high-tolerance encoded clock, [the circuit is designed for...]. Figure 11The circuit underwent a significant cascade modification. Four new D flip-flops were added horizontally in series between the matched output of the digital counter and the input of the first D flip-flop, designated as the first, second, third, and fourth newly added flip-flops, respectively. In the specific cascade connection, the matched output of the digital counter is connected to the D input of the first newly added flip-flop; the Q output of the first newly added flip-flop is connected to the D input of the second newly added flip-flop; the Q output of the second newly added flip-flop is connected to the D input of the third newly added flip-flop; the Q output of the third newly added flip-flop is connected to the D input of the fourth newly added flip-flop; and finally, the Q output of the fourth newly added flip-flop is connected to the D input of the original first D flip-flop. The clock inputs of these four series-added flip-flops are all connected to the main clock line of the chip's internal high-frequency oscillator, and their asynchronous reset terminals are all connected to the system's main reset signal line. These four series-added D flip-flops internally form a precise active delay chain and a multi-stage frequency division duty cycle adjustment state machine network. When the digital counter accumulates and reaches the set value under the drive of the main clock, its output generates a leading-edge step signal. The step signal cannot directly reach the original first D flip-flop. Instead, it must sequentially pass through these four newly added flip-flops under the synchronous control of the main high-frequency clock for multi-stage pacing and state latching delay. This cascaded architecture not only greatly expands the state space and counting capacity of the working monitoring circuit and lengthens the time monitoring window, but more importantly, the intermediate nodes of these four newly added flip-flops directly provide the secondary-side decision network with extremely accurate, paced-aligned hardware time base frequency divider nodes. By using different frequency division combinations of the high-frequency internal clock using these four newly added flip-flops, a 100kHz narrow pulse reference and a 10kHz wide pulse reference with extremely stable frequencies, unaffected by transient jumps in the preceding counters, can be directly derived. Even if the chip's internal oscillator experiences a slight inherent frequency drift due to a significant increase in ambient temperature, the synchronous state machine network composed of these four flip-flops can control the frequency tolerance of the pulse stream output to the control signal line within a very small range through a fixed frequency division ratio and timing alignment, completely isolating the interference of transient substrate noise on the encoded signal, fundamentally ensuring the absolute accuracy of the primary-side microcontroller's decoding.

[0061] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A magnetically isolated IGBT drive system, characterized in that, include: The primary-side low-voltage module is used to connect to an external microcontroller; The secondary high-voltage side module is used to connect functional semiconductor devices. It is communicatively connected to the primary low-voltage side module via an isolation strip module. The secondary high-voltage side module includes an adjustable power supply unit, an anti-interference unit, an adaptive drive unit, and a cooperative protection unit. The adjustable power supply unit includes power input terminals connected to the anti-interference unit, the adaptive drive unit, and the cooperative protection unit, respectively. The primary low-voltage side module is connected to the first input terminal of the anti-interference unit via the isolation strip module. The output terminal of the anti-interference unit is connected to the input terminal of the adaptive drive unit. The first output terminal of the adaptive drive unit is connected to the control electrode of the power semiconductor device. The second output terminal of the adaptive drive unit is connected to the first input terminal of the cooperative protection unit. The first output terminal of the cooperative protection unit is connected to the second input terminal of the anti-interference unit. The second output terminal of the cooperative protection unit is connected to the primary low-voltage side module via the isolation strip module.

2. The magnetically isolated IGBT drive system according to claim 1, characterized in that, The primary low-voltage side module includes an isolation transmission unit and an isolation status monitoring and receiving unit. The secondary high-voltage side module includes an isolation transmission and receiving unit and an isolation status monitoring and transmitting unit. The input terminal of the isolation transmission and receiving unit is connected to an external microcontroller. The output terminal of the isolation transmission and receiving unit is connected to the first input terminal of the anti-interference unit. The isolation transmission and receiving unit is connected to the isolation transmission and receiving unit through an isolation strip module. The input terminal of the isolation status monitoring and transmitting unit is connected to the second output terminal of the collaborative protection unit. The output terminal of the isolation status monitoring and receiving unit is connected to an external microcontroller. The isolation status monitoring and transmitting unit and the isolation status monitoring and receiving unit are connected through an isolation strip module.

3. The magnetically isolated IGBT drive system according to claim 2, characterized in that, The isolation strip module includes a first magnetic coupling transformer and a second magnetic coupling transformer. The output of the isolation transmission transmitting unit is connected to the primary side of the first magnetic coupling transformer, and the secondary side of the first magnetic coupling transformer is connected to the input of the isolation transmission receiving unit. The output of the isolation status monitoring transmitting unit is connected to the primary side of the second magnetic coupling transformer, and the secondary side of the second magnetic coupling transformer is connected to the input of the isolation status monitoring receiving unit.

4. The magnetically isolated IGBT drive system according to claim 1, characterized in that, The anti-interference unit includes a filter circuit and an RS flip-flop shaping circuit; the input terminal of the filter circuit serves as the first input terminal of the anti-interference unit, the output terminal is connected to the input terminal of the RS flip-flop shaping circuit, the output terminal of the RS flip-flop shaping circuit serves as the output terminal of the anti-interference unit, and the control terminal of the RS flip-flop shaping circuit serves as the second input terminal of the anti-interference unit and is connected to the first output terminal of the cooperative protection unit.

5. The magnetically isolated IGBT drive system according to claim 1, characterized in that, The adaptive drive unit includes a high-side drive circuit and a low-side drive circuit; the input terminal of the high-side drive circuit and the input terminal of the low-side drive circuit are connected to the output terminal of the anti-interference unit, the output terminal of the high-side drive circuit and the output terminal of the low-side drive circuit are connected to the control electrode of the power semiconductor device, and the control terminals of the high-side drive circuit and the low-side drive circuit are both connected to the first input terminal of the cooperative protection unit.

6. The magnetically coupled isolated IGBT drive system according to claim 1, characterized in that, The collaborative protection unit includes a desaturation protection circuit, an overcurrent protection circuit, an overtemperature protection circuit, an undervoltage protection circuit, and a soft shutdown control circuit. The input terminal of the desaturation protection circuit is connected to the power electrode of the power semiconductor device. The input terminal of the overcurrent protection circuit is also connected to the power electrode of the power semiconductor device. The output terminal of the desaturation protection circuit is connected to the first input terminal of the soft shutdown control circuit. The output terminal of the overcurrent protection circuit is connected to the second input terminal of the soft shutdown control circuit. The output terminal of the overtemperature protection circuit is connected to the third input terminal of the soft shutdown control circuit. The output terminal of the undervoltage protection circuit is connected to the fourth input terminal of the soft shutdown control circuit. The first output terminal of the soft shutdown control circuit is connected to the second input terminal of the anti-interference unit. The second output terminal of the soft shutdown control circuit is connected to the input terminal of the isolation state monitoring and transmitting unit.

7. The magnetically isolated IGBT drive system according to claim 1, characterized in that, The adjustable power supply unit includes a bandgap reference source circuit and a multi-channel adjustable LDO circuit; the output terminal of the bandgap reference source circuit is connected to the input terminal of the multi-channel adjustable LDO circuit, and the multiple output terminals of the multi-channel adjustable LDO circuit are respectively connected to the power input terminals of the anti-interference unit, the adaptive drive unit, and the cooperative protection unit.

8. The magnetically coupled isolated IGBT drive system according to claim 2, characterized in that, The isolation status monitoring and sending unit includes a fault reporting module. The input of the fault reporting module is connected to the second output of the collaborative protection unit, and the output of the fault reporting module is connected to the primary side of the second magnetic coupling transformer.

9. The magnetically isolated IGBT drive system according to claim 2, characterized in that, The isolated transmission transmitting unit integrates a refresh module circuit, and the isolated transmission receiving unit integrates a detection circuit; the input terminal of the refresh module circuit is connected to an external microcontroller, and the output terminal of the refresh module circuit is connected to the primary side of the first magnetic coupling transformer; the input terminal of the detection circuit is connected to the secondary side of the first magnetic coupling transformer, and the output terminal of the detection circuit is connected to the first input terminal of the anti-interference unit.

10. The magnetically coupled isolated IGBT drive system according to claim 6, characterized in that, The desaturation protection circuit is composed of a constant current source charging module, a blanking time control circuit, a high voltage detection diode interface, a voltage comparator, and a fault latch trigger connected in sequence; the input terminal of the blanking time control circuit is connected to the output terminal of the adaptive drive unit.

Images