A high parallelism storage-computation integrated polar code decoding method based on coset decoding

Abstract

The application discloses a high-parallelism storage-computation integrated polar code decoding method based on coset decoding, and belongs to the technical field of channel coding and decoding. The method comprises the following steps: constructing an error pattern group and a check constraint subgroup; performing coset division on the error pattern group to obtain a set of mutually disjoint cosets; screening a limited number of minimum cosets based on the minimum Hamming weight of the cosets; and performing parallel decoding processing on the paths corresponding to the minimum cosets in the storage-computation integrated architecture. k The number of paths in the traditional multi-bit decoding is reduced from 2 to a preset number L through coset division, and the parallel execution of the likelihood information updating and the path metric calculation is realized in combination with the calculation-type storage array, so that the decoding performance is ensured, the calculation complexity and the hardware resource consumption are significantly reduced, and the decoding throughput and the energy efficiency are improved.

Description

Technical Field

[0001] This invention relates to the field of channel coding and decoding technology, and in particular to a high-parallelism in-memory polar code decoding method based on coset decoding. Background Technology

[0002] Since its introduction by Professor Erdal Arikan in 2008, polar codes have become a milestone technology in the coding field due to their provable channel capacity approximation performance, and were selected by 3GPP as the standard coding scheme for the control channel in 5G eMBB scenarios in 2016.

[0003] Polar code decoding technology has undergone three generations of core evolution: the first generation is the Successive Cancellation (SC) decoding proposed by Professor Erdal Arikan, which has a simple structure but poor decoding performance and is difficult to meet the needs of high-speed communication; the second generation is the Successive Cancellation List (SCL) decoding, which reduces the bit error rate by using a list of multiple candidate paths and greatly improves decoding performance, becoming the mainstream solution for polar codes; the third generation consists of various improved SCLs (such as MSCL, CA-SCL, etc.), which focus on optimizing the efficiency and parallelism of SCL.

[0004] Multi-bit Successive Cancellation List (MSCL) decoding algorithms can overcome the limitations of bit-by-bit serial decoding by pre-decoding the decision layer into blocks, decoding multiple (M) bits within a block at a time, thereby increasing parallelism and effectively reducing decoding latency. However, this introduces new technical bottlenecks: limited parallelism and low decoding efficiency for complex modes. When decoding reaches a sub-block containing multiple (k) information bits (i.e., a scenario where non-frozen bits are concentrated), the number of possible paths generated by splitting increases exponentially with the increase of the number of bits M decoded in a single operation—in a decision involving k information bits, the path splitting of the entire information bit group will generate 2 k If k approaches M, then we can use 2... M This serves as the extreme upper limit to consider. This exponentially increasing path expansion not only significantly increases the number of candidate path traversals, leading to a surge in MSCL computation, but also significantly increases hardware implementation complexity: path value calculation consumes a large amount of computing resources, and the sorting unit experiences increased latency due to the increase in candidate paths, ultimately severely impacting decoding speed and power consumption control.

[0005] Therefore, how to effectively control the number of path extensions and reduce decoding complexity while maintaining high parallelism has become a technical problem that the MSCL algorithm urgently needs to solve. Summary of the Invention

[0006] The main objective of this invention is to provide a highly parallel in-memory polar code decoding method based on coset decoding.

[0007] Another objective of this invention is to propose a high-parallelism in-memory polar code decoding device based on coset decoding.

[0008] The third objective of this invention is to provide a computer device.

[0009] A fourth objective of this invention is to provide a non-transitory computer-readable storage medium.

[0010] To achieve the above objectives, a first aspect of the present invention proposes a high-parallelism in-memory polar code decoding method based on coset decoding, comprising:

[0011] Constructing the error mode group and the validation constraint subgroup: Define the binary vector space of length M as the error mode group G = ({0,1}). M , ⊕), where ⊕ represents bitwise XOR operation; construct a parity check matrix H based on the polar code generator matrix, and obtain a set of binary vectors H satisfying Hc^T = 0 as a subgroup of the error mode group; Perform minimum error pattern coset partitioning: For any error pattern e ∈ G, construct coset e ⊕ H = {e ⊕ h | h ∈ H}, traverse the error pattern group and remove duplicates to obtain a set of disjoint cosets; Filtering the minimum error cosets: Calculate the minimum Hamming weight of the error patterns in each coset, sort by coset weight, and filter out the minimum cosets of a preset number L as the candidate path set; Perform in-memory computation-based parallel multi-bit decoding: Provide an in-memory computation-based decoding architecture, which includes a computational storage array, a coset representative lookup table, a path metric calculation unit, and a path filtering unit; store and update the log-likelihood ratio in the computational storage array, perform multi-bit parallel path expansion based on the candidate path set, and complete path metric calculation and path filtering within the storage array, retaining the L paths with the smallest path metric values ​​as the decoding results.

[0012] In one embodiment of the present invention, the construction of the error mode group and the verification constraint subgroup includes: Determine the single-step decoding code length, and use all binary numbers of that length as a set. Perform an XOR operation as the group operation to form an error mode group, satisfying |G| = 2. M ; The parity-check matrix is ​​derived from the generator matrix at the polar code encoding end. Calculate all binary numbers that satisfy the check condition, forming a set of check bits, which serves as a subgroup of the error mode group, i.e., the check constraint subgroup, satisfying |H| = 2. M-k , where k is the number of information bits.

[0013] In one embodiment of the present invention, performing minimum error pattern coset partitioning includes: Based on the error mode group and the check constraint subgroup, the minimum weight error mode is selected as the coset representative element. For each minimum weight error pattern, calculate the XOR set of the error pattern and all elements in the check constraint subgroup as the coset; By recording the generated cosets and removing duplicates, multiple disjoint cosets can be obtained.

[0014] In one embodiment of the present invention, the filtering of the finite minimum error coset includes: Calculate the minimum Hamming weight of all error patterns in each coset as the coset weight; Sort by coset weight and select the minimum number of cosets as parallel decoding units.

[0015] In one embodiment of the present invention, the execution of in-memory computing-based parallel multi-bit decoding includes: Using the optimal path retained after coset partitioning as the parent path, and based on the updated likelihood information in the computational storage array, multiple bits of the next stage are decided in parallel for each parent path to generate a corresponding number of sub-paths. The path metric calculation unit calculates and accumulates the path metric value for each sub-path, the path filtering unit sorts and truncates the candidate paths, prunes them after verification, and then backtracks from the decoding endpoint to select the globally optimal path based on the path metric value.

[0016] In one embodiment of the present invention, it further includes: Calculate and sort the path metrics for all extended paths and the current decision codeword, and retain a preset number of paths with the smallest path metrics, where the preset number L << 2. k ; Repeat the decoding steps until all bit groups are decoded, and then recursively select the path with the smallest path metric value as the decoding result.

[0017] In one embodiment of the present invention, a path extension scheme is further included based on the number of information bits: When the number of information bits k is less than a preset threshold, iterate through all 2 k Combinations of information bits; When the number of information bits k is greater than or equal to a preset threshold, the minimum coset path compression mechanism is adopted.

[0018] To achieve the above objectives, a second aspect of the present invention provides a high-parallelism in-memory polar code decoding device based on coset decoding, comprising: The building module is used to construct the error mode group and the validation constraint subgroup: the binary vector space of length M is defined as the error mode group G = ({0,1}). M , ⊕), where ⊕ represents bitwise XOR operation; construct a parity check matrix H based on the polar code generator matrix, and obtain a set of binary vectors H satisfying Hc^T = 0 as a subgroup of the error mode group; The coset partitioning module is used to perform minimum error pattern coset partitioning: for any error pattern e ∈ G, construct coset e ⊕ H = {e ⊕ h | h ∈ H}, traverse the error pattern group and remove duplicates to obtain a set of disjoint cosets; The filtering module is used to filter a finite set of minimum error cosets: calculate the minimum Hamming weight of the error patterns in each coset, sort them by coset weight, and filter out a preset number L of minimum cosets as a candidate path set. A parallel decoding module is used to perform in-memory computation-based parallel multi-bit decoding: it provides an in-memory computation-based decoding architecture, which includes a computational storage array, a coset representative lookup table, a path metric calculation unit, and a path filtering unit; it stores and updates the log-likelihood ratio in the computational storage array, performs multi-bit parallel path expansion based on the candidate path set, and completes path metric calculation and path filtering within the storage array, retaining the L paths with the smallest path metric values ​​as the decoding results.

[0019] To achieve the above objectives, a third aspect of this application provides a computer device, including a processor and a memory; wherein the processor reads executable program code stored in the memory to run a program corresponding to the executable program code, for implementing a high-parallelism in-memory polar code decoding method based on coset decoding as described in the first aspect embodiment.

[0020] To achieve the above objectives, the fourth aspect of this application proposes a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements a high-parallel in-store and computational polar code decoding method based on coset decoding as described in the first aspect embodiment.

[0021] The embodiments of the present invention have the following beneficial effects: This invention reduces the number of path extensions from exponential to a preset range through coset partitioning and minimum coset selection mechanisms. Combined with an in-memory computing architecture, it allocates independent decoding logic units to each minimum coset, achieving multi-path parallel synchronous decoding. While maintaining excellent bit error rate performance, it significantly improves decoding parallelism, reduces computational complexity and hardware implementation difficulty, and effectively enhances decoding efficiency. It possesses good engineering application value and scalability. Attached Figure Description

[0022] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A flowchart of a high-parallelism in-memory polar code decoding method based on coset decoding is provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the verification matrix structure provided in an embodiment of the present invention; Figure 3 A simplified flowchart of the in-memory computing likelihood information update process provided in this embodiment of the invention; Figure 4 This is a schematic diagram of the decoding path structure provided in an embodiment of the present invention; Figure 5 A simplified flowchart of a partial verification and update process provided in an embodiment of the present invention; Figure 6 A simplified flowchart of the reverse recursive path selection process provided in this embodiment of the invention; Figure 7 A flowchart of a multi-bit parallel successive elimination list decoding algorithm for polar codes provided in an embodiment of the present invention; Figure 8 This is a structural diagram of a high-parallelism in-memory polar code decoding device based on coset decoding, provided in an embodiment of the present invention. Detailed Implementation

[0023] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0025] In traditional MSCL decoding algorithms, multi-bit decisions need to be processed. The combination of bit patterns and decision results results in storage and computational complexity of up to [amount missing]. This severely restricts parallelism and hardware implementation efficiency. To address this issue, this invention introduces the concept of coset partitioning, constructing the error mode space as an Abelian group, using the parity bit set as a subgroup, and dividing all possible error modes into disjoint cosets through coset decomposition. The coset with the smallest Hamming weight is selected as the parallel decoding unit, thereby compressing the number of path extensions from exponential to a preset parallelism (e.g., 32 paths).

[0026] Building upon this foundation, the present invention further integrates a memory-computing architecture, allocating an independent decoding logic unit to each parallel decoding unit to achieve parallel updates of likelihood information, synchronous path expansion, and parallel computation of metrics; simultaneously, it dynamically selects the path expansion scheme based on the number of information bits (when...). Traverse all Such combinations, when This method utilizes a minimum coset error code table (calling the table in real time) and supplements it with partial checksum early verification and reverse recursive optimal path selection. While maintaining excellent bit error rate performance, this method significantly improves decoding parallelism and throughput, reduces hardware resource overhead, and has good engineering application value.

[0027] The following describes, with reference to the accompanying drawings, a high-parallelism in-memory polar code decoding method based on coset decoding proposed according to an embodiment of the present invention.

[0028] Example 1 This embodiment provides a high-parallelism in-memory polar code decoding method based on coset decoding, namely, proposing a path compression mechanism based on coset partitioning. By constructing the error mode space, which is composed of the set of binary numbers representing the code length of a single step decoding step, as an Abelian group, and using a check constraint subgroup to partition it into cosets, all error modes are mapped to several disjoint cosets. Furthermore, a minimum Hamming weight selection strategy is used to retain only a limited number of optimal cosets as the decoding path set.

[0029] The M-bit binary vector space is defined by the single-step decoding code length: G = ({0,1} M , ⊕), where |G| = 2 M Based on the polar code generator matrix, a parity check matrix H is derived, and a parity check constraint subgroup H = {c ∈ {0,1} is defined. M | Hc^T = 0}.

[0030] like Figure 1 As shown, the method includes the following steps: S1, Constructing the error mode group and the validation constraint subgroup: Define the binary vector space of length M as the error mode group G = ({0,1}). M, ⊕), where ⊕ represents bitwise XOR operation; construct a parity check matrix H based on the polar code generator matrix, and obtain a set of binary vectors H satisfying Hc^T = 0 as a subgroup of the error mode group.

[0031] Specifically, the single-step decoding code length M is determined; in this embodiment, M = 16 bits, corresponding to the target parallelism requirement of 16. The set of M-bit binary numbers is defined as follows: The set contains =65536 elements, corresponding to all possible error patterns. Define the multiplication operation in the set as the XOR operation ⊕, and verify that the set and the XOR operation form an Abelian group: closure (the XOR of two 16-bit binary numbers results in a 16-bit binary number), associativity ((a⊕b)⊕c = a⊕(b⊕c)), identity element (a vector of all zeros 000…0), and modular inverse (the modular inverse of each element is itself, because a⊕a=000…0). Therefore, G=( ,⊕) constitute an Abelian group.

[0032] Furthermore, a generation matrix is ​​generated based on the polar code encoding end. The (16×16) derivation yields a parity check matrix H(k×16), where k is the number of information bits in the decoded segment, ensuring that the parity check matrix can accurately distinguish between valid and erroneous codewords. Calculate all codes that satisfy the parity check condition. A 16-bit binary number c, where c = 0 mod 2, forms the parity bit set H. We verify that the XOR operation of H with respect to the group G satisfies the subgroup conditions: containing the identity element (a vector of all zeros satisfies the parity condition), closure (the parity condition is still satisfied after XORing any two parity bits), and existence of inverses (each parity bit is itself an inverse). If so, we determine that H is a subgroup of G, denoted as H ≤ G. Figure 2 The diagram shown is a schematic of the verification matrix structure.

[0033] It should be noted that the traditional MSCL error pattern table construction, for M=16, has a total of 65536 bit patterns and 65536 possible decision results, resulting in an error pattern table complexity of 65536 × 65536 × 8, which severely impacts speed and hardware implementation. This invention optimizes this through a coset method: for a single 16-bit data set, an error pattern group G=({0,1}) is constructed. 16 Based on the polar code generator matrix, the check constraint subgroup H is derived, resulting in 2 k We select the smallest weight cosets, sort them in ascending order of coset weight, and choose the top 32 smallest cosets as parallel decoding units, which greatly reduces the number of paths and tabulation complexity.

[0034] S2, perform minimum error pattern coset partitioning: for any error pattern e ∈ G, construct coset e ⊕ H = {e ⊕ h | h ∈ H}, traverse the error pattern group and remove duplicates to obtain a set of disjoint cosets.

[0035] Specifically, the process of handling error patterns essentially involves calculating the coset of the subgroup H. The coset corresponding to the error pattern e is e⊕H = {e⊕c | c∈H}, which is the result of XORing the error vector with all check bits. All elements in the same coset can be represented as "check bit + fixed error", and therefore can correspond to the same error pattern. For example, if the error is e=001, then the elements in the coset e⊕H are all cases where the first check bit is incorrect.

[0036] Furthermore, the element with the smallest Hamming weight (i.e., the fewest error bits) is selected as the representative element of the coset. The data r received by the receiver must belong to a certain coset e⊕H. Once the representative element of this coset is found, the error correction method is r⊕e=c (restoring the parity bit c).

[0037] Specifically, the coset partitioning is performed using a "traversal-calculation-duplicate removal" process, including: Iterate through all 65536 error patterns e in group G and select the smallest weight error pattern as the coset representative element; For each minimum weight error pattern e, compute the coset. ={e⊕h | h∈H}, where h is any parity bit in the parity constraint subgroup H; The generated cosets are recorded using a hash table. If a newly calculated coset has no intersection with an existing coset, it is marked as a new coset.

[0038] The partitioning result is verified by the inherent properties of cosets of the subgroup: all cosets are disjoint (if...). ,but The size of the co-sets is the same (each co-set contains...) (Number of elements), covering the entire group (the union of all cosets is G), ultimately obtaining... A set of mutually exclusive sets.

[0039] S3, Filtering the finite minimum error cosets: Calculate the minimum Hamming weight of the error patterns in each coset, sort by coset weight, and filter out the minimum cosets of a preset number L as the candidate path set.

[0040] Specifically, the "coset weight" of each coset is calculated, which is the minimum Hamming weight of all error modes in the coset (the Hamming weight of the coset representative). Cosets are sorted in ascending order of weight, and a predetermined number of minimum weight cosets are selected as parallel decoding units. In this embodiment, the first 32 cosets are selected, denoted as {C1, C2, ..., C32}, and their corresponding coset representatives are {e1, e2, ..., e32} (the minimum weight error modes of each coset).

[0041] S4, Perform in-memory computation-based parallel multi-bit decoding: Provide an in-memory computation-based decoding architecture, which includes a computational storage array, a coset representative lookup table, a path metric calculation unit, and a path filtering unit; Store and update the log-likelihood ratio in the computational storage array, perform multi-bit parallel path expansion based on the candidate path set, and complete path metric calculation and path filtering within the storage array, retaining the L paths with the smallest path metric values ​​as the decoding results.

[0042] Specifically, the in-memory computing decoding architecture includes: Computational storage arrays are used to store log-likelihood ratios and perform parallel updates; The coset represents the original lookup table and is used to store the minimum storage pattern; The path metric calculation unit is used to perform path metric value calculation and accumulation. The path filtering unit is used to sort and truncate candidate paths.

[0043] Specifically, based on the in-memory computing decoding architecture, independent computing resources are allocated to each candidate path, and the following operations are performed in parallel and synchronously: (1) In-memory computation-integrated likelihood information update: Likelihood information (log-likelihood ratio LLR) is the basic input for decoding. In traditional architectures, the storage and updating of LLR are separated, resulting in data transfer latency. This step uses an in-memory computation-integrated architecture to store the LLR in computational storage units, update the likelihood information in parallel, and select from within the storage, reducing computational selection time. The computation still adopts the basic iterative process of traditional MSCL, updating and calculating the log-likelihood ratio and passing it to the s-decision layer (corresponding to the multi-bit decision layer), and directly saving the updated likelihood information in the storage array for subsequent decoding steps, without additional storage read latency. Figure 3 The diagram shown is a simplified flowchart of the in-memory computing likelihood information update process. (2) Error pattern partitioning based on coset: Select the corresponding path extension scheme according to the bit pattern of the current decoding block. If the number of information bits k is less than 5, obtain the set of parity bits in the coset and traverse all of them. A combination of information bits; if the number of information bits k is greater than or equal to 5, call the predefined minimum coset error code to compress the number of paths to 32.

[0044] (3) Decoding Path Expansion: Based on coset partitioning, the retained candidate paths are expanded in parallel using multiple bits. The optimal path retained after coset partitioning is used as the parent path. For each parent path, multiple bits for the next stage are determined in parallel based on the likelihood information updated in the in-memory computing unit, generating a corresponding number of sub-paths. Then, the path metric for each sub-path is calculated in parallel using an in-memory computing architecture for subsequent path selection. For example... Figure 4 The diagram shown is a schematic of the decoding path structure.

[0045] (4) Decoding Part Verification and Update Based on In-Memory Computing: Through an in-memory computing design, decoding part verification and updates are performed in blocks. During path expansion, some decoded bits are pre-verified to eliminate obviously erroneous paths, preventing invalid paths from entering subsequent recursions and further reducing the number of paths. For example... Figure 5 The diagram shown is a simplified flowchart of a partial verification and update process.

[0046] (5) Reverse recursive path selection: MSCL decoding adopts a bidirectional processing flow of forward expansion plus reverse recursion. Forward expansion generates candidate paths, and reverse recursion backtracks from the decoding endpoint to select the globally optimal path. For example Figure 6 The diagram shown is a simplified flowchart of the reverse recursive path selection process.

[0047] In this specific implementation, the code length N=1024, the number of multi-bit decisions M=16, and the decision layer... The code of length N is divided according to the number of multi-bit decisions M, and each group of bits is denoted as... For the current bit group The calculation process of the serial elimination list algorithm involves iteratively calculating the log-likelihood ratio of the received channel layer according to the f and g operation rules. When the algorithm reaches... When layering, the decision codeword is obtained by using the M LLR information retained in the current layer according to the following rules. , representing the decision information of M codewords in layer s. This process is performed in parallel in the computational storage unit, with the corresponding L L path in the list being calculated and stored simultaneously.

[0048] Perform multi-bit decision-making and select the corresponding path expansion scheme based on the bit pattern. For all expansion paths... The PM path metric is calculated based on the current decision codeword, using the following formula:

[0049] in, Represents the current expansion path Bit distribution, and These are the extended path codeword and the current decoded codeword, respectively. Bit number. After calculating all extended paths, the set of PM values ​​is obtained. Sort all paths according to their PM value, and retain the L paths with the smallest PM values ​​(the preset number of candidate paths L << 2). k (This reduces the path expansion complexity from exponential to a fixed size), thus completing the first... The bit decoding and path expansion of the group have been confirmed. The retained path information will then be mapped to layer 0 using a constructed matrix, merged with the previous decoding results, and saved into the corresponding path's data. Simultaneously, verification and updates of the decoding portion based on in-memory computing are performed.

[0050] Repeat the above process until all bit groups are decoded, then recursively select the path with the smallest PM value as the final decoding result. The complete execution flow of the above-described multi-bit parallel successive elimination list decoding of polar codes based on coset decoding is as follows: Figure 7 As shown, by integrating coset partitioning with in-memory computing architecture, high parallelism and low complexity polar code decoding are achieved, effectively balancing decoding performance and execution efficiency.

[0051] Example 2 This invention also provides a high-parallelism in-memory polar code decoding device based on coset decoding, such as... Figure 8 As shown, the device 10 includes: Module 100 is used to construct the error mode group and the validation constraint subgroup: the binary vector space of length M is defined as the error mode group G = ({0,1}). M , ⊕), where ⊕ represents bitwise XOR operation; construct a parity check matrix H based on the polar code generator matrix, and obtain a set of binary vectors H satisfying Hc^T = 0 as a subgroup of the error mode group; The coset partitioning module 200 is used to perform minimum error pattern coset partitioning: for any error pattern e ∈ G, construct coset e ⊕ H = {e ⊕ h | h ∈ H}, traverse the error pattern group and remove duplicates to obtain a set of disjoint cosets; The filtering module 300 is used to filter a finite set of minimum error cosets: calculate the minimum Hamming weight of the error patterns in each coset, sort them by coset weight, and filter out a preset number L of minimum cosets as a candidate path set. The parallel decoding module 400 is used to perform in-memory computation-based parallel multi-bit decoding: it provides an in-memory computation-based decoding architecture, which includes a computational storage array, a coset representative lookup table, a path metric calculation unit, and a path filtering unit; it stores and updates the log-likelihood ratio in the computational storage array, performs multi-bit parallel path expansion based on the candidate path set, and completes path metric calculation and path filtering within the storage array, retaining the L paths with the smallest path metric values ​​as the decoding results.

[0052] Example 3 To implement the methods of the above embodiments, the present invention also provides a computer device, which includes a memory and a processor; wherein the processor runs a program corresponding to the executable program code by reading executable program code stored in the memory, so as to implement the various steps of the methods described above.

[0053] Example 4 To implement the above embodiments, this application also proposes a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the method described in the foregoing embodiments.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0055] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0056] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

Claims

1. A high-parallelism in-memory polar code decoding method based on coset decoding, characterized in that, include: Constructing the error mode group and the validation constraint subgroup: Define the binary vector space of length M as the error mode group G = ({0,1}). M , ⊕), where ⊕ represents bitwise XOR operation; construct a parity check matrix H based on the polar code generator matrix, and obtain a set of binary vectors H satisfying Hc^T = 0 as a subgroup of the error mode group; Perform minimum error pattern coset partitioning: For any error pattern e ∈ G, construct coset e ⊕ H = {e ⊕ h |h ∈ H}, traverse the error pattern group and remove duplicates to obtain a set of disjoint cosets; Filtering the minimum error cosets: Calculate the minimum Hamming weight of the error patterns in each coset, sort by coset weight, and filter out the minimum cosets of a preset number L as the candidate path set; Perform in-memory computation-based parallel multi-bit decoding: Provide an in-memory computation-based decoding architecture, which includes a computational storage array, a coset representative lookup table, a path metric calculation unit, and a path filtering unit; store and update the log-likelihood ratio in the computational storage array, perform multi-bit parallel path expansion based on the candidate path set, and complete path metric calculation and path filtering within the storage array, retaining the L paths with the smallest path metric values ​​as the decoding results.

2. The method as described in claim 1, characterized in that, The construction of the error mode group and the verification constraint subgroup includes: Determine the single-step decoding code length, and use all binary numbers of that length as a set. Perform an XOR operation as the group operation to form an error mode group, satisfying |G| = 2. M ; The parity-check matrix is ​​derived from the generator matrix at the polar code encoding end. Calculate all binary numbers that satisfy the check condition, forming a set of check bits, which serves as a subgroup of the error mode group, i.e., the check constraint subgroup, satisfying |H| = 2. M-k , where k is the number of information bits.

3. The method as described in claim 1, characterized in that, The execution minimum error mode coset partitioning includes: Based on the error mode group and the check constraint subgroup, the minimum weight error mode is selected as the coset representative element. For each minimum weight error pattern, calculate the XOR set of the error pattern and all elements in the check constraint subgroup as the coset; By recording the generated cosets and removing duplicates, multiple disjoint cosets can be obtained.

4. The method as described in claim 1, characterized in that, The filtering of the finite minimum error coset includes: Calculate the minimum Hamming weight of all error patterns in each coset as the coset weight; Sort by coset weight and select the minimum number of cosets as parallel decoding units.

5. The method as described in claim 1, characterized in that, The execution of in-memory computing-based parallel multi-bit decoding includes: Using the optimal path retained after coset partitioning as the parent path, and based on the updated likelihood information in the computational storage array, multiple bits of the next stage are decided in parallel for each parent path to generate a corresponding number of sub-paths. The path metric calculation unit calculates and accumulates the path metric value for each sub-path, the path filtering unit sorts and truncates the candidate paths, prunes them after verification, and then backtracks from the decoding endpoint to select the globally optimal path based on the path metric value.

6. The method as described in claim 2, characterized in that, Also includes: Calculate and sort the path metrics for all extended paths and the current decision codeword, and retain a preset number of paths with the smallest path metrics, where the preset number L << 2. k ; Repeat the decoding steps until all bit groups are decoded, and then recursively select the path with the smallest path metric value as the decoding result.

7. The method as described in claim 1, characterized in that, It also includes selecting a path extension scheme based on the number of information bits: When the number of information bits k is less than a preset threshold, iterate through all 2 k Combinations of information bits; When the number of information bits k is greater than or equal to a preset threshold, the minimum coset path compression mechanism is adopted.

8. A high-parallelism in-memory polar code decoding device based on coset decoding, characterized in that, include: The building module is used to construct the error mode group and the validation constraint subgroup: the binary vector space of length M is defined as the error mode group G = ({0,1}). M , ⊕), where ⊕ represents bitwise XOR operation; construct a parity check matrix H based on the polar code generator matrix, and obtain a set of binary vectors H satisfying Hc^T = 0 as a subgroup of the error mode group; The coset partitioning module is used to perform minimum error pattern coset partitioning: for any error pattern e ∈ G, construct coset e⊕ H = {e ⊕ h | h ∈ H}, traverse the error pattern group and remove duplicates to obtain a set of disjoint cosets; The filtering module is used to filter a finite set of minimum error cosets: calculate the minimum Hamming weight of the error patterns in each coset, sort them by coset weight, and filter out a preset number L of minimum cosets as a candidate path set. A parallel decoding module is used to perform in-memory computation-based parallel multi-bit decoding: it provides an in-memory computation-based decoding architecture, which includes a computational storage array, a coset representative lookup table, a path metric calculation unit, and a path filtering unit; it stores and updates the log-likelihood ratio in the computational storage array, performs multi-bit parallel path expansion based on the candidate path set, and completes path metric calculation and path filtering within the storage array, retaining the L paths with the smallest path metric values ​​as the decoding results.

9. A computer device comprising a processor and a memory, characterized in that, The processor runs a program corresponding to the executable program code stored in the memory by reading the executable program code stored in the memory, so as to implement a high-parallelism in-memory polar code decoding method based on coset decoding as described in any one of claims 1-7.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements a highly parallel in-memory polar code decoding method based on coset decoding as described in any one of claims 1-7.

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