Children story machine playing system based on NFC near field communication

Abstract

This invention belongs to the field of near-field communication (NFC) technology, specifically relating to a children's story machine playback system based on NFC near-field communication. The system includes a near-field communication chip, a main control processor, an RF front-end impedance detection circuit, an adjustable impedance matching network, a receiver demodulator, and an antenna. The RF front-end impedance detection circuit collects the voltage signal corresponding to the reflected power at the antenna node. The main control processor calculates the antenna detuning offset based on the voltage signal and generates a control voltage, adjusting the capacitance value of the varactor diode in the adjustable impedance matching network to lock the antenna resonant frequency to the carrier frequency of the passive tag. During the stage of receiving the tag's load modulation signal, the main control processor generates a reference voltage adjustment signal based on the matching state, adjusting the flip-level threshold of the receiver demodulator. This invention eliminates antenna detuning caused by non-standard holding postures, ensures the coupling efficiency of RF energy in the detuned state, and maintains the connectivity of the near-field communication link under complex spatial postures.

Description

Technical Field

[0001] This invention belongs to the field of near-field communication technology, specifically relating to a children's story machine playback system based on NFC near-field communication. Background Technology

[0002] Existing children's story machine playback systems based on near-field communication (NFC) include a story machine motherboard, a NFC chip, and passive tags. The NFC chip on the motherboard is connected to a NFC antenna on a printed circuit board via a fixed-parameter impedance matching network. When the story machine approaches a book with a passive tag attached, the NFC chip emits radio frequency (RF) energy through the antenna. The passive tag senses the RF energy and returns a load-modulated signal containing audio index data. The impedance matching network in existing technology consists of a capacitor with a fixed capacitance and an inductor with a fixed inductance. Its resonant frequency is fixed at the factory based on the nominal inductance and nominal parasitic capacitance of the antenna in free space. During reading, the NFC chip continuously transmits and receives signals at a fixed transmit power and a fixed demodulation reference voltage.

[0003] When a child holds a story machine and touches the passive tag, the angle of their hand grip and the contact distance change randomly, causing slight deformation of the physical shape of the near-field communication antenna under stress. Simultaneously, the human body introduces additional parasitic capacitance. The combined effect of this change in antenna physical shape and the additional parasitic capacitance alters the equivalent inductance and equivalent parasitic capacitance of the near-field communication antenna in its current operating state. This causes the antenna resonant frequency to deviate from the carrier frequency of the passive tag, resulting in radio frequency detuning and reflection loss. The fixed-parameter impedance matching network cannot respond to the dynamic changes in the antenna's equivalent inductance and equivalent parasitic capacitance, preventing radio frequency energy from coupling to the passive tag in the detuned state. When the receiver demodulator processes the distorted signal according to a fixed reference voltage, data errors occur, leading to data reading failures in the near-field communication link under non-standard holding postures. Summary of the Invention

[0004] The purpose of this invention is to provide a children's story machine playback system based on NFC near-field communication, which can solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A children's story machine playback system based on NFC near-field communication includes a story machine motherboard, a near-field communication chip integrated into the story machine motherboard, a main control processor, an RF front-end impedance detection circuit, an adjustable impedance matching network, a receiver demodulator, and an NFC antenna. The transmit pin of the near-field communication chip is connected to the input terminal of the adjustable impedance matching network, and the output terminal of the adjustable impedance matching network is connected to the NFC antenna. The detection terminal of the RF front-end impedance detection circuit is connected to the node between the adjustable impedance matching network and the NFC antenna. The output terminal of the RF front-end impedance detection circuit is connected to the first input pin of the main control processor, and the first output pin of the main control processor is connected to the... The control terminal of the adjustable impedance matching network is connected to the reference voltage adjustment terminal of the receiver demodulator via the second output pin of the main control processor. The RF front-end impedance detection circuit collects the voltage signal corresponding to the antenna reflection power at the node and transmits it to the main control processor. The main control processor calculates the antenna detuning offset based on the voltage signal and generates a corresponding first control voltage. The main control processor outputs the first control voltage to the adjustable impedance matching network to adjust the capacitance value of the internal varactor diode. During the stage of receiving the passive NFC tag load modulation signal, the main control processor generates a reference voltage adjustment signal based on the matching state corresponding to the first control voltage and outputs it to the receiver demodulator.

[0006] Preferably, the RF front-end impedance detection circuit includes a directional coupler, a detector diode, a first low-pass filter, and an analog-to-digital converter (ADC). The input terminal of the directional coupler is connected to the transmit pin of the near-field communication chip, the coupling terminal of the directional coupler is connected to the anode of the detector diode, the cathode of the detector diode is connected to the input terminal of the first low-pass filter, the output terminal of the first low-pass filter is connected to the analog input terminal of the ADC, and the digital output terminal of the ADC serves as the output terminal of the RF front-end impedance detection circuit, connected to the first input pin of the main control processor. The main control processor is internally configured with a detuning offset register. The main control processor performs a difference operation between the digital voltage value output by the ADC and a pre-stored rated resonant voltage value, and stores the difference obtained from the difference operation in the detuning offset register as the antenna detuning offset.

[0007] Preferably, the adjustable impedance matching network includes a first series inductor, a first varactor diode, a second varactor diode, a first DC blocking capacitor, and a second DC blocking capacitor. The first end of the first series inductor serves as the input terminal of the adjustable impedance matching network and is connected to the transmit pin of the near-field communication chip. The second end of the first series inductor is connected to the cathodes of the first varactor diode and the second varactor diode, respectively. The anode of the first varactor diode is grounded through the first DC blocking capacitor, and the anode of the second varactor diode is grounded through the second DC blocking capacitor. The anodes of the first and second varactor diodes are respectively connected to the first output pin of the main control processor. The first and second DC blocking capacitors are used to block the DC component in the first control voltage output by the main control processor from entering the NFC antenna.

[0008] Preferably, the main control processor is internally configured with non-volatile memory and a digital signal processing core. The non-volatile memory pre-stores a mapping table between impedance matching states and reference voltage compensation values. Before receiving the passive NFC tag load modulation signal, the digital signal processing core reads the value of the currently output first control voltage. The digital signal processing core searches the mapping table based on the value of the first control voltage to obtain the reference voltage compensation value corresponding to the current first control voltage. The digital signal processing core performs an accumulation operation on the reference voltage compensation value and a preset fixed reference voltage, and outputs the result of the accumulation operation as the reference voltage adjustment signal through the second output pin of the main control processor.

[0009] Preferably, the receiver demodulator includes an envelope detector circuit, a programmable gain amplifier, and a hysteresis comparator. The input of the envelope detector circuit is connected to the node between the adjustable impedance matching network and the NFC antenna. The output of the envelope detector circuit is connected to the input of the programmable gain amplifier. The output of the programmable gain amplifier is connected to the non-inverting input of the hysteresis comparator. The inverting input of the hysteresis comparator is connected to the second output pin of the main control processor. The output of the hysteresis comparator is connected to the digital baseband input pin of the near-field communication chip. The inverting input of the hysteresis comparator receives the reference voltage adjustment signal to change the flip-flop threshold of the hysteresis comparator.

[0010] Preferably, the NFC antenna is a multi-turn rectangular spiral antenna printed on a flexible circuit board. The flexible circuit board is attached to the edge area of ​​the story machine motherboard and arranged around the grip area of ​​the story machine motherboard. The multi-turn rectangular spiral antenna includes a top layer trace, a middle layer trace, and a bottom layer trace arranged sequentially from the outside to the inside. The top layer trace and the bottom layer trace are connected in series through metallized vias disposed inside the flexible circuit board. The middle layer trace is suspended and not connected to the radio frequency circuit of the near-field communication chip. The middle layer trace physically covers the gap between the top layer trace and the bottom layer trace to compensate for the parasitic capacitance introduced when a child holds the device.

[0011] Preferably, the RF front-end impedance detection circuit further includes a temperature sensor and a compensation operational amplifier. The output of the temperature sensor is connected to the third input pin of the main control processor. The non-inverting input of the compensation operational amplifier is connected to the output of the first low-pass filter. The inverting input of the compensation operational amplifier is connected to the output of the digital-to-analog converter. The input of the digital-to-analog converter is connected to the third output pin of the main control processor. The main control processor has a pre-stored temperature-voltage offset curve of the detector diode. The main control processor extracts the corresponding offset voltage value from the temperature-voltage offset curve based on the ambient temperature value collected by the temperature sensor. The main control processor converts the offset voltage value into an analog signal and outputs it to the inverting input of the compensation operational amplifier through the digital-to-analog converter.

[0012] Preferably, the adjustable impedance matching network further includes a calibration resistor and a switching array. The first end of the calibration resistor is connected to the second end of the first series inductor, and the second end of the calibration resistor is connected to the common terminal of the switching array. The first selection terminal of the switching array is grounded, and the second selection terminal of the switching array is connected to the receiving pin of the near-field communication chip. The control terminal of the switching array is connected to the fourth output pin of the main control processor. During the power-on phase of the story machine, the main control processor controls the switching array to close to the first selection terminal. The main control processor gradually changes the amplitude of the first control voltage output to the first varactor diode and the second varactor diode according to a fixed voltage step, and synchronously reads the DC voltage value at the receiving pin of the near-field communication chip to generate a capacitance-voltage calibration lookup table for the varactor diode.

[0013] Preferably, the receiver demodulator further includes a high-speed analog-to-digital sampler and a field-programmable gate array (FPGA). The analog input of the high-speed analog-to-digital sampler is connected to the output of the hysteresis comparator, the digital output of the high-speed analog-to-digital sampler is connected to the data input of the FPGA, and the clock input of the FPGA is connected to the subcarrier recovery clock output of the near-field communication chip. The FPGA is internally configured with an edge interpolation filter. The edge interpolation filter oversamples the digital signal output by the high-speed analog-to-digital sampler using a specified multiple of the subcarrier recovery clock as the sampling clock. When the edge interpolation filter detects a level transition edge of the digital signal, it performs linear interpolation using the amplitudes of adjacent sampling points to reconstruct the precise bit synchronization clock edge position.

[0014] Preferably, an elastic conductive connection cable is provided between the flexible circuit board and the story machine motherboard. The elastic conductive connection cable has a wavy bending structure that extends along the long side of the gripping area of ​​the story machine motherboard. The flexible circuit board is electrically connected to the output terminal of the adjustable impedance matching network through the elastic conductive connection cable. The surface of the flexible circuit board facing away from the story machine motherboard is covered with a silicone buffer layer. A piezoelectric thin film sensor is embedded inside the silicone buffer layer. The signal output terminal of the piezoelectric thin film sensor is connected to the fifth input pin of the main control processor. The main control processor calculates the current physical deformation of the flexible circuit board based on the deformation electrical signal output by the piezoelectric thin film sensor. The main control processor corrects the antenna detuning offset stored in the detuning offset register based on the physical deformation.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention adds an RF front-end impedance detection circuit and an adjustable impedance matching network between the near-field communication chip and the antenna. The RF front-end impedance detection circuit collects the reflected power voltage signal of the antenna node in real time. The main control processor calculates the antenna detuning offset based on this voltage signal and outputs a control voltage to adjust the capacitance value of the varactor diode in the adjustable impedance matching network, locking the antenna resonant frequency to the carrier frequency of the passive tag. The main control processor generates a reference voltage adjustment signal based on the current matching state to adjust the flip-flop threshold of the hysteresis comparator in the receiver demodulator. The above configuration eliminates the RF detuning phenomenon caused by changes in the antenna equivalent parameters due to children's non-standard holding postures, ensuring the coupling efficiency of RF energy in the detuned physical state, enabling the receiver demodulator to demodulate the distorted signal based on the adjusted reference voltage, and maintaining the connectivity of the near-field communication link under complex spatial postures.

[0016] 2. A detection loop consisting of a directional coupler and a detector diode, combined with a temperature sensor and a compensation operational amplifier, eliminates the interference of the offset voltage generated by the detector diode due to changes in ambient temperature on the calculation of detuning offset. The calibration resistor and switching array in the adjustable impedance matching network construct a calibration loop during power-on. The main control processor sequentially changes the capacitance value of the varactor diode and synchronously reads the DC voltage, generating a capacitor voltage calibration lookup table to correct initial matching errors caused by component manufacturing differences. The suspended intermediate layer traces on the flexible circuit board physically cover the gap between the top and bottom layer traces, compensating for parasitic capacitance introduced by gripping. Elastic conductive connection cables, in conjunction with a piezoelectric thin-film sensor, detect the physical deformation of the flexible circuit board. The main control processor corrects the antenna detuning offset based on the deformation electrical signal, adapting to the RF parameter adjustment process under antenna bending conditions. The edge interpolation filter inside the field-programmable gate array performs oversampling and linear interpolation operations on the digital signal based on the subcarrier recovery clock, reconstructing the bit synchronization clock edge position and reducing clock jitter errors in signal sampling. Attached Figure Description

[0017] Figure 1 A flowchart illustrating the overall workflow of a children's story machine playback system based on NFC near-field communication, as provided in this embodiment of the invention. Figure 2 A flowchart illustrating the RF front-end impedance detection and temperature compensation process provided in this embodiment of the invention; Figure 3 A flowchart illustrating the power-on calibration process of the adjustable impedance matching network provided in this embodiment of the invention; Figure 4 This is a flowchart illustrating the NFC antenna parasitic capacitance compensation and deformation detection process provided in an embodiment of the present invention. Figure 5 A flowchart illustrating the dynamic adjustment process of the receiver demodulator reference voltage provided in this embodiment of the invention; Figure 6 This is a flowchart illustrating the bit synchronization clock reconstruction process of the edge interpolation filter provided in an embodiment of the present invention. Detailed Implementation

[0018] This invention relates to the field of near-field communication technology, and more specifically to an implementation method of a children's story machine playback system based on NFC near-field communication.

[0019] refer to Figure 1In one embodiment, the children's story machine playback system based on NFC near-field communication includes a story machine motherboard, a near-field communication chip integrated into the story machine motherboard, a main control processor, an RF front-end impedance detection circuit, an adjustable impedance matching network, a receiver demodulator, and an NFC antenna. The transmit pin of the near-field communication chip is connected to the input terminal of the adjustable impedance matching network, the output terminal of the adjustable impedance matching network is connected to the NFC antenna, the detection terminal of the RF front-end impedance detection circuit is connected to the node between the adjustable impedance matching network and the NFC antenna, the output terminal of the RF front-end impedance detection circuit is connected to the first input pin of the main control processor, the first output pin of the main control processor is connected to the control terminal of the adjustable impedance matching network, and the second output pin of the main control processor is connected to the reference voltage adjustment terminal of the receiver demodulator.

[0020] In this embodiment, the near-field communication chip adopts an RF communication chip conforming to the ISO / IEC 14443 Type A standard, operating at a specified rated carrier frequency. It is used to generate and transmit RF carrier signals, while simultaneously receiving load modulation signals returned by passive NFC tags. The near-field communication chip integrates a digital baseband processing unit, an RF transmitting unit, and an RF receiving unit. The output of the RF transmitting unit serves as the transmit pin of the near-field communication chip, and the input of the RF receiving unit serves as the receive pin. The digital baseband processing unit is used to decode and encode the load modulation signal, generate corresponding audio index data, and transmit the audio index data to the main control processor. The main control processor retrieves the corresponding story audio file based on the audio index data and plays it through the story machine's audio playback module.

[0021] Specifically, an adjustable impedance matching network is positioned between the transmit pin of the near-field communication (NFC) chip and the NFC antenna. Under the control of the main processor, it adjusts the impedance matching state of the RF front-end, ensuring that the input impedance of the NFC antenna matches the output impedance of the NFC chip's RF transmit unit. This reduces RF signal reflection loss and improves RF energy coupling efficiency. The detection terminal of the RF front-end impedance detection circuit is connected to the node between the adjustable impedance matching network and the NFC antenna. This node serves as both the RF signal transmitter and the load modulation signal receiver. The RF front-end impedance detection circuit acquires the RF signal at this node, extracts the voltage signal corresponding to the antenna reflection power, converts this voltage signal into a digital signal, and transmits it to the first input pin of the main processor.

[0022] Furthermore, the main control processor is internally configured with a digital signal processing core, a memory unit, and multiple input / output pins. The digital signal processing core processes the input digital voltage signal to calculate the antenna detuning offset. The antenna detuning offset characterizes the deviation between the actual resonant frequency of the NFC antenna and the rated carrier frequency. The greater the deviation, the more severe the antenna detuning, the higher the reflected power of the RF signal, and the higher the amplitude of the voltage signal output by the RF front-end impedance detection circuit. Based on the calculated antenna detuning offset, the main control processor's digital signal processing core generates a corresponding first control voltage. The first control voltage is a DC analog voltage signal, which is output to the control terminal of the adjustable impedance matching network through the main control processor's first output pin. This voltage is used to adjust the reverse bias voltage of the varactor diode inside the adjustable impedance matching network, thereby changing the junction capacitance of the varactor diode and adjusting the impedance parameters of the adjustable impedance matching network. This locks the resonant frequency of the NFC antenna to the rated carrier frequency, eliminating the reflection loss caused by antenna detuning.

[0023] In this embodiment, after adjusting the impedance matching state, the main control processor enters the receiving stage of the passive NFC tag load modulation signal. During the receiving stage, the main control processor generates a reference voltage adjustment signal based on the impedance matching state corresponding to the currently output first control voltage. This reference voltage adjustment signal is a DC analog voltage signal, which is output to the reference voltage adjustment terminal of the receiver demodulator through the second output pin of the main control processor. This adjustment is used to adjust the demodulation reference level inside the receiver demodulator, enabling it to adapt to the amplitude changes of the load modulation signal under the current impedance matching state and reducing the bit error rate of the demodulated signal.

[0024] In this embodiment, the rated resonant frequency of the NFC antenna is defined by the following formula:

[0025] in, This is the rated resonant frequency of the NFC antenna, in Hz. This is the nominal equivalent inductance of the NFC antenna in free space, expressed in H. This is the nominal equivalent parasitic capacitance of the NFC antenna in free space, expressed in volts (F).

[0026] The voltage reflection coefficient at the antenna port is calculated using the following formula:

[0027] in, The voltage reflection coefficient at the antenna port is dimensionless. This is the current input impedance of the NFC antenna, in Ω; This represents the characteristic impedance of the RF front-end, measured in Ω.

[0028] The reflected power at the antenna port is calculated using the following formula:

[0029] in, The reflected power at the antenna port is expressed in watts (W). This represents the incident power transmitted from the near-field communication chip to the antenna port, measured in W.

[0030] The relationship between the detector voltage output by the RF front-end impedance detection circuit and the reflected power is defined by the following formula:

[0031] in, This is the DC voltage output by the RF front-end impedance detection circuit, in volts (V). This refers to the voltage conversion factor of the detector circuit, expressed in V / ; This is the static offset voltage of the detector circuit, measured in volts (V).

[0032] The main control processor calculates the detector voltage difference corresponding to the antenna detuning offset using the following formula:

[0033] in, This is the difference in detector voltage, expressed in volts (V). This is the pre-stored rated resonant voltage value, which is the detector output voltage of the NFC antenna at the rated carrier frequency, in volts (V). The main control processor uses this detector voltage difference as the antenna detuning offset for subsequent processing.

[0034] The relationship between the junction capacitance of the varactor diode and the reverse bias voltage in an adjustable impedance matching network is defined by the following formula:

[0035] in, For varactor diodes under reverse bias voltage The junction capacitance, expressed in F; This is the junction capacitance of the varactor diode under zero bias, expressed in F. This is the built-in potential of the varactor diode, expressed in volts (V). This represents the capacitance gradient coefficient of the varactor diode, which is dimensionless. The first control voltage output by the main control processor is the reverse bias voltage applied to the varactor diode. By adjusting The amplitude can change the junction capacitance of the varactor diode, thereby adjusting the impedance parameters of the matching network.

[0036] The reference voltage adjustment signal generated by the main control processor is calculated using the following formula:

[0037] in, This is the reference voltage adjustment signal, measured in volts (V). A preset fixed reference voltage, in volts (V); To match the current first control voltage The corresponding reference voltage compensation value, in V.

[0038] The toggle level threshold of the hysteresis comparator in the receiver demodulator is defined by the following two sets of formulas:

[0039]

[0040] in, This is the upper threshold toggling level of the hysteresis comparator, in volts (V). This is the lower threshold toggle level of the hysteresis comparator, in volts (V). This is the positive feedback resistor for the hysteresis comparator, in Ω; This is the input resistance of the hysteresis comparator, in Ω; This is the high-level output of the hysteresis comparator, measured in volts (V). This is the low-level output of the hysteresis comparator, measured in volts (V). It represents the reference voltage adjustment signal output by the main control processor. The upper and lower threshold toggling levels of the hysteresis comparator can be directly changed to adapt to the signal amplitude changes under the current impedance matching state.

[0041] In this embodiment, in order to achieve rapid adjustment of impedance matching state, the following correspondence table is pre-stored in the non-volatile memory inside the main control processor: Table 1. Correspondence between detector voltage and control voltage under different antenna detuning states.

[0042] The interval divisions in the table above are determined based on the calibration data during the system's factory calibration phase. After obtaining the detector output voltage from the RF front-end impedance detection circuit, the digital signal processing kernel can quickly obtain the corresponding first control voltage output interval by looking up the table, shortening the impedance matching adjustment time and improving the system's response speed. The antenna detuning offset interval in the table is defined by the absolute value of the difference between the actual resonant frequency of the NFC antenna and the rated carrier frequency. The detector output voltage interval is the interval of the DC voltage signal output by the RF front-end impedance detection circuit corresponding to the reflected power. The first control voltage output interval is the DC reverse bias voltage interval output by the main control processor to the adjustable impedance matching network. The varactor diode junction capacitance change interval is the interval of the junction capacitance value change of the varactor diode under the corresponding reverse bias voltage. The voltage reflection coefficient interval is the RF signal reflection coefficient interval at the antenna port, used to characterize the degree of impedance matching.

[0043] In this embodiment, the voltage signal corresponding to the reflected power of the antenna port is collected in real time by the RF front-end impedance detection circuit. The main control processor calculates the antenna detuning offset based on the voltage signal and outputs the corresponding first control voltage to adjust the impedance parameters of the adjustable impedance matching network, locking the antenna resonant frequency to the rated carrier frequency. At the same time, the reference voltage of the receiver demodulator is adjusted according to the current impedance matching state, eliminating the RF detuning phenomenon caused by the change of antenna equivalent parameters when children hold the story machine, ensuring the coupling efficiency of RF energy and the demodulation accuracy of the load modulation signal, and maintaining the connectivity of the near-field communication link under non-standard holding postures.

[0044] refer to Figure 2 In a preferred embodiment, the RF front-end impedance detection circuit includes a directional coupler, a detector diode, a first low-pass filter, and an analog-to-digital converter (ADC). The input of the directional coupler is connected to the transmit pin of the near-field communication chip, the coupling end of the directional coupler is connected to the anode of the detector diode, the cathode of the detector diode is connected to the input of the first low-pass filter, the output of the first low-pass filter is connected to the analog input of the ADC, and the digital output of the ADC serves as the output of the RF front-end impedance detection circuit, connected to the first input pin of the main control processor. The directional coupler is used to couple a small portion of the RF signal transmitted by the near-field communication chip while isolating the RF signal reflected from the antenna port, ensuring that the signal output from the coupling end is only related to the reflected power of the antenna port. The detector diode is used to perform envelope detection on the coupled RF signal, converting the power amplitude of the RF signal into a corresponding DC voltage signal. The first low-pass filter is used to filter out high-frequency carrier components and noise components from the detected output voltage, outputting a smooth DC voltage signal. The ADC is used to convert the input analog DC voltage signal into a corresponding digital signal, which is then transmitted to the main control processor for subsequent processing.

[0045] Furthermore, the main control processor is internally equipped with a detuning offset register. The main control processor performs a difference operation between the digital voltage value output by the analog-to-digital converter and the pre-stored rated resonant voltage value, and stores the difference in the detuning offset register as the antenna detuning offset. The rated resonant voltage value is the digital quantity corresponding to the detection voltage output by the RF front-end impedance detection circuit when the NFC antenna resonates at the rated carrier frequency. This value is pre-stored in the non-volatile memory of the main control processor and is calibrated during the system's factory calibration phase.

[0046] Specifically, the adjustable impedance matching network includes a first series inductor, a first varactor diode, a second varactor diode, a first DC blocking capacitor, and a second DC blocking capacitor. The first end of the first series inductor serves as the input terminal of the adjustable impedance matching network and is connected to the transmit pin of the near-field communication chip. The second end of the first series inductor is connected to the cathodes of the first and second varactor diodes, respectively. The anode of the first varactor diode is grounded through the first DC blocking capacitor, and the anode of the second varactor diode is grounded through the second DC blocking capacitor. The anodes of the first and second varactor diodes are respectively connected to the first output pin of the main control processor. The first series inductor is used to construct the series reactance component of the RF matching network, and the first and second varactor diodes are used to construct the parallel adjustable reactance component of the RF matching network. By changing the reverse bias voltage applied to the anode of the varactor diode, the junction capacitance of the varactor diode is adjusted, thereby changing the parallel reactance component of the matching network and achieving dynamic adjustment of the impedance matching state. The capacitance values ​​of the first and second DC blocking capacitors exhibit extremely low impedance at the rated carrier frequency, which can be regarded as a short circuit state of the radio frequency path. At the same time, they are used to block the DC component in the first control voltage output by the main control processor from entering the radio frequency circuit of the NFC antenna, so as to avoid the DC component from interfering with the antenna resonance state.

[0047] In this embodiment, the main control processor is internally configured with non-volatile memory and a digital signal processing (DSP) core. The non-volatile memory pre-stores a mapping table between impedance matching states and reference voltage compensation values. Before receiving the passive NFC tag load modulation signal, the DSP core reads the value of the currently output first control voltage and searches the mapping table to obtain the reference voltage compensation value corresponding to the current first control voltage. The DSP core accumulates the reference voltage compensation value with a preset fixed reference voltage and outputs the result as a reference voltage adjustment signal through the second output pin of the main control processor. The preset fixed reference voltage is the reference voltage value required for the demodulator to normally demodulate the load modulation signal when the NFC antenna is in its rated resonant state. This value is calibrated during the system's factory calibration phase and pre-stored in the non-volatile memory.

[0048] refer to Figure 5 Furthermore, the receiver demodulator includes an envelope detector circuit, a programmable gain amplifier, and a hysteresis comparator. The input of the envelope detector circuit is connected to the node between the adjustable impedance matching network and the NFC antenna. The output of the envelope detector circuit is connected to the input of the programmable gain amplifier, the output of the programmable gain amplifier is connected to the non-inverting input of the hysteresis comparator, the inverting input of the hysteresis comparator is connected to the second output pin of the main control processor, and the output of the hysteresis comparator is connected to the digital baseband input pin of the near-field communication chip. The envelope detector circuit extracts the envelope of the load modulation signal returned by the passive NFC tag from the radio frequency signal received by the antenna and outputs the corresponding analog baseband signal. The programmable gain amplifier amplifies the analog baseband signal output by the envelope detector circuit; the amplification factor can be configured by the main control processor to adapt to input signals of different amplitudes. The hysteresis comparator is used to shape the amplified analog baseband signal, converting the analog signal into a binary digital signal that meets the requirements of digital baseband processing. The inverting input of the hysteresis comparator receives the reference voltage adjustment signal output by the main control processor to change the flip-flop threshold of the hysteresis comparator, adapt to the amplitude change of the baseband signal under the current impedance matching state, avoid false flips caused by signal noise, and reduce the demodulation bit error rate.

[0049] In a preferred embodiment, the RF front-end impedance detection circuit further includes a temperature sensor and a compensation operational amplifier. The output of the temperature sensor is connected to the third input pin of the main control processor. The non-inverting input of the compensation operational amplifier is connected to the output of the first low-pass filter, and the inverting input of the compensation operational amplifier is connected to the output of the digital-to-analog converter (DAC). The input of the DAC is connected to the third output pin of the main control processor. The temperature sensor is used to collect the ambient temperature value of the story machine and convert the temperature value into a corresponding digital signal, which is then transmitted to the main control processor. The main control processor internally stores a temperature-voltage offset curve of the detector diode. This curve characterizes the relationship between the static offset voltage of the detector diode and the ambient temperature. It is calibrated during the system's factory calibration phase and stored in non-volatile memory. Based on the ambient temperature value collected by the temperature sensor, the main control processor extracts the corresponding offset voltage value from the temperature-voltage offset curve, converts the offset voltage value into a corresponding digital control quantity, and outputs it to the DAC. The DAC converts the input digital control quantity into a corresponding analog voltage signal and outputs it to the inverting input of the compensation operational amplifier. The compensated operational amplifier forms a differential operational circuit, which performs differential operation on the detector voltage input at the non-inverting input terminal and the temperature offset voltage input at the inverting input terminal, and outputs the detector voltage signal after temperature compensation.

[0050] The temperature-compensated detector voltage is calculated using the following formula:

[0051] in, The detector voltage is after temperature compensation, and the unit is V; This represents the offset voltage value of the detector diode at the current ambient temperature T, in volts (V). This calculation eliminates the interference of the offset voltage of the detector diode caused by changes in ambient temperature on the calculation of detuning offset, thus improving the accuracy of impedance detection.

[0052] refer to Figure 3 Furthermore, the adjustable impedance matching network also includes a calibration resistor and a switching array. The first end of the calibration resistor is connected to the second end of the first series inductor, and the second end of the calibration resistor is connected to the common terminal of the switching array. The first selection terminal of the switching array is grounded, the second selection terminal of the switching array is connected to the receive pin of the near-field communication chip, and the control terminal of the switching array is connected to the fourth output pin of the main control processor. The calibration resistor is a high-precision, low-temperature drift surface-mount resistor that matches the characteristic impedance of the RF front-end. The switching array is a single-pole double-throw RF switch with low insertion loss and high isolation, used to switch the connection relationship of the RF loop between calibration and normal operation states.

[0053] In this embodiment, during the power-on phase of the story machine, the main control processor controls the switching array to close to the first selection terminal, so that the second terminal of the calibration resistor is grounded through the switching array, thus establishing a calibration circuit. The main control processor gradually changes the amplitude of the first control voltage output to the first and second varactor diodes in fixed voltage steps, while simultaneously reading the DC voltage value at the receiving pin of the near-field communication chip. It records the DC voltage value corresponding to each amplitude of the first control voltage, calculates the actual junction capacitance of the varactor diode under the corresponding voltage, and generates a capacitance-voltage calibration lookup table for the varactor diode. This lookup table is stored in the main control processor's non-volatile memory. During subsequent normal operation, the main control processor adjusts the output amplitude of the first control voltage according to this lookup table, correcting the initial matching error caused by manufacturing differences in the varactor diode components and improving the accuracy of impedance matching adjustment.

[0054] The node voltage under calibration conditions is calculated using the following formula:

[0055] in, This is the DC voltage value at the receiver pin of the near-field communication chip in calibration mode, in V. The resistance value is used for calibration; the unit is Ω. Current reverse bias voltage The impedance of the lower varactor diode, in Ω; This represents the amplitude of the radio frequency signal output from the transmit pin of the near-field communication chip, in volts (V). Using this formula, the actual impedance and junction capacitance of the varactor diode can be calculated based on the measured calibration voltage, thus completing the construction of the calibration lookup table.

[0056] In this embodiment, the generated capacitor-voltage calibration lookup table is as follows: Table 2. Varactor Diode Capacitor-Voltage Calibration Lookup Table

[0057] The sequences and interval divisions in the table above are determined based on the actual calibration data during the power-on phase. The first control voltage step sequence is the stepwise change sequence of the reverse bias voltage output by the main control processor. The measured calibration voltage sequence is the sequence of DC voltage values ​​collected at the receiving pin of the near-field communication chip under the corresponding control voltage. The calculated junction capacitance sequence is the sequence of actual junction capacitance values ​​of the varactor diode obtained through impedance calculation of the calibration circuit. The nominal junction capacitance sequence is the sequence of nominal capacitance values ​​given in the varactor diode datasheet under the corresponding reverse bias voltage. The error correction coefficient sequence is the sequence of ratios between the calculated junction capacitance and the nominal junction capacitance, which is used to correct the output amplitude of the first control voltage during normal operation and eliminate capacitance errors caused by component manufacturing tolerances.

[0058] In this embodiment, the detection circuit consisting of a directional coupler and a detector diode achieves accurate detection of antenna reflected power. The temperature compensation circuit consisting of a temperature sensor and a compensation operational amplifier eliminates the detection error caused by temperature drift of the detector diode. The calibration circuit consisting of a calibration resistor and a switching array completes the capacitance-voltage characteristic calibration of the varactor diode during the power-on stage, correcting the matching error caused by component manufacturing differences. At the same time, the dynamic adjustment of the reference voltage is achieved through the mapping table, ensuring the demodulation accuracy of the load modulation signal and further improving the working stability of the near-field communication system in complex environments.

[0059] refer to Figure 4 In another preferred embodiment, the NFC antenna is a multi-turn rectangular spiral antenna printed on a flexible circuit board. The flexible circuit board is attached to the edge area of ​​the story machine's main board and arranged around the grip area of ​​the main board. When children use the story machine, they usually hold the left and right edge areas. Arranging the flexible circuit board around the grip area ensures that the NFC antenna maintains an effective coupling area with the passive tag even when the child is holding it, avoiding a decrease in coupling efficiency due to hand obstruction. The flexible circuit board uses a polyimide substrate, which has excellent bending resistance and dielectric stability, and can adapt to the curved structure of the story machine's shell, achieving a tight fit with the shell.

[0060] Specifically, the multi-turn rectangular spiral antenna includes top-layer traces, middle-layer traces, and bottom-layer traces arranged sequentially from the outside in. The top-layer and bottom-layer traces are connected in series through metallized vias located inside the flexible circuit board, forming a complete spiral antenna circuit. Both the top-layer and bottom-layer traces use conductive metal traces. The trace width and spacing are designed based on the antenna's nominal inductance, and the number of spiral turns is determined based on the antenna's target inductance and coupling distance requirements. The middle-layer traces are suspended and not connected to the RF circuit of the near-field communication chip. Physically, the middle-layer traces cover the gap between the top-layer and bottom-layer traces. The width of the middle-layer traces matches the width of the gap between the top-layer and bottom-layer traces, ensuring that the middle-layer traces completely cover the trace gap. When a child holds the story machine, additional parasitic capacitance is introduced between the human tissue and the antenna traces, causing an increase in the antenna's equivalent parasitic capacitance, a decrease in the resonant frequency, and detuning. The suspended intermediate layer traces form mutual capacitance with the top and bottom layer traces. This mutual capacitance can cancel out the additional parasitic capacitance introduced by a child's hand gripping the device, compensate for changes in the antenna's equivalent parasitic capacitance, reduce the degree of antenna detuning, reduce the range of impedance matching adjustment, and improve the system's response speed.

[0061] The amount of parasitic capacitance compensation introduced by a child's hand grip is defined by the following formula:

[0062] in, The increase in parasitic capacitance introduced by a child's hand grip, measured in F; The mutual capacitance between the suspended intermediate layer traces and the top and bottom layer traces is expressed in F. The area of ​​the gap between the top and bottom layer wiring, in meters. 2 ; This represents the total area of ​​the intermediate layer traces, in square meters (m²). 2 This formula clarifies the compensation mechanism for parasitic capacitance introduced by the intermediate layer traces during gripping. By adjusting the coverage area of ​​the intermediate layer traces, matching compensation for the increase in parasitic capacitance can be achieved.

[0063] Furthermore, a flexible conductive connection cable is installed between the flexible circuit board and the story machine mainboard. This cable features a wavy, bent structure that extends along the long side of the gripping area of ​​the mainboard. The cable is composed of a metal conductive layer and an insulating elastic substrate, exhibiting excellent elasticity and bending life. When the flexible circuit board is subjected to pressure from a child's grip and undergoes physical deformation, the wavy, bent structure absorbs the stress through its elastic deformation, preventing breakage at the connection point between the flexible circuit board and the mainboard, while ensuring stable transmission of radio frequency signals. The flexible circuit board is electrically connected to the output of an adjustable impedance matching network via the flexible conductive connection cable. The characteristic impedance of the cable matches the characteristic impedance of the radio frequency front-end, preventing radio frequency signal reflection caused by impedance discontinuities.

[0064] In this embodiment, the surface of the flexible circuit board facing away from the story machine's main board is covered with a silicone buffer layer. This silicone buffer layer has excellent cushioning and insulation properties, preventing pressure from children directly acting on the flexible circuit board while holding it, and also isolating direct contact between human tissue and antenna traces, reducing the introduction of parasitic capacitance. An embedded piezoelectric thin-film sensor is made of a flexible polymer material with a piezoelectric effect, capable of deforming synchronously with the deformation of the flexible circuit board and outputting a corresponding deformation electrical signal. The signal output terminal of the piezoelectric thin-film sensor is connected to the fifth input pin of the main control processor. The deformation electrical signal output by the piezoelectric thin-film sensor is amplified and filtered before being transmitted to the main control processor. The main control processor calculates the current physical deformation of the flexible circuit board based on the amplitude of the deformation electrical signal.

[0065] The physical deformation of the flexible circuit board is calculated using the following formula:

[0066] in, The physical deformation of the flexible circuit board is dimensionless. 1 is the amplitude of the deformation electrical signal output by the piezoelectric thin film sensor, in V; 2 is the piezoelectric strain coefficient of the piezoelectric thin film, in C / N; 3 is the Young's modulus of the piezoelectric thin film, in Pa. The thickness of the piezoelectric film is expressed in meters (m).

[0067] Specifically, the main control processor has a pre-stored table of correspondence between physical deformation and detuning offset correction coefficients. This table is calibrated during the system's factory calibration phase and stored in non-volatile memory. Based on the calculated physical deformation, the main control processor looks up the corresponding correction coefficient in the table and uses this coefficient to correct the antenna detuning offset stored in the detuning offset register, obtaining the corrected antenna detuning offset. When the flexible circuit board is subjected to gripping pressure and undergoes bending deformation, the physical shape of the antenna traces changes, leading to a change in the antenna's equivalent inductance and causing resonant frequency detuning. By detecting the deformation of the flexible circuit board using a piezoelectric thin-film sensor and correcting the detuning offset in advance, the impedance matching adjustment time can be shortened, the system response speed improved, and the RF parameter adjustment process adapted to antenna bending scenarios can be enhanced.

[0068] The detector voltage difference corresponding to the corrected antenna detuning offset is calculated using the following formula:

[0069] in, The corrected detector voltage difference is expressed in volts (V). It is the deformation-voltage correction coefficient, with units of V / dimensionless, and is pre-stored in the main control processor's memory.

[0070] In this embodiment, the pre-stored deformation and mistuning offset correction parameters correspondence table is as follows: Table 3. Correction Parameters for Deformation and Mistuning Offset of Flexible Circuit Boards

[0071] The interval divisions in the table above are determined based on the calibration data during the system's factory calibration phase. Among them, the flexible circuit board deformation interval is the interval of relative deformation caused by external force on the flexible circuit board; the piezoelectric film output voltage interval is the amplitude interval of the deformation electrical signal output by the piezoelectric film sensor under the corresponding deformation; the detuning offset correction coefficient interval is the coefficient interval used to correct the antenna detuning offset under the corresponding deformation; and the corrected detuning offset interval is the result interval of the original detuning offset after correction, used to eliminate the calculation error of detuning offset caused by the physical deformation of the antenna.

[0072] In this embodiment, the parasitic capacitance introduced by a child's grip is compensated by the suspended intermediate layer traces through the multi-layer spiral trace structure on the flexible circuit board, reducing the degree of antenna detuning. The flexible conductive connection cable achieves a reliable connection between the flexible circuit board and the story machine motherboard, absorbing the stress caused by deformation. The piezoelectric thin film sensor inside the silicone buffer layer detects the physical deformation of the flexible circuit board and corrects the antenna detuning offset in advance, improving the response speed and accuracy of impedance matching adjustment, and further adapting to the complex physical scenario when a child holds the story machine.

[0073] refer to Figure 6 In another preferred embodiment, the receiver demodulator further includes a high-speed analog-to-digital sampler and a field-programmable gate array (FPGA). The analog input of the high-speed analog-to-digital sampler is connected to the output of the hysteresis comparator, the digital output of the high-speed analog-to-digital sampler is connected to the data input of the FPGA, and the clock input of the FPGA is connected to the subcarrier recovery clock output of the near-field communication chip. The high-speed analog-to-digital sampler is a single-channel, high-sampling-rate analog-to-digital converter used to sample the shaped digital signal output by the hysteresis comparator at high speed, converting the analog level signal into a multi-bit digital signal, which is then transmitted to the FPGA for further processing. The subcarrier recovery unit inside the near-field communication chip is used to recover the load-modulated subcarrier clock of the passive NFC tag from the received radio frequency signal. The subcarrier frequency is a specified division value of the rated carrier frequency. The subcarrier recovery clock output output outputs the recovered subcarrier clock to the clock input of the FPGA as a reference clock for the edge interpolation filter.

[0074] Specifically, the field-programmable gate array (FPGA) is internally configured with an edge interpolation filter. This filter uses a specified multiple of the subcarrier recovery clock as the sampling clock to oversample the digital signal output by the high-speed analog-to-digital sampler. The edge interpolation filter then performs a moving average filtering process on the multiple sets of sampled data obtained from the oversampling, filtering out high-frequency noise introduced during the sampling process and improving the signal-to-noise ratio of the sampled data.

[0075] Furthermore, when the edge interpolation filter detects a level transition edge in the digital signal, it locks two adjacent sampling points before and after the level transition edge. It then performs linear interpolation using the amplitudes of these adjacent sampling points to reconstruct the precise position of the bit synchronization clock edge. The bit synchronization clock edge of the load modulation signal returned by the passive NFC tag is aligned with the subcarrier clock edge. Due to signal attenuation, noise, and signal distortion caused by impedance detuning during signal transmission, the bit synchronization clock edge will shift and jitter. When sampling with a fixed subcarrier clock, the sampling point may deviate from the optimal sampling position of the signal, leading to data errors. By reconstructing the precise time position of the bit synchronization clock edge through linear interpolation, a bit synchronization clock that is completely synchronized with the load modulation signal can be generated. This ensures that the sampling point is always at the optimal sampling position of the signal, reducing clock jitter errors and improving the accuracy of signal demodulation.

[0076] The linear interpolation operation on the edge of the bit synchronization clock is achieved by the following formula:

[0077] in, The precise time position of the reconstructed bit synchronization clock edge, in seconds; This is the timestamp of the nth sampling point, in seconds. The threshold voltage for level transition, in volts (V). The amplitude at the nth sampling point is expressed in V. The amplitude at the (n+1)th sampling point is expressed in V. The sampling period for oversampling is expressed in seconds.

[0078] The reconstructed clock jitter error is defined by the following formula:

[0079] in, The root mean square error of the reconstructed clock jitter is expressed in seconds. The signal-to-noise ratio of the sampled signal is dimensionless.

[0080] In this embodiment, the field-programmable gate array is also equipped with a bit synchronization lock unit. The bit synchronization lock unit generates a bit synchronization lock signal based on the bit synchronization clock edge position reconstructed by the edge interpolation filter. When multiple consecutive bit synchronization clock edges are detected to deviate from the reconstructed edge position less than a preset threshold, the bit synchronization lock is determined to be completed, and the lock signal is output to the digital baseband processing unit of the near-field communication chip. The digital baseband processing unit decodes the load modulation signal based on the locked bit synchronization clock, further reducing the bit error rate of decoding.

[0081] In this embodiment, the corresponding relationship between interpolation reconstruction performance at different oversampling rates is shown in the following table: Table 4. Relationship between Oversampling Rate and Interpolation Reconstruction Clock Error

[0082] The interval divisions in the table above are determined based on system simulation and actual test data. The oversampling rate interval is defined by the ratio of the sampling clock frequency to the subcarrier clock frequency; the sampling period interval is the interval of the single sampling time interval at the corresponding sampling frequency; the maximum linear interpolation error interval is the interval of the maximum deviation between the reconstructed clock edge position and the actual edge position; the clock jitter root mean square interval is the interval of the root mean square error of the reconstructed clock jitter; and the demodulation bit error rate interval is the interval of the demodulation bit error rate of the load modulated signal under the corresponding parameters. This table allows for the determination of an oversampling rate suitable for the system performance requirements, achieving a balance between logic resource consumption and demodulation performance.

[0083] In this embodiment, the signal output by the hysteresis comparator is oversampled by a high-speed analog-to-digital sampler, and the sampled signal is linearly interpolated by the edge interpolation filter inside the field-programmable gate array. This reconstructs the precise position of the bit synchronization clock edge, reduces the clock jitter error of the signal sampling, improves the demodulation accuracy of the load modulation signal, and further ensures the stable connection of the near-field communication link in complex environments.

Claims

1. A children's story machine playback system based on NFC near-field communication, characterized in that, The device includes a story machine motherboard, a near-field communication chip integrated into the story machine motherboard, a main control processor, an RF front-end impedance detection circuit, an adjustable impedance matching network, a receiver demodulator, and an NFC antenna. The transmit pin of the near-field communication chip is connected to the input terminal of the adjustable impedance matching network, and the output terminal of the adjustable impedance matching network is connected to the NFC antenna. The detection terminal of the RF front-end impedance detection circuit is connected to the node between the adjustable impedance matching network and the NFC antenna. The output terminal of the RF front-end impedance detection circuit is connected to the first input pin of the main control processor, the first output pin of the main control processor is connected to the control terminal of the adjustable impedance matching network, and the second output pin of the main control processor is connected to the reference voltage adjustment terminal of the receiver demodulator. The RF front-end impedance detection circuit acquires the voltage signal corresponding to the antenna reflection power at the node and transmits it to the main control processor. The main control processor calculates the antenna detuning offset based on the voltage signal and generates a corresponding first control voltage. The main control processor outputs the first control voltage to the adjustable impedance matching network to adjust the capacitance value of the internal varactor diode. During the stage of receiving the passive NFC tag load modulation signal, the main control processor generates a reference voltage adjustment signal based on the matching state corresponding to the first control voltage and outputs it to the receiver demodulator.

2. The children's story machine playback system based on NFC near-field communication according to claim 1, characterized in that, The RF front-end impedance detection circuit includes a directional coupler, a detector diode, a first low-pass filter, and an analog-to-digital converter (ADC). The input of the directional coupler is connected to the transmit pin of the near-field communication chip, the coupling end of the directional coupler is connected to the anode of the detector diode, the cathode of the detector diode is connected to the input of the first low-pass filter, the output of the first low-pass filter is connected to the analog input of the ADC, and the digital output of the ADC serves as the output of the RF front-end impedance detection circuit, connected to the first input pin of the main control processor. The main control processor has an internal detuning offset register. The main control processor performs a difference operation between the digital voltage value output by the ADC and a pre-stored rated resonant voltage value, and stores the difference in the detuning offset register as the antenna detuning offset.

3. The children's story machine playback system based on NFC near-field communication according to claim 1, characterized in that, The adjustable impedance matching network includes a first series inductor, a first varactor diode, a second varactor diode, a first DC blocking capacitor, and a second DC blocking capacitor. The first end of the first series inductor serves as the input terminal of the adjustable impedance matching network and is connected to the transmit pin of the near-field communication chip. The second end of the first series inductor is connected to the cathodes of the first varactor diode and the second varactor diode, respectively. The anode of the first varactor diode is grounded through the first DC blocking capacitor, and the anode of the second varactor diode is grounded through the second DC blocking capacitor. The anodes of the first and second varactor diodes are respectively connected to the first output pin of the main control processor. The first and second DC blocking capacitors are used to block the DC component in the first control voltage output by the main control processor from entering the NFC antenna.

4. The children's story machine playback system based on NFC near-field communication according to claim 1, characterized in that, The main control processor is internally configured with non-volatile memory and a digital signal processing core. The non-volatile memory pre-stores a mapping table between impedance matching states and reference voltage compensation values. Before receiving the passive NFC tag load modulation signal, the digital signal processing core reads the value of the currently output first control voltage. The digital signal processing core searches the mapping table based on the value of the first control voltage to obtain the reference voltage compensation value corresponding to the current first control voltage. The digital signal processing core accumulates the reference voltage compensation value with a preset fixed reference voltage and outputs the result of the accumulation operation as the reference voltage adjustment signal through the second output pin of the main control processor.

5. The children's story machine playback system based on NFC near-field communication according to claim 1, characterized in that, The receiver demodulator includes an envelope detector circuit, a programmable gain amplifier, and a hysteresis comparator. The input of the envelope detector circuit is connected to the node between the adjustable impedance matching network and the NFC antenna. The output of the envelope detector circuit is connected to the input of the programmable gain amplifier. The output of the programmable gain amplifier is connected to the non-inverting input of the hysteresis comparator. The inverting input of the hysteresis comparator is connected to the second output pin of the main control processor. The output of the hysteresis comparator is connected to the digital baseband input pin of the near-field communication chip. The inverting input of the hysteresis comparator receives the reference voltage adjustment signal to change the flip-flop threshold of the hysteresis comparator.

6. The children's story machine playback system based on NFC near-field communication according to claim 1, characterized in that, The NFC antenna is a multi-turn rectangular spiral antenna printed on a flexible circuit board. The flexible circuit board is attached to the edge area of ​​the story machine motherboard and arranged around the grip area of ​​the story machine motherboard. The multi-turn rectangular spiral antenna includes a top layer trace, a middle layer trace, and a bottom layer trace arranged sequentially from the outside to the inside. The top layer trace and the bottom layer trace are connected in series through metallized vias disposed inside the flexible circuit board. The middle layer trace is suspended and not connected to the radio frequency circuit of the near-field communication chip. The middle layer trace physically covers the gap between the top layer trace and the bottom layer trace to compensate for the parasitic capacitance introduced when a child holds the device.

7. The children's story machine playback system based on NFC near-field communication according to claim 2, characterized in that, The RF front-end impedance detection circuit also includes a temperature sensor and a compensation operational amplifier. The output of the temperature sensor is connected to the third input pin of the main control processor. The non-inverting input of the compensation operational amplifier is connected to the output of the first low-pass filter. The inverting input of the compensation operational amplifier is connected to the output of the digital-to-analog converter. The input of the digital-to-analog converter is connected to the third output pin of the main control processor. The main control processor has a pre-stored temperature-voltage offset curve of the detector diode. The main control processor extracts the corresponding offset voltage value from the temperature-voltage offset curve based on the ambient temperature value collected by the temperature sensor. The main control processor converts the offset voltage value into an analog signal and outputs it to the inverting input of the compensation operational amplifier through the digital-to-analog converter.

8. The children's story machine playback system based on NFC near-field communication according to claim 3, characterized in that, The adjustable impedance matching network further includes a calibration resistor and a switching array. The first end of the calibration resistor is connected to the second end of the first series inductor, and the second end of the calibration resistor is connected to the common terminal of the switching array. The first selection terminal of the switching array is grounded, and the second selection terminal of the switching array is connected to the receiving pin of the near-field communication chip. The control terminal of the switching array is connected to the fourth output pin of the main control processor. During the power-on phase of the story machine, the main control processor controls the switching array to close to the first selection terminal. The main control processor gradually changes the amplitude of the first control voltage output to the first varactor diode and the second varactor diode according to a fixed voltage step, and synchronously reads the DC voltage value at the receiving pin of the near-field communication chip to generate a capacitance-voltage calibration lookup table for the varactor diode.

9. The children's story machine playback system based on NFC near-field communication according to claim 5, characterized in that, The receiver demodulator also includes a high-speed analog-to-digital sampler and a field-programmable gate array (FPGA). The analog input of the high-speed analog-to-digital sampler is connected to the output of the hysteresis comparator, and the digital output of the high-speed analog-to-digital sampler is connected to the data input of the FPGA. The clock input of the FPGA is connected to the subcarrier recovery clock output of the near-field communication chip. The FPGA is internally configured with an edge interpolation filter. The edge interpolation filter oversamples the digital signal output by the high-speed analog-to-digital sampler using a specified multiple of the subcarrier recovery clock as the sampling clock. When the edge interpolation filter detects a level transition edge of the digital signal, it performs linear interpolation using the amplitudes of adjacent sampling points to reconstruct the precise bit synchronization clock edge position.

10. The children's story machine playback system based on NFC near-field communication according to claim 6, characterized in that, A flexible conductive connection cable is provided between the flexible circuit board and the story machine motherboard. The flexible conductive connection cable has a wavy bending structure that extends along the long side of the gripping area of ​​the story machine motherboard. The flexible circuit board is electrically connected to the output terminal of the adjustable impedance matching network through the flexible conductive connection cable. The surface of the flexible circuit board facing away from the story machine motherboard is covered with a silicone buffer layer. A piezoelectric thin film sensor is embedded inside the silicone buffer layer. The signal output terminal of the piezoelectric thin film sensor is connected to the fifth input pin of the main control processor. The main control processor calculates the current physical deformation of the flexible circuit board based on the deformation electrical signal output by the piezoelectric thin film sensor. The main control processor corrects the antenna detuning offset stored in the detuning offset register based on the physical deformation.

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