A high frame rate cooled infrared thermal imager and its implementation method

Abstract

This invention discloses a high frame rate cooled infrared thermal imager, aiming to achieve high frame rate output for high-resolution cooled infrared thermal imagers, applicable to high-definition observation of high-speed targets or targets on high-speed moving vehicles. It includes an image detection module, an analog signal processing module, and an FPGA module. The image detection module includes infrared target radiation, an infrared lens, and an infrared detector. Infrared target radiation enters the infrared lens and is captured by the infrared detector, resulting in infrared image acquisition. The acquired high frame rate infrared image data is then transmitted to the analog signal processing module. The analog signal processing module includes a high-speed signal conditioning circuit and a high-speed analog-to-digital conversion circuit. The high-speed signal conditioning circuit is a high-bandwidth operational amplifier circuit, and the high-speed digital-to-analog conversion circuit is a high-speed AD conversion circuit. This invention achieves high frame rate output for high-resolution cooled infrared thermal imagers, specifically a 200Hz frame rate output for a 1280*1024 cooled infrared thermal imager, meeting the requirements of high-speed image acquisition.

Description

Technical Field

[0001] This invention relates to the field of infrared applications, specifically a high frame rate cooled infrared thermal imager and its implementation method. Background Technology

[0002] Frame rate refers to the number of images processed by a thermal imager per second. The faster the sensor, the higher the processing speed of the internal circuitry, and the higher the frame rate. The frame rate directly indicates the performance and response speed of the infrared thermal imager. The higher the frame rate, the better the performance and the faster the response speed. A high frame rate infrared thermal imager can accurately capture fast-moving objects.

[0003] Many users use high frame rate infrared thermal imagers to capture images of objects, and sometimes they also use drones for combined observation. This requires the infrared thermal imager to have a high frame rate. Currently, the mainstream 1280*1024 cooled infrared thermal imagers on the market have a frame rate of 25HZ-30HZ, which cannot meet the needs of high-speed image acquisition. Therefore, there is an urgent need for a high frame rate cooled infrared thermal imager to solve the above technical problems. Summary of the Invention

[0004] The purpose of this invention is to provide a high frame rate cooled infrared thermal imager and its implementation method to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A high frame rate cooled infrared thermal imager is designed to achieve high frame rate output of high resolution cooled infrared thermal imager, which can be used for high-definition observation of high-speed targets or high-definition observation of targets on high-speed moving vehicles. It includes: an image detection module, an analog signal processing module and an FPGA module.

[0007] As a further aspect of the present invention: the image detection module includes: infrared target radiation, an infrared lens, and an infrared detector. The infrared target radiation enters the infrared lens and is used to acquire infrared images through the infrared detector. The acquired high-frame-rate infrared image data is then transmitted to the analog signal processing module.

[0008] As a further aspect of the present invention: the analog signal processing module includes: a high-speed signal conditioning circuit and a high-speed analog-to-digital conversion circuit. The high-speed signal conditioning circuit is a high-bandwidth operational amplifier circuit, and the high-speed digital-to-analog conversion circuit is a high-speed AD conversion circuit. The video buffer is selected from MAX4225 with 1G bandwidth, the differential amplifier is selected from LTC6409 with 10G bandwidth, and the analog-to-digital converter is selected from AD9653 with 125M sampling rate, which is divided into four channels.

[0009] As a further aspect of the present invention: the FPGA module includes: DDR, detector driver and signal processing circuit, high-speed video interface, AD sampling and image processing, wherein the detector driver includes detector triggering and configuration, AD sampling is to obtain image data after AD conversion, and image processing is to perform NUC correction, background correction, blind pixel filling, temporal filtering, spatial filtering, image enhancement, histogram, brightness and contrast adjustment.

[0010] A method for implementing a high frame rate cooled infrared thermal imager, with a detector resolution of 1280*1024, includes the following steps:

[0011] Step 1: The FPGA module generates the timing signals required by the detector, driving the detector to operate at a frame rate of 200Hz.

[0012] Step 2: The image detection module acquires high-frequency infrared data images with a resolution of 1280*1024, a frame rate of 200Hz, and 4-channel output. Calculation shows that the highest pixel clock is 65.5M (1280*1024*200 / 4). After adding the blanking part, the highest pixel clock is 70M.

[0013] Step 3: The detector outputs 4 raw image signals, which are then passed through the MAX4225 video buffer to increase the driving capability and adjust the signal impedance to match the input of the differential amplifier. The maximum bandwidth of a single video signal is a square wave signal of 70M. In order to transmit the signal to the differential amplifier without distortion, a 1G bandwidth video buffer MAX4225 is selected.

[0014] Step 4: After being buffered, the signal enters the differential amplifier LTC6409, which converts the single-ended signal into a differential signal. In order to transmit the signal to the analog-to-digital converter without distortion, a differential amplifier LTC6409 with a bandwidth of 10G is selected.

[0015] Step 5: The converted differential signal is transmitted to the differential input of the AD9653 analog-to-digital converter, which converts the analog signal into a digital signal and outputs it to the FPGA module;

[0016] Step 6: The FPGA module receives four 70M pixel clock-to-digital video signals and restores them to the original 280M pixel clock-to-digital video signals;

[0017] Step 7: The raw digital video signal undergoes basic image processing, NUC correction, background correction, blind pixel filling, and image algorithms, including temporal filtering, spatial filtering, image enhancement, histogram adjustment, and brightness and contrast adjustment, before entering the DDR buffer.

[0018] Step 8: Read the processed image data from DDR, add electronic magnification, pseudo-color, and icon overlay functions, and output video data according to the Cameralink timing requirements in FULL mode;

[0019] The maximum bandwidth of DDR is calculated as follows:

[0020] 1) The NUC calibration k value is 16 bits, and the DDR read bandwidth is 16 bits × 280 MHz = 4.48 Gb / s;

[0021] 2) The NUC calibration b value is 16 bits, and the DDR read bandwidth is 16 bits × 280 MHz = 4.48 Gb / s;

[0022] 3) During the background correction process, DDR is written and read simultaneously, occupying a bandwidth of (32bit+32bit)×280MHz=17.92Gb / s;

[0023] 4) The 8-bit blind fill reading scheme has a bandwidth of 8 bits × 280 MHz = 2.24 Gb / s;

[0024] 5) Time-domain filtering simultaneously writes to and reads from DDR, occupying a bandwidth of (16bit + 16bit) × 280MHz = 8.96Gb / s;

[0025] 6) Spatial filtering, image enhancement, and histogram analysis do not consume bandwidth;

[0026] 7) The image after brightness and contrast adjustment is written to DDR, occupying a bandwidth of 16bit × 280MHz = 4.48Gb / s;

[0027] 8) Cameralink reads DDR bandwidth of 16 bits × 280 MHz = 4.48 Gb / s;

[0028] In summary, the pixel clock is 280MHz. During background correction, DDR read / write operations 2), 4), 5), and 7) are disabled. At this time, the total DDR bandwidth is 1)+3)+8), which is 26.88Gb / s. After background correction is completed, the instantaneous total DDR bandwidth when the image is output normally is 1)+2)+4)+5)+7)+8), which is (32bit+8bit+16bit+16bit+16bit+16bit)×280MHz=29.12Gb / s. According to the chip datasheet, the theoretical bandwidth of 16-bit DDR is 6.4Gb / s. Calculated at 80% efficiency: 29.12Gb / s / (6.4Gb / s×80%)=5.6875. Therefore, 6 16-bit DDR chips are selected.

[0029] Compared with the prior art, the beneficial effects of the present invention are:

[0030] This invention enables high frame rate output of a high-resolution cooled infrared thermal imager, namely a 200Hz frame rate output of a 1280*1024 cooled infrared thermal imager, to meet the requirements of high-speed image acquisition. Attached Figure Description

[0031] Figure 1 This is a system structure diagram of a high frame rate cooled infrared thermal imager.

[0032] Figure 2 This is the circuit diagram of a high frame rate cooled infrared thermal imager.

[0033] Figure 3 This is a flowchart of the FPGA module and a schematic diagram of the DDR input / output ports in a high frame rate cooled infrared thermal imager. Detailed Implementation

[0034] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0035] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0036] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented even without certain specific details. In some instances, methods, means, and elements well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0037] Example 1

[0038] Please see Figure 1-2 The system aims to achieve high frame rate output of a high-resolution cooled infrared thermal imager, which can be used for high-definition observation of high-speed targets or high-definition observation of targets on high-speed moving vehicles. It includes an image detection module, an analog signal processing module, and an FPGA module.

[0039] Preferably, the image detection module includes: infrared target radiation, an infrared lens, and an infrared detector. The infrared target radiation enters the infrared lens and is used to acquire infrared images through the infrared detector. The acquired high-frame-rate infrared image data is then transmitted to the analog signal processing module.

[0040] Preferably, the analog signal processing module includes: a high-speed signal conditioning circuit and a high-speed analog-to-digital conversion circuit. The high-speed signal conditioning circuit is a high-bandwidth operational amplifier circuit, and the high-speed digital-to-analog conversion circuit is a high-speed AD conversion circuit. The video buffer is selected from MAX4225 with 1G bandwidth, the differential amplifier is selected from LTC6409 with 10G bandwidth, and the analog-to-digital converter is selected from AD9653 with 125M sampling rate, which is divided into four channels.

[0041] Preferably, the FPGA module includes: DDR, detector driver and signal processing circuit, high-speed video interface, AD sampling and image processing, wherein the detector driver includes detector triggering and configuration, AD sampling is to obtain image data after AD conversion, and image processing is to perform NUC correction, background correction, blind pixel filling, temporal filtering, spatial filtering, image enhancement, histogram, brightness and contrast adjustment.

[0042] Please see Figure 3 A method for implementing a high frame rate cooled infrared thermal imager, with a detector resolution of 1280*1024, includes the following steps:

[0043] Step 1: The FPGA module generates the timing signals required by the detector, driving the detector to operate at a frame rate of 200Hz.

[0044] Step 2: The image detection module acquires high-frequency infrared data images with a resolution of 1280*1024, a frame rate of 200Hz, and 4-channel output. Calculation shows that the highest pixel clock is 65.5M (1280*1024*200 / 4). After adding the blanking part, the highest pixel clock is 70M.

[0045] Step 3: The detector outputs 4 raw image signals, which are then passed through the MAX4225 video buffer to increase the driving capability and adjust the signal impedance to match the input of the differential amplifier. The maximum bandwidth of a single video signal is a square wave signal of 70M. In order to transmit the signal to the differential amplifier without distortion, a 1G bandwidth video buffer MAX4225 is selected.

[0046] Step 4: After being buffered, the signal enters the differential amplifier LTC6409, which converts the single-ended signal into a differential signal. In order to transmit the signal to the analog-to-digital converter without distortion, a differential amplifier LTC6409 with a bandwidth of 10G is selected.

[0047] Step 5: The converted differential signal is transmitted to the differential input of the AD9653 analog-to-digital converter, which converts the analog signal into a digital signal and outputs it to the FPGA module;

[0048] Step 6: The FPGA module receives four 70M pixel clock-to-digital video signals and restores them to the original 280M pixel clock-to-digital video signals;

[0049] Step 7: The raw digital video signal undergoes basic image processing, NUC correction, background correction, blind pixel filling, and image algorithms, including temporal filtering, spatial filtering, image enhancement, histogram adjustment, and brightness and contrast adjustment, before entering the DDR buffer.

[0050] Step 8: Read the processed image data from DDR, add electronic magnification, pseudo-color, and icon overlay functions, and output video data according to the Cameralink timing requirements in FULL mode;

[0051] The maximum bandwidth of DDR is calculated as follows:

[0052] 1) The NUC calibration k value is 16 bits, and the DDR read bandwidth is 16 bits × 280 MHz = 4.48 Gb / s;

[0053] 2) The NUC calibration b value is 16 bits, and the DDR read bandwidth is 16 bits × 280 MHz = 4.48 Gb / s;

[0054] 3) During the background correction process, DDR is written and read simultaneously, occupying a bandwidth of (32bit+32bit)×280MHz=17.92Gb / s;

[0055] 4) The 8-bit blind fill reading scheme has a bandwidth of 8 bits × 280 MHz = 2.24 Gb / s;

[0056] 5) Time-domain filtering simultaneously writes to and reads from DDR, occupying a bandwidth of (16bit + 16bit) × 280MHz = 8.96Gb / s;

[0057] 6) Spatial filtering, image enhancement, and histogram analysis do not consume bandwidth;

[0058] 7) The image after brightness and contrast adjustment is written to DDR, occupying a bandwidth of 16bit × 280MHz = 4.48Gb / s;

[0059] 8) Cameralink reads DDR bandwidth of 16 bits × 280 MHz = 4.48 Gb / s;

[0060] In summary, the pixel clock is 280MHz. During background correction, DDR read / write operations 2), 4), 5), and 7) are disabled. At this time, the total DDR bandwidth is 1)+3)+8), which is 26.88Gb / s. After background correction is completed, the instantaneous total DDR bandwidth when the image is output normally is 1)+2)+4)+5)+7)+8), which is (32bit+8bit+16bit+16bit+16bit+16bit)×280MHz=29.12Gb / s. According to the chip datasheet, the theoretical bandwidth of 16-bit DDR is 6.4Gb / s. Calculated at 80% efficiency: 29.12Gb / s / (6.4Gb / s×80%)=5.6875. Therefore, 6 16-bit DDR chips are selected.

[0061] It should be specifically noted that this invention achieves high frame rate output of a high-resolution cooled infrared thermal imager, namely, a 200Hz frame rate output of a 1280*1024 cooled infrared thermal imager, which meets the requirements of high-speed image acquisition.

[0062] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.

[0063] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A high frame rate cooled infrared thermal imager, designed to achieve high frame rate output of a high-resolution cooled infrared thermal imager, applicable to high-definition observation of high-speed targets or high-definition observation of targets on high-speed moving vehicles, characterized in that, include: Image detection module, analog signal processing module, and FPGA module.

2. The high frame rate cooled infrared thermal imager according to claim 1, characterized in that, The image detection module includes: infrared target radiation, an infrared lens, and an infrared detector. The infrared target radiation enters the infrared lens and is used by the infrared detector to acquire infrared images. The acquired high-frame-rate infrared image data is then transmitted to the analog signal processing module.

3. The high frame rate cooled infrared thermal imager according to claim 2, characterized in that, The analog signal processing module includes a high-speed signal conditioning circuit and a high-speed analog-to-digital conversion circuit. The high-speed signal conditioning circuit is a high-bandwidth operational amplifier circuit, and the high-speed digital-to-analog conversion circuit is a high-speed AD conversion circuit.

4. The high frame rate cooled infrared thermal imager according to claim 1, characterized in that, The FPGA module includes: DDR, detector driver and signal processing circuit, high-speed video interface, AD sampling and image processing. The detector driver includes detector triggering and configuration, AD sampling is to obtain image data after AD conversion, and image processing includes NUC correction, background correction, blind pixel filling, temporal filtering, spatial filtering, image enhancement, histogram, brightness and contrast adjustment.

5. A method for implementing a high frame rate cooled infrared thermal imager as described in claims 1-4, characterized in that, The detector has a resolution of 1280*1024 and includes the following steps: Step 1: The FPGA module generates the timing signals required by the detector, driving the detector to operate at a frame rate of 200Hz. Step 2: The image detection module acquires high-frequency infrared data images with a resolution of 1280*1024, a frame rate of 200Hz, and 4-channel output. Calculation shows that the highest pixel clock is 65.5M (1280*1024*200 / 4). After adding the blanking part, the highest pixel clock is 70M. Step 3: The detector outputs 4 raw image signals, which are then passed through the MAX4225 video buffer to increase the driving capability and adjust the signal impedance to match the input of the differential amplifier. The maximum bandwidth of a single video signal is a square wave signal of 70M. In order to transmit the signal to the differential amplifier without distortion, a 1G bandwidth video buffer MAX4225 is selected. Step 4: After being buffered, the signal enters the differential amplifier LTC6409, which converts the single-ended signal into a differential signal. In order to transmit the signal to the analog-to-digital converter without distortion, a differential amplifier LTC6409 with a bandwidth of 10G is selected. Step 5: The converted differential signal is transmitted to the differential input of the AD9653 analog-to-digital converter, which converts the analog signal into a digital signal and outputs it to the FPGA module; Step 6: The FPGA module receives four 70M pixel clock-to-digital video signals and restores them to the original 280M pixel clock-to-digital video signals; Step 7: The raw digital video signal undergoes basic image processing, NUC correction, background correction, blind pixel filling, and image algorithms, including temporal filtering, spatial filtering, image enhancement, histogram adjustment, and brightness and contrast adjustment, before entering the DDR buffer. Step 8: Read the processed image data from DDR, add electronic magnification, pseudo-color, and icon overlay functions, and output video data according to the Cameralink timing requirements in FULL mode; The maximum bandwidth of DDR is calculated as follows: 1) The NUC calibration k value is 16 bits, and the DDR read bandwidth is 16 bits × 280 MHz = 4.48 Gb / s; 2) The NUC calibration b value is 16 bits, and the DDR read bandwidth is 16 bits × 280 MHz = 4.48 Gb / s; 3) During the background correction process, DDR is written and read simultaneously, occupying a bandwidth of (32bit+32bit)×280MHz=17.92Gb / s; 4) The 8-bit blind fill reading scheme has a bandwidth of 8 bits × 280 MHz = 2.24 Gb / s; 5) Time-domain filtering simultaneously writes to and reads from DDR, occupying a bandwidth of (16bit + 16bit) × 280MHz = 8.96Gb / s; 6) Spatial filtering, image enhancement, and histogram analysis do not consume bandwidth; 7) The image after brightness and contrast adjustment is written to DDR, occupying a bandwidth of 16bit × 280MHz = 4.48Gb / s; 8) Cameralink reads DDR bandwidth of 16 bits × 280 MHz = 4.48 Gb / s; In summary, the pixel clock is 280MHz. During background correction, DDR read / write operations 2), 4), 5), and 7) are disabled. At this time, the total DDR bandwidth is 1)+3)+8), which is 26.88Gb / s. After background correction is completed, the instantaneous total DDR bandwidth when the image is output normally is 1)+2)+4)+5)+7)+8), which is (32bit+8bit+16bit+16bit+16bit+16bit)×280MHz=29.12Gb / s. According to the chip datasheet, the theoretical bandwidth of 16-bit DDR is 6.4Gb / s. Calculated at 80% efficiency: 29.12Gb / s / (6.4Gb / s×80%)=5.6875. Therefore, 6 16-bit DDR chips are selected.

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