Back contact cells and methods of manufacture

Abstract

The application discloses a back contact cell and a preparation method, relates to the field of solar cells, and aims to improve current collection capability. The back contact cell comprises a silicon substrate, a first conductive area and a second conductive area on the back surface of the silicon substrate, and an edge conductive area arranged on one side edge or opposite two side edges of the back surface; wherein the edge conductive area comprises a first area extending along a first direction and at least one concave area extending along a second direction; one end of each concave area intersects with the first area, and the other end is connected with the first conductive area or the second conductive area which is not adjacent to the concave area and is closest to the concave area; a first seed layer is electrically connected with the first conductive area; a second seed layer is electrically connected with the second conductive area; and a third seed layer is electrically connected with the first area and the concave area, and is electrically connected with the seed layer of the first conductive area or the second conductive area which is not adjacent to the third seed layer and is closest to the third seed layer.

Description

Technical Field

[0001] This invention relates to the field of solar cells, and more specifically to a back-contact cell and its preparation method. Background Technology

[0002] Back-contact solar cells place all electrode contacts on the back of the cell, fundamentally eliminating power loss caused by shading from the front grid lines. This represents a significant development direction for high-efficiency crystalline silicon photovoltaic back-contact cell technology. With continuous technological iteration in the industry, fine-grid interconnection has become the mainstream method for achieving efficient interconnection in back-contact solar cells.

[0003] This fine-grid interconnection process first involves screen printing a thin-line-width silver paste seed layer onto the back of the back contact cell. Then, conductive wires, such as tin-plated copper wire, are directly soldered onto the seed layer to complete the series interconnection between the back contact cells. Compared to traditional main grid soldering methods, this fine-grid interconnection structure significantly reduces the amount of silver paste used, lowers series resistance, and reduces the probability of hot spots. Furthermore, it eliminates the need for additional insulating adhesive, thus balancing increased power generation with controlled production costs.

[0004] The inventors have discovered that the prior art has at least the following problems: the current fine grid interconnect structure is significantly inadequate in terms of current collection at the edge of the back contact battery. Summary of the Invention

[0005] This invention proposes a back-contact battery and its preparation method to improve current collection capability.

[0006] Some embodiments of the present invention provide a back contact battery, comprising: The silicon substrate includes, on its back side, alternating first and second conductive regions with opposite conductivity types, wherein adjacent first and second conductive regions are electrically isolated; it also includes an edge conductive region disposed on one side edge or opposite sides edge of the back side of the silicon substrate, wherein the edge conductive region has the same conductivity type as the first or second conductive region that is not adjacent to it and is closest to it. The edge conductive region includes a first region extending along a first direction and at least one concave region extending along a second direction; one end of each concave region intersects with the first region, and the other end is connected to the first conductive region or the second conductive region that is not adjacent to it and is closest to it; the height of each concave region is lower than the first region, the first conductive region and the second conductive region. The first seed layer includes at least a first main seed layer extending along a first direction and is electrically connected to the first conductive region; The second seed layer includes at least a second main seed layer extending along the first direction and is electrically connected to the second conductive region; and The third seed layer is electrically connected to both the first region and the concave region, and is also electrically connected to the seed layer of the first conductive region or the second conductive region that is not adjacent to it and is closest to it.

[0007] In some embodiments, a recessed portion is provided at the location where the first region intersects with the recessed region, and the height of the recessed portion is the same as the height of the corresponding recessed region.

[0008] In some embodiments, the width of the concave region in the first direction is 100 micrometers to 1000 micrometers; And / or, The line width of the third seed layer is 10 micrometers to 100 micrometers; And / or, The depth of the concave region is 1 micrometer to 20 micrometers.

[0009] In some embodiments, both the first conductive region and the second conductive region are interdigitated structures.

[0010] In some embodiments, the first seed layer further includes a first branch seed layer extending along a second direction, the first branch seed layer intersecting with the first main seed layer and electrically connected to the first conductive region; The second seed layer further includes a second branch seed layer extending along the second direction. The second branch seed layer intersects with the second main seed layer and is electrically connected to the second conductive region. The second branch seed layer and the first branch seed layer are staggered and alternately distributed. The third seed layer includes a first sub-seed layer extending along a first direction and a second sub-seed layer extending along a second direction. The first sub-seed layer is electrically connected to the first region. The second sub-seed layer is electrically connected to the concave region and to the first sub-seed layer, as well as to the main seed layer of the seed layer of the first conductive region or the second conductive region that is not adjacent to it but is closest to it. The second sub-seed layer is correspondingly arranged with the second branch seed layer or the first branch seed layer.

[0011] In some embodiments, the edge conductive region further includes at least one second region extending along a second direction, each second region being arranged at intervals from each of the recessed regions, each second region being connected to the first region, and the second region not extending to the first conductive region or the second conductive region adjacent to the edge conductive region; The third seed layer further includes a third sub-seed layer extending along the second direction. The third sub-seed layer is electrically connected to the second region and to the first sub-seed layer. Both the third sub-seed layer and the second sub-seed layer are corresponding to either the second sub-seed layer or the first sub-seed layer.

[0012] In some embodiments, two edge conductive regions are correspondingly disposed on opposite sides of the back surface of the silicon substrate, and the first conductive region and the second conductive region are disposed between the two edge conductive regions; The first conductive region is adjacent to one of the edge conductive regions, and the second conductive region is the closest to one of the edge conductive regions that is not adjacent to it; the second conductive region is adjacent to another edge conductive region, and the first conductive region is the closest to another edge conductive region that is not adjacent to it.

[0013] In some embodiments, the back contact battery further includes: The first conductive wire is fixed and electrically connected to the first main seed layer of the first seed layer; and The second conductive wire is fixed and electrically connected to the second main seed layer of the second seed layer.

[0014] This invention also provides a method for preparing a back contact battery, comprising the following steps: A recessed region is formed at a predetermined position on the back side of the silicon substrate to form a silicon substrate with the recessed region; The back side of the silicon substrate with the concave region is doped with doping elements of different conductivity types to form alternating first and second conductive regions with opposite conductivity types. At the same time, an edge conductive region containing the concave region is formed on one side edge or opposite sides edge of the back side of the silicon substrate. The edge conductive region has the same conductivity type as the first or second conductive region that is not adjacent to it and is closest to it. The edge conductive region is connected to the first or second conductive region that is not adjacent to it and is closest to it through the concave region. A first seed layer is processed in the first conductive region and electrically connected to the first conductive region; a second seed layer is processed in the second conductive region and electrically connected to the second conductive region; a third seed layer is processed in the edge conductive region and electrically connected to the edge conductive region, and electrically connected to the seed layer of the first conductive region or the second conductive region that is not adjacent to it and is closest to it. The first conductive wire is fixed to the first seed layer and electrically connected, and the second conductive wire is fixed to the second seed layer and electrically connected.

[0015] In some embodiments, the width of the concave region is 100 micrometers to 1000 micrometers; And / or, The depth of the concave region is 1 micrometer to 20 micrometers.

[0016] In some embodiments, a picosecond laser is used to process the concave region; The process parameters of the picosecond laser include: wavelength of 355nm or 532nm, pulse energy range of 2-50 μJ, repetition frequency of 50-400 kHz, and scanning speed of 0.2-3 m / s.

[0017] The back-contact battery provided by the above technical solution is suitable for various photovoltaic application scenarios, such as distributed photovoltaic power generation systems. Due to its compact structure and good electrical performance, it can effectively utilize limited space. It is also suitable for large-scale ground-mounted photovoltaic power plants, which can improve the power generation efficiency per unit area and reduce costs. Furthermore, the back-contact battery structure achieves current collection at the edge by rationally arranging the edge conductive area and the third seed layer, optimizing the electric field distribution at the edge of the back-contact battery, reducing edge leakage, and improving current collection efficiency. At the same time, the above-mentioned back-contact battery is easy to mass-produce, reducing production costs. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the three-dimensional structure of the back contact battery provided in an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the back contact battery planar structure provided in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the back contact battery planar structure of a comparative embodiment.

[0021] Figure label: 1. Silicon substrate; 2. First conductive region; 3. Second conductive region; 4. Edge conductive region; 5. First seed layer; 6. Second seed layer; 7. Third seed layer; 8. First conductive filament; 9. Second conductive filament; 41. First region; 42. Concave region; 411. Concave part; 43. Second region; 71. First seed layer; 72. Second seed layer; 73. Third seed layer; Comparative examples: 1000, first seed layer; 2000, second seed layer. Detailed Implementation

[0022] The following is combined with Figures 1-3The technical solutions provided by this invention will be described in more detail below. The descriptions of exemplary embodiments are merely illustrative and are in no way intended to limit this disclosure or its application or use. This disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make this disclosure thorough and complete, and to fully express the scope of this disclosure to those skilled in the art. It should be noted that, unless otherwise specifically stated, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as merely exemplary and not as limiting.

[0023] The terms “first,” “second,” and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as “including” or “contains” mean that the element preceding the word covers the element listed after the word, and do not exclude the possibility of covering other elements as well.

[0024] In this disclosure, when a specific device is described as being located between a first device and a second device, an intermediary device may or may not be present between the specific device and the first or second device. When a specific device is described as being connected to other devices, the specific device may be directly connected to the other devices without an intermediary device, or it may be not directly connected to the other devices but have an intermediary device.

[0025] All terms used in this disclosure, including technical or scientific terms, have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0026] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment shall be considered part of the specification.

[0027] The dimensions of the various parts shown in the accompanying drawings are not drawn to actual scale. Common structural elements or elements of the same kind are given the same reference numerals in the various drawings, and repeated descriptions of them are omitted where appropriate.

[0028] In the following description of specific embodiments, for ease of explanation, the length direction (i.e., the first direction) of the first region 41 is marked as X, and the length direction (i.e., the second direction) of the second region 43 is marked as Y.

[0029] The inventors discovered that to ensure insulation safety during component use and prevent short circuits, the conductive wires must maintain a certain safe distance from the physical edge of the battery and cannot be laid close to the edge. Because of this safety distance, the battery edge is located outside the coverage area of ​​the conductive wires, and the photogenerated carriers generated there cannot be collected through the conventional vertical conduction path, thus creating a dead zone for edge current collection and resulting in a loss of battery power generation efficiency.

[0030] The inventors continued their research and discovered that currently, the industry uses two battery structures to address the problem of current collection blind spots in this type of edge collection blind spot, but both solutions have unavoidable defects.

[0031] The first type is the edge-single polarity design. Specifically, within a safe distance at the edge of the battery, only one type of emitter or doped region is placed, such as a uniform N-type region. This design has a simple overall structure, a large process tolerance during manufacturing, and virtually no edge short-circuit issues, making it suitable for conventional mass production processes. However, this approach also has significant drawbacks. The other polarity of charge carriers generated within the edge safety zone, such as holes generated in the N-type region, cannot be effectively collected nearby and must instead travel a long lateral distance to the collection area inside the battery. This process significantly increases the series resistance in that area, leading to severe carrier recombination losses and ultimately a noticeable loss in battery efficiency.

[0032] The second type is the edge bipolar finger-intercalation design. Theoretically, if the internal structure of the battery can be replicated within a safe distance at the edge, and alternating narrow doped finger-like regions of P-type and N-type are arranged, efficient collection of edge carriers can be achieved nearby, compensating for blind zone losses and improving the overall battery efficiency. However, this solution is extremely difficult to apply in practice: to accurately fabricate and insulate two high-concentration doped regions within an extremely narrow edge space, the precision requirements for photolithography, laser doping, or ion implantation equipment are extremely high, resulting in extremely complex manufacturing processes and significantly increased production costs. More importantly, this structure greatly increases the risk of short circuits in the PN junction at the edge, directly affecting battery production yield and long-term reliability, making large-scale mass production highly impractical.

[0033] The inability to use insulating adhesive in fine-grid interconnect structures makes addressing the edge current collection dead zone extremely difficult. The core reason fine-grid interconnect structures cannot use insulating adhesive is that they eliminate the traditional main grid, lacking a dedicated main grid carrier for current collection. The function of insulating adhesive is to guide edge current towards the main grid; however, without a main grid, the current cannot be collected after being guided, rendering the insulating adhesive ineffective. Furthermore, even if forced to use it, it would increase the material cost of the insulating adhesive and additional processing costs. The insulating adhesive would also cause unevenness on the cell surface, potentially leading to microcracks and film delamination during subsequent lamination and encapsulation, affecting module quality and long-term reliability.

[0034] Therefore, within the framework of advanced fine-grid interconnected back-contact battery technology, there is an urgent need for an innovative technical solution. This solution needs to meet the following requirements: it should not use insulating adhesive, should not significantly increase the complexity of the manufacturing process, should not affect the reliability of the battery and components, and should effectively solve the current collection problem caused by the edge unipolar design, thereby fully realizing the efficiency potential of fine-grid interconnected back-contact batteries. The technical solution of this invention is proposed to address this urgent technical need.

[0035] Figure 1 This is a schematic diagram of the three-dimensional structure of the back contact battery provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the back contact battery planar structure provided in an embodiment of the present invention.

[0036] See Figure 1 and Figure 2This invention provides a back-contact battery, including a silicon substrate 1, a first seed layer 5, a second seed layer 6, and a third seed layer 7. The back surface of the silicon substrate 1 includes alternating first conductive regions 2 and second conductive regions 3 with opposite conductivity types, adjacent first conductive regions 2 and second conductive regions 3 being electrically isolated. It also includes an edge conductive region 4 disposed on one side edge or opposite sides of the back surface of the silicon substrate 1, the edge conductive region 4 having the same conductivity type as the nearest non-adjacent first conductive region 2 or second conductive region 3. The edge conductive region 4 includes a first region 41 extending along a first direction and at least one recessed region 42 extending along a second direction; one end of each recessed region 42 intersects with the first region 41, and the other end is connected to the nearest non-adjacent first conductive region 2 or second conductive region 3; the height of each recessed region 42 is lower than the first region 41, the first conductive region 2, and the second conductive region 3. The first seed layer 5 includes at least a first main seed layer extending along the first direction, and the first main seed layer is electrically connected to the first conductive region 2. The second seed layer 6 includes at least a second main seed layer extending along the first direction, and the second main seed layer is electrically connected to the second conductive region 3. The third seed layer 7 is electrically connected to both the first region 41 and the concave region 42, and is electrically connected to the seed layer of the first conductive region 2 or the second conductive region 3 that is not adjacent to it and is closest to it.

[0037] The silicon substrate 1 provides a supporting structure for the entire back contact cell. Its shape is, for example, square or rectangular, and the silicon substrate 1 is used to support other parts.

[0038] Both the first conductive region 2 and the second conductive region 3 are disposed on the back side of the silicon substrate 1 and are arranged alternately along the second direction. The width, length, and doping concentration of the first conductive region 2 and the second conductive region 3 are designed according to the performance requirements of the back contact battery; for example, the width may be in the range of several micrometers to tens of micrometers.

[0039] In some embodiments, the first conductive region 2 is an interdigitated structure, specifically one of an N-type finger-doped region and a P-type finger-doped region, and the second conductive region 3 is an interdigitated structure, specifically another of an N-type finger-doped region and a P-type finger-doped region.

[0040] When the first conductive region 2 is an N-type finger-doped region, doping with impurities such as phosphorus makes electrons the majority carriers in the silicon substrate 1. At this time, the second conductive region 3 is a P-type finger-doped region, doped with impurities such as boron, making holes the majority carriers. Under illumination, the N-type finger-doped region collects electrons, and the P-type finger-doped region collects holes. Under the influence of the built-in electric field, electrons and holes move in opposite directions, forming a current path and realizing photoelectric conversion in the back-contact battery.

[0041] Conversely, if the first conductive region 2 is a P-type finger-doped region and the second conductive region 3 is an N-type finger-doped region, the working principle is similar, but the carrier collection and movement directions are opposite. The P-type finger-doped region collects holes, and the N-type finger-doped region collects electrons, thus completing the photoelectric conversion process.

[0042] Different configurations of these doped regions allow back-contact batteries to be optimized for specific applications and performance requirements. In scenarios with high open-circuit voltage requirements, specific combinations of doped region types can be selected. By utilizing the built-in electric field characteristics formed by different doped regions, the separation efficiency of electron-hole pairs can be improved, thereby increasing the open-circuit voltage of the back-contact battery and ultimately improving the overall power generation efficiency. Furthermore, different combinations of doped regions also have unique characteristics in terms of process implementation, adapting to different manufacturing processes and cost requirements, thus providing more possibilities for the large-scale production and diversified applications of back-contact batteries.

[0043] The edge conductive region 4 is disposed on one side edge or opposite two sides of the back surface of the silicon substrate 1 in the first direction.

[0044] The concave region 42 is lower than the first region 41, the first conductive region 2, and the second conductive region 3. This structural design allows current in the edge region to be transmitted, which helps to collect current at the edge of the silicon substrate 1 and optimizes the electrical performance of the back contact battery edge.

[0045] The working principle of the back contact battery is as follows: When light shines on the surface of the back contact battery, the light enters the silicon substrate 1, generating electron-hole pairs within the silicon substrate 1. Due to the built-in electric field formed by the first conductive region 2 and the second conductive region 3, electrons and holes move to different regions respectively. Specifically, the first conductive region 2 is responsible for collecting one type of hole or electron, and the second conductive region 3 is responsible for collecting the other type. For example, the first seed layer 5 is electrically connected to the first conductive region 2, exporting the charge carried by the collected holes; the second seed layer 6 is electrically connected to the second conductive region 3, exporting the charge carried by the electrons. The third seed layer 7 is electrically connected to the edge conductive region 4, optimizing charge collection at the edge of the back contact battery, and is also electrically connected to the second seed layer 6, assisting in the overall charge transfer process and ultimately achieving current output.

[0046] The back-contact battery provided by the above technical solution is suitable for various photovoltaic application scenarios, such as distributed photovoltaic power generation systems. Due to its compact structure and good electrical performance, it can effectively utilize limited space. It is also suitable for large-scale ground-mounted photovoltaic power plants, which can improve the power generation efficiency per unit area and reduce costs. Furthermore, the back-contact battery structure achieves current collection at the edge by rationally arranging the edge conductive region 4 and the third seed layer 7, optimizing the electric field distribution at the edge of the back-contact battery, reducing edge leakage, and improving current collection efficiency. At the same time, the above-mentioned back-contact battery is easy to mass-produce, reducing production costs.

[0047] In some embodiments, a recessed portion 411 is provided in the first region 41 at the position where it intersects with the recessed region 42, and the height of the recessed portion 411 is the same as the height of the corresponding recessed region 42.

[0048] In some embodiments, the line width of the third seed layer 7 is between 10 micrometers and 100 micrometers. A narrower width is beneficial for improving the compactness and precision of the circuit layout, while a wider width can enhance the current collection capability. With a line width within the aforementioned range, the third seed layer 7 can effectively collect current. Printed at a designated location at the bottom of the recess 411, the third seed layer 7 achieves efficient current collection across the entire edge conductive area 4, optimizing the current collection efficiency of the back contact battery edge region and improving the overall performance of the back contact battery.

[0049] In some embodiments, where both the first conductive region 2 and the second conductive region 3 are interdigitated structures, the first seed layer 5 further includes a first branch seed layer extending along a second direction, which intersects with the first main seed layer and is electrically connected to the first conductive region 2. The second seed layer 6 further includes a second branch seed layer extending along a second direction, which intersects with the second main seed layer and is electrically connected to the second conductive region 3, and the second branch seed layer and the first branch seed layer are staggered and alternately distributed. The third seed layer 7 includes a first sub-seed layer 71 extending along a first direction and a second sub-seed layer 72 extending along a second direction. The first sub-seed layer 71 is electrically connected to the first region 41, and the second sub-seed layer 72 is electrically connected to the concave region 42 and to the main seed layer of the seed layer of the first conductive region 2 or the second conductive region 3 that is not adjacent to it and is closest to it. The second sub-seed layer 72 is correspondingly disposed with the first branch seed layer or the second seed layer. Note that the above-mentioned staggered and alternating distribution of the second seed layer and the first seed layer, as well as the corresponding arrangement of the second sub-seed layer 72 with the first seed layer or the second seed layer, all refer to the distribution of the relevant seed layers along the first direction.

[0050] The first seed layer 71 is arranged along the length direction X of the first region 41. The length of the first region 41 is almost the same as the length of the first seed layer 71, while the length of the first seed layer 71 is slightly shorter than the length of the first region 41. The first seed layer 71 extends in conjunction with the first region 41 and is responsible for collecting the charge of the first region 41.

[0051] The second seed layer 72 is arranged along the length Y direction of the concave region 42 and is electrically connected to the first seed layer 71. The length of the concave region 42 is almost the same as the length of the second seed layer 72, while the length of the second seed layer 72 is slightly shorter than that of the concave region 42. The second seed layer 72 extends along the concave region 42 and is responsible for collecting the charge in the concave region 42. Through its connection with the first seed layer 71, the second seed layer 72 can electrically transfer the charge it collects, as well as the charge collected by the first seed layer 71, to the second seed layer 71.

[0052] In some embodiments, the edge conductive region 4 further includes at least one second region 43 extending along a second direction. Each second region 43 is spaced apart from each concave region 42. Each second region 43 is connected to the first region 41. The second region 43 does not extend to the first conductive region 2 or the second conductive region 3 adjacent to the edge conductive region 4, that is, there is an electrically isolated region between the second region 43 and the first conductive region 2 or the second conductive region 3 adjacent to it. The third seed layer 7 further includes a third sub-seed layer 73 extending along the second direction. The third sub-seed layer 73 is electrically connected to the second region 43 and to the first sub-seed layer 71. The third sub-seed layer 73 and the second sub-seed layer 72 are both corresponding to the second sub-seed layer or the first sub-seed layer.

[0053] Each second region 43 and each concave region 42 are arranged at intervals in the first direction, and each second region 43 is connected to the first region 41. For example, the concave region 42 and the second region 43 are spaced apart by a certain distance. This arrangement can increase the path and range of charge collection at the edge of the back contact battery. The third seed layer 7 is electrically connected not only to the first region 41 and the concave region 42, but also to each of the second regions 43. The third seed layer 7 covers a larger area of ​​the edge region of the back contact battery, which is beneficial for current collection.

[0054] The aforementioned technical solution significantly improves the charge collection efficiency in the edge region of the back contact battery. The multi-region design allows the back contact battery to more fully collect the charge generated at the edge, reducing charge loss and improving the overall power generation efficiency of the back contact battery. Furthermore, the flexible structural design allows for adjustment of the number and spacing of the second regions 43 according to different back contact battery performance requirements, achieving even more efficient current collection.

[0055] The third seed layer 73 is arranged along the length Y direction of the second region 43, parallel to the second seed layer 72. The length of the second region 43 and the length of the third seed layer 73 are almost the same, while the length of the third seed layer 73 is slightly shorter than that of the second region 43. The third seed layer 73 is responsible for collecting the charge in the second region 43. The third seed layer 73 is electrically connected to the first seed layer 71. The charge collected by the third seed layer 73 is transferred to the second seed layer 6 through the first seed layer 71 and the second seed layer 72, and then transferred out. In this way, a multi-directional charge collection and transmission network structure is formed in the edge region of the back contact battery.

[0056] In the above technical solution, during the operation of the back contact battery, the charges generated in each region move under the influence of an electric field. The first sub-seed layer 71 collects the charges in the first region 41 along its length, and the second sub-seed layer 72 collects the charges in the concave region 42 and transfers them to the second seed layer 6 through an electrical connection. The third sub-seed layer 73 collects the charges in the second region 43, and because it is electrically connected to the first sub-seed layer 71, and the first sub-seed layer 71 is electrically connected to the second sub-seed layer 72, the charges collected by the first sub-seed layer 71 and the third sub-seed layer 73 can be uniformly transferred to the second seed layer 6, thus optimizing the charge collection and transmission path.

[0057] This structural design improves charge collection efficiency in the edge region of the back contact battery. The multi-directional seed layer arrangement allows for more comprehensive collection of charges from different regions and directions, reducing charge loss and thus improving the overall performance of the back contact battery. Furthermore, this flexible layout facilitates adjustments based on different design requirements and application scenarios, making it suitable for both small photovoltaic devices and large-scale photovoltaic power plants.

[0058] In the above embodiments, in the first direction, the width of the concave region 42 is 100 micrometers to 1000 micrometers.

[0059] The aforementioned width range is compatible with the design width of conventional doping regions, such as N-type doped regions. The second sub-seed layer 72, located within the recessed region 42, has a width ranging from 10 micrometers to 100 micrometers. The second sub-seed layer 72, serving as a current collection layer, is printed at a predetermined position at the bottom of the recessed region 42. This design allows the second sub-seed layer 72 to effectively collect the lateral current throughout the entire recessed region 42, ensuring efficient and stable current collection within the back-contact battery.

[0060] In some embodiments, the depth of the concave region 42 is 1 micrometer to 20 micrometers. Preferably, the depth of the concave region 42 is 5 micrometers to 15 micrometers.

[0061] The recessed region 42, with its aforementioned depth range, serves two purposes. First, it effectively accommodates the subsequent seed layer, ensuring sufficient space for its uniform distribution within the recessed region 42. This provides a good pathway for current conduction, allowing the seed layer to function properly within the back contact battery structure. Second, it provides sufficient vertical insulation distance for the overhead conductive wires, preventing electrical contact between the wires and the structure within the recessed region 42 or the underlying silicon wafer layer, thus avoiding short circuits and ensuring reliable electrical performance of the back contact battery. Furthermore, it avoids excessive damage to the mechanical strength of the silicon wafer. Commonly used silicon wafers are approximately 135µm thick. If 20µm is etched, the remaining 115µm of silicon wafer becomes fragile, affecting production and operational stability. A depth of 5-15 micrometers maximizes the preservation of the silicon wafer's mechanical strength and reduces risk.

[0062] The depth of the recessed region 42 depends on the matching of the laser, cleaning process, or photolithography ink and cleaning process, and is mainly determined by the laser and cleaning process parameters. Higher laser energy and longer cleaning time result in a deeper depth; conversely, lower energy and lower cleaning time result in a shallower depth.

[0063] From the perspective of back-contact battery performance, the shallow depth of the recessed region (42) and the thick silicon substrate are beneficial for long-wavelength light absorption to increase current, but this increases the load because it needs to carry more electron-hole pair transport. A deeper recess results in a thinner silicon substrate, which reduces the load and is beneficial for increasing the open-circuit voltage because the electron-hole pair transport path is shortened. However, this leads to reduced light absorption, lower current, and the thinner silicon wafer becomes more brittle and prone to microcracks.

[0064] By employing the aforementioned depth range, both current and open-circuit voltage are considered, ensuring good mechanical properties of the silicon wafer, reducing or even eliminating microcracks in the silicon wafer, and achieving optimal overall performance of the back-contact battery. Simultaneously, this depth range also takes into account the requirement that the second seed layer 72, located within the recessed region 42, needs to be insulated from the other polarity conductive wire above it to avoid contact.

[0065] In some embodiments, a clearance area is provided for the first conductive region 2 or the second conductive region 3 adjacent to the first region 41 of the edge conductive region 4, and the clearance area provides arrangement space for the concave region 42; the clearance area is not provided with a corresponding seed layer for the first conductive region 2 or the second conductive region 3.

[0066] The clearance area provides space for the recessed area 42 to optimize the internal structural layout of the back contact battery. The clearance area is, for example, rectangular, with its length and width determined by the dimensions of the recessed area 42 and the overall design of the back contact battery, ensuring sufficient space for the recessed area 42 without interference from surrounding areas. Furthermore, no seed layer corresponding to the first conductive area 2 or the second conductive area 3 adjacent to the edge conductive area 4 is provided within the clearance area to avoid interference between the seed layer and the seed layer located in the recessed area 42, ensuring the normal functioning of all parts of the back contact battery.

[0067] During the operation of the back contact battery, charge is conducted in various regions. The first conductive region 2 collects the corresponding charge, and due to the existence of the avoidance region, it does not affect the charge collection and transmission in the concave region 42. Through the coordinated operation of the third seed layer 7, the first region 41, and the concave region 42, the concave region 42 achieves efficient charge collection and transmission in all regions of the back contact battery.

[0068] The back contact battery adopts the above structure, which optimizes the internal spatial layout of the back contact battery, allowing for a more rational distribution of each area, reducing mutual interference between different areas, and improving the overall performance of the back contact battery. Simultaneously, the avoidance area does not have a seed layer corresponding to the first conductive area 2 or the second conductive area 3 adjacent to the edge conductive area 4, which helps simplify the structure, reduce process complexity, improve production efficiency, and avoid short circuits and other problems that may be caused by redundant seed layers. This enhances the stability and reliability of the back contact battery, enabling it to operate stably in various environments.

[0069] In some embodiments, two edge conductive regions 4 are respectively disposed on opposite sides of the back surface of the silicon substrate 1, and a first conductive region 2 and a second conductive region 3 are disposed between the two edge conductive regions 4. The first conductive region 2 is adjacent to one edge conductive region 4, and the second conductive region 3 is not adjacent to one edge conductive region 4 but is closest to it; the second conductive region 3 is adjacent to another edge conductive region 4, and the first conductive region 2 is not adjacent to another edge conductive region 4 but is closest to it.

[0070] With the above structure, the current generated by the two edge conductive regions 4 can be effectively collected, and the current collection inside the back contact battery is more efficient.

[0071] In some embodiments, the back contact battery further includes a first conductive wire 8 and a second conductive wire 9. The first conductive wire 8 is fixed and electrically connected to the first main seed layer of the first seed layer 5. The second conductive wire 9 is fixed and electrically connected to the second main seed layer of the second seed layer 6.

[0072] The first conductive wire 8 is fixed and electrically connected to the first seed layer 5. This connection method allows the first conductive wire 8 to be firmly attached to the first seed layer 5, ensuring that charge can be smoothly conducted from the first seed layer 5 to the first conductive wire 8. For example, the two can be fixed and electrically connected through a specific metal welding process, ensuring that the connection is strong and the conductivity is good, so that the charge collected in the first seed layer 5 can be smoothly conducted to the first conductive wire 8.

[0073] The second conductive wire 9 is fixed and electrically connected to the second seed layer 6. Similarly, a suitable process is used to ensure the reliability of the connection, so that the charge collected by the second seed layer 6 can be efficiently transferred to the second conductive wire 9.

[0074] Neither the first conductive wire 8 nor the second conductive wire 9 is arranged within the recessed region 42. From the depth direction of the back contact battery, there is no contact between the conductive wires and the recessed region 42. This layout design allows the conductive wires to efficiently perform their conductivity function without being limited by the space of the recessed region 42 when undertaking current transmission tasks. Furthermore, the recessed region 42 can serve as a precise alignment mark for screen printing, improving the accuracy of the printing process during the back contact battery manufacturing process. In addition, it optimizes the internal current conduction path of the back contact battery, working in conjunction with the recessed region 42 to play a positive role in improving the overall performance of the back contact battery, ensuring stable and efficient operation.

[0075] When the back-contact battery is in operation, after photogenerated charge carriers are generated, the charge collected in the first conductive region 2 is transferred to the first seed layer 5, and then conducted out through the first conductive wire 8 connected to it. At the same time, the charge collected in the second conductive region 3 is transferred to the second seed layer 6, and then conducted out through the second conductive wire 9. The two conductive wires correspond to the charge transport paths of doped regions with different conductivity characteristics, orderly transporting different types of charges, and ultimately realizing the current output of the back-contact battery.

[0076] In some embodiments, the back contact battery includes a plurality of first conductive regions 2, a plurality of second conductive regions 3, and one or two edge conductive regions 4. Except for the first conductive regions 2 or second conductive regions 3 adjacent to the edge conductive regions 4 which adopt the special structure described above, the other first conductive regions 2 or second conductive regions 3 can adopt conventional structures.

[0077] This invention also provides a photovoltaic module, including a back contact cell provided by any of the technical solutions of this invention.

[0078] Photovoltaic modules, due to their back-contact cells as described above, also possess the beneficial effects described above.

[0079] This invention provides another method for preparing a back contact battery, used to manufacture the back contact battery described above. This method includes the following steps: In step S100, a recessed region 42 is formed at a predetermined position on the back side of the silicon substrate 1 to form a silicon substrate 1 with the recessed region 42.

[0080] In step S100 above, for example, a picosecond laser is used to process the concave region 42. The laser wavelength of the picosecond laser is 355nm or 532nm, the pulse energy range is set to 2-50μJ, the repetition frequency is 50-400kHz, and the scanning speed is 0.2-3m / s.

[0081] Taking a laser with a wavelength of 355nm as an example, this wavelength of laser has the characteristics of concentrated energy and good focusing, which can accurately act on the surface of silicon substrate 1. The laser etching equipment emits a high-energy laser beam according to a preset path. The silicon material in the preset area of ​​silicon substrate 1 quickly absorbs the energy. Due to the high laser energy, the temperature of the silicon material rises sharply and instantly vaporizes and detaches from silicon substrate 1, thereby forming a concave region 42.

[0082] During the processing, the dimensions of the recessed region 42 can be precisely controlled by flexibly adjusting parameters such as laser scanning speed, energy output, and the number of scans. For example, in the first direction, the width can be adjusted between 100 and 1000 micrometers; the depth can vary between 1 and 20 micrometers to meet different design requirements.

[0083] Specifically, when the laser pulse energy is set to 10 μJ, the repetition frequency is adjusted to 200 kHz, and the scanning speed is set to 1.0 m / s, a recessed region 42 of a specific size can be processed on the back edge of the silicon wafer in a single scan. The depth H of the recessed region 42 is 10 ± 2 micrometers, which is within the preferred range of 1 micrometer to 20 micrometers; the width is 400 micrometers, which is within the range of 100-1000 micrometers; and the length extends 2.0 mm from the edge of the silicon wafer inward.

[0084] If subsequent processes employ laser technology, in the Laser1 step—the first operation in the entire laser processing flow—it is necessary to remove the P-poly in the concave region 42. P-poly refers to P-type doped polysilicon, which is produced by doping with elements such as boron, making holes the majority carriers in the polysilicon. Then, N-poly, or N-type doped polysilicon, is prepared within the concave region 42, where electrons are the majority carriers by doping with elements such as phosphorus. This ensures that each process step is closely interconnected and carried out in an orderly manner.

[0085] By pre-setting the recessed area 42, the risk of relying on insulating adhesive to solve the contact between the conductive wire and the opposite polarity area is avoided, and an effective way to collect edge current is provided. Without sacrificing the edge power generation capacity, the stability and reliability of the back contact battery manufacturing process are improved, and the overall collection efficiency and module reliability of the edge area of ​​the back contact battery are enhanced.

[0086] In step S200, the back side of the silicon substrate 1 with the concave region 42 is doped with doping elements of different conductivity types to form alternating first conductive regions 2 and second conductive regions 3 with opposite conductivity types. At the same time, an edge conductive region 4 containing the concave region 42 is formed on one side edge or opposite sides edge of the back side of the silicon substrate 1. The edge conductive region 4 has the same conductivity type as the first conductive region 2 or the second conductive region 3 that is not adjacent to it and is closest to it. The edge conductive region 4 is connected to the first conductive region 2 or the second conductive region 3 that is not adjacent to it and is closest to it through the concave region 42.

[0087] In some embodiments, a first conductive region 2, a second conductive region 3, and an edge conductive region 4 are formed on the back side of a silicon substrate using LPCVD and thermal diffusion processes.

[0088] LPCVD, or Low-Pressure Chemical Vapor Deposition, is a technique that deposits solid thin films on a heated substrate by reacting gaseous chemicals under relatively low pressure. In back-contact solar cell fabrication, this technique is used to form specific doped regions on the back side of a silicon substrate, controlling the growth and quality of the thin film to meet the performance requirements of different regions.

[0089] The specific operation process is as follows: First, a thin film containing specific impurity atoms is deposited on the back side of a silicon substrate 1 using LPCVD. LPCVD is performed under low pressure, which allows the film to be uniformly deposited on the complex surface of the silicon substrate 1, including the concave region 42. Subsequently, a thermal diffusion process is performed. Under high temperature, the impurity atoms in the film gain sufficient energy to diffuse into the silicon substrate 1. Based on the type of impurity atoms and parameters such as diffusion time and temperature, the first conductive region 2, the second conductive region 3, and the edge conductive region 4 are precisely formed. At the same time, the high-temperature process also passivates the surface of the silicon substrate 1, reducing surface defects and carrier recombination. For example, to form an N-type doped region, after depositing a phosphorus-containing thin film by LPCVD, phosphorus atoms can be diffused into the silicon substrate 1 through thermal diffusion to form an N-type region; to form a P-type doped region, a boron-containing thin film can be deposited and then thermally diffused. The above steps reduce carrier recombination and improve photoelectric conversion efficiency.

[0090] A passivation and antireflection layer can also be deposited on the surface of the silicon substrate 1 after step S200 and before step S300. The passivation and antireflection layer can reduce light reflection, allowing more light to be absorbed by the silicon substrate 1, thereby increasing the photoelectric conversion efficiency of the back contact cell. In step S300, a first seed layer 5 is processed in the first conductive region 2 and electrically connected to the first conductive region 2; a second seed layer 6 is processed in the second conductive region 3 and electrically connected to the second conductive region 3; a third seed layer 7 is processed in the edge conductive region 4 and electrically connected to the edge conductive region 4, and electrically connected to the seed layer of the first conductive region 2 or the second conductive region 3 that is not adjacent to it and is closest to it.

[0091] In some embodiments, a first seed layer 5, a second seed layer 6, and a third seed layer 7 are processed on the back side of the silicon substrate 1 using a screen printing machine.

[0092] The above step S300 specifically includes the following steps: First, the edge contour of the concave region 42 is used as an alignment mark to align the pattern to be printed with the silicon substrate 1.

[0093] In some embodiments, the alignment accuracy between the pattern to be printed and the silicon substrate 1 is within ±15 micrometers.

[0094] Precise alignment is required in the screen printing process of back-contact battery production. Back-contact batteries have extremely high requirements for printing alignment; misalignment of the grid lines can easily lead to device failures such as leakage. However, silicon wafers themselves have dimensional errors, and relying solely on the printer's vision system to identify the wafer edges for alignment will introduce corresponding errors.

[0095] In related technologies, four CCD cameras are used in industrial settings to capture dedicated marker points at the four corners of the silicon wafer, which serve as the silicon substrate 1. The pattern is, for example, solid circles and crosshairs. The cameras accurately capture the center coordinates of the marker points, and the vision system calculates the position and angular deviation of the silicon wafer based on this. This information is then fed back to a precision motion platform, which performs micron-level displacement and rotation compensation to achieve precise alignment between the stencil and the silicon wafer.

[0096] The technical solution of this invention utilizes a recessed region 42, created by pre-dopated areas at the edge of the silicon wafer, as an additional identification point. The edge contour of the recessed region 42 serves as an alignment mark; its clear outline and fixed position make it an ideal reference. Before printing, an optical or mechanical positioning system, such as a high-precision camera, captures an image of the edge of the recessed region 42. After software analysis and processing, the screen position is adjusted to achieve precise alignment within ±15 micrometers, ensuring accurate seed layer printing and consistent back-contact battery performance.

[0097] Compared to the traditional method that relies solely on four corner markers, this recessed area 42 adds a crucial alignment reference. During actual screen printing, the camera identifies points in the recessed area 42, assisting the vision system in more accurately determining the position and angle of the silicon wafer, improving printing accuracy, providing a more reliable alignment guarantee for back-contact battery production, and reducing the risk of device failure due to grid line misalignment.

[0098] Next, the first seed layer 5, the second seed layer 6, and the third seed layer 7 are formed in sequence.

[0099] The screen printing machine transfers the paste on the screen through the corresponding pattern holes to the back of the silicon substrate 1. The formation order of the first seed layer 5, the second seed layer 6, and the third seed layer 7 can be set as needed. For example, the first seed layer 5 can be printed first, and after it dries or cures, the second seed layer 6 can be printed, and finally the third seed layer 7 can be printed. During the printing process, parameters such as paste composition, viscosity, printing pressure, and speed are controlled to ensure that the thickness, shape, and properties of each sublayer meet the design requirements.

[0100] In step S400, the first conductive wire 8 is fixed to the first seed layer 5 and electrically connected, and the second conductive wire 9 is fixed to the second seed layer 6 and electrically connected.

[0101] If a welding process is used, for the connection between the first conductive wire 8 and the first seed layer 5, a micro-spot welding device can be used to precisely distribute tiny solder points on the contact area between the two. The heat generated by the instantaneous high current melts the metal material at the solder point, and after cooling, a strong electrical and mechanical connection is formed. The same method is used for the connection between the second conductive wire 9 and the second seed layer 6. If an adhesive process is used, a highly conductive adhesive is selected, evenly applied to the contact area between the conductive wire and the seed layer, a certain pressure is applied, and the adhesive is allowed to cure to achieve a stable connection and ensure stable charge transfer.

[0102] The above-described technical solution involves fabricating a recessed region 42 of a predetermined depth within a pre-dopated area at the edge of the silicon wafer before the back-contact battery production process begins. This recessed region 42 extends inward towards the silicon wafer and connects with the first homopolar region inside. During subsequent conventional processes and seed layer screen printing, this recessed region 42 serves as a precise alignment mark, providing a reliable reference for accurate printing. Finally, through conductive wire welding, the edge fine gate seed layer achieves electrical connection with the internal homopolar main gate via this special structure of the recessed region 42. This creates a low-resistance collection channel for edge photogenerated carriers. Simultaneously, it ensures insulation from adjacent heteropolar conductive wires. This fabrication method avoids a series of problems associated with using insulating adhesive and significantly improves the current collection efficiency in the edge region of the back-contact battery, enhancing the overall performance of the back-contact battery.

[0103] Existing technologies struggle to collect current from the edge regions of fine-grid interconnected back-contact batteries. Designing the edge region as a single-conductive polarity region requires carriers to traverse a long lateral transport distance, significantly increasing the probability of recombination losses and directly leading to a sharp decline in edge efficiency. While designing it as a bipolar interlaced finger region optimizes the collection path to some extent, it introduces new problems: significantly increased process complexity, a markedly higher risk of short circuits, and difficulty in effectively guaranteeing reliability. Furthermore, the traditional method of using insulating adhesive for current collection is also unsatisfactory, not only adding extra steps but also negatively impacting the surface flatness of the back-contact battery, thereby reducing packaging reliability.

[0104] The technical solution of this invention can successfully collect current in the edge region of a fine-grid interconnected back contact battery. On one hand, the optimized structural design of the back contact battery effectively shortens the lateral transport distance of charge carriers, significantly reduces recombination losses, and improves the current collection efficiency in the edge region. On the other hand, the unique layout simplifies the fabrication process, reduces the risk of short circuits, and greatly improves the reliability of the back contact battery. Simultaneously, the technical solution of this invention does not use insulating adhesive, avoiding many drawbacks associated with its use. This simplifies the process and ensures the surface flatness of the back contact battery, providing a solid guarantee for packaging reliability.

[0105] The following is a comparative example. The comparative example is the fabrication method of an existing edge-single polarity back contact battery.

[0106] This comparative example is used to prepare, for example... Figure 3 The conventional fine-grid interconnected solar back contact cell shown has a different manufacturing process than the previous embodiment. It does not involve the concave part processing step and has a different edge design.

[0107] First: Conventional back-contact cell fabrication.

[0108] An N-type silicon wafer with the same specifications as in the example was selected, and the deposition doping process was started directly.

[0109] Doping: P+ and N+ regions are generated on the back side of the silicon wafer using existing processes. The difference from the preparation method of this invention is that, in the comparative example, only a second conductive region is planned and prepared within a range of H (e.g., 1.5 mm) from the edge of the back contact cell, thereby forming a continuous edge single polarity region, while the back contact cell still adopts a finger-insertion design.

[0110] Passivation: Depositing a passivation antireflection layer on the surface of a silicon wafer.

[0111] Second: Seed layer printing and alignment.

[0112] Because the comparison model lacks a pre-processed recess as a marker, the printing press's vision system can only achieve alignment by relying on other features.

[0113] Pattern formation: Print a first seed layer 1000 and a second seed layer 2000. The second seed layer 2000 terminates at the edge on a single P+ area at the edge.

[0114] Third: Welding of conductive wires.

[0115] After the seed layer is printed, the first and second conductive wires are soldered. The outermost conductive wire is soldered to the gate line of the first P+ region inside. In this way, electrons generated in the edge P+ region have no effective way to exit and can only rely on the silicon wafer itself for long-distance lateral transport, which greatly increases the series resistance of this region.

[0116] Table 1: Component power test results of the examples and comparative examples

[0117] The meanings of the parameters in the table header above are as follows.

[0118] Pmpp: Maximum power point power (or simply maximum power).

[0119] Vmpp: Maximum power point voltage.

[0120] Impp: Maximum power point current.

[0121] Isc: Short-circuit current (the maximum current that passes through when the positive and negative terminals of the component are directly short-circuited).

[0122] FF: Fill factor (a key indicator for measuring the output performance of back-contact batteries; a higher value indicates higher efficiency).

[0123] Rs: Series resistance (composed of back contact cell resistance, grid line resistance, etc., ideally it should be as small as possible).

[0124] Rsh: Parallel resistance (also known as bypass resistance, ideally the larger the better to reduce leakage current).

[0125] Voc: Open circuit voltage (refers to the voltage value across the module when the positive and negative terminals are not connected to a load and are in an open circuit state under standard test conditions (light, temperature), which is the module's limit output voltage).

[0126] As can be seen from the above comparison of the preparation process and final structure of the embodiments and comparative examples of the present invention, there are significant differences in the technical effects between the two.

[0127] This invention adds a parameter-controllable concave region 42 fabrication step before the standard fabrication process, and uses this concave region 42 as a marker during back-end printing alignment. This design achieves two key functions. First, it constructs a low-resistance current channel for the N-region in the edge-finger-type design, enabling efficient current extraction from the edge region and avoiding energy loss due to poor current transmission. Second, by utilizing the depth of the concave region 42, it spatially prevents the conductive wire from contacting the intersecting opposite polarity regions, thus achieving automatic insulation without the need for additional insulating adhesives, simplifying the process and improving the reliability of the back contact battery structure.

[0128] In contrast, due to the use of a single polarity design at the edge, electrons generated in the edge region lack an effective exit path and can only rely on the silicon wafer itself for long-distance lateral transport. This not only leads to a significant increase in the series resistance in this region, but also creates an inherent bottleneck in current collection loss, seriously affecting the overall performance of the back contact battery.

[0129] The comparison shows that the manufacturing process of this invention, with only one ingenious prefabrication step, successfully solves the long-standing problem of simultaneously achieving edge efficiency and reliability in the field of back contact battery manufacturing, demonstrating significant technical advantages.

[0130] This invention provides a back contact battery manufacturing system, including a memory and a processor coupled to the memory. The processor is configured to execute the back contact battery manufacturing method of any of the foregoing embodiments based on instructions stored in the memory.

[0131] Memory may include, for example, system memory, fixed non-volatile storage media, etc. System memory may store, for example, the operating system, application programs, boot loader, and other programs.

[0132] Some embodiments of this disclosure also provide a computer-readable storage medium having a computer program stored thereon. When executed by a processor, the program implements the back contact battery fabrication method of any of the above embodiments.

[0133] The processors described herein may include general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in alternatives, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration.

[0134] Storage media can be any available medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Any connection is also properly referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disk and disc include compact discs (CDs), laser discs, optical discs, digital multi-purpose discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, and discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0135] Those skilled in the art will understand that the method embodiments of this disclosure can be provided as a method, system, or computer program product. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable non-transitory storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0136] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0137] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0138] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0139] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the scope of protection of this invention. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0140] In the description of this invention, each technical feature may be combined with other technical features where feasible.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. However, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A back-contact battery, characterized in that, include: The silicon substrate (1) includes alternating first conductive regions (2) and second conductive regions (3) with opposite conductivity types on its back side, and adjacent first conductive regions (2) and second conductive regions (3) are electrically isolated; it also includes an edge conductive region (4) disposed on one side edge or opposite sides edge of the back side of the silicon substrate (1), and the edge conductive region (4) has the same conductivity type as the first conductive region (2) or the second conductive region (3) that is not adjacent to it and is closest to it; The edge conductive region (4) includes a first region (41) extending along a first direction and at least one concave region (42) extending along a second direction; one end of each concave region (42) intersects with the first region (41), and the other end is connected to the first conductive region (2) or the second conductive region (3) that is not adjacent to it and is closest to it; the height of each concave region (42) is lower than the first region (41), the first conductive region (2) and the second conductive region (3). The first seed layer (5) includes at least a first main seed layer extending along a first direction and is electrically connected to the first conductive region (2); The second seed layer (6) includes at least a second main seed layer extending along a first direction and is electrically connected to the second conductive region (3); and The third seed layer (7) is electrically connected to both the first region (41) and the concave region (42), and is also electrically connected to the seed layer of the first conductive region (2) or the second conductive region (3) that is not adjacent to it and is closest to it.

2. The back contact battery according to claim 1, characterized in that, A recessed portion (411) is provided at the position where it intersects with the recessed region (42) in the first region (41), and the height of the recessed portion (411) is the same as the height of the corresponding recessed region (42).

3. The back contact battery according to claim 1, characterized in that, In the first direction, the width of the concave region (42) is 100 micrometers to 1000 micrometers; And / or, The line width of the third seed layer (7) is 10 micrometers to 100 micrometers; And / or, The depth of the concave region (42) is 1 micrometer to 20 micrometers.

4. The back contact battery according to claim 1, characterized in that, Both the first conductive region (2) and the second conductive region (3) are interdigitated structures; The first seed layer (5) further includes a first branch seed layer extending along the second direction, the first branch seed layer intersecting with the first main seed layer and electrically connected to the first conductive region (2); The second seed layer (6) further includes a second branch seed layer extending along the second direction. The second branch seed layer intersects with the second main seed layer and is electrically connected to the second conductive region (3). The second branch seed layer and the first branch seed layer are staggered and alternately distributed. The third seed layer (7) includes a first sub-seed layer (71) extending along a first direction and a second sub-seed layer (72) extending along a second direction. The first sub-seed layer (71) is electrically connected to the first region (41), and the second sub-seed layer (72) is electrically connected to the concave region (42) and to the first sub-seed layer (71) and to the main seed layer of the seed layer of the first conductive region (2) or the second conductive region (3) that is not adjacent to it and is closest to it.

5. The back contact battery according to claim 4, characterized in that, The edge conductive region (4) further includes at least one second region (43) extending along the second direction. Each second region (43) is arranged at intervals from each of the concave regions (42). Each second region (43) is connected to the first region (41). The second region (43) does not extend to the first conductive region (2) or the second conductive region (3) adjacent to the edge conductive region (4). The third seed layer (7) also includes a third sub-seed layer (73) extending along the second direction. The third sub-seed layer (73) is electrically connected to the second region (43) and to the first sub-seed layer (71), and both the third sub-seed layer (73) and the second sub-seed layer (72) are configured corresponding to the second branch seed layer or the first branch seed layer.

6. The back contact battery according to any one of claims 1 to 5, characterized in that, Two edge conductive regions (4) are respectively disposed on opposite sides of the back surface of the silicon substrate (1), and the first conductive region (2) and the second conductive region (3) are disposed between the two edge conductive regions (4); The first conductive region (2) is adjacent to one of the edge conductive regions (4), and the second conductive region (3) is not adjacent to one of the edge conductive regions (4) and is closest to it; the second conductive region (3) is adjacent to another edge conductive region (4), and the first conductive region (2) is not adjacent to another edge conductive region (4) and is closest to it.

7. The back contact battery according to any one of claims 1 to 5, characterized in that, The back contact battery also includes: The first conductive wire (8) is fixed and electrically connected to the first main seed layer of the first seed layer (5); and The second conductive wire (9) is fixed and electrically connected to the second main seed layer of the second seed layer (6).

8. A method for preparing a back contact battery, characterized in that, Includes the following steps: A recessed region (42) is formed at a predetermined position on the back side of the silicon substrate (1) to form a silicon substrate (1) with the recessed region (42). The back side of the silicon substrate (1) with the concave region (42) is doped with doping elements of different conductivity types to form alternating first conductive regions (2) and second conductive regions (3) with opposite conductivity types. At the same time, an edge conductive region (4) containing the concave region (42) is formed on one side edge or opposite sides edge of the back side of the silicon substrate (1). The edge conductive region (4) has the same conductivity type as the first conductive region (2) or the second conductive region (3) that is not adjacent to it and is closest to it. The edge conductive region (4) is connected to the first conductive region (2) or the second conductive region (3) that is not adjacent to it and is closest to it through the concave region (42). A first seed layer (5) is processed in the first conductive region (2) and electrically connected to the first conductive region (2); a second seed layer (6) is processed in the second conductive region (3) and electrically connected to the second conductive region (3); a third seed layer (7) is processed in the edge conductive region (4) and electrically connected to the edge conductive region (4) and electrically connected to the seed layer of the first conductive region (2) or the second conductive region (3) that is not adjacent to it and is closest to it. The first conductive wire (8) is fixed to the first seed layer (5) and electrically connected, and the second conductive wire (9) is fixed to the second seed layer (6) and electrically connected.

9. The method for preparing a back contact battery according to claim 8, characterized in that, The width of the concave region (42) is 100 micrometers to 1000 micrometers; And / or, The depth of the concave region (42) is 1 micrometer to 20 micrometers.

10. The method for preparing a back contact battery according to claim 8 or 9, characterized in that, The concave region (42) is formed by processing with a picosecond laser. The process parameters of the picosecond laser include: wavelength of 355nm or 532nm, pulse energy range of 2-50μJ, repetition frequency of 50-400 kHz, and scanning speed of 0.2-3 m / s.

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