Hardware augmentation of space data processing and knowledge management system

Abstract

The application discloses a kind of hardware supplement method, system and circuit of space data processing and knowledge management system, belong to spaceborne data processing technical field, for solving existing spaceborne data processing relies on central processing unit and software architecture, it is easy to be affected by space single particle effect, space radiation interference and appear operation exception, real-time and reliability insufficient problem.The core method of the application includes: reading cache knowledge according to time decay calculation current confidence;Data packet hop count or survival time is directly discarded when exceeding limit;After inter-satellite link interruption recovers, master artificial intelligence node is elected according to preset rule and conflict is judged;When cache is written, it is accumulated to the minimum writing unit after being written once, and wear leveling is triggered according to the number of erasing and writing.The whole process of the application is automatically executed by pure hardware circuit, without central processing unit, without instruction execution, without software code running, with the characteristics of anti-radiation, high real-time, high reliability, can be adapted to space on-orbit environment.

Description

Technical Field

[0001] This invention belongs to the field of aerospace onboard data processing technology, and particularly relates to a hardware supplementation method, system and circuit for a space data processing and knowledge management system. Background Technology

[0002] In deep space exploration missions, onboard data processing and knowledge management systems must withstand extreme conditions such as extremely long communication delays, unstable link quality, strong space radiation interference, and high ground maintenance difficulties. Most existing onboard data processing systems employ a serial execution architecture consisting of a central processing unit, an embedded operating system, and application software. This architecture presents the following prominent problems in the on-orbit environment of space: 1. Insufficient anti-interference capability: Space single-event effects and space ionizing radiation can easily cause abnormal operation of central processing unit programs, software lag, and memory data flipping, which are difficult to repair remotely in on-orbit scenarios and may lead to the interruption of satellite data processing system operation; 2. Insufficient real-time performance: The software's serial execution relies on instruction cycles, resulting in high processing latency for critical operations such as confidence calculation, packet loop detection, cluster election, and wear leveling. This makes it difficult to adapt to the high-speed data processing requirements of inter-satellite links and can easily lead to packet overflow and link congestion. 3. Insufficient security redundancy: The software implementation relies on modifiable instruction code, which is susceptible to silent distortion of space environment data and malicious code injection, and lacks hardware-level security protection capabilities; 4. Low integration: Existing pure hardware solutions can only achieve a single function and cannot cover the complete process of knowledge timeliness management, loop protection, cluster re-return, and cache lifecycle management. Cascading multiple chips leads to an increase in the size, weight, and power consumption of onboard equipment, which does not meet the design requirements of satellite payloads.

[0003] Currently, there is a lack of a space data processing and knowledge management solution that is entirely hardware-based and requires no central processing unit or software involvement, making it difficult to meet the high reliability and real-time on-orbit data processing requirements of deep space exploration and low-Earth orbit constellation networking. Summary of the Invention

[0004] 1. Technical problems to be solved The purpose of this invention is to overcome the above-mentioned shortcomings of the prior art and provide a hardware supplement method, system and circuit for a space data processing and knowledge management system. The entire process is executed through pure hardware circuits, without a central processing unit, instruction execution and software code operation. This solves the problems of insufficient reliability, real-time performance and security of existing solutions in the space environment, while achieving a highly integrated design to adapt to the usage requirements of spaceborne payloads.

[0005] 1. Technical Solution To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a method for space data processing and knowledge management, comprising the following steps: When reading cached knowledge, the current confidence level is calculated based on time decay. Data packets that exceed the hop count or time-to-live limit will be discarded. After the inter-satellite link is restored from an interruption, a master AI node is elected and conflicts are adjudicated according to preset rules. When writing to the cache, the data is accumulated to the minimum write unit and then written all at once, and wear leveling is triggered based on the number of erase and write operations.

[0006] Furthermore, the step of calculating the current confidence level based on time decay includes: adding a preset half-life to each piece of knowledge, calculating the current confidence level based on the difference between the current time and the knowledge cache time and the half-life, and returning an unknown status code when the confidence level is lower than a preset threshold; all processes of the method are automatically executed by pure hardware circuits, without the participation of a central processing unit, instruction execution, or software code execution.

[0007] Furthermore, the preset rule for electing the master AI node is: the one with the latest Earth confirmation timestamp takes priority, and if they are the same, the one with the smaller segment physical identifier takes priority; all processes of the method are automatically executed by pure hardware circuits, without the participation of a central processing unit, without instruction execution, and without software code execution.

[0008] Furthermore, the method also includes: calculating the entropy value of preset bytes before extracting the data frame; if the value exceeds the threshold, it is determined to be low compressibility and compression is skipped; all processes of the method are automatically executed by pure hardware circuits, without the participation of a central processing unit, instruction execution, or software code execution.

[0009] Furthermore, the method also includes: adding a second-level sub-priority to the zero-priority data; sending multiple alarms according to their sub-priority when they exist simultaneously; and automatically aggregating multiple alarms from the same module generated at the same timestamp into a single summary alarm. All processes of the method are automatically executed by pure hardware circuits, without the participation of a central processing unit, instruction execution, or software code execution.

[0010] Furthermore, the method also includes: extracting semantic features to calculate a complete semantic hash and storing it in metadata when caching text knowledge; recalculating the complete semantic hash and comparing it when reading; if the verification passes but the semantic hash does not match, it is determined that the data is silently distorted and discarded; all processes of the method are automatically executed by pure hardware circuits, without the participation of a central processing unit, instruction execution, or software code execution.

[0011] Secondly, the present invention provides a hardware supplementary system for a space data processing and knowledge management system that implements the above-mentioned method, including a knowledge timeliness management circuit, a data packet loop detection circuit, a cluster re-homing circuit, and a cache write management circuit; all processes of the system are automatically executed by pure hardware circuits, without the participation of a central processing unit, without instruction execution, and without software code execution. The knowledge timeliness management circuit is used to calculate the current confidence level based on time decay when reading cached knowledge. The packet loop detection circuit is used to directly discard packets when the number of hops or the lifespan of the data packet exceeds the limit. The cluster re-return circuit is used to elect a master AI node and adjudicate conflicts according to preset rules after the inter-satellite link is restored from an interruption. The cache write management circuit is used to accumulate to the minimum write unit and write it all at once, and trigger wear leveling based on the number of erase and write cycles.

[0012] Furthermore, the data packet loop detection circuit also includes a recent data packet hash table circuit, which is implemented by a content-addressable memory. The recent data packet hash table circuit automatically clears all entries every 24 hours, and outputs a loop drop signal when a new data packet hash matches the table.

[0013] Thirdly, the present invention provides a hardware supplementary circuit for a space data processing and knowledge management system that implements the above method, including a timestamp comparison circuit, a confidence decay calculation circuit, a hop count comparison circuit, a survival time comparison circuit, a cluster election circuit, a write aggregation buffer circuit, and an erase / write count statistics and wear leveling circuit; all processes of the circuit are automatically executed by pure hardware circuits, without the participation of a central processing unit, without instruction execution, and without software code execution. The timestamp comparison circuit is used to calculate the difference between the current time and the knowledge cache time, and output the time difference data. The confidence decay calculation circuit, whose input is connected to the output of the timestamp comparison circuit, consists of a fixed coefficient multiplier and an exponential lookup table, and is used to output the current confidence level based on the time difference and a preset half-life. The hop count comparison circuit and the lifetime comparison circuit have their inputs directly connected to the outputs of the corresponding fields in the data packet header. They are used to compare the hop count of the data packet with the preset maximum hop count and the lifetime with the preset maximum lifetime, respectively. If either exceeds the limit, a discard signal is output. The cluster election circuit has its input directly connected to the output of the last confirmation timestamp register and the physical identifier register, and is used to output the election results of the master AI node according to preset rules. The write aggregation buffer circuit is implemented by a fixed-depth first-in-first-out memory. Its input is connected to the data bus to be written, and it is used to accumulate data to the smallest write unit and then output a one-time write signal. The erase / write count statistics and wear leveling circuit has its input directly connected to the physical block address output of the flash memory chip and the output of the write aggregation buffer circuit. It is used to count the number of erase / write cycles for each physical block and trigger wear leveling when the threshold is exceeded.

[0014] Furthermore, the circuit also includes: The data entropy calculation circuit is connected to the data frame bus at its input end. It is used to extract the preset bytes before the frame to calculate the entropy value. When the threshold is exceeded, it outputs a skip compression signal. The priority zero-level arbitration circuit includes a sub-priority comparator, the input of which is connected to the alarm data bus and is used to output the alarm sending order according to the sub-priority. The alarm aggregation circuit, with its input connected to the alarm data bus, is used to detect multiple associated alarms from the same module generated at the same timestamp and output an aggregated summary. The semantic hash verification circuit consists of a cryptographic hash algorithm hardware accelerator and a hash comparison register. When caching, it calculates the complete semantic hash and stores it in the metadata. When reading, it recalculates the complete semantic hash and compares it. When there is a mismatch, it outputs a silent data distortion and discard signal.

[0015] 1. Beneficial effects Compared with the prior art, the present invention has the following advantages: 1. Effectively improves operational reliability in the space environment: The entire process of this invention is executed by pure hardware circuitry, without a central processing unit, instruction execution, or software code operation. It can avoid problems such as program operation abnormalities, software lag, and data flipping caused by single-event effects and space radiation. The on-orbit fault-free operation time is significantly improved compared with existing software solutions, and it can be adapted to the use scenario of deep space exploration without human intervention.

[0016] 2. Improved real-time data processing: All core operations of this invention are executed in parallel hardware, significantly reducing the processing latency of operations such as confidence calculation, loop detection, cluster election, and wear leveling. This makes it suitable for the line-speed data processing requirements of high-speed inter-satellite links and reduces the risk of packet overflow and link congestion.

[0017] 3. Hardware-level security protection: All execution logic of this invention is solidified through hardware circuits, making it impossible to tamper with or inject malicious code through software. At the same time, semantic hash hardware verification can deal with the problem of silent data distortion in the space environment, which has obvious protection advantages compared with existing software solutions.

[0018] 4. High integration and low power consumption design: This invention integrates the entire process functions such as knowledge timeliness management, loop detection, cluster relocation, and cache lifecycle management into a single chip, eliminating the need for multi-chip cascading. This reduces the size, weight, and power consumption of onboard equipment, meeting the design requirements of satellite payloads.

[0019] 5. Wide range of applicable scenarios: Through its layered design, this invention covers multiple scenarios of onboard data processing, such as data compression pre-detection, alarm classification and aggregation, and data integrity verification. It can be adapted to various aerospace mission scenarios, such as low-Earth orbit constellation networking, deep space exploration, and manned spaceflight. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to specific embodiments. Those skilled in the art can implement the technical solutions of the present invention, solve corresponding technical problems, and achieve the intended technical effects based on the content disclosed in these embodiments.

[0021] All circuits in this embodiment are designed using radiation-resistant complementary metal-oxide-semiconductor (CMOS) technology to meet the total dose radiation and single-event protection requirements of the space on-orbit environment. All circuits are implemented using pure digital logic circuits, without embedded processors, instruction sets, or software code storage and execution units. Example

[0022] This embodiment provides a hardware supplementary system for a space data processing and knowledge management system, including a knowledge timeliness management circuit, a data packet loop detection circuit, a cluster re-homing circuit, and a cache write management circuit; all processes of the system are automatically executed by pure hardware circuits, without the participation of a central processing unit, instruction execution, or software code execution.

[0023] The knowledge timeliness management circuit includes a timestamp comparison circuit and a confidence decay calculation circuit. The timestamp comparison circuit is implemented using a 32-bit hardware subtractor. Its input is directly connected to a 32-bit real-time clock counter driven by a 1MHz radiation-resistant hardware crystal oscillator, and to the output of the cached timestamp register in the knowledge cache metadata. The hardware calculates the difference between the current time and the cached time in real time. The confidence decay calculation circuit consists of a 16-bit fixed-coefficient multiplier and a 16-bit wide-exponential lookup table read-only memory. The preset half-life is 30 days, and the decay coefficient is stored in the read-only memory. After parallel calculation based on the time difference, it outputs a 16-bit confidence value to the threshold comparator. When the confidence level is below the 0.3 threshold, a data discard signal is directly output.

[0024] The packet loop detection circuit includes a hop count comparison circuit, a time-to-live (TTL) comparison circuit, and a recent packet hash table circuit. Both the hop count and TTL comparison circuits are implemented using 8-bit hardware comparators, with their inputs directly connected to the corresponding field outputs of the packet header parsing circuit. The preset maximum hop count is 16 and the maximum TTL is 60 seconds; if either parameter exceeds the limit, a packet drop signal is output directly. The recent packet hash table circuit is implemented using content-addressable memory (CNTM), which automatically clears all entries every 24 hours. When a new packet hash matches this table, a loop drop signal is output.

[0025] The cluster re-homing circuit includes a 32-bit timestamp comparator, an 8-bit identifier comparator, and a parallel priority arbiter. The input is directly connected to the output of the last confirmation timestamp register and physical identifier register of each node. After parallel comparison according to the preset rule of "the latest timestamp takes priority, and if the timestamps are the same, the physical identifier with the smaller value takes priority", the circuit directly outputs the election result of the master AI node and the conflict resolution signal.

[0026] The cache write management circuit includes a write aggregation buffer circuit and an erase / write count and wear leveling circuit. The write aggregation buffer circuit is implemented using a 128-bit, 256-bit synchronous first-in-first-out (FIFO) memory. Its input is connected to the data bus to be written. When the FIFO memory is full, a one-time write trigger signal is directly output to the flash memory controller for the corresponding 4KB minimum write unit. The erase / write count and wear leveling circuit consists of a 32-bit erase / write counter, a threshold comparator, and a physical block address mapping table. Each erase / write operation increments the counter for the corresponding physical block by 1. When the count exceeds the 100,000-time threshold, the hardware automatically triggers address remapping to achieve wear leveling.

[0027] This embodiment also includes a data entropy calculation circuit, a priority zero-level arbitration circuit, an alarm aggregation circuit, and a semantic hash verification circuit. The data entropy calculation circuit is implemented using an 8-bit parallel entropy calculator, extracting the first 128 bytes of the frame to calculate the entropy value; if the threshold is exceeded, a skip compression signal is output. The semantic hash verification circuit is implemented using a fully pipelining cryptographic hash algorithm hardware accelerator and a 256-bit hash comparison register. During caching, the complete semantic hash is calculated and stored in metadata; during retrieval, the complete semantic hash is recalculated and compared; if a mismatch occurs, a data silent distortion and discard signal is output.

[0028] The working process of this embodiment is as follows: 1. When reading cached knowledge, the timestamp comparison circuit calculates the difference between the current time and the cache time, and the confidence decay calculation circuit calculates the current confidence based on the time difference and the preset half-life. If the confidence is lower than 0.3, the knowledge data is directly discarded. 2. When receiving data packets, the hop count comparison circuit and the time-to-live comparison circuit check the hop count and time-to-live respectively, and the packet is discarded directly if either exceeds the limit; the recent data packet hash table checks for loop data packets, and if a match is found, the packet is discarded directly. 3. After the inter-satellite link is restored, the cluster re-entry circuit automatically collects the timestamps and physical identifiers of each node, elects the master AI node according to preset rules, and resolves conflicts. 4. During cache writing, data first enters the write aggregation buffer circuit, accumulates to a minimum write unit of 4KB, and then is written to flash memory all at once; 5. The erase / write count and wear leveling circuit counts the number of erase / write cycles for each physical block in real time, and automatically triggers wear leveling when the count exceeds the threshold of 100,000 cycles. Example

[0029] The difference between this embodiment and Embodiment 1 is that parameters such as the preset half-life, maximum number of hops, maximum survival time, confidence threshold, and erase / write count threshold can all be configured through a one-time programmable fuse array before the chip leaves the factory. Once configured, it cannot be modified by software and can be adapted to different exploration missions and deep space exploration scenarios of different cycles.

Claims

1. A method for space data processing and knowledge management, characterized in that, Includes the following steps: When reading cached knowledge, the current confidence level is calculated based on time decay. Data packets that exceed the hop count or time-to-live limit will be discarded. After the inter-satellite link is restored from an interruption, a master AI node is elected and conflicts are adjudicated according to preset rules. When writing to the cache, the data is accumulated to the minimum write unit and then written all at once, and wear leveling is triggered based on the number of erase and write operations.

2. A hardware supplement system for a space data processing and knowledge management system, characterized in that, It includes a knowledge timeliness management circuit, a data packet loop detection circuit, a cluster re-homing circuit, and a cache write management circuit; all processes of the system are automatically executed by pure hardware circuits, without the participation of a central processing unit, instruction execution, or software code execution; The knowledge timeliness management circuit is used to calculate the current confidence level based on time decay when reading cached knowledge. The packet loop detection circuit is used to directly discard packets when the number of hops or the lifespan of the data packet exceeds the limit. The cluster re-return circuit is used to elect a master AI node and adjudicate conflicts according to preset rules after the inter-satellite link is restored from an interruption. The cache write management circuit is used to accumulate to the minimum write unit and write it all at once, and trigger wear leveling based on the number of erase and write cycles.

3. A hardware supplementary circuit for a space data processing and knowledge management system, characterized in that, It includes a timestamp comparison circuit, a confidence decay calculation circuit, a hop count comparison circuit, a lifetime comparison circuit, a cluster election circuit, a write aggregation buffer circuit, and an erase / write count statistics and wear leveling circuit; all processes of the circuit are automatically executed by pure hardware circuits, without the participation of a central processing unit, instruction execution, or software code execution; The timestamp comparison circuit is used to calculate the difference between the current time and the knowledge cache time, and output the time difference data. The confidence decay calculation circuit, whose input is connected to the output of the timestamp comparison circuit, consists of a fixed coefficient multiplier and an exponential lookup table, and is used to output the current confidence level based on the time difference and a preset half-life. The hop count comparison circuit and the lifetime comparison circuit have their inputs directly connected to the outputs of the corresponding fields in the data packet header. They are used to compare the hop count of the data packet with the preset maximum hop count and the lifetime with the preset maximum lifetime, respectively. If either exceeds the limit, a discard signal is output. The cluster election circuit has its input directly connected to the output of the last confirmation timestamp register and the physical identifier register, and is used to output the election results of the master AI node according to preset rules. The write aggregation buffer circuit is implemented by a fixed-depth first-in-first-out memory. Its input is connected to the data bus to be written, and it is used to accumulate data to the smallest write unit and then output a one-time write signal. The erase / write count statistics and wear leveling circuit has its input directly connected to the physical block address output of the flash memory chip and the output of the write aggregation buffer circuit. It is used to count the number of erase / write cycles for each physical block and trigger wear leveling when the threshold is exceeded.

4. The method according to claim 1, characterized in that, The calculation of the current confidence level based on time decay includes: adding a preset half-life to each piece of knowledge, calculating the current confidence level based on the difference between the current time and the knowledge cache time and the half-life, and returning an unknown status code when the confidence level is lower than a preset threshold; all processes of the method are automatically executed by pure hardware circuits, without the participation of a central processing unit, instruction execution, or software code execution.

5. The method according to claim 1, characterized in that, The preset rule for electing the master AI node is: the one with the latest Earth confirmation timestamp takes priority, and if they are the same, the one with the smaller physical identifier of the module takes priority; all processes of the method are automatically executed by pure hardware circuits, without the participation of a central processing unit, without instruction execution, and without software code execution.

6. The method according to claim 1, characterized in that, The method further includes: calculating the entropy value of preset bytes before extracting the data frame; if the value exceeds the threshold, it is determined to be low compressibility and compression is skipped; all processes of the method are automatically executed by pure hardware circuits, without the participation of a central processing unit, instruction execution, or software code execution.

7. The method according to claim 1, characterized in that, The method further includes: adding a second-level sub-priority to the zero-priority data; sending multiple alarms according to their sub-priority when they exist simultaneously; and automatically aggregating multiple alarms from the same module generated at the same timestamp into a single summary alarm. All processes of the method are automatically executed by pure hardware circuits, without the participation of a central processing unit, instruction execution, or software code execution.

8. The method according to claim 1, characterized in that, The method further includes: extracting semantic features when caching text knowledge, calculating the complete semantic hash and storing it in metadata; recalculating the complete semantic hash and comparing it when reading; if the verification passes but the semantic hash does not match, it is determined that the data is silently distorted and discarded; all processes of the method are automatically executed by pure hardware circuits, without the participation of a central processing unit, without instruction execution, and without software code execution.

9. The system according to claim 2, characterized in that, The packet loop detection circuit also includes a recent packet hash table circuit, which is implemented by a content-addressable memory. It automatically clears all entries every 24 hours and outputs a loop drop signal when a new packet hash matches the table.

10. The circuit according to claim 3, characterized in that, Also includes: The data entropy calculation circuit is connected to the data frame bus at its input end. It is used to extract the preset bytes before the frame to calculate the entropy value. When the threshold is exceeded, it outputs a skip compression signal. The priority zero-level arbitration circuit includes a sub-priority comparator, the input of which is connected to the alarm data bus and is used to output the alarm sending order according to the sub-priority. The alarm aggregation circuit, with its input connected to the alarm data bus, is used to detect multiple associated alarms from the same module generated at the same timestamp and output an aggregated summary. The semantic hash verification circuit consists of a cryptographic hash algorithm hardware accelerator and a hash comparison register. When caching, it calculates the complete semantic hash and stores it in the metadata. When reading, it recalculates the complete semantic hash and compares it. When there is a mismatch, it outputs a silent data distortion and discard signal.