A data exchange device for network interface devices and SRIO interface devices
The data exchange device, composed of a main chip and a network switching chip, solves the problem that traditional SRIO switching chips cannot meet the data exchange needs between different devices. It enables flexible data exchange between network interface devices and SRIO interface devices, supports the access of any number of devices, and broadens the application scope.
Patent Information
- Application Number
- CN202610634683.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-09
- Publication Date
- 2026-08-25
AI Technical Summary
Traditional SRIO high-speed serial port switching chips cannot meet the flexible data exchange requirements between network interface devices and SRIO interface devices. Existing technologies cannot achieve data interoperability between devices without high-speed RapidIO interface devices and devices without network interface devices.
The data switching device consists of a main chip and a network switching chip. The main chip integrates a processor system and programmable logic, interacts with the AXI bus to realize gigabit network switching function of the network port, and forms an SRIO switching network through the programmable logic. It supports custom RapidIO interface protocol, dynamically configures switching nodes, and uses Nwrite+Doorbell for data transmission.
It enables flexible data exchange between network interface devices and SRIO interface devices, supports the access of any number of devices, broadens the application scope of data exchange devices, and meets the data interoperability needs between different devices.
Smart Images
Figure CN122633630A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic circuit design technology, and in particular to a data exchange device for network interface devices and SRIO interface devices. Background Technology
[0002] Traditional SRIO high-speed serial port switching is implemented using dedicated SRIO switching chips such as TSI578. TSI578 is a dedicated SRIO switching chip that uses the standard SRIO protocol and supports 1X and 4X modes. In conventional designs, multiple devices are connected to a single switching chip to achieve data interaction between the devices. Network switching, on the other hand, is implemented using network switching chips, and its usage is relatively fixed.
[0003] With the development of electronic circuit technology, the demand for data exchange is increasing. Traditional fixed-use data exchange chips can no longer meet the data exchange needs between various devices. Therefore, there is an urgent need to invent a data exchange device that can be used for both network interface devices and SRIO interface devices to meet the data interoperability between devices without high-speed RapidIO interface devices and devices without network interface devices, and to achieve more flexible data exchange functions. Summary of the Invention
[0004] The purpose of this invention is to provide a data exchange device that can be used for data exchange between network interface devices and SRIO interface devices simultaneously, to meet the data interoperability between devices without high-speed RapidIO interface devices and devices without network interface devices, and to realize more flexible data exchange functions.
[0005] The technical solution to achieve the purpose of this invention is: a data exchange device for network interface devices and SRIO interface devices, comprising a main chip and a network switching chip;
[0006] The main chip integrates a processor system (PS) and programmable logic (PL). The processor system (PS) is connected to a network switching chip to enable data communication between external terminals with network interfaces. The programmable logic (PL) forms an SRIO switching network to enable physical SRIO communication between the main chips and data communication between external terminals with RapidIO high-speed serial ports.
[0007] The network switching chip is used to implement gigabit network switching function of the network port.
[0008] Furthermore, the main chip is an FMQL45T900 chip, and the network switching chip is an SF2507 chip.
[0009] Furthermore, the data exchange device for network interface devices and SRIO interface devices consists of n network switching chips and n main chips. The n network switching chips form a network switching matrix, and the SRIO switching network of the n main chips forms an SRIO switching matrix; n≥2.
[0010] Furthermore, the MQL45T900 chip provides 16 high-speed transceiver channels in 1X mode, and the processor system PS and programmable logic PL interact via the AXI bus.
[0011] Furthermore, the operating system runs on the PS side of the processor system and loads applications. By configuring the parameters of the SRIO switching network and network switching chip on the PL side of the programmable logic, the following usage modes are achieved:
[0012] (1) External terminals with network interfaces are connected to a network switching matrix composed of n SF2507 chips, enabling data exchange between external terminals through the network interface;
[0013] (2) External terminals equipped with RapidIO high-speed serial ports are connected to an SRIO switching matrix composed of n SRIO switching networks, and data communication between external terminals is achieved through ID numbers;
[0014] (3) Data communication between external terminals with network interfaces but no high-speed RapidIO interfaces and external terminals without network interfaces but with high-speed RapidIO interfaces is achieved.
[0015] When using mode (1) and mode (2), after configuring the switching parameters through the application software of the processor system PS, the external terminal directly realizes data interaction through the network switching chip or SRIO switching network.
[0016] When using mode (3), after obtaining data from the external terminal through the processor system PS, the data format and protocol are converted, and then the data is sent to the programmable logic PL through the AXI bus. The programmable logic PL then sends the data to the corresponding external terminal through the SRIO switching network.
[0017] Furthermore, the SRIO switching network can dynamically configure the switching nodes in the network. The switching nodes connected to the SRIO switching matrix all adopt a custom RapidIO interface protocol and use the Nwrite+Doorbell method for data transmission. The user rate of a single node reaches 1Gbps. All switching nodes are configured with a fixed physical ID according to the hardware device connection relationship, and the port user ID is dynamically configured to match the source ID of each node.
[0018] Furthermore, the SRIO switching network adopts the RapidIO protocol, and all data transmitted in the SRIO switching network includes the destination user ID and the source user ID.
[0019] Furthermore, after receiving a data packet, the node in the SRIO switching matrix first stores the data packet in the buffer corresponding to that node and waits for forwarding; then it parses out the destination user ID and sends it to the corresponding physical RapidIO interface according to the corresponding user ID.
[0020] Furthermore, each network switching chip and SRIO switching network uses a unique ID number. When an external terminal mounted on each network switching chip or SRIO switching network needs to send data to an external terminal not on this network switching chip or SRIO switching network, the switching matrix algorithm transmits the data to other network switching chips or SRIO switching networks based on the destination ID. Once the network switching chip or SRIO switching network recognizes the ID within its own ID range, it sends the data to the corresponding terminal.
[0021] Furthermore, the data exchange device, by cascading multiple main chips and network switching chips and using the SRIO switching matrix algorithm, enables access to any number of services even when interrupted.
[0022] Compared with the prior art, the present invention has the following significant advantages: (1) It adopts the SRIO soft switch method and customizes the RapidIO communication protocol according to the application requirements, realizing data interaction between network interface devices and SRIO interface devices, and achieving greater flexibility; (2) By using multiple boards to cascade and in conjunction with the SRIO switching matrix algorithm, any number of devices can be connected, thus broadening the application scope of the data switching device. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of the structure of the data exchange device of the present invention for network interface devices and SRIO interface devices.
[0024] Figure 2 This is a schematic diagram of the SRIO exchange matrix in this invention. Detailed Implementation
[0025] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0026] like Figure 1 As shown, the present invention provides a data exchange device for network interface devices and SRIO interface devices, comprising a main chip and a network switching chip.
[0027] The main chip is an FMQL45T900 chip, which integrates a processor system (PS) and programmable logic (PL). The processor system (PS) is connected to a network switching chip to enable data communication between external terminals with network interfaces. The programmable logic (PL) forms an SRIO switching network to enable physical SRIO communication between the main chips and data communication between external terminals with RapidIO high-speed serial ports.
[0028] The network switching chip uses the SF2507 chip to implement gigabit network switching function of the network port.
[0029] As a specific example, such as Figure 2 As shown, the data exchange device consists of n network switching chips and n main chips. The n network switching chips form a network switching matrix, and the SRIO switching network of the n main chips forms an SRIO switching matrix.
[0030] As a specific example, the MQL45T900 chip can provide 16 high-speed transceiver channels in 1X mode. The chip integrates a processor system (PS) and programmable logic (PL), and the processor system (PS) and programmable logic (PL) interact with each other via an AXI bus.
[0031] As a specific example, the processor system's PS side runs an operating system that loads applications. By configuring the parameters of the programmable logic PL side SRIO switching network and the network switching chip SF2507, the following usage modes can be achieved:
[0032] (1) Service terminals with network interfaces are connected to a network switching matrix composed of n SF2507s, enabling data exchange between service terminals through the network interface;
[0033] (2) Service terminals equipped with RapidIO high-speed serial ports are connected to an SRIO switching matrix composed of n SRIO switching networks, and data communication between service terminals is realized through ID numbers;
[0034] (3) Data communication between service terminals with network interfaces but no high-speed RapidIO interfaces and service terminals without network interfaces but with high-speed RapidIO interfaces is achieved.
[0035] In usage modes (1) and (2), after configuring the switching parameters through the PS application software, the service terminal can directly achieve data interaction through the network switching chip or the SRIO switching network. In usage mode (3), after obtaining the data from the service terminal through the PS end, the data format and protocol are converted, and then the data is sent to the PL end through the AXI bus. The PL end sends the data to the corresponding service terminal through the SRIO switching network.
[0036] As a specific example, the SRIO switching network can dynamically configure the switching nodes in the network. The switching nodes connected to the SRIO switching matrix all adopt a custom RapidIO interface protocol and use the Nwrite+Doorbell method for data transmission. The user rate of a single node can reach 1Gbps. All switching nodes are configured with a fixed physical ID according to the hardware device connection relationship, and the port user ID is dynamically configured to match the source ID of each node.
[0037] As a specific example, the SRIO switching network uses the RapidIO protocol, and all data transmitted in this network includes the destination user ID and the source user ID.
[0038] As a specific example, after receiving a data packet, a node in the SRIO switching matrix first stores the data packet in the buffer corresponding to that node and waits for forwarding; then it parses out the destination user ID and sends it to the corresponding physical RapidIO interface according to the corresponding user ID.
[0039] As a specific example, to ensure that there are no ID conflicts between service terminals connected to the data exchange device, each network switching chip and SRIO switching network uses a unique ID number. When a service terminal mounted on each network switching chip or SRIO switching network needs to send data to a service terminal not on its own network switching chip or SRIO switching network, the switching matrix algorithm transmits the data to other network switching chips or SRIO switching networks according to the destination ID. Once the network switching chip or SRIO switching network recognizes the ID within its own ID range, it sends the data to the corresponding terminal.
[0040] As a specific example, the data exchange device can achieve access for any number of services interrupted by cascading multiple main chips and network switching chips and using the SRIO switching matrix algorithm.
[0041] Example
[0042] 1. Overall framework design
[0043] This design uses the FMQL45T900 as the main chip. Each chip provides 16 sets of 1X interfaces, which interact via an AXI bus. The PS end connects to an external network switching chip, the SF2507, which interconnects with each other via Ethernet ports. Each SF2507 provides three Gigabit network interfaces, enabling 3*n port Gigabit network switching functionality. The PL ends of the FMQL45T900 chips on each board are interconnected via high-speed differential ports, achieving physical SRIO interoperability between the chips. The remaining ports connect to optical modules, which, theoretically, can connect to 3*n external terminals via fiber optic connections. The overall connection diagram is shown below. Figure 1 As shown.
[0044] The operating system on the PS side loads an application that allows for parameter configuration of the SRIO switching matrix and the SF2507 network switching chip on the PL side. The application on the PS side enables the following usage modes:
[0045] 1) Supports external terminals with network interfaces to connect to the network switching matrix composed of SF2507s, enabling data exchange between terminals via network ports;
[0046] 2) Supports service terminals with RapidIO high-speed serial ports to connect to the SRIO switching matrix, and enables data communication between service terminals through ID numbers;
[0047] 3) Supports data communication between devices with network interfaces but no high-speed RapidIO interfaces and devices without network interfaces but with high-speed RapidIO interfaces.
[0048] In usage modes 1) and 2), after configuring the exchange parameters through the PS application software, external terminals can directly exchange data via network or SRIO. In usage mode 3), the PS obtains data from the external terminal, converts the data format and protocol, and then sends the data to the PL via the AXI bus. The PL then sends the data to the corresponding terminal via SRIO softswitch.
[0049] 2. SRIO Switching Matrix Design
[0050] SRIO softswitches can dynamically configure switching nodes in the network. All switching nodes connected to the switching matrix use a custom RapidIO interface protocol and employ Nwrite+Doorbell for data transmission, achieving a user rate of up to 1Gbps per node. Each switching node is configured with a fixed physical ID based on its hardware connection relationship, and the port user ID is dynamically configured to match the source ID of each node. Based on the RapidIO protocol, all data packets transmitted in this network contain both the destination user ID and the source user ID according to the protocol format.
[0051] like Figure 2 As shown, the switching network contains several switching matrices, which provide communication pathways between any nodes. Data received by any node can be sent out from other ends based on the destination ID. After receiving a data packet, each node parses out the destination user ID, then uses the corresponding physical ID to go to the appropriate physical RapidIO interface. The data is stored in the corresponding buffer of that node, waiting for forwarding.
[0052] To ensure no ID conflicts in the entire switching network, each switching matrix uses a different ID number. The switching matrix algorithm fully considers the data interaction between different switching matrices. When a terminal mounted on a switching matrix needs to send data to a device not mounted on that switching matrix, the switching matrix algorithm transmits the data to other switching matrices level by level according to the destination ID. Once the switching matrix recognizes the ID within the range of IDs contained in the switching matrix, it sends the data to the corresponding terminal.
[0053] In summary, the data switching device integrating network switching and SRIO switching provided by this invention uses the SF2057 chip for network switching and FPGA software for SRIO switching. The switching channel can be expanded by cascading multiple boards, making it more widely applicable. The software on the PS end can flexibly perform protocol conversion to realize data interaction between network interface devices and SRIO interface devices, making the switching function design more flexible.
[0054] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A data exchange apparatus for network interface devices and SRIO interface devices, characterized in that, Including main chip and network switching chip; The main chip integrates a processor system (PS) and programmable logic (PL). The processor system (PS) is connected to a network switching chip to enable data communication between external terminals with network interfaces. The programmable logic (PL) forms an SRIO switching network to enable physical SRIO communication between the main chips and data communication between external terminals with RapidIO high-speed serial ports. The network switching chip is used to implement gigabit network switching function of the network port.
2. The data exchange apparatus for network interface devices and SRIO interface devices according to claim 1, characterized in that, The main chip is the FMQL45T900 chip, and the network switching chip is the SF2507 chip.
3. The data exchange apparatus for network interface devices and SRIO interface devices according to claim 1, characterized in that, The device consists of n network switching chips and n main chips. The n network switching chips form a network switching matrix, and the SRIO switching network of the n main chips forms an SRIO switching matrix; n≥2.
4. The data exchange apparatus for network interface devices and SRIO interface devices according to claim 2, characterized in that, The MQL45T900 chip provides 16 high-speed transceiver channels in 1X mode, and the processor system PS and programmable logic PL interact via the AXI bus.
5. The data exchange apparatus for network interface devices and SRIO interface devices according to claim 4, characterized in that, The operating system runs on the PS side of the processor system and loads applications. By configuring the parameters of the SRIO switching network and network switching chip on the PL side of the programmable logic, the following usage modes can be achieved: (1) External terminals with network interfaces are connected to a network switching matrix composed of n SF2507 chips, enabling data exchange between external terminals through the network interface; (2) External terminals equipped with RapidIO high-speed serial ports are connected to an SRIO switching matrix composed of n SRIO switching networks, and data communication between external terminals is achieved through ID numbers; (3) Data communication between external terminals with network interfaces but no high-speed RapidIO interfaces and external terminals without network interfaces but with high-speed RapidIO interfaces is achieved. When using mode (1) and mode (2), after configuring the switching parameters through the application software of the processor system PS, the external terminal directly realizes data interaction through the network switching chip or SRIO switching network. When using mode (3), after obtaining data from the external terminal through the processor system PS, the data format and protocol are converted, and then the data is sent to the programmable logic PL through the AXI bus. The programmable logic PL then sends the data to the corresponding external terminal through the SRIO switching network.
6. The data exchange apparatus for network interface devices and SRIO interface devices according to claim 3, characterized in that, The SRIO switching network can dynamically configure the switching nodes in the network. The switching nodes connected to the SRIO switching matrix all adopt a custom RapidIO interface protocol and use Nwrite+Doorbell for data transmission. The user rate of a single node reaches 1Gbps. All switching nodes are configured with a fixed physical ID according to the hardware device connection relationship, and the port user ID is dynamically configured to match the source ID of each node.
7. The data exchange apparatus for network interface devices and SRIO interface devices according to claim 6, characterized in that, The SRIO switching network uses the RapidIO protocol, and all data transmitted in the SRIO switching network includes the destination user ID and the source user ID.
8. The data exchange apparatus for network interface devices and SRIO interface devices according to claim 7, characterized in that, After receiving a data packet, the node in the SRIO switching matrix first stores the data packet in the buffer corresponding to the node and waits for forwarding; then it parses out the destination user ID and sends it to the corresponding physical RapidIO interface according to the corresponding user ID.
9. The data exchange apparatus for network interface devices and SRIO interface devices according to claim 8, characterized in that, Each network switching chip and SRIO switching network uses a unique ID number. When an external terminal connected to each network switching chip or SRIO switching network needs to send data to an external terminal not on this network switching chip or SRIO switching network, the switching matrix algorithm transmits the data to other network switching chips or SRIO switching networks based on the destination ID. Once the network switching chip or SRIO switching network recognizes the ID within the ID range contained in its own network switching chip or SRIO switching network, it sends the data to the corresponding terminal.
10. The data exchange apparatus for network interface devices and SRIO interface devices according to claim 9, characterized in that, The data exchange device uses multiple main chips and network switching chips cascaded together, along with the SRIO switching matrix algorithm, to enable access to any number of services even during interruptions.