Rapidio link configuration systems, methods, and media

Abstract

The application discloses a RapidIO link configuration system, method and medium, and belongs to the field of spaceflight TT&C (Tracking, Telemetry and Command), and comprises the following steps: firstly, a central node configures the routing between any two nodes connected through a RapidIO switching network; and secondly, a FPGA receiving node configures the link of a communication node related to the FPGA receiving node and the link of the FPGA receiving node itself. The application provides a simple and reliable RapidIO link configuration scheme with high flexibility and capable of reducing the coupling relationship between the central node and the leaf node.

Description

Technical Field

[0001] This invention relates to the field of aerospace telemetry and control technology, and more specifically, to a RapidIO link configuration system, method, and medium. Background Technology

[0002] With the rapid development of the aerospace industry, aerospace telemetry, tracking, and command (TT&C) has gradually expanded from single networks to multi-networked systems, from ground-based to space-based systems, and from single-satellite TT&C to multi-satellite combined TT&C. Aerospace TT&C has evolved from its original single-function approach to an increasingly complex one, combining multiple functions and services, thus placing higher demands on efficient data processing. The real-time acquisition, distribution, and processing of data in TT&C systems place increasingly higher demands on the transmission rate, reliability, and real-time performance of interconnect buses between devices and chips. Traditional parallel buses for data transmission are no longer sufficient to meet the demands of large-capacity data transmission. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a RapidIO link configuration system, method, and medium. Without increasing software complexity, this invention solves the problems of high maintenance costs and low reliability caused by the centralized node pre-configuration of communication links in existing measurement and control systems. It effectively reduces the strong coupling between the central node and leaf nodes, improving the system's integration efficiency and reliability.

[0004] The objective of this invention is achieved through the following solution:

[0005] A RapidIO link configuration system includes a central node, communication nodes, a RapidIO switching network, and receiving nodes. The central node, communication nodes, and receiving nodes are connected to the RapidIO switching network. The central node configures the routing between any two nodes interconnected through the RapidIO switching network. The receiving nodes configure the links with their associated communication nodes. After receiving one or more channel communication link configuration information input by the user, the receiving nodes send it through a RapidIO port. The configuration information sent by the receiving nodes through the RapidIO port is processed in two ways: first, configuring the channel link configuration information of the FPGA receiving node itself, which is routed back to the receiving node through the RapidIO switching network; second, configuring the link configuration information of the peer node communicating with the receiving node, which is routed to the communication node through the RapidIO switching network.

[0006] Furthermore, the receiving node includes an FPGA receiving node; the central node is of type PPC; the number of communication nodes is N, where N is an integer greater than or equal to 1, and the communication nodes include any one or more of FPGA, DSP, and PPC types.

[0007] Furthermore, the central node is connected to the RapidIO switching network through one 4X or 1X RapidIO port; communication nodes 1 to N are each connected to the RapidIO switching network through one 4X or 1X RapidIO port; the FPGA receiving node is connected to the RapidIO switching network through one 4X RapidIO port; the chips in the RapidIO switching network include those using CPS1848 chips.

[0008] Furthermore, when the receiving node is an FPGA receiving node, and the FPGA receiving node includes a RapidIO IPcore, a channel user configuration information sending module, M channel user configuration information receiving modules, a channel link configuration information receiving module, and X channel link configuration information receiving and parsing modules, where M and X are both integers greater than or equal to 1.

[0009] A RapidIO link configuration method, based on the RapidIO link configuration system described above, further includes the following steps:

[0010] First, the FPGA receiving node receives user channel configuration information Ch1_User_Cfg_info~ChM_User_Cfg_info and writes it into the corresponding channel user configuration information receiving module 1~M. After being processed by the channel user configuration information sending module, it forms link configuration sending information User_Cfg_info_data, which is sent to the RapidIO switching network through the RapidIO IP core and routed to the relevant communication nodes.

[0011] Secondly, the FPGA receiving node receives data from the RapidIO switching network, converts it into RapidIO data packets (RapidIO_Data) through the RapidIO IP core, and after being processed by the channel link configuration information receiving module, it is distributed to the channel link configuration information receiving and parsing modules 1 to X to parse out the corresponding channel link configuration information (Ch1_Link_Cfg_info to ChX_Link_Cfg_info).

[0012] Furthermore, the configuration information sent by the FPGA receiving node through the RapidIO port is handled in two ways: firstly, the channel link configuration information of the FPGA receiving node itself is configured and looped back to the FPGA receiving node via the RapidIO switching network; secondly, the link configuration information of the peer node communicating with the FPGA receiving node is configured and routed to communication nodes 1 to N via the RapidIO switching network.

[0013] Furthermore, in the FPGA receiving node, the channel user configuration information transmission process enters the initial state after power-on reset;

[0014] The system monitors whether the empty flag of the user configuration information packet-level FIFO is valid. If it is valid, it means that the user configuration information of a single channel has not been fully received. If it is invalid, it means that the user configuration information of one or more channels in the user configuration information packet-level FIFO has been fully received, and the process is transferred to the target end RapidIO ID extraction process.

[0015] After the RapidIO ID extraction process is completed at the target end, the process proceeds to the current channel configuration information packet assembly process. After the current channel configuration information packet assembly process is completed, the information is sent to the RapidIO switching network via the RapidIO IP core sending port and returns to the initial state.

[0016] Furthermore, in the FPGA receiving node, the channel link configuration information receiving and processing flow enters the initial state after power-on reset;

[0017] Monitor whether the RapidIO data packet received by the RapidIO IP core is a link configuration information data packet; if so, enter the channel address field parsing process, and distribute the link configuration information data packet to the corresponding channel link configuration information receiving and parsing module 1 to X according to the preset value of each channel address segment, and return to the initial state.

[0018] Furthermore, it monitors whether the RapidIO data packet received by the RapidIO IP core is a link configuration information data packet; if not, it does not process the received RapidIO data packet and returns the status of monitoring whether the RapidIO data packet is a link configuration information data packet.

[0019] A computer-readable storage medium storing a computer program therein, the computer program being loaded by a processor and executing the method as described in any of the preceding claims.

[0020] The beneficial effects of this invention include:

[0021] (1) This invention reduces manpower maintenance costs and improves system integration efficiency. This invention configures one or more channel links between the FPGA receiving node and its communicating leaf nodes by configuring channel link information on the FPGA receiving node. In the system, adding or removing leaf nodes, or adding or removing links between one or more leaf nodes, does not require re-organizing all link configuration information in the system; it only requires updating the configuration information of the FPGA receiving node and its communicating leaf nodes.

[0022] (2) This invention reduces the strong coupling between the central node and the leaf nodes, thus improving the system's reliability. This invention replaces the original design's method of pre-configuring the central node's links by configuring the FPGA receiving node with the communication link information of each leaf node. The centralized node is no longer responsible for channel link configuration, and a failure of the centralized node will not affect the function of configuring the links between the FPGA receiving node and its communicating leaf nodes. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the RapidIO link configuration method according to an embodiment of the present invention;

[0025] Figure 2 for Figure 1 The implementation principle diagram;

[0026] Figure 3 for Figure 2 Flowchart of channel user configuration information sending and processing;

[0027] Figure 4 for Figure 2 The flowchart for receiving and processing channel link configuration information. Detailed Implementation

[0028] All features disclosed in all embodiments of this specification, or steps in all methods or processes implied in the disclosure, may be combined and / or extended or replaced in any way, except for mutually exclusive features and / or steps.

[0029] In light of the problems mentioned in the background, the inventors of this invention, after creative analysis and consideration, believe that the serial RapidIO bus based on a packet-switched architecture, with its high bandwidth, low latency, and high reliability, provides a good solution for high-speed interconnection between multiple devices and chips within a telemetry and control system. In recent years, Field-Programmable Gate Arrays (FPGAs), with their excellent real-time performance and parallel processing capabilities, have gradually become the mainstream configuration chip for hardware platforms in the aerospace telemetry and control field. The hardware architecture in these systems often adopts combinations such as FPGA+DSP, FPGA+PPC, and FPGA+FPGA. Multiple nodes within the system are interconnected via a serial RapidIO bus, forming a large, heterogeneous node RapidIO switching network. Each communication node completes the reception, distribution, and processing of data and instructions by constructing one or more communication link channels. Typically, a central node is responsible for the routing, link configuration, dynamic network entry, and traffic monitoring of all leaf nodes in the entire system. This centralized management approach is very convenient when the system is small, as the central node can clearly know the information of all leaf nodes. However, the inventors of this invention have discovered the following technical problem: as the system scale increases, the drawbacks become increasingly apparent. On the one hand, the number of communication links between communication nodes increases exponentially with the scale of the system; pre-compiling a channel pre-configuration table by identifying all communication links between nodes becomes increasingly labor-intensive. On the other hand, as the number of nodes in the system changes dynamically, the information in the channel pre-configuration table also changes constantly, making manual compilation inefficient. Furthermore, a failure of the central node could potentially paralyze the entire system.

[0030] To address the aforementioned technical problems, this invention provides a RapidIO link configuration scheme. For example... Figure 1 As shown, in a specific implementation, a RapidIO link configuration method is provided, comprising: a central node (PPC type) + communication nodes 1 to N (any type of FPGA / DSP / PPC) + a RapidIO switching network + a receiving node (FPGA type). The central node in the system connects to the RapidIO switching network through one 4X RapidIO port; communication nodes 1 to N each connect to the RapidIO switching network through one 4X RapidIO port; the FPGA receiving node connects to the RapidIO switching network through one 4X RapidIO port; the chips in the RapidIO switching network use CPS1848 or equivalent domestically produced switching devices.

[0031] like Figure 2As shown, the FPGA receiving node is implemented using a software architecture consisting of RapidIO IP core + channel user configuration information sending module + channel user configuration information receiving module (1~M) + channel link configuration information receiving module + channel link configuration information receiving and parsing module (1~X).

[0032] Figure 2 First, the FPGA receiving node receives user channel configuration information Ch1_User_Cfg_info to ChM_User_Cfg_info and writes it into the corresponding channel user configuration information receiving module (1 to M). After processing by the channel user configuration information sending module, it forms link configuration sending information (User_Cfg_info_data) and sends it to the RapidIO switching network through the RapidIO IP core, where it is routed to the relevant communication nodes. Second, the FPGA receiving node receives data from the RapidIO switching network, converts it into RapidIO data packets (RapidIO_Data) through the RapidIO IP core, processes it through the channel link configuration information receiving module, and distributes it to the channel link configuration information receiving and parsing module (1 to X) to parse out the corresponding channel link configuration information Ch1_Link_Cfg_info to ChX_Link_Cfg_info.

[0033] Figure 2 In this process, the configuration information sent by the FPGA receiving node through the RapidIO port is divided into two cases. The first is to configure the channel link configuration information of the FPGA receiving node itself, which is routed back to the FPGA receiving node through the RapidIO switching network. The second is to configure the link configuration information of the peer node communicating with the FPGA receiving node, which is routed to communication nodes 1 to N through the RapidIO switching network.

[0034] like Figure 3 As shown, the channel user configuration information transmission process in the FPGA receiving node enters the initial state after power-on reset. It monitors the validity of the empty flag in the channel user configuration information packet-level FIFO. If valid, it indicates that the user configuration information for a single channel has not been fully received; if invalid, it indicates that the user configuration information for one or more channels in the user configuration information packet-level FIFO has been fully received, and the process proceeds to the target-side RapidIO ID extraction process. After the target-side RapidIO ID extraction process is completed, the process proceeds to the current channel configuration information packet assembly process. After the current channel configuration information packet assembly process is completed, it is sent to the RapidIO switching network via the RapidIO IPcore transmission port and returns to the initial state.

[0035] like Figure 4As shown, the channel link configuration information receiving and processing flow in the FPGA receiving node enters the initial state after power-on reset. It monitors whether the RapidIO data packet received by the RapidIO IP core is a link configuration information data packet; if so, it enters the channel address field parsing process, and distributes the link configuration information data packet to the corresponding channel link configuration information receiving and parsing module (1~X) according to the preset value of each channel address segment, and returns to the initial state.

[0036] It should be noted that, within the scope of protection defined in the claims of this invention, the following embodiments can be combined and / or extended or replaced in any logical manner from the above specific embodiments, such as the disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0037] Example 1

[0038] A RapidIO link configuration system includes a central node, a communication node, a RapidIO switching network, and a receiving node, wherein the central node, the communication node, and the receiving node are connected to the RapidIO switching network;

[0039] The central node configures the routing between any two nodes interconnected by the RapidIO switching network in the system; the receiving node configures the links with its related communication nodes; after receiving one or more channel communication link configuration information input by the user, the receiving node sends it through the RapidIO port.

[0040] The configuration information sent by the receiving node through the RapidIO port is divided into two cases: one is to configure the channel link configuration information of the FPGA receiving node itself, which is routed back to the receiving node through the RapidIO switching network; the other is to configure the link configuration information of the peer node communicating with the receiving node, which is routed to the communication node through the RapidIO switching network.

[0041] Example 2

[0042] Based on Embodiment 1, the receiving node includes an FPGA receiving node; the central node is of type PPC; the number of communication nodes is N, where N is an integer greater than or equal to 1, and the communication nodes include any one or more of FPGA, DSP, and PPC types.

[0043] Example 3

[0044] Based on Example 2, the central node is connected to the RapidIO switching network through one 4X or 1X RapidIO port; communication nodes 1 to N are each connected to the RapidIO switching network through one 4X or 1X RapidIO port; the FPGA receiving node is connected to the RapidIO switching network through one 4X RapidIO port; the chips in the RapidIO switching network include those using CPS1848 chips.

[0045] Example 4

[0046] Based on Example 1, when the receiving node is an FPGA receiving node, and the FPGA receiving node includes a RapidIO IP core, a channel user configuration information sending module, M channel user configuration information receiving modules, a channel link configuration information receiving module, and X channel link configuration information receiving and parsing modules, where M and X are both integers greater than or equal to 1.

[0047] Example 5

[0048] A RapidIO link configuration method, based on the RapidIO link configuration system described in Embodiment 4, further includes the following steps:

[0049] First, the FPGA receiving node receives user channel configuration information Ch1_User_Cfg_info~ChM_User_Cfg_info and writes it into the corresponding channel user configuration information receiving module 1~M. After being processed by the channel user configuration information sending module, it forms link configuration sending information User_Cfg_info_data, which is sent to the RapidIO switching network through the RapidIO IP core and routed to the relevant communication nodes.

[0050] Secondly, the FPGA receiving node receives data from the RapidIO switching network, converts it into RapidIO data packets (RapidIO_Data) through the RapidIO IP core, and after being processed by the channel link configuration information receiving module, it is distributed to the channel link configuration information receiving and parsing modules 1 to X to parse out the corresponding channel link configuration information (Ch1_Link_Cfg_info to ChX_Link_Cfg_info).

[0051] Example 6

[0052] Based on Example 5, the configuration information sent by the FPGA receiving node through the RapidIO port is divided into two cases: one is to configure the channel link configuration information of the FPGA receiving node itself, which is routed back to the FPGA receiving node through the RapidIO switching network; the other is to configure the link configuration information of the peer node communicating with the FPGA receiving node, which is routed to communication nodes 1 to N through the RapidIO switching network.

[0053] Example 7

[0054] Based on Example 5, in the FPGA receiving node, the channel user configuration information sending process enters the initial state after power-on reset;

[0055] The system monitors whether the empty flag of the user configuration information packet-level FIFO is valid. If it is valid, it means that the user configuration information of a single channel has not been fully received. If it is invalid, it means that the user configuration information of one or more channels in the user configuration information packet-level FIFO has been fully received, and the process is transferred to the target end RapidIO ID extraction process.

[0056] After the RapidIO ID extraction process is completed at the target end, the process proceeds to the current channel configuration information packet assembly process. After the current channel configuration information packet assembly process is completed, the information is sent to the RapidIO switching network via the RapidIO IP core sending port and returns to the initial state.

[0057] Example 8

[0058] Based on Example 5, in the FPGA receiving node, the channel link configuration information receiving and processing flow enters the initial state after power-on reset;

[0059] Monitor whether the RapidIO data packet received by the RapidIO IP core is a link configuration information data packet; if so, enter the channel address field parsing process, and distribute the link configuration information data packet to the corresponding channel link configuration information receiving and parsing module 1 to X according to the preset value of each channel address segment, and return to the initial state.

[0060] Example 9

[0061] Based on Example 8, it monitors whether the RapidIO data packet received by the RapidIO IP core is a link configuration information data packet; if not, it does not process the received RapidIO data packet and returns the status of monitoring whether the RapidIO data packet is a link configuration information data packet.

[0062] Example 10

[0063] A computer-readable storage medium storing a computer program, which is loaded by a processor and executed as described in any one of Examples 5 to 9.

[0064] The units described in the embodiments of the present invention can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0065] According to one aspect of the present invention, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and executes the computer instructions, causing the computer device to perform the methods provided in the various optional implementations described above.

[0066] In another aspect, embodiments of the present invention also provide a computer-readable medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device. The computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the methods described in the above embodiments.

[0067] In addition to the examples above, other embodiments may be obtained by those skilled in the art based on the above disclosure or by making modifications using knowledge or technology in related fields. The features of each embodiment may be interchanged or replaced. Modifications and changes made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A RapidIO link configuration system, characterized by, The system comprises a center node, a communication node, a RapidIO switching network and a receiving node, wherein the center node, the communication node and the receiving node access the RapidIO switching network; The center node configures the routing between any two nodes connected by the RapidIO switching network; the receiving node configures the link with the communication node; the receiving node sends the channel communication link configuration information input by the user through the RapidIO port; The configuration information sent by the receiving node through the RapidIO port is divided into two cases: one is to configure the channel link configuration information of the FPGA receiving node itself, and the configuration information is sent back to the receiving node through the RapidIO switching network routing; the other is to configure the channel link configuration information of the opposite node communicating with the receiving node, and the configuration information is sent to the communication node through the RapidIO switching network routing.

2. The RapidIO link configuration system of claim 1, wherein, The receiving node comprises an FPGA receiving node; the center node is a PPC type; the number of the communication nodes is N, N is an integer greater than or equal to 1, and the communication nodes comprise any one or more of FPGA, DSP and PPC types.

3. The RapidIO link configuration system of claim 2, wherein, The center node accesses the RapidIO switching network through a 4X or 1X RapidIO port; each of the communication nodes 1 to N accesses the RapidIO switching network through a 4X or 1X RapidIO port; the FPGA receiving node accesses the RapidIO switching network through a 4X RapidIO port; and the chip in the RapidIO switching network is a CPS1848 chip.

4. The RapidIO link configuration system of claim 1, wherein, The receiving node is an FPGA receiving node, which comprises a RapidIO IP core, a channel user configuration information sending module, M channel user configuration information receiving modules, a channel link configuration information receiving module and X channel link configuration information receiving and analyzing modules, wherein M and X are integers greater than or equal to 1.

5. A method of configuring a RapidIO link, the method comprising: The RapidIO link configuration system according to claim 4 further comprises the following steps: First, the FPGA receiving node writes the received channel communication link configuration information Ch1_User_Cfg_info to ChM_User_Cfg_info from the user input into the corresponding channel user configuration information receiving modules 1 to M, processes the channel user configuration information through the channel user configuration information sending module, forms link configuration sending information User_Cfg_info_data, and sends the information to the RapidIO switching network through the RapidIO IP core and routes to the related communication node; Secondly, the FPGA receiving node receives data from the RapidIO switching network, converts the data into RapidIO data packets RapidIO_Data through the RapidIO IP core, processes the data through the channel link configuration information receiving module, and distributes the data to the channel link configuration information receiving and analyzing modules 1-X, and analyzes the corresponding channel link configuration information Ch1_Link_Cfg_info-ChX_Link_Cfg_info.

6. The method of configuring a RapidIO link according to claim 5, wherein, In the FPGA receiving node, the channel user configuration information sending processing flow enters an initial state after power-on reset is completed. It is monitored whether the channel user configuration information packet level FIFO empty flag is valid, and if yes, it indicates that the user configuration information of a single channel is not received completely. If no, it indicates that the user configuration information of one or more channels in the user configuration information packet level FIFO is received completely, and the target end RapidIO ID extraction flow is entered. After the target end RapidIO ID extraction flow is completed, the current channel configuration information packet forming flow is entered, and after the current channel configuration information packet forming flow is completed, the data is sent to the RapidIO switching network through the RapidIO IP core sending port, and the initial state is returned.

7. The method of configuring a RapidIO link according to claim 5, wherein, In the FPGA receiving node, the channel link configuration information receiving processing flow enters an initial state after power-on reset is completed. It is monitored whether the RapidIO data packet received through the RapidIO IP core is a link configuration information data packet, and if yes, the channel address field analysis flow is entered, and the link configuration information data packet is distributed to the corresponding channel link configuration information receiving and analyzing modules 1-X according to the preset value of each channel address segment, and the initial state is returned.

8. The method of configuring a RapidIO link according to claim 7, wherein, If no, the received RapidIO data packet is not processed, and the state of monitoring whether the RapidIO data packet is a link configuration information data packet is returned.

9. A computer-readable storage medium, characterized in that, A computer program is stored in a readable storage medium, the computer program is loaded and executed by a processor, and the method in any one of claims 5-8 is executed.

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