Array substrate, display panel and driving method

Abstract

The application belongs to the technical field of display driving, and particularly relates to an array substrate, a display panel and a driving method, the array substrate comprising 2N rows of scanning lines and M columns of pixel columns, the pixel column comprising a data line, a constant voltage line and N rows of pixel circuits; wherein the nth row of pixel circuits comprises a first sub-pixel unit, a second sub-pixel unit and a control unit, the control unit being configured to apply a constant voltage on the constant voltage line to a pixel electrode of the first sub-pixel unit before the first sub-pixel unit writes the first data voltage, and to apply the constant voltage on the constant voltage line to a pixel electrode of the second sub-pixel unit before the second sub-pixel unit writes the second data voltage; the application effectively improves the problem of insufficient charging when high refresh rate display is performed under the Dual Gate architecture, eliminates bright and dark lines under specific pictures such as water blue pictures, and improves the picture quality uniformity of the display panel.

Description

Technical Field

[0001] This application belongs to the field of display driving technology, specifically relating to an array substrate, a display panel, and a driving method. Background Technology

[0002] LCD displays widely adopt the Dual Gate driving architecture to reduce the number of source driver chips and manufacturing costs. However, when displaying a specific image (such as a light blue image) using the Dual Gate architecture, due to the significant difference in target voltage between different color sub-pixels, the voltage of some data lines is always in a jumping state, while the voltage of other data lines alternates between jumping and constant.

[0003] The voltage fluctuations of the data line are affected by its parasitic resistance and capacitance, causing some sub-pixels to appear darker due to insufficient charging and others to appear brighter due to sufficient charging. This results in alternating bright and dark lines when displaying specific images, affecting the display effect.

[0004] Therefore, how to improve the bright and dark line phenomenon caused by data line voltage jumps in the Dual Gate architecture is an urgent problem to be solved. Summary of the Invention

[0005] This application provides an array substrate, a display panel, and a driving method. This application effectively improves the problem of insufficient charging when displaying at high refresh rates under the Dual Gate architecture, eliminates bright and dark lines in specific scenes such as light blue images, and improves the uniformity of image quality of the display panel.

[0006] In a first aspect, this application provides an array substrate, the array substrate including 2N rows of scan lines extending along a first direction and M columns of pixel columns, the pixel columns including: data lines extending along a second direction, configured to: output a first data voltage and a second data voltage in a time-division multiplexing manner; constant voltage lines extending along the second direction, configured to: output a constant voltage; and N rows of pixel circuits arranged along the second direction; wherein, the nth row of pixel circuits includes: a first sub-pixel unit, respectively connected to the data lines and the (2n-1)th row of scan lines, configured to: write the first data voltage output on the data lines in response to a scan signal on the (2n-1)th row of scan lines; a second sub-pixel unit, respectively... A control unit, connected to the data line and the 2nth row of scan lines, is configured to: write a second data voltage output on the data line in response to a scan signal on the 2nth row of scan lines; and a control unit, connected to the constant voltage line, the first sub-pixel unit, and the second sub-pixel unit, is configured to: apply a constant voltage on the constant voltage line to the pixel electrode of the first sub-pixel unit before writing the first data voltage to the first sub-pixel unit, and apply a constant voltage on the constant voltage line to the pixel electrode of the second sub-pixel unit before writing the second data voltage to the second sub-pixel unit; wherein 1≤n≤N, and N and M are positive integers.

[0007] Optionally, the control unit includes: a first control transistor, the control terminal of which is connected to the 2n-2nd scan line, the 2Nth scan line, or the compensation scan line; a first terminal of which is connected to the constant voltage line; and a second terminal of which is connected to the pixel electrode of the first sub-pixel unit; and a second control transistor, the control terminal of which is connected to the 2n-1th scan line; a first terminal of which is connected to the constant voltage line; and a second terminal of which is connected to the pixel electrode of the second sub-pixel unit.

[0008] Optionally, when n=1, the control terminal of the first control transistor is connected to the 2Nth row of scan lines; or, when n=1, the control terminal of the first control transistor is connected to the compensation scan line; wherein the compensation scan line is configured to receive a frame start signal.

[0009] Optionally, the first sub-pixel unit and the second sub-pixel unit are disposed on the same side of the data line; the constant voltage line is disposed between the first sub-pixel unit and the second sub-pixel unit.

[0010] Optionally, the first sub-pixel unit and the second sub-pixel unit are respectively disposed on both sides of the data line; the m-th column constant voltage line is disposed between the second sub-pixel unit in the m-th column and the first sub-pixel unit in the (m+1)-th column; wherein, 1≤m<M; the M-th column constant voltage line is disposed on the side of the second sub-pixel unit in the M-th column away from the data line.

[0011] Optionally, the first sub-pixel unit includes a first pixel transistor and a first pixel capacitor; the control terminal of the first pixel transistor is connected to the (2n-1)th row of scan lines, the first end of the first pixel transistor is connected to the data line, and the second end of the first pixel transistor is connected to the first end of the first pixel capacitor; wherein, the first end of the first pixel capacitor serves as the pixel electrode of the first sub-pixel unit, and the second end of the first pixel capacitor serves as the common electrode of the first sub-pixel unit; the second sub-pixel unit includes a second pixel transistor and a second pixel capacitor; the control terminal of the second pixel transistor is connected to the (2n)th row of scan lines, the first end of the second pixel transistor is connected to the data line, and the second end of the second pixel transistor is connected to the first end of the second pixel capacitor; wherein, the first end of the second pixel capacitor serves as the pixel electrode of the second sub-pixel unit, and the second end of the second pixel capacitor serves as the common electrode of the second sub-pixel unit.

[0012] Optionally, the constant voltage lines in column M are electrically connected to each other; and / or, the constant voltage output on the constant voltage lines is the same as the common electrode voltage in the first sub-pixel unit.

[0013] Secondly, this application provides a display panel, the display panel comprising: an array substrate; a gate driving circuit electrically connected to 2N scan lines for outputting gate driving signals to the scan lines; a data driving circuit electrically connected to M data lines for outputting data voltages to the data lines; and a constant voltage circuit electrically connected to M columns of constant voltage lines for outputting constant voltages to the constant voltage lines.

[0014] Thirdly, this application provides a driving method applied to a display panel, the driving method comprising: in a pre-charging phase of a row n pixel circuit, applying a constant voltage on a constant voltage line to the pixel electrode of a first sub-pixel unit via a control unit; in a first charging phase of the row n pixel circuit, writing a first data voltage output on a data line to the pixel electrode of the first sub-pixel unit; simultaneously, applying a constant voltage on the constant voltage line to the pixel electrode of a second sub-pixel unit via the control unit; and in a second charging phase of the row n pixel circuit, writing a second data voltage output on the data line to the pixel electrode of the second sub-pixel unit.

[0015] Optionally, the control unit includes a first control transistor and a second control transistor; during the pre-charging phase of the nth row pixel circuit, applying a constant voltage on the constant voltage line to the pixel electrode of the first sub-pixel unit through the control unit includes: during the pre-charging phase, in response to the scan signal on the (2n-2)th row scan line, the first control transistor is in an on state, and the constant voltage on the constant voltage line is applied to the pixel electrode of the first sub-pixel unit through the on-state first control transistor.

[0016] Optionally, applying a constant voltage on the constant voltage line to the pixel electrode of the second sub-pixel unit via the control unit includes: during the first charging phase, in response to a scan signal on the (2n-1)th row scan line, a second control transistor is turned on, and the constant voltage on the constant voltage line is applied to the pixel electrode of the second sub-pixel unit via the turned-on second control transistor.

[0017] The technical solution provided in this application has at least the following beneficial effects:

[0018] This application incorporates a constant voltage line and a control unit within the pixel columns of a Dual Gate architecture. The constant voltage line is configured to output a constant voltage, and the control unit is connected to the constant voltage line, the first sub-pixel unit, and the second sub-pixel unit. In each row of pixel circuits, before data is written to the first and second sub-pixel units, the control unit pre-applies the constant voltage from the constant voltage line to the pixel electrodes of the first and second sub-pixel units. This raises the initial potential of the pixel electrodes before formal charging to an intermediate potential between the residual voltage of the previous frame and the target data voltage. Because this intermediate potential is close to the data voltage to be written, the voltage difference that the pixel electrodes need to overcome during formal charging is significantly reduced, thereby significantly shortening the data voltage rise time within a limited charging window and improving the charging rate of the pixel electrodes. Simultaneously, since the constant voltage on the constant voltage line remains stable throughout the entire display area and all pixel columns are equipped with this constant voltage line, the charging rate of sub-pixel units driven by different data lines in each pixel column tends to be consistent, eliminating charging differences caused by data line voltage transition delays and thus avoiding periodic alternating bright and dark stripes. Therefore, this application effectively improves the Dual Gate architecture. The Gate architecture addresses the issue of insufficient charging during high refresh rate displays, eliminating bright and dark lines in specific scenes such as aquamarine, improving the uniformity of image quality on the display panel, and meeting the requirements of high refresh rate applications for a short charging window. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0020] Figure 1 The diagram shown is a schematic of the Dual Gate architecture in related technologies.

[0021] Figure 2 The image shown is a schematic diagram of a water-blue display in related technologies.

[0022] Figure 3 The diagram shown illustrates voltage transitions on data lines in related technologies.

[0023] Figure 4 The image shown is a partial schematic diagram of an array substrate provided in an embodiment of this application.

[0024] Figure 5 The figure shown is a voltage change timing diagram provided in an embodiment of this application.

[0025] Figure 6 The diagram shown is a structural schematic of the first array substrate provided in the embodiment of this application.

[0026] Figure 7 The diagram shown is a structural schematic of the second type of array substrate provided in the embodiment of this application.

[0027] Figure 8 The diagram shown is a flowchart of a driving method provided in an embodiment of this application.

[0028] Explanation of reference numerals in the attached figures: 10. Array substrate; 100, scan lines; 200, pixel columns; 210 Data cable; 220 Constant voltage line; 230 First sub-pixel unit; 240 Second sub-pixel unit; 250 Control unit; T1, first pixel transistor; T2, second pixel transistor; M1, first control transistor; M2, second control transistor; C1, first pixel capacitor; C2, second pixel capacitor. Detailed Implementation

[0029] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0030] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0031] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0032] In the driving technology of thin-film transistor liquid crystal displays, the dual-gate driving architecture is widely used to reduce the number of source driver chips and manufacturing costs, such as... Figure 1 As shown, in the Dual Gate architecture, the number of data lines on the array substrate is reduced by half compared to the traditional architecture, while the number of scan lines is doubled. This architecture uses time-division multiplexing, requiring the same data line to sequentially provide data signals to two adjacent sub-pixels. Specifically, taking the common RGB pixel arrangement as an example, in the first row (odd-numbered rows), the red sub-pixel (R) and the green sub-pixel (G) share the same data line D1, while the blue sub-pixel (B) shares data line D2 with the next group of red sub-pixels; in the second row (even-numbered rows), the red sub-pixel (R) and the green sub-pixel (G) share data line D2, while the blue sub-pixel (B) shares data line D3 with the next group of red sub-pixels, and so on, forming a layout where data lines are alternately connected between adjacent rows.

[0033] Aquamarine is a specific type of image, such as... Figure 2 This typically manifests as blue sub-pixels being illuminated at higher gray levels, green sub-pixels at medium or higher gray levels, and red sub-pixels being unilluminated (i.e., 0 gray level or extremely low gray level). In this image, the data voltage carried by different data lines exhibits drastically different variation patterns. Specifically: Data line D1 requires sequential high voltage (green or blue) and low voltage (red) writing in both odd and even rows, thus its voltage is always in a fluctuating state; data line D2 is similar, with a constant voltage fluctuation. Figure 3 As shown.

[0034] For data line D3, it connects green and blue sub-pixels (both at high voltage) in odd-numbered rows, with the voltage remaining constant. In even-numbered rows, it connects blue and red sub-pixels, requiring a voltage transition from high to low. Data line D4 exhibits the opposite pattern: there is a voltage transition in odd-numbered rows, while the voltage remains constant in even-numbered rows.

[0035] Because data cables inherently possess parasitic resistance and capacitance, their voltage rise and fall edges require a certain settling time. When a voltage jump occurs, the data cable cannot immediately reach the preset target voltage the moment the charging window opens, resulting in insufficient effective charging time and a low charging rate for the sub-pixels driven by that data cable (especially the first sub-pixel charged after the jump). However, not all insufficient charging affects the display. Taking data cable D4 as an example, in odd-numbered rows, the second sub-pixel driven after the jump is also a green sub-pixel, which is also undercharged and appears dark; while green sub-pixels driven by other data cables are fully charged and appear normal and bright. Since the human eye is more sensitive to green, these green sub-pixels with different charging characteristics are arranged periodically in space, forming alternating bright and dark stripes, i.e., the bright-dark line phenomenon.

[0036] Furthermore, to prevent liquid crystal polarization, LCD drivers typically employ polarity reversal technology, meaning that for the same sub-pixel, the pixel voltage polarity of the previous frame is opposite to that of the next frame. Under these circumstances, when the data line voltage itself already fluctuates, the need to complete a large voltage jump from positive to negative polarity exacerbates the problem of insufficient charging.

[0037] To improve the bright and dark line phenomenon caused by data line voltage transitions in the Dual Gate architecture, this application provides an array substrate, specifically including the following embodiments: Figure 4 The image shown is a partial schematic diagram of an array substrate 10 provided in an embodiment of this application; as shown Figure 4 As shown, the array substrate 10 is provided with multiple scan lines 100 extending along a first direction (such as the X direction), multiple data lines 210 extending along a second direction (such as the Y direction), and constant voltage lines 220; the scan lines 100 have a total of 2N rows and are arranged in parallel along the first direction; the data lines 210 and constant voltage lines 220 have a total of M columns and are arranged in parallel along the second direction, and the data lines 210 and constant voltage lines 220 are arranged alternately; wherein, the scan lines 100, data lines 210, and constant voltage lines 220 intersect to define a pixel area that is distributed in a matrix.

[0038] In this embodiment, each pixel region corresponds to one pixel circuit, and all pixel circuits are arranged in N rows along the second direction. Each row of pixel circuits includes a first sub-pixel unit 230, a second sub-pixel unit 240, and a control unit 250. Figure 4This is only a partial schematic diagram of the array substrate 10. The pixel circuit composed of the first sub-pixel unit 230, the second sub-pixel unit 240, and the control unit 250 is the smallest repeating unit of the array substrate 10. The pixel circuit structure of other pixel areas is similar to... Figure 4 same.

[0039] In this embodiment, the data line 210 outputs a first data voltage for driving the first sub-pixel unit 230 and a second data voltage for driving the second sub-pixel unit 240 in a time-division manner. Since one data line 210 needs to provide data signals to two adjacent sub-pixels under the dual-gate architecture, the data line 210 outputs two different data voltages in sequence during operation. Therefore, by driving two sub-pixels in a time-division manner with one data line 210, the total number of data lines 210 can be halved, thereby reducing the number of source driver chips and reducing manufacturing costs.

[0040] In this embodiment, the constant voltage line 220 is arranged parallel to the data line 210. Its function is to output a constant voltage that remains stable throughout the display process and does not change with variations in the data voltage or scan signal. The constant voltage line 220 provides a stable reference potential as a pre-charge voltage source. The value of this constant voltage is designed to be between the first data voltage and the second data voltage, thereby effectively shortening the ramp-up time for subsequent charging.

[0041] In this embodiment, the first sub-pixel unit 230 is connected to the data line 210 and the 2n-1th row scan line 100 respectively. When the scan signal on the 2n-1th row scan line 100 arrives, in response to the scan signal, the first data voltage currently output on the data line 210 is written into the pixel electrode inside the first sub-pixel unit 230 and held, so that the first sub-pixel unit 230 can display the corresponding gray level.

[0042] In this embodiment, the second sub-pixel unit 240 is connected to the data line 210 and the 2nth row scan line 100 respectively. When the scan signal on the 2nth row scan line 100 arrives, in response to the scan signal, the second data voltage currently output on the data line 210 is written into the pixel electrode inside the second sub-pixel unit 240 and held, so that the second sub-pixel unit 240 can display the corresponding gray level.

[0043] In this embodiment, the control unit 250 is connected to the constant voltage line 220, the first sub-pixel unit 230, and the second sub-pixel unit 240, respectively, and its main functions include: (1) Before the first data voltage is written to the first sub-pixel unit 230, a constant voltage on the constant voltage line 220 is applied to the pixel electrode of the first sub-pixel unit 230. That is, for a period of time before the scan signal of the 2n-1th row is valid, the control unit 250 is turned on first, so that the pixel electrode of the first sub-pixel unit 230 is pre-charged to the constant voltage of the constant voltage line 220.

[0044] (2) Before the second data voltage is written to the second sub-pixel unit 240, a constant voltage on the constant voltage line 220 is applied to the pixel electrode of the second sub-pixel unit 240. That is, for a period of time before the 2n-line scan signal is valid, the control unit 250 is turned on first, so that the pixel electrode of the second sub-pixel unit 240 is pre-charged to the constant voltage of the constant voltage line 220.

[0045] This embodiment pre-sets the pixel electrode to a constant voltage before the formal data voltage is written, which greatly reduces the voltage difference that the pixel electrode needs to cross during formal charging, thereby shortening the charging ramp-up time and achieving a higher charging rate within a limited charging window. This can effectively improve the problem of uneven brightness and bright-dark lines caused by insufficient charging.

[0046] Therefore, this application sets a constant voltage line 220 and a control unit 250 in the pixel column of the Dual Gate architecture. The constant voltage line 220 is configured to output a constant voltage, and the control unit 250 is connected to the constant voltage line 220, the first sub-pixel unit 230, and the second sub-pixel unit 240, respectively. In each row of pixel circuits, before the data of the first sub-pixel unit 230 and the second sub-pixel unit 240 is written, the control unit 250 pre-applies the constant voltage on the constant voltage line 220 to the pixel electrodes of the first sub-pixel unit 230 and the second sub-pixel unit 240, so that the initial potential of the pixel electrodes before the formal charging begins is raised to a value between the residual voltage of the previous frame and the target data voltage. The intermediate potential between the two values ​​is close to the data voltage to be written. Since this intermediate potential is close to the data voltage to be written, the voltage difference that the pixel electrode needs to cross during actual charging is significantly reduced, thereby significantly shortening the data voltage rise time within a limited charging window and improving the charging rate of the pixel electrode. Simultaneously, since the constant voltage on the constant voltage line 220 remains stable throughout the entire display area and all pixel columns are equipped with this constant voltage line 220, the charging rate of sub-pixel units driven by different data lines 210 in each pixel column tends to be consistent, eliminating the charging difference caused by the voltage jump delay of the data line 210, thus avoiding periodic bright and dark alternating stripes. Therefore, this application effectively improves the charging insufficiency problem in high refresh rate displays under the Dual Gate architecture, eliminates bright and dark lines in specific scenes such as aquamarine, improves the uniformity of the display panel's image quality, and meets the requirements of high refresh rate applications for a short charging window.

[0047] like Figure 4 As shown, the control unit 250 of this embodiment includes a first control transistor M1 and a second control transistor M2. Specifically, the control terminal of the first control transistor M1 is connected to the 2n-2nd row scan line 100, the 2Nth row scan line 100 or the compensation scan line, the first terminal of the first control transistor M1 is connected to the constant voltage line 220, and the second terminal of the first control transistor M1 is connected to the pixel electrode of the first sub-pixel unit 230. The control terminal of the second control transistor M2 is connected to the 2n-1st row scan line 100, the first terminal of the second control transistor M2 is connected to the constant voltage line 220, and the second terminal of the second control transistor M2 is connected to the pixel electrode of the second sub-pixel unit 240.

[0048] It should be noted that the purpose of the control unit 250 in this embodiment is to preset the voltage of the pixel electrode to an intermediate potential that is closer to the target data voltage before the actual data is written, thereby shortening the ramp-up time required for subsequent charging.

[0049] For example: Figure 5 As shown, let the residual voltage on the pixel electrode at the end of the previous frame be V1, the target data voltage to be written in this frame be V3, and the constant voltage provided by the constant voltage line 220 be V2. The value of V2 is between V1 and V3, usually an intermediate value, such as the common electrode voltage. Here, taking the nth row pixel circuit (n≥2) as an example, its timing process is as follows: (1) Pre-charging and formal writing of the first sub-pixel unit 230.

[0050] During the effective period of the (2n-2)th scan line 100, i.e., the time period from t1 to t2: the first control transistor M1 is turned on in response to the scan signal on the (2n-2)th scan line 100. The constant voltage V2 on the constant voltage line 220 is applied to the pixel electrode of the first sub-pixel unit 230 through the turned-on first control transistor M1, which quickly pulls the pixel electrode voltage from the residual voltage V1 to V2, completing the pre-charging.

[0051] During the effective period of scan line 100 in row 2n-1, i.e., time period t2 to t3: the first sub-pixel unit 230 is turned on in response to the scan signal in row 2n-1, writing the first data voltage (i.e., V3) output on data line 210 into the pixel electrode. Since the starting voltage of the pixel electrode is already V2 instead of V1, and V2 is closer to V3, the voltage difference required for charging is reduced, and the rise time is shortened. Figure 5 As shown by the dashed line, the actual charging ramp-up time of this scheme is from t2 to t3; while Figure 5 The solid line in the diagram represents the climb time of the traditional technique from t2 to t4. Clearly, t3-t2... <t4-t2。

[0052] (2) Pre-charging and formal writing of the second sub-pixel unit 240.

[0053] Meanwhile, during the time period t2 to t3, the second control transistor M2 is turned on in response to the scan signal on the same (2n-1)th row scan line 100, and applies the constant voltage V2 on the constant voltage line 220 to the pixel electrode of the second sub-pixel unit 240, thus completing the pre-charging of the second sub-pixel unit 240.

[0054] During the time period from t3 to t4 (i.e., during the active period of the 2nth row scan line 100), the second sub-pixel unit 240 is turned on in response to the 2nth row scan signal, writing the second data voltage (not shown in the figure) output on the data line 210 into the pixel electrode. Since the pixel electrode has been preset to V2 close to the second data voltage, its charging ramp-up time is also significantly shortened.

[0055] (3) Boundary processing of the first row of pixel circuits.

[0056] When n=1, the control terminal of the control transistor of the first sub-pixel unit 230 in the first row pixel circuit cannot be connected to the 0th row scan line. This embodiment provides the following two implementation methods: ① Implementation method 1: Connect the control terminal of the first control transistor M1 to the 2Nth scan line 100 (i.e., the last scan line 100). During the effective period of the last scan signal of the previous frame, the pre-charge of the first sub-pixel unit 230 of the first row is completed. The blanking time between frames ensures that the pre-charge does not interfere with the normal timing of the current frame.

[0057] ② Implementation Method 2: Add a new compensation scan line and configure it as the receive frame start signal. At the beginning of each frame, the frame start signal enables the compensation scan line, turns on the first control transistor M1, and completes pre-charging.

[0058] Therefore, this embodiment, by turning on the first control transistor M1 and the second control transistor M2 according to a predetermined timing sequence, pre-sets the pixel electrode to a constant voltage before the actual data is written, thereby shortening the charging rise time. At high refresh rates, the effective time of each scan line (100) is significantly compressed. The shortened rise time brought about by pre-charging ensures that the pixel electrode can be charged to the target voltage within a limited window, thus effectively improving the bright and dark line phenomenon caused by insufficient charging. At the same time, this solution only requires adding one transistor and one constant voltage line 220 in each sub-pixel, resulting in low hardware overhead and ease of implementation.

[0059] In one embodiment, such as Figure 6As shown, the first sub-pixel unit 230 and the second sub-pixel unit 240 in each pixel circuit are located on the same side of the data line 210. Specifically, the data line 210 extends vertically along the second direction, and the first sub-pixel unit 230 and the second sub-pixel unit 240 are located to the left or right of the data line 210. The constant voltage line 220 is located between the first sub-pixel unit 230 and the second sub-pixel unit 240, that is, the data line 210 is located on the outermost side, and the constant voltage line 220 is located in the middle position of two sub-pixels in the same column; wherein, Figure 6 The vertical dashed line in the figure represents the constant voltage line 220. In this embodiment, since the constant voltage line 220 is located between two sub-pixels, the trace lengths connecting the pixel electrodes of the two sub-pixels are basically equal, which helps to reduce the difference in parasitic capacitance and make the pre-charging effect of the two sub-pixels consistent.

[0060] In another embodiment, such as Figure 7 As shown, the first sub-pixel unit 230 and the second sub-pixel unit 240 in each pixel circuit are respectively disposed on both sides of the data line 210. Specifically, the data line 210 extends vertically along the second direction, the first sub-pixel unit 230 is located on one side of the data line 210, and the second sub-pixel unit 240 is located on the other side of the data line 210, that is, the data line 210 passes between the two sub-pixels.

[0061] In this embodiment, the constant voltage line 220 is arranged as follows: For the m-th pixel column 200 (1≤m<M), the constant voltage line 220 is located between the second sub-pixel unit 240 of the m-th column and the first sub-pixel unit 230 of the (m+1)-th column. That is, the constant voltage line 220 is located in the gap between two adjacent pixel columns 200, with the second sub-pixel unit 240 of the m-th column on the left and the first sub-pixel unit 230 of the (m+1)-th column on the right. For the last column (the M-th column), since there is no (M+1)-th column, the constant voltage line 220 is located on the side of the second sub-pixel unit 240 of the M-th column that is away from the data line 210 (i.e., the outermost side).

[0062] In this embodiment, the constant voltage line 220 is arranged using the gap between the data lines 210, which eliminates the need to increase the width of the pixel column 200 and facilitates the achievement of high pixel density.

[0063] like Figure 6 and Figure 7 As shown, the M columns of constant voltage lines 220 are electrically connected to each other. That is to say, in the array substrate 10, the constant voltage lines 220 in each column of pixel 200 are not independent and unconnected to each other, but are short-circuited together in the non-display area outside the display area to form a common potential line, so that all constant voltage lines 220 are at the same potential, forming a mesh structure as a whole.

[0064] In this embodiment, after the constant voltage lines 220 in each column are short-circuited, the voltage at any position on the constant voltage lines 220 across the entire surface is the same. Even if a certain constant voltage line 220 has a slight voltage drop due to its long length, the constant voltage lines 220 in other columns can compensate for it by interconnecting with each other, thereby ensuring that the constant voltage output by the constant voltage lines 220 in the entire display area is highly consistent. In addition, since the voltage of all constant voltage lines 220 is equal, the pre-charge voltage obtained by the sub-pixel units in different pixel columns 200 is exactly the same, avoiding the inconsistency in charging rate caused by voltage differences between constant voltage lines 220, and further eliminating bright and dark lines.

[0065] In one embodiment, such as Figure 4 As shown, the first sub-pixel unit 230 in this embodiment includes a first pixel transistor T1 and a first pixel capacitor C1; the control terminal of the first pixel transistor T1 is connected to the 2n-1th row scan line 100, the first end of the first pixel transistor T1 is connected to the data line 210, and the second end of the first pixel transistor T1 is connected to the first end of the first pixel capacitor C1; wherein, the first end of the first pixel capacitor C1 serves as the pixel electrode of the first sub-pixel unit 230, and the second end of the first pixel capacitor C1 serves as the common electrode of the first sub-pixel unit 230.

[0066] It should be noted that when the scan signal on the (2n-1)th scan line 100 is valid, the first pixel transistor T1 is turned on. At this time, the first data voltage output on the data line 210 is written to the first terminal of the first pixel capacitor C1 through the turned-on first pixel transistor T1, that is, the pixel electrode is charged to this data voltage. The first pixel capacitor C1 holds this voltage to drive the liquid crystal molecules to deflect to the corresponding angle, thereby displaying the corresponding grayscale. When the (2n-1)th scan signal ends, the first pixel transistor T1 is turned off, and the voltage on the pixel electrode is held by the first pixel capacitor C1 until it is updated when the next frame scan signal arrives.

[0067] like Figure 4 As shown, the second sub-pixel unit 240 in this embodiment includes a second pixel transistor T2 and a second pixel capacitor C2; the control terminal of the second pixel transistor T2 is connected to the 2nth row scan line 100, the first terminal of the second pixel transistor T2 is connected to the data line 210, and the second terminal of the second pixel transistor T2 is connected to the first terminal of the second pixel capacitor C2; wherein, the first terminal of the second pixel capacitor C2 serves as the pixel electrode of the second sub-pixel unit 240, and the second terminal of the second pixel capacitor C2 serves as the common electrode of the second sub-pixel unit 240.

[0068] It should be noted that when the scan signal on the 2nth scan line 100 is valid, the second pixel transistor T2 is turned on. At this time, the second data voltage output on the data line 210 is written to the first terminal of the second pixel capacitor C2 through the turned-on second pixel transistor T2, that is, the pixel electrode is charged to this data voltage. The second pixel capacitor C2 holds this voltage to drive the liquid crystal molecules of the corresponding sub-pixel to deflect and display the corresponding grayscale. When the 2nth scan line signal ends, the second pixel transistor T2 is turned off, and the pixel electrode voltage is maintained until the next frame.

[0069] It is worth noting that the first pixel transistor T1 and the second pixel transistor T2 are turned on in a time-division multiplexing manner, corresponding to the write timing of the two sub-pixels under the DualGate architecture. They work independently and do not interfere with each other. The control unit 250 of this application relies on this pixel unit to pre-apply a constant voltage on the constant voltage line 220 to the corresponding pixel electrode before the respective pixel transistors are turned on, thereby shortening the charging ramp-up time.

[0070] In one embodiment, this application provides a display panel, specifically including: (1) Array substrate: The array substrate shown in the above embodiment is used, that is, multiple scan lines, data lines, constant voltage lines and pixel circuits arranged in a matrix are provided on the substrate. Each pixel circuit includes two sub-pixel units and a control unit, which can pre-charge the pixel electrode through the constant voltage line before data writing.

[0071] (2) Gate driving circuit: It is electrically connected to the 2N scan lines on the array substrate and is used to output gate driving signals (i.e. scan signals) line by line to turn on the pixel transistors and control transistors in each row of pixel circuits in turn to control the timing of data writing and precharging.

[0072] (3) Data driving circuit: electrically connected to the M data lines, used to output the corresponding data voltage to each data line according to the display content. In the dual-gate architecture, the data driving circuit needs to output two different data voltages in a time-division multiplexing within one row cycle, corresponding to the first sub-pixel unit and the second sub-pixel unit in the same row, respectively.

[0073] (4) Constant voltage circuit: Electrically connected to the M column of constant voltage lines, used to output a stable constant voltage to each constant voltage line. This constant voltage is usually the common electrode voltage VCOM, and its value is set between the first data voltage and the second data voltage output by the data drive circuit to ensure the best pre-charging effect.

[0074] Figure 8 The diagram shown is a flowchart of a driving method provided in an embodiment of this application; the driving method of this embodiment is applied to the display panel shown in the above embodiment, such as... Figure 8As shown, the specific steps include: Step S100: During the pre-charging phase of the nth row pixel circuit, a constant voltage on the constant voltage line is applied to the pixel electrode of the first sub-pixel unit by the control unit.

[0075] Specifically, when the control unit includes a first control transistor and a second control transistor, during the pre-charging phase, in response to the scan signal on the 2n-2th scan line, the first control transistor is in the on state, and the constant voltage on the constant voltage line is applied to the pixel electrode of the first sub-pixel unit through the on-state first control transistor.

[0076] Step S200: In the first charging stage of the nth row pixel circuit, the first data voltage output on the data line is written into the pixel electrode of the first sub-pixel unit; at the same time, the constant voltage on the constant voltage line is applied to the pixel electrode of the second sub-pixel unit through the control unit.

[0077] Specifically, when the control unit includes a first control transistor and a second control transistor, during the first charging phase, in response to the scan signal on the (2n-1)th row scan line, the second control transistor is in the on state, and the constant voltage on the constant voltage line is applied to the pixel electrode of the second sub-pixel unit through the on-state second control transistor.

[0078] Step S300: In the second charging stage of the nth row pixel circuit, the second data voltage output on the data line is written into the pixel electrode of the second sub-pixel unit.

[0079] It should be noted that the specific working principle of the driving method in this embodiment is as follows: (1) During the pre-charging phase, the scan signal on the (2n-2)th scan line is valid, and the first control transistor is turned on in response to the scan signal. Since the first terminal of the first control transistor is connected to the constant voltage line and the second terminal is connected to the pixel electrode of the first sub-pixel unit, the constant voltage on the constant voltage line is directly applied to the pixel electrode of the first sub-pixel unit through the turned-on first control transistor, so that the pixel electrode voltage of the first sub-pixel unit is quickly pulled from the residual voltage of the previous frame to the constant voltage, thus completing the pre-charging of the first sub-pixel unit.

[0080] (2) During the first charging stage of the nth row pixel circuit, two operations are performed simultaneously: first, the first data voltage output on the data line is written to the pixel electrode of the first sub-pixel unit; second, the constant voltage on the constant voltage line is applied to the pixel electrode of the second sub-pixel unit through the control unit.

[0081] Specifically, during the first charging phase, the scan signal on the (2n-1)th scan line is active. The first pixel transistor in the first sub-pixel unit turns on in response to the scan signal, and the first data voltage output on the data line is written to the pixel electrode of the first sub-pixel unit through the turned-on first pixel transistor, completing the data update of the first sub-pixel unit. At the same time, the second control transistor turns on in response to the same (2n-1)th scan signal, and the constant voltage on the constant voltage line is applied to the pixel electrode of the second sub-pixel unit through the turned-on second control transistor, completing the pre-charging of the second sub-pixel unit.

[0082] (3) During the second charging phase, the scan signal on the 2nth row of the scan line is valid. The second pixel transistor in the second sub-pixel unit is turned on in response to the scan signal, and the second data voltage output on the data line is written to the pixel electrode of the second sub-pixel unit through the turned-on second pixel transistor, thus completing the data update of the second sub-pixel unit.

[0083] Therefore, this embodiment utilizes the inherent scanning signal timing of the Dual Gate architecture to achieve pipelined operation of pre-charging and data writing through the above three stages: the pre-charging stage uses the previous row of scanning signals to pre-charge the first sub-pixel; the first charging stage uses the first row of scanning signals to simultaneously complete the data writing of the first sub-pixel and the pre-charging of the second sub-pixel; and the second charging stage uses the second row of scanning signals to complete the data writing of the second sub-pixel. The entire process does not consume additional time, and the pre-charging significantly reduces the voltage rise during formal charging, thereby significantly improving the charging rate at high refresh rates and eliminating bright and dark lines caused by insufficient charging.

[0084] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0085] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0086] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. An array substrate, characterized in that, The array substrate includes 2N rows of scan lines extending along a first direction and M columns of pixels, the pixel columns including: The data line extending along the second direction is configured to output the first data voltage and the second data voltage in a time-division manner; The constant voltage line extending along the second direction is configured to output a constant voltage; N rows of pixel circuits are arranged along the second direction; wherein the nth row of pixel circuits includes: The first sub-pixel unit, which is connected to the data line and the 2n-1th row of scan lines respectively, is configured to: write the first data voltage output on the data line in response to the scan signal on the 2n-1th row of scan lines; The second sub-pixel unit, which is connected to the data line and the 2nth row of scan lines respectively, is configured to: write the second data voltage output on the data line in response to the scan signal on the 2nth row of scan lines; The control unit, which is connected to the constant voltage line, the first sub-pixel unit and the second sub-pixel unit respectively, is configured to: apply a constant voltage on the constant voltage line to the pixel electrode of the first sub-pixel unit before the first data voltage is written to the first sub-pixel unit, and apply a constant voltage on the constant voltage line to the pixel electrode of the second sub-pixel unit before the second data voltage is written to the second sub-pixel unit. Where 1≤n≤N, and N and M are positive integers.

2. The array substrate according to claim 1, characterized in that, The control unit includes: The first control transistor has its control terminal connected to the 2n-2nd row of scan lines, the 2Nth row of scan lines, or the compensation scan line. The first terminal of the first control transistor is connected to the constant voltage line, and the second terminal of the first control transistor is connected to the pixel electrode of the first sub-pixel unit. The second control transistor has its control terminal connected to the (2n-1)th row of scan lines, its first terminal connected to the constant voltage line, and its second terminal connected to the pixel electrode of the second sub-pixel unit.

3. The array substrate according to claim 2, characterized in that, When n=1, the control terminal of the first control transistor is connected to the 2Nth row of scan lines; Alternatively, when n=1, the control terminal of the first control transistor is connected to the compensation scan line; wherein the compensation scan line is configured to receive the frame start signal.

4. The array substrate according to claim 1, characterized in that, The first sub-pixel unit and the second sub-pixel unit are disposed on the same side of the data line; The constant voltage line is disposed between the first sub-pixel unit and the second sub-pixel unit.

5. The array substrate according to claim 1, characterized in that, The first sub-pixel unit and the second sub-pixel unit are respectively disposed on both sides of the data line; The constant voltage line in column m is set between the second sub-pixel unit in column m and the first sub-pixel unit in column (m+1); where 1 ≤ m < M; The constant voltage line in column M is located on the side of the second sub-pixel unit in column M that is away from the data line.

6. The array substrate according to any one of claims 1-5, characterized in that, The first sub-pixel unit includes a first pixel transistor and a first pixel capacitor; the control terminal of the first pixel transistor is connected to the 2n-1th row of scan lines, the first terminal of the first pixel transistor is connected to the data line, and the second terminal of the first pixel transistor is connected to the first terminal of the first pixel capacitor; wherein, the first terminal of the first pixel capacitor serves as the pixel electrode of the first sub-pixel unit, and the second terminal of the first pixel capacitor serves as the common electrode of the first sub-pixel unit. The second sub-pixel unit includes a second pixel transistor and a second pixel capacitor; the control terminal of the second pixel transistor is connected to the 2n-th row of scan lines, the first terminal of the second pixel transistor is connected to the data line, and the second terminal of the second pixel transistor is connected to the first terminal of the second pixel capacitor; wherein, the first terminal of the second pixel capacitor serves as the pixel electrode of the second sub-pixel unit, and the second terminal of the second pixel capacitor serves as the common electrode of the second sub-pixel unit.

7. The array substrate according to any one of claims 1-5, characterized in that, The constant voltage lines in column M are electrically connected to each other; And / or, the constant voltage output on the constant voltage line is the same as the common electrode voltage in the first sub-pixel unit.

8. A display panel, characterized in that, The display panel includes: The array substrate according to any one of claims 1 to 7; A gate drive circuit, electrically connected to 2N scan lines, is used to output gate drive signals to the scan lines; A data driving circuit, electrically connected to M data lines, is used to output data voltage to the data lines; A constant voltage circuit, electrically connected to M columns of constant voltage lines, is used to output a constant voltage to the constant voltage lines.

9. A driving method, characterized in that, Applied to the display panel of claim 8, the driving method includes: During the pre-charging phase of the nth row pixel circuit, a constant voltage on the constant voltage line is applied to the pixel electrode of the first sub-pixel unit by the control unit. During the first charging phase of the nth row pixel circuit, the first data voltage output on the data line is written to the pixel electrode of the first sub-pixel unit; at the same time, the constant voltage on the constant voltage line is applied to the pixel electrode of the second sub-pixel unit through the control unit. During the second charging phase of the nth row pixel circuit, the second data voltage output on the data line is written into the pixel electrode of the second sub-pixel unit.

10. The driving method according to claim 9, characterized in that, The control unit includes a first control transistor and a second control transistor; During the pre-charging phase of the nth row pixel circuit, a constant voltage from the constant voltage line is applied to the pixel electrode of the first sub-pixel unit via a control unit, including: During the pre-charging phase, in response to the scan signal on the 2n-2th scan line, the first control transistor is turned on, and the constant voltage on the constant voltage line is applied to the pixel electrode of the first sub-pixel unit through the turned-on first control transistor. Applying a constant voltage from the constant voltage line to the pixel electrode of the second sub-pixel unit via the control unit includes: During the first charging phase, in response to the scan signal on the (2n-1)th row of the scan line, the second control transistor is turned on, and the constant voltage on the constant voltage line is applied to the pixel electrode of the second sub-pixel unit through the turned-on second control transistor.

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