Semiconductor device structure and method of forming the same

Abstract

A semiconductor device structure and method of forming the same. The method of forming the semiconductor device structure can be a plurality of sequences of forming semiconductor devices on a substrate and performing a metal interconnect formation process. Each of the sequences includes depositing a dielectric material, forming a void in the dielectric material, and forming a first interconnect structure in the void. A first set of the first metal interconnect structures includes a first vertically-extending conductive path having a first electrically-active metal via structure at a first via level. A second set includes at least one electrically-floating metallization structure in a frame-shaped region in a plan view. The first electrically-active metal via structure is located at a corner portion of the frame-shaped region. A bond pad is formed on the dielectric material layer and the first metal interconnect structure. The bond pad can be electrically connected to the first vertically-extending conductive path.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor device structures, and more particularly to the configuration of electrically active metal via structures and electrically floating metallization structures in their metal interconnect structures. Background Technology

[0002] The miniaturization and increasing complexity of semiconductor devices necessitate advanced packaging technologies to meet the demands of modern electronic systems. A challenge in semiconductor packaging is the potential for damage to the underlying metal interconnect structures within the semiconductor die. Specifically, mechanical stresses generated during bonding and underfill processes can induce structural damage within the metal interconnect structures. In embodiments where the underlying dielectric layer contains a dielectric material with an extremely low dielectric constant, the risk of such structural damage is increased. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device structure and a method for forming the same, in order to solve at least one of the above-mentioned problems.

[0004] An embodiment of the present invention provides a method for forming a device structure, comprising: forming a plurality of semiconductor devices on a semiconductor substrate; after forming the semiconductor devices, performing a multiple sequence of multiple metal interconnect forming processes, wherein each multiple sequence of metal interconnect forming processes includes: an individual dielectric material deposition process for depositing an individual dielectric material layer; an individual dielectric patterning process for forming an individual plurality of voids in an individual dielectric material layer; and an individual metal deposition and patterning process for forming an individual plurality of first metal interconnect structures in an individual void, wherein the first group of first metal interconnect structures formed by the multiple sequence includes a first vertically extending conductive path, which includes at least one first electrically active metal via structure formed in a first via layer, and the second group of first metal interconnect structures includes at least one electrically floating metallized structure formed in a frame-shaped region in a plan view, wherein at least one electrically active metal via structure is formed within the inner periphery of the frame-shaped region in the plan view; and forming a plurality of bonding pads on the dielectric material layer and the first metal interconnect structures, wherein one of the bonding pads is electrically connected to the first vertically extending conductive path.

[0005] An embodiment of the present invention provides a method for forming a device structure, comprising: forming a plurality of semiconductor devices on a semiconductor substrate; performing a multiple sequence of multiple metal interconnect formation processes, wherein each multiple sequence of metal interconnect formation processes includes: an individual dielectric material deposition process for depositing an individual dielectric material layer; an individual dielectric patterning process for forming an individual plurality of voids in an individual dielectric material layer; and an individual metal deposition and patterning process for forming an individual plurality of first metal interconnect structures in an individual void, wherein the first group of first metal interconnect structures formed by the multiple sequence includes a first vertically extending conductive path, which includes a first electrically active metal via. The structure is formed on a first via layer, and the second group of first metal interconnect structures includes at least one electrically floating metallized structure formed in the frame region in the plan view; a plurality of additional dielectric material layers and a plurality of second metal interconnect structures are formed on the dielectric material layers and the first metal interconnect structures, wherein the dielectric constant of individual additional dielectric material layers is higher than the dielectric constant of dielectric material layers deposited by the multiple sequence of the metal interconnect formation process, wherein some of the second metal interconnect structures include additional vertically extending conductive paths; and a plurality of bonding pads are formed on the additional dielectric material layers, such that one of the bonding pads is electrically connected to the first vertically extending conductive path and the additional vertically extending conductive path.

[0006] An embodiment of the present invention provides a device structure comprising: a plurality of semiconductor devices located on a semiconductor substrate; a plurality of first metal interconnect structures located in a plurality of first dielectric material layers on the semiconductor devices, wherein a first group of first metal interconnect structures includes a first vertically extending conductive path, which includes at least one electrically active metal via structure located in a first via layer, and a second group of first metal interconnect structures includes at least one electrically floating metallized structure located in a frame-shaped region in a plan view, wherein at least one electrically active metal via structure is located in the central portion of the frame-shaped region in the plan view; and a plurality of bonding pads located on the first dielectric material layers and the first metal interconnect structures, wherein one of the bonding pads is electrically connected to the first vertically extending conductive path. Attached Figure Description

[0007] Figure 1A This is a top view of a first exemplary structure after forming a semiconductor device, a first dielectric material layer, a first metal interconnect structure, and an edge sealing ring structure, in one embodiment of the present invention, wherein the wafer contains an array of semiconductor grains.

[0008] Figure 1B The first exemplary structure along Figure 1A The first example of a vertical sectional view of a structure with vertical section B-B'.

[0009] Figure 1C for Figure 1AThe top view of region C of the first exemplary structure, and the illustration in Figure 1C shows Figure 1C A magnified view of the area in the image.

[0010] Figure 1D for Figure 1B An enlarged view of region D in the first exemplary structure.

[0011] Figures 2A to 2C This is a perspective view of the regions of a set of first metal interconnect structures (40, 140) forming a first conductive path and a plurality of electrically floating metallized structures in one embodiment of the present invention.

[0012] Figures 3A to 3L This is a perspective view of various configurations of the area surrounding a set of first metal interconnect structures after the formation of a first conductive path and an electrically floating metallized structure, according to various embodiments of the present invention.

[0013] Figure 4 This is a vertical cross-sectional view of the region of an exemplary structure after the formation of the second dielectric material layer and the second metal interconnect structure, as shown in one embodiment of the present invention.

[0014] Figure 5 This is a vertical cross-sectional view of an exemplary structure after the formation of the first dielectric passivation layer and the pad opening, as shown in one embodiment of the present invention.

[0015] Figure 6 This is a vertical cross-sectional view of an exemplary structure region after the bonding pad is formed, according to one embodiment of the present invention.

[0016] Figure 7 This is a vertical cross-sectional view of the region where an exemplary structure is formed and patterned after the second dielectric passivation layer and the third pad passivation layer are formed, according to one embodiment of the present invention.

[0017] Figure 8A This is a vertical cross-sectional view of an exemplary structure after the metallization pad under the bump is formed, according to one embodiment of the present invention.

[0018] Figure 8B for Figure 8A A top view of an exemplary structure.

[0019] Figure 8C for Figure 8A An enlarged view of region C, which is an example of the structure.

[0020] Figure 9 This is a vertical cross-sectional view of an exemplary structure following the bonding of solder material to the under-bump metallization pad in one embodiment of the present invention.

[0021] Figure 10 This is a vertical cross-sectional view of a semiconductor die in one embodiment of the present invention.

[0022] Figure 11 This is a vertical cross-sectional view of a first semiconductor package formed by attaching a semiconductor die to a packaging substrate, according to one embodiment of the present invention.

[0023] Figure 12 This is a vertical cross-sectional view of a portion of the first semiconductor package after the underfill material has been applied, according to one embodiment of the present invention.

[0024] Figure 13 This is a vertical cross-sectional view of a first semiconductor package after the reinforcing ring and cover structure are attached, according to one embodiment of the present invention.

[0025] Figure 14 This is a vertical cross-sectional view of a second semiconductor package assembly containing semiconductor grains and an interposer layer, according to one embodiment of the present invention.

[0026] Figure 15 This is a first flowchart of the process steps used to manufacture the apparatus structure in one embodiment of the present invention.

[0027] Figure 16 This is a second flowchart illustrating the sequence of process steps used in manufacturing the apparatus structure according to one embodiment of the present invention.

[0028] The attached figures are labeled as follows: B-B': Vertical section C,D: Areas ECP1, ECP2: Conductive paths FSA: Framed Area hd1: First horizontal direction hd2: Second horizontal direction LL1: First Line Layer LL2: Second Line Layer LL3: Third Line Layer LL4: Fourth Line Layer LL5: Fifth Line Layer VL1: First through-hole layer VL2: Second through-hole layer VL3: Third through-hole layer VL4: Fourth through-hole layer 10: Semiconductor substrate 20: Semiconductor devices 30: First dielectric material layer 38: Sealing ring 40,60: Electrically Active Metallization Structure 46,66: Electrically active metallic through-hole structure 48, 68: Electrically active metallic circuits 50: Second dielectric material layer 70: Dielectric passivation layer 72: First dielectric passivation layer 74: Second dielectric passivation layer 76: Third dielectric passivation layer 81: Pad opening 82,298: Joint pad 87: Opening 88: Under-bump metallization pad 92,699: Solder Material Section 100: Semiconductor die 105,605: Substrate material section 110: Semiconductor grain region 140: Electrically floating metallized structure 143: Electrically Floating Metallization Assembly 145: Metallized assembly of internal wiring within the frame 146: Electrically Floating Metal Through-Hole Structure 147: Scaffolded wall-shaped internal wiring metallization assembly 148: Electrically floating metal circuit 148S: Sidewall metal wiring 200: Packaging substrate 208: Substrate bump structure 220:Substrate body 299: Solder ball 301: Adhesive layer 310: Reinforced Ring 311: Second adhesive layer 320: Cover structure 321: Thermal interface material layer 600: Intermediary Layer 608: Intermediate Layer Bump Structure 620: Intermediary Layer Main Body 698: Intermediate Layer Joint Structure 900: Cutting Channel Area 1000: Wafer 1510, 1520, 1530, 1620, 1640, 1660: Steps Detailed Implementation

[0029] The following detailed description, accompanied by accompanying drawings, is provided to aid in understanding the embodiments of the present invention. Various structures of the units may not be drawn to scale. For clarity, some units may be omitted from the drawings.

[0030] The following provides numerous different embodiments or examples for implementing various features of the subject matter. Specific examples of components and configurations described below illustrate embodiments of the invention, and are for illustrative purposes only and not for limiting the scope of the invention. The drawings are not drawn to scale. Unless otherwise explicitly stated, elements having the same reference numerals are considered to have the same material composition and the same thickness range. Unless otherwise explicitly stated, it is assumed that all structures of the original embodiments exist in any derivative embodiments. Therefore, the structures described with reference to the relevant embodiments in the drawings and / or specification can support the structures of the embodiments. Unless otherwise explicitly stated, embodiments may implement any embodiment with repeated said elements. Embodiments may be implemented with omitted non-essential elements, even if these embodiments are not explicitly disclosed but are known in the art.

[0031] Furthermore, spatial relative terms such as “below,” “below,” “lower,” “above,” “higher,” or similar terms are used to describe the relationship between some elements or structures in the figures and another element or structure. If the entire volume of a first physical unit lies within a hypothetical volume defined by a set of hypothetical surfaces, and this set of hypothetical surfaces has the minimum total surface area selected from all hypothetical surfaces containing the entire outer surface of the second element and is topologically isomorphic to a sphere, then the first physical unit is “embedded” in the second physical unit. This set of hypothetical surfaces selects the outer surface with the smallest surface area from all possible sets of open surfaces to cover every opening (if any) in the outer surface. These spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the figures. When the device is rotated in different orientations (rotated 90 degrees or other orientations), the spatial relative adjectives used will also be interpreted according to the orientation after the rotation. Unless otherwise explicitly stated, elements with the same reference numerals are considered to have the same material composition and the same thickness range. Unless otherwise explicitly stated, each material portion is assumed to have a uniform material composition.

[0032] In the context of this description, if the rate of removal of the first material is at least three times greater than the rate of removal of the second material, then the method of removing the first material relative to the second material is "selective." Unless otherwise explicitly stated, selective removal of the first material relative to the second material means that the ratio of removal rates may be greater than or equal to 3.0 and / or 10 and / or 100 and / or 1,000. In the context of this description, if the second surface is located above or below the first surface, and there exists a vertical plane or substantially vertical plane containing both the first and second surfaces, then the first and second surfaces are "perpendicularly aligned" with each other. A vertical plane is a two-dimensional manifold containing a continuous set of infinitely many vertical lines and having a uniform one-dimensional horizontal cross-sectional shape that remains unchanged when translated along the vertical direction. When the uniform one-dimensional horizontal cross-sectional shape is a line, the vertical plane may be a Euclidean plane; when the uniform one-dimensional shape is not a line, the vertical plane may be a non-Euclidean plane. A substantially vertical line is a straight line with an angle of deviation from the vertical direction of less than 5 degrees. A substantially vertical plane is a two-dimensional manifold containing a continuous set of infinitely many substantially vertical lines and / or vertical lines.

[0033] Figure 1A This is a top view of a wafer 1000 after semiconductor devices and metal interconnect structures have been formed in the dielectric material on a semiconductor substrate. The wafer includes a two-dimensional array of semiconductor die regions 110 and dicing channel regions 900. The semiconductor die regions 110 are rectangular portions of the wafer 1000, which can be converted into semiconductor dies once the wafer 1000 is diced in subsequent process steps. The dicing channel regions 900 are lattice-shaped portions of the wafer 1000, and can be removed when the wafer 1000 is diced.

[0034] Figure 1B For along Figure 1A The first example of a vertical sectional view of a structure with vertical section B-B'. Figure 1C for Figure 1A The first example is a top view of region C in the exemplary structure. Figure 1C The illustration in the middle is Figure 1C A magnified view of the area in the image. Figure 1D for Figure 1B An enlarged view of region D in the first exemplary structure. (See attached image.) Figures 1B to 1D As shown, wafer 1000 includes a semiconductor substrate 10, which may be a commercially available semiconductor wafer such as a single-crystal wafer. Semiconductor devices 20 may be formed on the semiconductor substrate 10 in each region of the semiconductor die region 110. Semiconductor devices 20 may include any type of semiconductor device known in the art, such as field-effect transistors, capacitors, resistors, inductors, diodes, or the like.

[0035] A first dielectric material layer 30 and a first metal interconnect structure (40, 140) may be formed on the semiconductor device 20. The first dielectric material layer 30 includes interlayer dielectric materials known in the art, which may include undoped silicate glass, doped silicate glass (such as borosilicate glass, borophosphosilicate glass, or fluorosilicate glass, or the like), dielectric materials with a low dielectric constant of approximately 2.5 to 3.9, dielectric materials with an ultra-low dielectric constant of approximately 2.0 to 2.5, and / or dielectric materials with an extremely low dielectric constant of approximately 1.0 to 2.0. Exemplary low dielectric materials include fluorosilicate glass or organosilicon glass. Exemplary ultra-low dielectric materials include porous organosilicon glass and spin-coated organic polymers such as benzocyclobutene. Exemplary extremely low dielectric materials include air-gap structures, and these porous materials have a high gas content.

[0036] In one embodiment, a first metal interconnect structure (40, 140) may be formed in a first dielectric material layer 30. The first metal interconnect structure (40, 140) includes a first electrically active metallization structure 40 and an electrically floating metallization structure 140. The “electrically active” metallization structure described herein can be considered as a metallization structure electrically connected to at least one electrical node, configured to transmit and / or receive electrical signals and / or electrical bias voltages. The electrical connection can be via a conductive path, via intended capacitive coupling, or via intended inductive coupling. The “electrically isolated” metallization structure described herein can be considered as a metallization structure electrically isolated from any other electrical node except for unintended parasitic capacitive coupling and / or unintended parasitic inductive coupling. A sealing ring 38 may be formed around the perimeter of each region C.

[0037] The method for forming the first dielectric material layer 30 and the first metal interconnect structure (40, 140) can be a multiple sequence of metal interconnect formation processes. Each sequence may include a dielectric material deposition step (depositing individual first dielectric material layers 30), a dielectric material patterning step (patterning individual first dielectric material layers to form individual groups of voids), and a metallization structure formation step (depositing and patterning at least one metal to form individual groups of first metal interconnect structures (40, 140) in the individual groups of voids). In one embodiment, one or more and / or each first dielectric material layer 30 includes (and / or is substantially composed of) an individual dielectric material having an individual dielectric constant between 1.0 and 3.0. In another embodiment, one or more and / or each first dielectric material layer 30 includes (and / or is substantially composed of) an individual dielectric material having an individual dielectric constant between 1.0 and 2.0. In one embodiment, one or more and / or each of the first dielectric material layers 30 may comprise a vertical stack of porous dielectric materials (each having a dielectric constant between 1.0 and 2.0) and non-porous dielectric materials (each having a dielectric constant higher than that of the porous dielectric materials). In this embodiment, the volume ratio of porous dielectric material relative to the total volume of the individual first dielectric material layers 30 may be 30% to 90%, but smaller or larger volume ratios may also be used.

[0038] Each set of voids formed in the individual dielectric material patterning step may include circuit voids, via voids, and / or integrated circuit and via voids. As described above, the metallization step may each form metal circuits (48, 148), metal via structures (46, 146), and / or integrated metal circuit and via structures {(48, 46), (148, 146)}. The metal circuits (48, 148) include electrically active metal circuits 48 and electrically floating metal circuits 148. The metal via structures (46, 146) include electrically active metal via structures 46 and electrically floating metal via structures 146. In an embodiment employing integrated metal circuitry and via structure {(48,46), (148, 146)}, the integrated metal circuitry and via structure {(48, 46), (148, 146)} may include an electrically active integrated metal circuitry and via structure (48, 46) and an electrically floating integrated metal circuitry and via structure (148, 146).

[0039] In embodiments where the metal interconnect formation process sequence includes a single damascene process, a set of metal traces (48, 148) may be formed on the circuit layer, or a set of metal via structures (46, 146) may be formed on the via layer. In embodiments where the metal interconnect formation process sequence includes a dual damascene process, a set of integrated metal traces and via structures {(48, 46), (148, 146)} may be formed to extend on the circuit layer and via layer. Generally, the metal interconnect formation process sequence each forms a set of electrically active metal traces 48, a set of electrically active metal via structures 46, or a set of electrically active integrated metal traces and via structures (48, 46).

[0040] A set of electrically floating metal lines 148, a set of electrically floating metal via structures 146, and / or a set of electrically active integrated metal lines and via structures (148, 146) are formed in the topmost circuit layer (here regarded as the first circuit layer LL1) and the second circuit layer (here regarded as the second circuit layer LL2) from the top in the first dielectric material layer 30. Additional sets of electrically floating metal lines 148, additional sets of electrically floating metal via structures 146, and / or additional sets of electrically active integrated metal lines and via structures (148, 146) may be formed in the second via layer (here regarded as the second via layer VL2) from the top and the third circuit layer (here regarded as the third circuit layer LL3) from the top in the first dielectric material layer 30.

[0041] Generally, the electrically floating metallization structure 140 can be formed in the topmost 2N layer or the topmost (2N+1) layer, where N is a positive integer. In the embodiment where the electrically floating metallization structure 140 is formed in the topmost (2N) layer, the topmost 2N layer includes each circuit layer between the Nth circuit layer counted downwards from the top and the first circuit layer LL1, and each via layer between the Nth via layer counted downwards from the top and the first via layer VL1. In the embodiment where the electrically floating metallization structure 140 is formed in the topmost (2N+1) layer, the topmost (2N+1) layer includes each circuit layer between the (N+1)th circuit layer counted downwards from the top and the first circuit layer LL1, and each via layer between the (N)th via layer counted downwards from the top and the first via layer VL1. Although Figure 1C In the illustrated embodiment, the electrically floating metallized structure 140 is formed in the first circuit layer LL1, the first via layer VL1, the second circuit layer LL2, the second via layer VL2, and the third circuit layer LL3. The embodiment here explicitly envisions that the bottom layer of the electrically floating metallized structure 140 may be the second circuit layer LL2, the second via layer VL2, the third via layer VL3, the fourth circuit layer LL4, the fourth via layer VL4, the fifth circuit layer LL5, or any other lower layer.

[0042] In an embodiment of the invention, a first set of electrically active metallization structures 40 forms a first vertically extending conductive path ECP1. The first vertically extending conductive path ECP1 extends vertically through each layer through which the electrically floating metallization structure 140 extends vertically. In one embodiment, a two-dimensional array of the first vertically extending conductive paths ECP1 may be formed in each semiconductor die region 110. Some or all of the vertically extending conductive paths ECP1 may extend vertically through each first dielectric material layer 30 selected from the first dielectric material layer 30 and may be electrically connected to individual electrical nodes selected from the semiconductor device 20. In some embodiments, a semiconductor device or passive device may be embedded in a set of first dielectric material layers 30 beneath the layers of the electrically floating metallization structure 140, and a set of first vertically extending conductive paths ECP1 may be electrically connected to individual nodes of the semiconductor device or passive device embedded in the first dielectric material layer 30.

[0043] In one embodiment of the invention, the first metal interconnect structure (40, 140) of the second group includes at least one electrically floating metallization structure 140 formed around the continuous electrically active metallization structure 40 of the individual group (which defines the upper portion of the individual first vertically extending conductive path ECP1). In one embodiment, at least one electrically floating metallization structure 140 around the continuous electrically active metallization structure 40 of the individual group may be formed in the individual frame region. In this embodiment, the upper portion of the individual first vertically extending conductive path ECP1 may be formed entirely in the region defined by the inner periphery of the frame region.

[0044] The "frame-shaped region" described herein can be considered as the area between the inner perimeter and the outer perimeter, with the outer perimeter laterally offset outward from the inner perimeter. The lateral offset distance between the inner and outer perimeters may be the same or different. The shapes of the inner and outer perimeters can be any two-dimensional shape with a single closed perimeter. In one embodiment of the invention, the upper portion of each individual first vertically extending conductive path ECP1 includes at least one electrically active metal via structure 46, and each of the at least one electrically active metal via structure 46 is completely formed within the inner perimeter of the frame-shaped region FSA in the plan view.

[0045] In one embodiment, the upper portion of a particular first vertical conductive path ECP1 may include a first electrically active metal via structure 46 formed in a first via layer VL1 (which is the topmost via layer of the first dielectric material layer 30), and may optionally include a second electrically active metal via structure 46 formed in a second via layer VL2 (below the first via layer VL1), and may optionally include one or more additional electrically active metal via structures 46 formed below the second via layer.

[0046] Figures 2A to 2C This is a perspective view of the region surrounding a set of first metal interconnect structures (140, 40) when a first conductive path ECP1 is formed and an electrically floating metallized structure 140 is formed therearound it, according to one embodiment of the present invention.

[0047] like Figure 2A As shown, after forming the first dielectric material layer 30 for use as a circuit layer (selected as the third circuit layer from the top circuit layer among all the circuit layers in the set of first dielectric material layers 30 to be formed), the region surrounding the upper portion of the first conductive path ECP1 is formed. The third circuit layer from the top circuit layer can be regarded here as the third circuit layer LL3. The first electrically active metal line 48 and a plurality of electrically floating metal lines 148 may be formed in the first dielectric material layer in the third circuit layer LL3.

[0048] like Figure 2B As shown, at least one additional first dielectric material layer 30 can be deposited for use as a via layer and for use as an additional wiring layer. The via layer may be the second via layer counting from the top via layer in a set of all first dielectric material layers 30 to be formed, which can be regarded here as the second via layer VL2. The additional wiring layer may be a wiring layer selected from a set of all first dielectric material layers 30 to be formed, which may be the second wiring layer counting from the top wiring layer. The second wiring layer counting from the top wiring layer can be regarded here as the second wiring layer LL2. The first electrically active metal line 48, the first electrically active metal via structure 46, the plurality of electrically floating metal lines 148, and the plurality of electrically floating metal via structures 146 may be formed in at least one additional first dielectric material layer 30 in the second via layer VL2 and the second wiring layer LL2.

[0049] like Figure 2C As shown, at least one additional first dielectric material layer 30 may be deposited for use as a via layer and for use as an additional wiring layer. The via layer may be the topmost via layer in a set of all first dielectric material layers 30 to be formed, and is here regarded as the first via layer VL1. The additional wiring layer may be the topmost wiring layer selected from a set of all first dielectric material layers 30 to be formed. The topmost wiring layer is here regarded as the first wiring layer LL1. A first electrically active metal line 48, a first electrically active metal via structure 46, a plurality of electrically floating metal lines 148, and a plurality of electrically floating metal via structures 146 may be formed in at least one additional first dielectric material layer 30 in the first via layer VL1 and the first wiring layer LL1.

[0050] A frame-shaped region FSA can be defined based on the area surrounding a set of electrically floating metallized structures 140 around the upper portion of the first conductive path ECP1 (which contains the first electrically active metallized via structure 46). Specifically, the frame-shaped region FSA can be defined as all areas containing the set of electrically floating metallized structures 140 around the first conductive path ECP1 in a planar view (i.e., the attached figure from a vertical perspective), excluding the areas of all electrically active metallized via structures 46 formed on and above the third circuit layer LL3 in the upper portion of the first conductive path ECP1.

[0051] In embodiments where the first electrically active metallization structure 40 and the electrically floating metallization structure 140 include a first sidewall parallel to a first horizontal direction hd1 and a second sidewall parallel to a second horizontal direction hd2, the frame-shaped region FSA may be a rectangular frame-shaped region containing an outer rectangular perimeter and an inner rectangular perimeter. In one embodiment, the frame-shaped region may have an outer rectangular perimeter that conforms to a set of sidewalls of at least one electrically floating metallization structure 140. The frame-shaped region FSA may also include an inner rectangular perimeter that conforms to at least one vertically extending edge of at least one electrically floating metallization structure 140. All regions of at least one electrically floating metallization structure 140 may be formed in the frame-shaped region FSA. The first electrically active metallization via structure 46 may be laterally offset inward from the inner rectangular perimeter of the frame-shaped region FSA.

[0052] Figures 3A to 3L This is a perspective view of various configurations of the area surrounding a set of first metal interconnect structures (40, 140) after forming the first conductive path ECP1 and the electrically floating metallized structure 140, according to various embodiments of the present invention.

[0053] Figure 3A This represents a first configuration of a first conductive path ECP1 and at least one electrically floating metallized structure 140. The at least one electrically floating metallized structure 140 may include multiple electrically floating metallized structures 140 separated from each other. In the first configuration, the at least one electrically floating metallized structure 140 is formed as a plurality of electrically floating metallized assemblies 143, each including an electrically floating metal via structure 146 located in a first via layer VL1, a first electrically floating metal line 148 located in a first line layer LL1, a second electrically floating metal line 148 located in a second line layer LL2, additional electrically floating metal via structures 146 located, as appropriate, in the second via layer VL2, and individual vertical stacks of additional electrically floating metal lines 148 located in a third line layer LL3. In one embodiment, the plurality of electrically floating metallized assemblies 143 may each be located in individual corner regions of a frame-shaped region FSA in a plan view.

[0054] Generally, all electrically active metal via structures 46 in the first electrically active metallization structure 40 of the first conductive path ECP1 in the layer of at least one electrically floating metallization structure 140 are completely located within the inner periphery of the individual frame-shaped region FSA. Electrically active metal lines 48 in the first electrically active metallization structure 40 of the first conductive path ECP1 in the layer of at least one electrically floating metallization structure 140 may be completely located within the inner periphery of the individual frame-shaped region FSA. Electrically active metal lines 48 in the first electrically active metallization structure 40 of the first conductive path ECP1 in the layer of at least one electrically floating metallization structure 140 may be partially located within the frame-shaped region FSA and may be partially located outside the outer periphery of the frame-shaped region FSA. In other words, the electrically active metal lines 48 may extend laterally into the frame-shaped region FSA and / or may extend outside the outer periphery of the frame-shaped region FSA.

[0055] Figure 3B A second arrangement is provided for the first conductive path ECP1 and at least one electrically floating metallization structure 140. The second arrangement may be derived from the first arrangement, forming sidewall metal lines 148S along the periphery of the frame-shaped region FSA. The sidewall metal lines 148S are additional electrically floating metal lines 148 that extend laterally along a first horizontal direction hd1 or a second horizontal direction hd2 and are formed on a circuit layer such as a first circuit layer LL1, a second circuit layer LL2, or a third circuit layer LL3. In one embodiment, the frame-shaped region FSA may include a rectangular frame-shaped region, and the at least one electrically floating metallization structure 140 may include a plurality of sidewall metal lines 148S arranged laterally and separated from each other along the sides of the outer rectangular periphery of the frame-shaped region FSA in a plan view.

[0056] Figure 3C A third arrangement is provided for the first conductive path ECP1 and at least one electrically floating metallized structure 140. The third arrangement includes a frame-shaped interconnect metallized assembly 145 extending around the periphery of the frame-shaped region FSA in the plan view. The frame-shaped interconnect metallized assembly 145 is a set of continuous electrically floating metallized structures 140, which includes a pair of first electrically floating metal lines 148 extending laterally along a first horizontal direction hd1, and a pair of second electrically floating metal lines 148 extending laterally along a second horizontal direction hd2.

[0057] Generally, a pair of first electrically floating metal lines 148 extending laterally along the first horizontal direction hd1 and a pair of second electrically floating metal lines 148 extending laterally along the second horizontal direction hd2 can be located in the same circuit layer or different circuit layers. In the example described, the pair of first electrically floating metal lines 148 extending laterally along the first horizontal direction hd1 can be formed in the first circuit layer LL1, while the pair of second electrically floating metal lines 148 extending laterally along the second horizontal direction hd2 can be formed in the second circuit layer LL2. In one embodiment, the frame-shaped interconnect metallization assembly 145 may further include four electrically floating metal via structures 146. The electrically floating metal via structures 146 can each connect an individual first electrically floating metal line 148 in the first circuit layer LL1 to an individual second electrically floating metal line 148 in the second circuit layer LL2. The frame-shaped interconnect metallization assembly 145 is a continuous frame structure located around the periphery of the frame-shaped region FSA and can span multiple circuit layers. Separate first electrically floating metal lines 148 may be provided in the corner areas of the frame-shaped region FSA. In addition, sidewall metal lines (not shown) may exist along one or more sides of the frame-shaped region FSA in the plan view.

[0058] Figure 3D A fourth arrangement is provided for the first conductive path ECP1 and at least one electrically floating metallized structure 140. The fourth arrangement includes a frame-shaped interconnect metallized assembly 145 extending around the periphery of the frame-shaped region FSA in the plan view. The frame-shaped interconnect metallized assembly 145 is a group of continuous electrically floating metallized structures 140, which includes three or more pairs of first electrically floating metal lines 148. Each pair of electrically floating metal lines 148 may extend laterally along a first horizontal direction hd1 or a second horizontal direction hd2.

[0059] In the illustrated example, a pair of first electrically floating metal lines 148 extend laterally along a first horizontal direction hd1 and may be formed in a first circuit layer LL1. A pair of second electrically floating metal lines 148 extend laterally along a second horizontal direction hd2 and may be formed in a second circuit layer LL2. A pair of third electrically floating metal lines 148 extend laterally along the first horizontal direction hd1 and may be formed in a third circuit layer LL3. In one embodiment, the frame-shaped interconnect metallization assembly 145 may further include electrically floating metal via structures 146 to provide vertical structural connections to the electrically floating metal lines 148. The frame-shaped interconnect metallization assembly 145 is a continuous frame structure located around the periphery of the frame-shaped region FSA and may span multiple circuit layers.

[0060] Figure 3EA fifth arrangement is provided for the first conductive path ECP1 and at least one electrically floating metallized structure 140. The fifth arrangement includes at least one scaffolded inline interconnect metallized assembly 147 located on individual sides of the frame-shaped region FSA in the plan view, extending vertically over at least two wiring layers (potentially at least three wiring layers). Each scaffolded inline interconnect metallized assembly 147 may be located between adjacent paired sides of the inner periphery of the rectangular frame region and sides of the outer periphery of the rectangular frame region. Each scaffolded inline interconnect metallized assembly 147 may be a separate group of continuous electrically floating metallized structures 140, comprising two or more first electrically floating metal lines 148. In the fifth arrangement, the first electrically active metal lines 48 may be entirely located within the inner periphery of the frame-shaped region FSA in the plan view. For example, the first electrically active metal lines 48 of the second wiring layer LL2 may be entirely located within the inner periphery of the frame-shaped region FSA in the plan view.

[0061] Figure 3F A sixth arrangement is provided for the first conductive path ECP1 and at least one electrically floating metallized structure 140. The sixth arrangement may be derived from the fifth arrangement, which forms a sidewall metal line 148S along the periphery of the frame-shaped region FSA.

[0062] Figure 3G A seventh configuration is provided for the first conductive path ECP1 and at least one electrically floating metallized structure 140. The seventh configuration includes a frame-shaped interconnect metallized assembly 145 extending over two circuit layers and a via layer. The seventh configuration may also include separate first electrically floating metal lines 148 formed in the corner regions of the frame-shaped region FSA. In the seventh configuration, the first electrically active metal lines 48 may be entirely located within the inner periphery of the frame-shaped region FSA in the plan view. For example, the first electrically active metal lines 48 of the second circuit layer LL2 may be entirely located within the inner periphery of the frame-shaped region FSA in the plan view.

[0063] Figure 3H An eighth configuration is provided for the first conductive path ECP1 and at least one electrically floating metallized structure 140. The eighth configuration includes a frame-shaped interconnect metallized assembly 145 extending over three circuit layers and two via layers. In this eighth configuration, the first electrically active metallized line 48 may be entirely located within the inner periphery of the frame-shaped region FSA in the plan view. For example, the first electrically active metallized line 48 of the second circuit layer LL2 may be entirely located within the inner periphery of the frame-shaped region FSA in the plan view.

[0064] Figure 3IA ninth arrangement is provided for the first conductive path ECP1 and at least one electrically floating metallized structure 140. The ninth arrangement includes a frame-shaped interconnect metallized assembly 145 extending around the periphery of the frame-shaped region FSA in the plan view. The frame-shaped interconnect metallized assembly 145 is a group of continuous electrically floating metallized structures 140, containing a pair of first electrically floating metal lines 148 extending laterally along a first horizontal direction hd1, and a pair of second electrically floating metal lines 148 extending laterally along a second horizontal direction hd2. In the ninth arrangement, the first electrically active metal lines 48 on the bottom surface of the frame-shaped interconnect metallized assembly may each be entirely located within the inner periphery of the frame-shaped region FSA in the plan view. In one embodiment, the frame-shaped interconnect metallized assembly 145 includes three or more pairs of first electrically floating metal lines 148. Each pair of electrically floating metal lines 148 may extend laterally along either the first horizontal direction hd1 or the second horizontal direction hd2.

[0065] In an exemplary example, a pair of first electrically floating metal lines 148 extend laterally along a first horizontal direction hd1 and may be formed in a first circuit layer LL1. A pair of second electrically floating metal lines 148 extend laterally along a second horizontal direction hd2 and may be formed in a second circuit layer LL2. A pair of third electrically floating metal lines 148 extend along the first horizontal direction hd1 and may be formed in a third circuit layer LL3. In one embodiment, the frame-in-frame interconnect metallization assembly 145 may further include electrically floating metal via structures 146 to provide vertical structural connections to the electrically floating metal lines 148. The frame-in-frame interconnect metallization assembly 145 is a continuous frame structure located around the periphery of the frame-shaped region FSA and may span multiple circuit layers. The electrically active metal lines 48 in the first electrically active metallization structure 40 in the first conductive path ECP1 in the layer of at least one electrically floating metallization structure 140 may be located entirely within the inner periphery of the individual frame-shaped region FSA.

[0066] Figure 3J A tenth arrangement is provided for the first conductive path ECP1 and at least one electrically floating metallization structure 140. This tenth arrangement may be derived from the ninth arrangement, for example, by forming sidewall metal lines 148S along the periphery of the frame-shaped region FSA. The sidewall metal lines 148S are additional electrically floating metal lines 148 extending laterally along a first horizontal direction hd1 or a second horizontal direction hd2, and are formed on a circuit layer such as a first circuit layer LL1, a second circuit layer LL2, or a third circuit layer LL3. In one embodiment, the frame-shaped region FSA may include a rectangular frame-shaped region, and at least one electrically floating metallization structure 140 may include a plurality of sidewall metal lines 148S, which are arranged laterally and separated from each other along the sides of the outer rectangular periphery of the frame-shaped region FSA in the plan view.

[0067] Figure 3K An eleventh arrangement is provided for the first conductive path ECP1 and at least one electrically floating metallized structure 140. The eleventh arrangement includes a frame-shaped interconnect metallized assembly 145 extending around the periphery of the frame-shaped region FSA in the plan view. The frame-shaped interconnect metallized assembly 145 is a group of continuous electrically floating metallized structures 140, which includes at least one pair of first electrically floating metal lines 148 extending laterally along a first horizontal direction hd1, and at least one pair of second electrically floating metal lines 148 extending laterally along a second horizontal direction hd2.

[0068] In one embodiment, multiple pairs of first electrically floating metal lines 148 extend laterally along a first horizontal direction hd1 and may be located in multiple circuit layers; and / or multiple pairs of second electrically floating metal lines 148 extend along a second horizontal direction hd2 and may be located in multiple circuit layers. In this embodiment, the first pair of first electrically floating metal lines 148 extends laterally along the first horizontal direction hd1 and may be formed in the first circuit layer LL1. The second pair of first electrically floating metal lines 148 extends laterally along the first horizontal direction hd1 and may be formed in the second circuit layer LL2. The first pair of second electrically floating metal lines 148 extends laterally along the second horizontal direction hd2 and may be formed in the first circuit layer LL1. The second pair of second electrically floating metal lines 148 extends laterally along the second horizontal direction hd2 and may be formed in the second circuit layer LL2. In one embodiment, the frame-shaped interconnect metallization assembly 145 may further include multiple electrically floating metal via structures 146. The electrically floating metal via structure 146 can each connect an individual first electrically floating metal line 148 to an individual second electrically floating metal line 148 in a different layer. The frame-shaped interconnect metallization assembly 145 is a continuous frame-shaped structure located around the periphery of the frame-shaped region FSA and can span multiple circuit layers. Separate first electrically floating metal lines 148 can be provided in the corner regions of the frame-shaped region FSA. In addition, the sidewall metal lines 148S can be along one or more sides of the frame-shaped region FSA in the plan view.

[0069] Figure 3L A twelfth arrangement is provided for the first conductive path ECP1 and at least one electrically floating metallized structure 140. The twelfth arrangement includes a frame-shaped interconnect metallized assembly 145 extending over three circuit layers and two via layers. In the twelfth arrangement, a first electrically active metal line 48 located on the bottom surface of the frame-shaped interconnect metallized assembly can each be completely located within the inner periphery of the frame-shaped region FSA in the plan view. For example, the first electrically active metal line 48 in the first circuit layer LL1, the second electrically active metal line 48 in the second circuit layer LL2, and the third electrically active metal line 48 in the third circuit layer LL3 can be completely located within the inner periphery of the frame-shaped region FSA in the plan view.

[0070] like Figures 1A to 3L As shown, the first metal interconnect structure (40, 140) includes a first electrically active metallization structure 40 and an electrically floating metallization structure 140. The first electrically active metallization structure 40 may include an electrically active metal via structure 46 and an electrically active metal line 48. The first set of first metal interconnect structures (40, 140) may include a first vertically extending conductive path ECP1, which includes the first electrically active metal via structure 46 in the first via layer VL1. The second set of metal interconnect structures (40, 140) includes at least one electrically floating metallization structure 140 formed in the frame-shaped region in the plan view. At least one electrically active metal via structure 46 may be located within the inner periphery of the frame-shaped region in the plan view.

[0071] In one embodiment, the frame region may be a rectangular frame region, including an outer frame perimeter that aligns with a set of sidewalls of at least one electrically floating metallized structure 140. The rectangular frame region may also include an inner rectangular perimeter that aligns with at least one vertically extending edge of the at least one electrically floating metallized structure 140. All regions of the at least one electrically floating metallized structure 140 may be formed within the rectangular frame region. A first electrically active metal via structure 46 may be laterally offset inward from the inner rectangular perimeter of the rectangular frame region.

[0072] The electrically floating metallization structure 140 may include a group of consecutive metallization structures extending vertically over at least two circuit layers. In one embodiment, the at least two circuit layers include a first circuit layer LL1 located on a first via layer VL1, and a second circuit layer LL2 located below the first via layer VL1. In another embodiment, at least one electrically floating metallization structure 140 includes a plurality of electrically floating metallization structures 140 separated from each other.

[0073] At least one electrically floating metallized structure 140 may include a frame-shaped interconnect metallized assembly 145 extending around the periphery of a rectangular frame region in a plan view. In one embodiment, the frame-shaped interconnect metallized assembly 145 includes a pair of first electrically floating metal lines 148 extending laterally along a first horizontal direction hd1; and a pair of second electrically floating metal lines 148 extending laterally along a second horizontal direction hd2. In one embodiment, the pair of first electrically floating metal lines 148 is formed in a wiring layer such as a first wiring layer LL1. The pair of second electrically floating metal lines 148 may be formed in another wiring layer such as a second wiring layer LL2. The frame-shaped interconnect metallized assembly 145 may further include four electrically floating metal via structures 146 to connect individual pairs of first and second electrically floating metal lines 148 in combinations of pairs of first and second electrically floating metal lines 148. In one embodiment, the frame-shaped interconnect metallization assembly 145 includes at least one first electrically floating metal line 148 in the first circuit layer LL1, at least one first electrically floating metal via structure 146 in the first via layer VL1, at least one second electrically floating metal line 148 in the second circuit layer LL2, at least one second electrically floating metal via structure 146 in the second via layer VL2, and at least one third electrically floating metal line 148 in the third circuit layer LL3.

[0074] In one embodiment, at least one electrically floating metallized structure 140 includes a plurality of sidewall metal lines 148S, which are arranged along the sides of the outer rectangular periphery of a rectangular frame region in the plan view and are laterally separated from each other. In one embodiment, a first electrically active metal line 48 and a second electrically active metal line 48 may be completely formed in the outer periphery of the rectangular frame region in the plan view. In one embodiment, the first electrically active metal line 48 and the second electrically active metal line 48 may extend laterally into the frame region FSA in the plan view and / or extend outward from the outer periphery of the frame region FSA.

[0075] like Figure 4 As shown, a second dielectric material layer 50 and an additional metal interconnect structure are then formed on top of the first dielectric material layer 30 and the first metal interconnect structure (40, 140). In the following description and / or claims, the additional metal interconnect structure may be considered as an upper metal interconnect structure or a second metal interconnect structure. As mentioned above, ordinal numbers such as "first" and "second" are merely adjectives and not part of the unit name.

[0076] The second dielectric layer 50 may include and / or is primarily composed of and / or substantially composed of non-porous silicate glass material having an individual dielectric constant of 3.4 to 3.9. For example, the second dielectric layer 50 may include and / or is primarily composed of and / or substantially composed of undoped silicate glass or doped silicate glass (such as borosilicate glass, borophosphosilicate glass, or fluorosilicate glass). The total number of circuit layers in the second dielectric layer 50 may be 1 to 6, for example 2 to 3. If the dielectric material occupies more than 50% of the total volume of the material layer, the material layer may be considered to be primarily composed of dielectric material.

[0077] The second metal interconnect structure in the second dielectric material layer 50 includes a second electrically active metallization structure 60, which constitutes a component of an individual second conductive path ECP2. The second electrically active metallization structure 60 may include a second electrically active metal line 68 (which can also be regarded as an upper electrically active metal line 68) and a second electrically active metal via structure 66 (which can also be regarded as an upper electrically active metal via structure).

[0078] In one embodiment of the present invention, after forming a second dielectric material layer 50 containing a second electrically active metallization structure 60, each of the electrically floating metallization structures 140 formed in the first dielectric material layer 30 is electrically floating. In one embodiment, the topmost surface of the electrically floating metallization structure 140 does not extend above the horizontal plane containing the interface between the first dielectric material layer 30 and the second dielectric material layer 50. In one embodiment, the bottommost surface of the electrically floating metallization structure 140 contacts the individual underlying first dielectric material layer 30. In one embodiment, all surfaces of the electrically floating metallization structure 140 may contact the first dielectric material layer 30, the second dielectric material layer 50, or another electrically floating metallization structure 140.

[0079] like Figure 5 As shown, a first dielectric passivation layer 72 can be formed on the second dielectric material layer 50. The dielectric material included in the first dielectric passivation layer 72 can effectively block the diffusion of hydrogen, moisture, and metallic impurities. For example, the first dielectric passivation layer 72 may include (and / or be composed of) silicon nitride or silicon carbonitride. The first dielectric passivation layer 72 can be formed by chemical vapor deposition. The thickness of the first dielectric passivation layer 72 can be from 200 nm to 2000 nm, but smaller or larger thicknesses are also possible. A pad opening 81 can be formed to pass through the first dielectric passivation layer 72 on the topmost second electrically active metal line 68 of the second conductive path ECP2.

[0080] like Figure 6As shown, at least one metallization material can be deposited on the first dielectric passivation layer 72, and the metallization material can be patterned to form an array of bonding pads 82. The at least one metallization material may comprise a combination of at least one metallization pad material and at least one highly conductive metal. Exemplary metallization pad materials include titanium nitride, tantalum nitride, tungsten nitride, and / or molybdenum nitride. Exemplary highly conductive metals include copper, aluminum, or alloys thereof. The deposition method for the at least one metallization pad material can be physical vapor deposition or chemical vapor deposition, and its thickness can be from 20 nm to 200 nm, but smaller or larger thicknesses are also possible. The deposition method for the at least one highly conductive metal can be physical vapor deposition or chemical vapor deposition, and its thickness can be from 500 nm to 5000 nm, but smaller or larger thicknesses are also possible.

[0081] At least one metallization material of the patternable bonding pad 82 is provided, and the patterning method may involve applying a photoresist layer with a photolithography pattern onto the deposited at least one metallization material, and transferring the pattern in the photoresist layer through the at least one metallization material using at least one etching process, wherein the etching process may include at least one anisotropic etching process. The patterned photoresist layer can then be removed, and the removal method may be ashing. The retained portion of the at least one metallization material constitutes the bonding pad 82. In one embodiment, the bonding pad 82 may be a two-dimensional periodic array of bonding pads 82. The lateral dimensions (such as width and length, or diameter) of the bonding pad 82 may be from 20 micrometers to 200 micrometers, but smaller or larger lateral dimensions may also be used. The bonding pad 82 may be designed to conform to subsequent controlled-collapse wafer interconnect bonding processes. In some embodiments, the bonding pad 82 may be circular to facilitate consistent solder wetting and bump formation. In other examples, the bonding pad 82 may be square or rectangular to maximize the bonding area in the feasible space on the wafer surface.

[0082] like Figure 7 As shown, a second dielectric passivation layer 74 can be formed on the bonding pad 82 and the first dielectric passivation layer 72. The second dielectric passivation layer 74 includes a dielectric material that effectively blocks the diffusion of hydrogen, moisture, and metallic impurities. For example, the second dielectric passivation layer 74 may include silicon nitride or silicon carbonitride. For example, the second dielectric passivation layer 74 can be formed by chemical vapor deposition. The thickness of the second passivation dielectric layer 74 can be from 200 nm to 2000 nm, but smaller or larger thicknesses are also possible. An opening can be formed through the central portion of the second dielectric passivation layer 74 of each bonding pad 82, and the formation method can be a combination of photolithography and anisotropic etching processes.

[0083] A third dielectric passivation layer 76 may be formed on the second dielectric passivation layer 74. The third dielectric passivation layer 76 comprises and / or is substantially composed of at least one polymer dielectric material (such as polyimide, benzocyclobutene, or polybenzoxazole). The third dielectric passivation layer 76 may be formed by spin coating, spraying, or other suitable deposition methods. The thickness of the third dielectric passivation layer 76 may be from 1 micrometer to 20 micrometers, but smaller or larger thicknesses are also possible. An opening 87 may be formed through the third dielectric passivation layer 76 on the central portion of each bonding pad 82, and the formation method may be a combination of photolithography patterning and anisotropic etching processes.

[0084] like Figures 8A to 8C As shown, under-bump metallization pads 88 may be formed in each opening 87 on the bonding pad 82. For example, a layered stack of under-bump metallization material layers may be deposited over the physically exposed upper surface portion of the bonding pad 82 and over the dielectric passivation layer 70. The layered stack of under-bump metallization material layers may include multiple metallization layers with different compositions and functions. For example, the layered stack may include an adhesive layer, a diffusion barrier layer, and a wetting layer. The adhesive layer may include materials such as titanium, chromium, or tantalum, and its thickness may be from 10 nm to 100 nm. The diffusion barrier layer may include materials such as titanium nitride, tantalum nitride, or tungsten nitride, and its thickness may be from 20 nm to 200 nm. The wetting layer may include materials such as copper, nickel, or gold, and its thickness may be from 50 nm to 500 nm.

[0085] Various deposition methods can be used to deposit the metallization layer under the bump. For example, physical vapor deposition methods such as sputtering or evaporation can be used. Chemical vapor deposition or atomic layer deposition methods can be used instead or additionally. Electroless or electroplating processes can also be used instead or additionally to deposit these layers, especially the wetted layer.

[0086] The under-bump metallization layer can then be patterned to form an under-bump metallization pad 88. For example, a photoresist layer (not shown) can be applied to the deposited under-bump metallization layer, and the photoresist layer can be photolithographically patterned. One or more etching processes can then be performed to transfer the pattern in the photoresist layer to the underlying under-bump metallization layer. The etching processes may include wet etching, dry etching, or a combination thereof, depending on the etched material and the desired profile of the under-bump metallization pad 88. The photoresist layer can then be removed using a photoresist stripping solution or a plasma ashing process.

[0087] The lateral dimension of the under-bump metallization pad 88 can be larger than the lateral dimension of the opening 87 in the third dielectric passivation layer 76. Therefore, the peripheral regions of each under-bump metallization pad 88 can partially overlap with the peripheral regions of the third dielectric passivation layer 76 and the second dielectric passivation layer 74 on the bonding pad 82. The thickness of the under-bump metallization pad 88 can be from 0.5 micrometers to 5 micrometers, but smaller or larger thicknesses are also possible.

[0088] like Figure 9 As shown, solder material portions 92 can be applied to each under-bump metallization pad 88. Thus, a two-dimensional array of solder material portions 92 can be formed on a two-dimensional array of under-bump metallization pads 88 (which may be a two-dimensional array of controllable die bonding pads).

[0089] like Figure 10 As shown, a semiconductor substrate 10 of wafer 1000 can be thinned from the back side. The method for thinning the semiconductor substrate 10 can be grinding, polishing, isotropic etching, and / or anisotropic etching. The thickness of the semiconductor substrate 10 after the thinning process can be from 10 micrometers to 60 micrometers, but smaller or larger thicknesses can also be used.

[0090] The wafer 1000 can then be diced along the dicing channel. During the dicing process, material can be removed from the dicing channel region 900. The separated portions of the wafer 1000 after the dicing process include material from the semiconductor die regions 110. Each of the semiconductor die regions 110 retained after the dicing process constitutes a semiconductor die 100.

[0091] Generally, wafer 1000 includes a passivation layer stack, a first dielectric material layer 30, a metal interconnect structure (40, 140), a semiconductor device 20, and a semiconductor substrate 10. After forming the under-bump metallization pad 88, wafer 1000 can be diced along a dicing channel into a plurality of semiconductor dies 100. Each semiconductor die 100 includes a diced portion of the semiconductor substrate 10, which can be regarded here as the semiconductor substrate 10 of the semiconductor die 100.

[0092] like Figure 11As shown, a semiconductor die 100 can be bonded to a package substrate 200. Generally, the package substrate is package substrate 200, which can be any type of package substrate known in the art. For example, package substrate 200 can be a core package substrate, a coreless package substrate, or a ceramic package substrate. Package substrate 200 can be modified to include an integrated package-on-a-system substrate (containing a redistribution layer and / or an interlayer dielectric layer) and at least one buried interposer (such as a silicon interposer). Package substrate 200 includes a substrate body 220, a two-dimensional array of substrate bump structures 208 located proximal to the substrate body 220, and a two-dimensional array of bonding pads 298 (such as control collapse die connection bonding pads) located distal to the substrate body 220. The two-dimensional array of substrate bump structures 208 and the two-dimensional array of under-bump metallization pads 88 may have the same spacing.

[0093] An array of solder material portions 92 can be placed on a two-dimensional array of substrate bump structures 208, and the solder material portions 92 can be reflowed to bond the semiconductor die 100 to the package substrate 200. The semiconductor die 100 can be any of the semiconductor dies described above. A bonding assembly of the semiconductor die 100 and the package substrate 200 is provided.

[0094] like Figure 12 As shown, an underfill material can be applied around the array of solder material portions 92 to form an underfill material portion 105. Mechanical stress generated during the application of the underfill material may be applied to the semiconductor die 100, and the electrically floating metallized structure 140 formed in the first dielectric material layer 30 can deform and / or displace to partially absorb the aforementioned mechanical stress. Therefore, the deformation and / or displacement of the first electrically active metallized structure 40 in the first dielectric material layer 30 can be reduced.

[0095] like Figure 13 As shown, an adhesive layer 301 can be applied to the proximal horizontal surface of the package substrate 200. A reinforcing ring 310 can be bonded to the first adhesive layer 301. A second adhesive layer 311 can be applied to the upper surface of the reinforcing ring 310. A thermal interface material layer 321 can be applied to the back side of the semiconductor substrate 10. A cap structure 320 can be bonded to the second adhesive layer 311 and the thermal interface material layer 321. Solder balls 299 can be bonded to bonding pads 298. A first semiconductor package is provided.

[0096] like Figure 14In the second semiconductor package shown, the interposer 600 is bonded to the semiconductor die 100 before being bonded to the package substrate 200. The interposer 600 may include an organic interposer, a semiconductor interposer, a ceramic interposer, or any other type of interposer known in the art. The interposer 600 includes an interposer body 620, an array of interposer bump structures 608 located proximal to the interposer body 620 and having the same spacing as the array of under-bump metallization pads 88, and a two-dimensional array of interposer bonding structures 698 located distal to the interposer body 620 and having the same spacing as the two-dimensional array of substrate bump structures 208.

[0097] In this embodiment, the semiconductor die 100 can be bonded to the interposer 600 via an array of solder material portions 92 (which can be bonded by reflow and recuring), and an underfill portion 105 can be applied around the array of solder material portions 92. As described above, the mechanical stress generated by applying the underfill material will be applied to the semiconductor die 100, and the electrically floating metallized structure 140 embedded in the first dielectric layer 30 can deform and / or displace to partially absorb the mechanical stress. The assembly of the semiconductor die 100 and the interposer 600 can then be bonded to the package substrate 200 via an array of solder material portions 699. Additional underfill portions 605 can be formed around an additional array of solder material portions 699. Mechanical stabilizing structures (310, 320) can then be bonded to the package substrate 200 and the semiconductor die 100.

[0098] Figure 15 The first sequence of process steps used to form the device structure.

[0099] like Figures 1A to 1D As shown, step 1510 can form a plurality of semiconductor devices 20 on the semiconductor substrate 10.

[0100] like Figures 1A to 3LAs shown, in step 1520, after forming multiple semiconductor devices, a multiple sequence of metal interconnect formation processes is performed. Each sequence of metal interconnect formation processes includes an individual dielectric material deposition process, which deposits an individual dielectric material layer; an individual dielectric patterning process, which forms an individual plurality of voids in an individual dielectric material layer; and an individual metal deposition and patterning process, which forms an individual plurality of first metal interconnect structures (40, 140) in an individual void. The first group of first metal interconnect structures (40, 140) formed by the multiple sequence includes a first vertically extending conductive path ECP1, which includes at least one first electrically active metal via structure 46 formed in a first via layer VL1. The second group of first metal interconnect structures (40, 140) includes at least one electrically floating metallized structure 140 formed in a frame-shaped region FSA in the plan view. At least one electrically active metal via structure is formed within the inner periphery of the frame-shaped region in the plan view.

[0101] In one embodiment, the dielectric material layer deposited during multiple sequences (such as the first dielectric material layer 30) comprises individual dielectric materials, each having a dielectric constant greater than 1.0 and less than 3.0. In one embodiment, the electrically floating metallization structure 140 comprises a set of consecutive plurality of metallization structures (146, 148) extending vertically over at least two circuit layers, the at least two circuit layers comprising a first circuit layer LL1 above a first via layer VL1, and a second circuit layer LL2 below the first via layer VL1.

[0102] In one embodiment, the frame-shaped region FSA includes an outer rectangular perimeter that aligns with a set of sidewalls of at least one electrically floating metallized structure 140, and an inner rectangular perimeter that aligns with at least one vertically extending edge of the at least one electrically floating metallized structure 140; all regions of the at least one electrically floating metallized structure 140 are formed within the frame-shaped region FSA; and a first electrically active metallized via structure 46 is laterally offset inward from the inner rectangular perimeter of the frame-shaped region FSA. In one embodiment, the at least one electrically floating metallized structure 140 includes a plurality of electrically floating metallized structures 140 separated from each other.

[0103] In one embodiment, at least one electrically floating metallized structure 140 includes a frame-shaped interconnect metallized assembly 145 extending around the peripheral portion of a frame-shaped region FSA in a plan view. In one embodiment, the frame-shaped interconnect metallized assembly 145 includes: a pair of first electrically floating metal lines 148 extending laterally along a first horizontal direction hd1; and a pair of second electrically floating metal lines 148 extending laterally along a second horizontal direction hd2. In one embodiment, the pair of first electrically floating metal lines 148 are formed in a wiring layer such as a first wiring layer LL1; the pair of second electrically floating metal lines 148 are formed in another wiring layer such as a second wiring layer LL2; and the frame-shaped interconnect metallized assembly 145 further includes four electrically floating metal via structures 146 to connect individual pairs of first electrically floating metal lines 148 and second electrically floating metal lines 148 in a combination of a pair of first electrically floating metal lines 148 and a pair of second electrically floating metal lines 148. In one embodiment, at least one electrically floating metallized structure 140 includes a plurality of sidewall metal lines 148S arranged along the sides of the outer rectangular perimeter of the frame region FSA in the plan view and laterally separated from each other.

[0104] like Figures 4 to 14 As shown, step 1530 may form a plurality of bonding pads, such as under-bump metallization pads 88, on a dielectric material layer, such as a first dielectric material layer 30, and a first metal interconnect structure (40, 140). One of the bonding pads, such as the under-bump metallization pads 88, is electrically connected to a first vertically extending conductive path ECP1.

[0105] Figure 16 The second sequence of process steps used to form the device structure.

[0106] like Figures 1A to 1D As shown, step 1610 can form a plurality of semiconductor devices 20 on the semiconductor substrate 10.

[0107] like Figures 1A to 3L As shown, step 1620 involves a multiple sequence of metal interconnect formation processes. Each multiple sequence of metal interconnect formation processes includes an individual dielectric material deposition process that deposits an individual dielectric material layer; an individual dielectric patterning process that forms individual plurality of voids in the individual dielectric material layer; and an individual metal deposition and patterning process that forms individual plurality of first metal interconnect structures (40, 140) in the individual voids. The first group of first metal interconnect structures (40, 140) formed by the multiple sequence includes a first vertically extending conductive path ECP1, which includes a first electrically active metal via structure 46 formed in a first via layer VL1, while the second group of first metal interconnect structures (40, 140) includes at least one electrically floating metallized structure 140 formed in the frame-shaped region FSA in the planar view.

[0108] In one embodiment, the dielectric material layers deposited by the multiple sequences (such as the first dielectric material layer 30) include individual dielectric materials with a dielectric constant greater than 1.0 and less than 3.0, and the additional dielectric material layers (such as the second dielectric material layer 50) include individual silicon oxide-based dielectric materials with a dielectric constant of 3.4 to 3.9. In one embodiment, the first vertically extending conductive path ECP1 includes a first electrically active metal line 48 formed on a first electrically active metal via structure 46; and a second electrically active metal line 48, wherein the first electrically active metal via structure 46 is formed on the second electrically active metal line 48. In one embodiment, the first electrically active metal line 48 and the second electrically active metal line 48 are completely formed in the outer periphery of the frame-shaped region FSA in the plan view.

[0109] In one embodiment, at least one electrically floating metallized structure 140 includes a frame-shaped interconnect metallized assembly 145, which contains at least one first electrically floating metal line (148) formed on a first circuit layer LL1, at least one first electrically floating metal via structure (146) formed on a first via layer VL1, at least one second electrically floating metal line (148) formed on a second circuit layer LL2, at least one second electrically floating metal via structure (146) formed on a second via layer, and at least one third electrically floating metal line (148) formed on a third circuit layer.

[0110] like Figure 4 and 5 As shown, step 1640 may form a combination of multiple additional dielectric material layers (such as a second dielectric material layer 50) and multiple second metal interconnect structures (60) on the dielectric material layer (such as a first dielectric material layer 30) and the first metal interconnect structure (40, 140). The individual dielectric constant of the additional dielectric material layer (such as the second dielectric material layer 50) is higher than the dielectric constant of the dielectric material layer deposited by the multiple sequence of the metal interconnect formation process, wherein the second metal interconnect structure (60) includes additional vertically extending conductive paths (such as a second vertically extending conductive path ECP2).

[0111] like Figures 6 to 13 As shown, step 1660 may form a plurality of bonding pads, such as under-bump metallization pads 88, on an additional dielectric material layer, such that one of the bonding pads, such as the under-bump metallization pads 88, is electrically connected to a first vertically extending conductive path ECP1 and an additional vertically extending conductive path (such as a second vertically extending conductive path ECP2). In one embodiment, at least one dielectric passivation layer 70 may be formed on the additional dielectric material layer (50). An array of a plurality of openings 87 is formed to pass through at least one dielectric passivation layer 70. A plurality of under-bump metallization pads 88 are formed in the array of openings 87.

[0112] As shown in all the accompanying drawings and various embodiments of the present invention, a device structure is provided, comprising a plurality of semiconductor devices 20 located on a semiconductor substrate 10; a plurality of first metal interconnect structures (40, 140) located in a plurality of first dielectric material layers 30 on the semiconductor devices 20, wherein a first group of first metal interconnect structures (40, 140) includes a first vertically extending conductive path ECP1, which includes at least one electrically active metal via structure 46 located in a first via layer VL1, and a second group of first metal interconnect structures (40, 140) includes at least one electrically floating metallization structure 140 located in a frame-shaped region FSA in a plan view (e.g., in the four corner areas of the frame-shaped region FSA), wherein at least one electrically active metal via structure 46 is located in the central portion of the frame-shaped region FSA in a plan view; and a plurality of bonding pads, such as under-bump metallization pads 88, located between the first dielectric material layers 30 and the first metal interconnect structures (40, 140). On 140), one of the bonding pads, such as the under-bump metallized pad 88, is electrically connected to the first vertically extending conductive path ECP1.

[0113] In one embodiment, the first dielectric material layer 30 includes individual dielectric materials, each having a dielectric constant greater than 1.0 and less than 3.0. In one embodiment, the frame-shaped region FSA includes an outer rectangular perimeter that coincides with a set of sidewalls of at least one electrically floating metallized structure 140, and an inner rectangular perimeter that coincides with at least one vertically extending edge of at least one electrically floating metallized structure 140; all regions of the at least one electrically floating metallized structure 140 are located within the frame-shaped region FSA; and a first electrically active metal via structure 46 is laterally offset inward from the inner rectangular perimeter of the frame-shaped region FSA.

[0114] In one embodiment, at least one electrically floating metallized structure 140 includes a frame-shaped interconnect metallized assembly 145 extending around the peripheral portion of the frame-shaped region FSA in the plan view. In one embodiment, the device structure includes a plurality of second metal interconnect structures (60) located in a plurality of second dielectric material layers 50 on a first dielectric material layer 30. The individual dielectric constants of the second dielectric material layers 50 are greater than the dielectric constants of the dielectric material in the first dielectric material layer 30; and bonding pads such as under-bump metallized pads 88 are each electrically connected to an individual first metal interconnect structure (40, 140) via an individual set of second metal interconnect structures (60).

[0115] This invention employs an electrically floating metallization structure 140 around the first conductive path ECP1 to reduce mechanical stress on the electrically active metallization structure of the first conductive path ECP1. In embodiments where the first dielectric layer 30 comprises a dielectric material with an extremely low dielectric constant and contains voids therein, reducing mechanical stress is particularly beneficial for improving the reliability of the first conductive path ECP1. The electrically floating metallization structure 140 helps mitigate the risk of via breakage in the electrically active metallization structure 40 of the first conductive path ECP1 passing through the first dielectric layer 30, especially in embodiments where the first dielectric layer 30 uses a dielectric material with an extremely low dielectric constant.

[0116] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the embodiments of the present invention. Each embodiment described herein using the term "comprising" also discloses additional embodiments, wherein the term "comprising" may be replaced by "substantially consisting of" or "consisting of," unless otherwise explicitly stated. When two or more units are listed side-by-side in the same or different paragraphs, it implies the Markus group of those two or more units. When this disclosure uses "may" to describe a unit's formation or processing step, embodiments without this unit's formation or processing step are also explicitly contemplated, provided that the resulting apparatus or device provides equivalent results. Therefore, "may" in forming a unit or performing a processing step should be interpreted as "may" or "may not," provided that omitting this unit's formation or processing step provides the same or equivalent results. Equivalent results include slightly better and slightly worse results. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on the foregoing to achieve the same purpose and / or the same advantages as the embodiments of the present invention. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present invention, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of the embodiments of the present invention.

Claims

1. A method for forming a semiconductor device structure, comprising: Multiple semiconductor devices are formed on a semiconductor substrate; After forming multiple semiconductor devices, a multiple sequence of multiple metal interconnect formation processes is performed, wherein each of the multiple sequences of the multiple metal interconnect formation processes includes: Another dielectric material deposition process, which deposits a separate dielectric material layer; Another dielectric patterning process forms individual multiple voids within individual dielectric material layers; and Another metal deposition and patterning process forms individual multiple first metal interconnect structures within individual multiple said voids. The first group of multiple first metal interconnect structures formed by the multiple sequences includes a first vertically extending conductive path, which includes at least one first electrically active metal via structure formed in a first via layer. The second group of multiple first metal interconnect structures includes at least one electrically floating metallized structure formed in a frame-shaped region in the planar view, wherein the at least one first electrically active metal via structure is formed within the inner periphery of the frame-shaped region in the planar view. Multiple bonding pads are formed on the multiple dielectric material layers and the multiple first metal interconnect structures, wherein one of the multiple bonding pads is electrically connected to the first vertically extending conductive path.

2. The method for forming a semiconductor device structure as claimed in claim 1, wherein the plurality of dielectric material layers deposited during the multiple sequence include individual dielectric materials having an individual dielectric constant greater than 1.0 and less than 3.

0.

3. The method for forming a semiconductor device structure as claimed in claim 1, wherein the at least one electrically floating metallized structure comprises a group of consecutive plurality of metallized structures extending vertically on at least two circuit layers, the at least two circuit layers comprising a first circuit layer above the first via layer and a second circuit layer below the first via layer.

4. The method for forming a semiconductor device structure as described in claim 1, wherein: The frame-shaped region includes an outer rectangular perimeter that coincides with a set of sidewalls of the at least one electrically floating metallized structure, and also includes an inner rectangular perimeter that coincides with at least one vertically extending edge of the at least one electrically floating metallized structure. All regions of the at least one electrically floating metallized structure are formed in the frame-shaped region; as well as The at least one first electrically active metallic via structure is laterally offset inward from the periphery of the inner rectangle of the frame region.

5. A method for forming a semiconductor device structure, comprising: Multiple semiconductor devices are formed on a semiconductor substrate; A multiple sequence of multiple metal interconnect formation processes, wherein each of the multiple sequences of the multiple metal interconnect formation processes includes: Another dielectric material deposition process, which deposits a separate dielectric material layer; Another dielectric patterning process forms individual multiple voids within individual dielectric material layers; and Another metal deposition and patterning process forms individual multiple first metal interconnect structures within individual multiple said voids. The first group of multiple first metal interconnect structures formed by the multiple sequences includes a first vertically extending conductive path, which includes a first electrically active metal via structure formed in a first via layer, while the second group of multiple first metal interconnect structures includes at least one electrically floating metallized structure formed in a frame region in the planar view. A combination of multiple additional dielectric material layers and multiple second metal interconnect structures is formed on the multiple dielectric material layers and multiple first metal interconnect structures, wherein the individual dielectric constants of the multiple additional dielectric material layers are higher than the dielectric constants of the multiple dielectric material layers deposited by the multiple sequence of the multiple metal interconnect formation processes, and wherein the multiple second metal interconnect structures include an additional vertically extending conductive path; and Multiple bonding pads are formed on multiple additional dielectric material layers, such that one of the multiple bonding pads is electrically connected to the first vertically extending conductive path and the additional vertically extending conductive path.

6. The method for forming a semiconductor device structure as described in claim 5, wherein: The multiple dielectric material layers deposited by the multiple sequences include individual dielectric materials whose individual dielectric constants are greater than 1.0 and less than 3.0; and The additional dielectric material layers include individual silicon oxide-based dielectric materials with a dielectric constant of 3.4 to 3.

9.

7. The method for forming a semiconductor device structure as described in claim 5, further comprising: At least one dielectric protective layer is formed on the plurality of said additional dielectric material layers; An array of multiple openings is formed to pass through the at least one dielectric protective layer; as well as Multiple bump-shaped metallized pads are formed in an array of the multiple openings.

8. A semiconductor device structure, comprising: Multiple semiconductor devices are located on a semiconductor substrate; Multiple first metal interconnect structures are located in multiple first dielectric material layers on multiple semiconductor devices, wherein the multiple first metal interconnect structures in a first group include a first vertically extending conductive path, which includes at least one electrically active metal via structure located in a first via layer, and the multiple first metal interconnect structures in a second group include at least one electrically floating metallized structure located in a frame-shaped region in a plan view, wherein the at least one electrically active metal via structure is located in the central portion of the frame-shaped region in the plan view; as well as Multiple bonding pads are located on multiple first dielectric material layers and multiple first metal interconnect structures, wherein one of the multiple bonding pads is electrically connected to the first vertically extending conductive path.

9. The semiconductor device structure of claim 8, wherein the plurality of first dielectric material layers comprise individual dielectric materials having an individual dielectric constant greater than 1.0 and less than 3.

0.

10. The semiconductor device structure as claimed in claim 8, wherein: The frame-shaped region includes an outer rectangular perimeter that coincides with a set of sidewalls of the at least one electrically floating metallized structure, and also includes an inner rectangular perimeter that coincides with at least one vertically extending edge of the at least one electrically floating metallized structure. All regions of the at least one electrically floating metallized structure are located within the frame-shaped region; as well as The at least one electrically active metallic via structure is laterally offset inward from the periphery of the inner rectangle of the frame region.

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