Chip, PCB circuit board and ball grid array packaging structure

Abstract

The application relates to a chip, a PCB circuit board and a ball grid array packaging structure. The chip comprises a PCB circuit board and a ball grid array packaging structure; the PCB circuit board comprises a board body and a via; the board layers in the board body are connected through the vias; the vias comprise signal vias and ground vias; the vias are arranged in a first direction to form multiple via rows; the ball grid array packaging structure comprises a ball array layer, the ball array layer comprises multiple solder balls, the solder balls comprise signal solder balls and ground solder balls; the solder balls are arranged in the first direction to form multiple solder ball rows; wherein each via row corresponds to a solder ball row; the first projection of at least part of the via rows and the second projection of the corresponding solder ball row do not completely overlap; the first projection is the vertical projection of each ground via in the ball array layer, and the second projection is the vertical projection of each ground solder ball in the ball array layer. The chip has high performance.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip, PCB circuit board and ball grid array packaging structure. Background Technology

[0002] With the continuous development of communication technology, network switching protocol speeds have upgraded from 112Gbps per channel to 224Gbps per channel, and the basic frequency has increased from 28GHz to 56GHz. This has brought significant challenges to the physical channel design of chips. The 28GHz fundamental frequency difference causes a rapid deterioration in the physical channel frequency domain parameters of the chip's PCB circuit, such as inter-channel crosstalk, affecting chip performance. Therefore, it is urgent to solve the problem of how to improve the physical channel frequency domain parameters of PCB circuit boards for 224G chips to enhance chip performance. Summary of the Invention

[0003] Based on this, a chip, PCB circuit board, and ball grid array packaging structure that can improve chip performance is provided.

[0004] In a first aspect, this application provides a chip. The chip includes a PCB circuit board and a ball grid array (BGA) package structure; the PCB circuit board includes a board body and vias; the layers in the board body are connected by vias; the vias include signal vias and ground vias; the vias are arranged along a first direction to form multiple rows of vias; the BGA package structure includes a ball array layer, the ball array layer includes multiple solder balls, the solder balls include signal solder balls and ground solder balls; the solder balls are arranged along the first direction to form multiple rows of solder balls; wherein each row of vias corresponds to a row of solder balls; at least a portion of the first projection of the via row does not completely overlap with the second projection of the corresponding row of solder balls, the first projection being the vertical projection of the vias in the via row onto the ball array layer, and the second projection being the vertical projection of the solder balls in the row of solder balls onto the ball array layer.

[0005] In one embodiment, each via row includes multiple signal vias and multiple ground vias; each solder ball row includes multiple signal solder balls and multiple ground solder balls; or, in two adjacent via rows, the first via row includes multiple signal vias and multiple ground vias, and the second via row includes multiple ground vias; in two adjacent solder ball rows, the first solder ball row includes multiple signal solder balls and multiple ground solder balls, and the second solder ball row includes multiple ground solder balls; the second via row corresponds to the second solder ball row.

[0006] In one embodiment, in a via row including multiple signal holes and multiple ground holes, two adjacent signal holes constitute a pair of high-speed signal holes; wherein, at least two ground holes are provided between two adjacent pairs of high-speed signal holes.

[0007] In one embodiment, two adjacent first solder balls in the first row of solder balls are arranged in a diamond or rectangular pattern with two adjacent second solder balls in the second row of solder balls; the two second solder balls are closest to the two first solder balls, and the first row of solder balls and the second row of solder balls are adjacent to each other.

[0008] In one embodiment, the first spacing between a pair of high-speed signal vias is smaller than the second spacing between two other adjacent ground vias; the third spacing between a pair of high-speed signal solder balls corresponding to a pair of high-speed signal vias is smaller than the fourth spacing between two other adjacent ground solder balls.

[0009] In one embodiment, the first spacing between a pair of high-speed signal holes is smaller than the third spacing between the corresponding pair of high-speed signal solder balls.

[0010] In one embodiment, the first spacing and the third spacing are determined based on the chip's preset loss index and channel crosstalk requirements; the preset loss index includes: return loss, and / or, insertion loss; the preset loss index includes that the loss when the chip supports the target transmission rate is less than the target loss threshold; the channel crosstalk requirement includes that the crosstalk between signal channels when the chip indicates the target transmission rate is less than the target crosstalk threshold.

[0011] In one embodiment, the diameter of the signal hole and the diameter of the signal solder ball are determined according to preset loss parameters and channel crosstalk requirements.

[0012] Secondly, this application also provides a PCB circuit board for use with the chip described in the first aspect. The PCB circuit board includes a board body and vias; the layers in the board body are connected by vias; the vias include signal vias and ground vias; the vias are arranged along a first direction to form multiple rows of vias; wherein each row of vias corresponds to a row of solder balls in the ball array layer of the ball grid array package structure corresponding to the PCB circuit board; at least some of the first projections of the via rows do not completely overlap with the second projections of the corresponding solder ball rows, the first projection being the vertical projection of the vias in the via row onto the ball array layer, and the second projection being the vertical projection of the solder balls in the solder ball row onto the ball array layer; wherein the ball array layer includes multiple solder balls, the solder balls including signal solder balls and ground solder balls; the solder balls are arranged along the first direction to form multiple rows of solder balls.

[0013] Thirdly, this application also provides a ball grid array (BGA) packaging structure applied to the chip described in the first aspect. The BGA packaging structure includes a ball array layer, which includes multiple solder balls, including signal solder balls and ground solder balls. Each solder ball is arranged along a first direction to form multiple rows of solder balls. Each row of solder balls corresponds to a via row in the PCB circuit board corresponding to the BGA packaging structure. The second projection of the solder ball row does not completely overlap with the first projection of the corresponding via row. The first projection is the vertical projection of each via in the via row onto the ball array layer, and the second projection is the vertical projection of each solder ball in the solder ball row onto the ball array layer. The PCB circuit board includes a board body and vias. The layers in the board body are connected by vias. The vias include signal vias and ground vias. Each via is arranged along the first direction to form multiple rows of vias.

[0014] The aforementioned chip, PCB circuit board, and ball grid array (BGA) package structure are described above. The chip includes a PCB circuit board and a BGA package structure. The PCB circuit board includes a board body and vias. The layers in the board body are connected by vias. The vias include signal vias and ground vias. The vias are arranged along a first direction to form multiple rows of vias. The BGA package structure includes a ball array layer, which includes multiple solder balls, including signal solder balls and ground solder balls. The solder balls are arranged along a first direction to form multiple rows of solder balls. Each row of vias corresponds to a row of solder balls. At least some of the first projections of the via rows do not completely overlap with the second projections of the corresponding solder ball rows. The first projection is the vertical projection of the vias in the via row onto the ball array layer, and the second projection is the vertical projection of the solder balls in the solder ball rows onto the ball array layer. Since the first and second projections do not completely overlap, and the first projection is the vertical projection of each via in the via row onto the ball array layer, while the second projection is the vertical projection of each solder ball in the solder ball row onto the ball array layer, it means that there is no need for a one-to-one correspondence between ground vias and ground solder balls with completely overlapping projections. This decouples the ground vias and ground solder balls. Therefore, when there is no need for a one-to-one correspondence and completely overlapping projections between ground vias and ground solder balls, the number of ground vias is not limited by the number of ground solder balls. In other words, the number of ground vias can be maximized, thereby using each ground via to isolate crosstalk between signal vias and improving crosstalk between signal lines corresponding to the signal vias.

[0015] Other beneficial effects of this application will be further explained and illustrated in detail when combined with the accompanying drawings and specific embodiments. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the solder ball arrangement in one embodiment;

[0018] Figure 2 This is a schematic diagram comparing chip losses in one embodiment;

[0019] Figure 3 This is a top view of the chip in one embodiment;

[0020] Figure 4 This is a side view of the chip in one embodiment;

[0021] Figure 5 This is a top view schematic diagram of another chip in one embodiment;

[0022] Figure 6 This is a top view schematic diagram of another chip in one embodiment;

[0023] Figure 7 This is a schematic diagram of a crosstalk attack between differential pairs in one embodiment;

[0024] Figure 8 This is a top view schematic diagram of another chip in one embodiment;

[0025] Figure 9 This is a schematic diagram of the solder ball arrangement in one embodiment;

[0026] Figure 10 This is a schematic diagram of another solder ball arrangement in one embodiment. Detailed Implementation

[0027] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that many specific details are set forth in the following description in order to provide a full understanding of this application, but this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0029] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0030] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0031] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0032] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0033] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0034] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0035] The upgrade of network switching protocol speed from 112Gbps to 224Gbps per channel and the fundamental frequency from 28GHz to 56GHz present significant challenges to physical channel design. The 28GHz fundamental frequency difference causes a rapid deterioration in the physical channel's frequency domain metrics, including insertion loss, return loss, and inter-channel crosstalk. Current 112G chip BGA (Ball Grid Array) designs are no longer viable, necessitating new BGA design development and optimization for 224G. Insertion loss describes the attenuation of electrical signals by the physical channel, expressed as the sum of the signal output power and input power. Return loss describes the reflection of electrical signals due to changes in physical channel impedance, expressed as the sum of the reflected power and input power. Inter-channel crosstalk refers to the phenomenon in a circuit system where the energy of one signal channel is coupled to another adjacent or nearby signal channel via electromagnetic coupling, causing interference or noise to the latter. Far-end crosstalk is one type of crosstalk, generally referring to crosstalk when the source and target signals have the same transmission direction.

[0036] Existing 112Gbps BGA and PCB designs are essentially one-ball-one-via, meaning one solder ball corresponds to one PCB via. Furthermore, the ball map layout lacks sufficient isolation between signals to support the 56GHz crosstalk requirements. Additionally, the large size and low impedance of BGA solder balls result in significant return loss, and the coaxial cable-like structure formed by the substrate vias, solder balls, and PCB vias has low bandwidth. Here, "ball map" refers to the pin definition mapping table of the BGA in the chip package. It specifies the correspondence between the chip's power, ground, and signal lines and the external solder balls. Essentially, it is the logical definition of the pin layout in the package design, directly affecting the connection method and electrical performance between the chip and the PCB.

[0037] like Figure 1 This diagram illustrates a conventional solder ball arrangement. The BGA arrangement of the 112Gbps switch chip shows white solder balls for signals and red solder balls for GND (ground). Crosstalk paths between signals are divided into... Figure 1The diagram shows two types of crosstalk: lateral and longitudinal. This BGA design exhibits poor frequency domain performance, including insertion loss, return loss, and far-end crosstalk. As shown in Figure 2, it can be seen that in existing chip designs, as the signal rate increases from 112Gbps to 224Gbps and the base frequency increases from 28GHz to 56GHz, the insertion loss changes from -0.72dB to -8.39dB, the return loss from -20.39dB to -2.83dB, and the far-end crosstalk from -41.99dB to 31.15dB. In other words, all frequency domain performance indicators are rapidly deteriorating. Therefore, it is necessary to optimize the return loss and far-end crosstalk to meet the requirements of 224G signals.

[0038] In view of this, embodiments of this application provide a chip that reduces crosstalk between signals by designing ground holes and ground solder balls for decoupling, and improves the chip's return loss performance by designing signal solder balls and signal hole offsets.

[0039] In optional embodiments of this application, the chip may be a switching chip or a network chip, which is not fully exemplified here. Exemplarily, the chip may be a PCIe chip, etc. A switching chip can be used in network switching devices. Network switching devices are communication devices dedicated to receiving, processing, and forwarding data packets in a network, such as, but not limited to: Ethernet switches, routers, switching chips, smart network interface cards (SmartNICs), forwarding engines in data processor units (DPUs), etc.

[0040] In one embodiment, such as Figure 3 A top view of the chip is shown. The chip includes a PCB circuit board and a ball grid array (BGA) package structure. The PCB circuit board includes a board body and vias; the layers within the board body are connected vias. Figure 3 (Not shown). Vias include signal vias and ground vias; the vias are arranged in multiple rows along a first direction. The ball grid array package structure includes a ball array layer, the ball array layer includes multiple solder balls, the solder balls include signal solder balls and ground solder balls; the solder balls are arranged in multiple rows along a first direction.

[0041] Each via row corresponds to a solder ball row. At least some via rows have a first projection that does not completely overlap with the second projection of the corresponding solder ball row. The first projection is the vertical projection of each via in the via row onto the ball array layer, and the second projection is the vertical projection of each solder ball in the solder ball row onto the ball array layer.

[0042] Signal vias are used to establish electrical connections between signal traces on different board layers. Ground vias connect the ground position on the PCB to the GND ground plane, serving purposes such as shielding, return current, electrostatic discharge protection, and impedance reduction.

[0043] Signal solder balls transmit the chip's signals. They are soldered to the corresponding signal pads on the PCB and connected to the signal traces. The signal traces achieve signal connectivity between different board layers through signal vias. Ground solder balls are grounded. They are soldered to the corresponding ground pads on the PCB and connected to the ground plane layer through ground vias, forming a stable ground loop.

[0044] For example, each row of vias corresponds one-to-one with each row of solder balls.

[0045] In an optional embodiment of this application, the first direction is a direction parallel to a certain edge of the PCB circuit board. Alternatively, the first direction may be the routing direction of the PCB circuit board. It can be understood that the first direction is the extension direction of multiple vias or multiple solder balls arranged sequentially, and no specific limitation is made to the first direction here.

[0046] A via row may include signal vias, wherein a signal via may be adjacent to another signal via or to a ground via. For example, the signal via is a differential signal via, therefore, as... Figure 3 As illustrated, in a via row, two signal vias form a differential signal via pair for connecting differential signal traces. This can be a high-speed differential signal via, thus supporting high-speed differential signals.

[0047] At least some of the first projections of the via rows do not completely overlap with the second projections of the corresponding solder ball rows. That is, the first projections of some via rows do not completely overlap with the second projections of the corresponding solder ball rows, while the first projections of other via rows can completely overlap with the second projections of the corresponding solder ball rows. Alternatively, the first projections of all via rows do not completely overlap with the second projections of the corresponding solder ball rows.

[0048] It should be noted that due to manufacturing process issues, complete overlap includes vias and corresponding solder balls that are almost completely overlapped, although there may be minor areas where they do not overlap.

[0049] It should be noted that incomplete overlap includes situations where the first projection of the via row and the second projection of the corresponding solder ball row have a large overlap, or where the first projection of the via row and the second projection of the corresponding solder ball row have a small overlap, or where the first projection of the via row and the second projection of the corresponding solder ball row do not overlap at all.

[0050] Furthermore, the first projection is the vertical projection of each hole in the via row onto the ball array layer, and the second projection is the vertical projection of each solder ball in the solder ball row onto the ball array layer. For example, the vertical projection of each hole onto the ball array layer can refer to the total vertical projection of all the holes, and the vertical projection of each solder ball onto the ball array layer can refer to the total vertical projection of all the solder balls onto the ball array layer. Based on this, that is, for a corresponding set of via rows and solder ball rows, if the first projection of the via row and the second projection of the solder ball row do not completely overlap, in one case, it can mean that the vertical projections of some holes in the via row do not completely overlap with the vertical projections of some solder balls; in another case, it can mean that the vertical projections of all holes in the via row do not completely overlap with the vertical projection of any solder ball.

[0051] In an optional embodiment of this application, for a set of via rows and solder ball rows, the vertical projection of each signal hole in the via row onto the ball array layer can completely overlap with the vertical projection of the corresponding signal solder ball onto the ball array layer.

[0052] In summary, since the projections of the ground vias and ground solder balls do not completely overlap, thus achieving decoupling between the ground vias and ground solder balls, the number of ground vias can be maximized within the limits of PCB manufacturing processes. Multiple ground vias form a ground via fence, which improves chip isolation and reduces crosstalk coupling between signals in the second direction, for example, improving... Figure 1 The longitudinal crosstalk shown reduces far-end crosstalk.

[0053] In one alternative implementation, in two adjacent rows of vias, the first row of vias includes multiple signal vias and multiple ground vias, and the second row of vias includes multiple ground vias; in two adjacent rows of solder balls, the first row of solder balls includes multiple signal solder balls and multiple ground solder balls, and the second row of solder balls includes multiple ground solder balls.

[0054] That is, in a PCB circuit board, the first row of vias and the second row of vias are distributed alternately; in a ball array layer, the first row of solder balls and the second row of solder balls are distributed alternately.

[0055] In this configuration, one second row of vias corresponds to one second row of solder balls, meaning that the first projection of at least some second row of vias does not completely overlap with the second projection of the corresponding second row of solder balls. Optionally, the first projection of all second row of vias does not completely overlap with the second projection of the corresponding second row of solder balls.

[0056] For example, such as Figure 4A side view diagram of the chip corresponding to this implementation is shown. It can be seen that the second row of vias forms a ground via fence, and the second row of solder balls has multiple ground solder balls corresponding to each via. Adjacent signals are isolated by the ground solder balls, reducing crosstalk. The continuous row of ground solder balls can quickly conduct chip heat to the PCB ground plane. Moreover, the entire row of ground solder balls provides a continuous, low-impedance ground reference, which is beneficial for power integrity and EMI suppression. Figure 5 The diagram shows a top view of the chip corresponding to this implementation method, from which it can be seen that... Figure 5 The green part in the middle is a pair of differential signal holes (differential signal solder balls).

[0057] Optionally, one row of first-row vias corresponds to one row of first-row solder balls. Optionally, refer to... Figure 4 and Figure 5 The first projection of the first row of vias completely overlaps with the second projection of the corresponding first row of solder balls. Optionally, refer to... Figure 4 and Figure 5 In the first row of vias, the vertical projections of each signal via and the corresponding signal solder ball in the solder ball row onto the ball array layer can completely overlap.

[0058] In another alternative implementation, each via row includes multiple signal vias and multiple ground vias. Each solder ball row includes multiple signal solder balls and multiple ground solder balls, see reference. Figure 6 A top view schematic diagram of another chip is shown as an example.

[0059] That is, each via row includes multiple signal vias and multiple ground vias, wherein two signal vias form a group of differential signal vias. Each solder ball row includes multiple signal solder balls and multiple ground solder balls, wherein two signal solder balls form a group of differential signal solder balls.

[0060] In optional embodiments of this application, reference is made to... Figure 6 As shown, there is no vertical projection of ground holes in the vertical projection of adjacent signal solder balls and ground solder balls in the same row in the ball array layer.

[0061] In the aforementioned chip, since the first projection and the second projection do not completely overlap, and the first projection is the vertical projection of the vias in the via row onto the ball array layer, while the second projection is the vertical projection of the solder balls in the solder ball row onto the ball array layer, it is unnecessary for the ground vias and solder balls to correspond one-to-one and have completely overlapping projections, thus decoupling the ground vias and solder balls. Therefore, when the ground vias and solder balls do not need to correspond one-to-one and have completely overlapping projections, the number of ground vias is not limited by the number of solder balls. That is, the number of ground vias can be maximized, thereby using each ground via to isolate crosstalk between signal vias and improving crosstalk between signal lines corresponding to signal vias. Furthermore, by increasing the number of ground vias and solder balls in the first direction, combined with a ground via fence, crosstalk is further significantly improved.

[0062] In one embodiment, in a via row including multiple signal vias and multiple ground vias, two adjacent signal vias constitute a pair of high-speed signal vias. At least two ground vias are provided between two adjacent pairs of high-speed signal vias.

[0063] In one embodiment, in a row of solder balls comprising multiple signal solder balls and multiple ground solder balls, two adjacent signal solder balls constitute a pair of high-speed signal solder balls. At least two ground solder balls are provided between two adjacent pairs of high-speed signal solder balls.

[0064] For example, refer to Figure 3 In the implementation shown, two ground vias are provided between two adjacent pairs of high-speed signal vias. In related technologies, a single ground via between two adjacent pairs of high-speed signal vias is insufficient to support the crosstalk requirements of 56GHz. In this embodiment, the isolation ground balls and ground vias between differential signal pairs in the first direction are increased from one column to two columns, effectively improving lateral crosstalk.

[0065] For example, refer to Figure 6 In the implementation shown, five ground holes are provided between two adjacent pairs of high-speed signal holes. Figure 1 Compared to the arrangement shown, the number of ground holes between two adjacent pairs of high-speed signal holes and the number of ground solder balls between two adjacent pairs of high-speed signal solder balls are increased, which can support the crosstalk requirements of 56GHz and effectively improve lateral crosstalk.

[0066] In one embodiment, the first spacing between a pair of high-speed signal holes is smaller than the second spacing between two other adjacent ground holes.

[0067] The spacing between the two high-speed signal vias is the first spacing, and the spacing between the two ground vias is the second spacing. The first spacing is smaller than the second spacing, meaning that, compared to the distribution of other ground vias, the high-speed signal vias are offset, shortening the spacing between the signal vias within the differential pair.

[0068] Optionally, the spacing between the signal hole and the ground hole is also a second spacing.

[0069] In one embodiment, the third spacing between a pair of high-speed signal solder balls corresponding to a pair of high-speed signal holes is smaller than the fourth spacing between the other two adjacent ground solder balls.

[0070] The spacing between the two high-speed signal solder balls is the third spacing, and the spacing between the two ground solder balls is the fourth spacing. The third spacing is smaller than the fourth spacing, meaning that compared to the distribution of other ground solder balls, the high-speed signal solder balls are offset, shortening the spacing between the signal solder balls within the differential pair.

[0071] Optionally, the spacing between the signal solder ball and the ground solder ball is also a fourth spacing.

[0072] As mentioned above, in addition to improving crosstalk, optimizing return loss is also crucial. Return loss is related to channel impedance variations. Solder balls have relatively low impedance; therefore, using smaller solder balls can increase impedance and improve return loss. Furthermore, return loss is also related to the conversion of the transverse electromagnetic wave mode (TEM mode) in the coaxial cable structure to higher-order modes. Minimizing the conversion of the TEM mode to other higher-order modes can improve return loss and channel bandwidth. The TEM mode refers to a waveguide mode in which there are no electric or magnetic field components in the transmission direction of the electromagnetic wave. Additionally, the BGA interface uses a coaxial cable physical structure, where electromagnetic field transmission is primarily in the TEM mode (transverse electromagnetic field mode), which has almost no impact on the longitudinally transmitted signal. The cutoff frequency of the higher-order mode TE11 limits the upper limit of the TEM bandwidth. That is, the upper limit of the coaxial cable bandwidth is determined by the cutoff frequency of the first TE11 mode. According to the calculation formula, the smaller the outer and inner diameters of the vertical coaxial cable structure formed by the solder balls and vias, the higher the TEM mode bandwidth and the better the return loss. In summary, the smaller the solder ball diameter, solder ball spacing, via diameter, and via antipad diameter, the better the return loss and the higher the upper limit of the physical path bandwidth.

[0073] In this embodiment, the first spacing is smaller than the second spacing, and the third spacing is smaller than the fourth spacing. This allows for the use of smaller diameter signal solder balls and signal vias under the same impedance, thereby improving return loss and meeting the 224Gbps standard. Furthermore, this allows the electromagnetic field to be more concentrated within the differential pairs, increasing the distance between differential signal pairs and further improving lateral crosstalk. Moreover, because the signal solder balls and signal vias are smaller in diameter, the chip area is not increased. Figure 7 An exemplary diagram of crosstalk attacks between differential pairs is shown. In this embodiment, the crosstalk effect is reduced by using offset signal balls and offset signal holes.

[0074] In one embodiment, the first spacing between a pair of high-speed signal vias is smaller than the third spacing between the corresponding pair of high-speed signal solder balls. That is, the spacing between the pairs of signal vias is smaller than the spacing between the signal solder balls, thereby making it easier to set more vias and increase isolation.

[0075] In one embodiment, two adjacent first solder balls in the first row of solder balls are arranged in a diamond or rectangular pattern with two adjacent second solder balls in the second row of solder balls; the two second solder balls are closest to the two first solder balls, and the first row of solder balls and the second row of solder balls are adjacent to each other.

[0076] For example, refer to Figure 5 As shown, it illustrates a diamond-shaped arrangement. This diamond arrangement can significantly reduce row spacing while maintaining the same number of solder balls and the same solder ball spacing, thereby shortening the overall chip width / length and ultimately saving chip area.

[0077] For example, such as Figure 8 A top view schematic diagram of another chip is shown, for reference. Figure 8 As shown, this illustrates a rectangular arrangement. A rectangular arrangement allows for a more uniform electric field distribution between adjacent solder balls, more consistent parasitic parameters, and less signal crosstalk, thereby improving electrical performance and signal integrity.

[0078] This increases the flexibility in designing the arrangement of high-speed signal pairs.

[0079] For example, in a diamond arrangement, the axial distance between two adjacent ground balls is 0.95 mm.

[0080] For example, the ground solder ball diameter is 0.5mm, the signal solder ball offset has a wheelbase of 0.76mm, the signal hole is formed with an 8mil diameter, and the signal hole offset has a wheelbase of 0.71mm.

[0081] For example, ground hole fences are used between differential signal pairs. The ground holes are formed with an 8-millimeter diameter and the axial distance between the ground holes is controlled at 0.5~0.6mm. They are arranged at equal intervals.

[0082] In one embodiment, the first spacing and the third spacing are determined based on the chip's preset loss parameters and channel crosstalk requirements. For example, the preset loss parameters in this embodiment include: return loss, and / or, insertion loss, etc., wherein return loss measures the strength of signal reflection, and insertion loss measures the attenuation during signal transmission; both together reflect the stability and transmission efficiency of the link.

[0083] The preset loss index includes the requirement that the loss of the chip when supporting the target transmission rate is less than the target loss threshold. For example, if the target transmission rate that the chip needs to support is 224Gbps as mentioned above, then the target loss threshold corresponding to the preset loss index can be -10dB.

[0084] Channel crosstalk requirements include ensuring that the crosstalk between signal channels is less than the target crosstalk threshold when the chip indicates the target transmission rate. For example, if the chip needs to support a target transmission rate of 224Gbps as mentioned above, then the target crosstalk threshold can be -40dB.

[0085] In one embodiment, the diameter of the signal aperture and the diameter of the signal solder ball are determined based on preset loss parameters and channel crosstalk requirements. For example, the diameter of the signal aperture and the diameter of the signal solder ball are determined to meet the requirements of return loss less than -10dB and far-end crosstalk less than -40dB.

[0086] based on Figure 7The ball map model shown verifies the chip's electrical performance under different solder ball sizes and spacings. When the solder ball diameter is 0.4mm, the ground solder ball spacing is 0.95mm, the signal solder ball spacing is 0.66mm, and the signal via spacing is 0.66mm, the chip loss is -0.41dB, the return loss is -14.28dB, and the far-end crosstalk is -19.62dB. When the solder ball diameter is 0.5mm, the ground solder ball spacing is 0.95mm, the signal solder ball spacing is 0.76mm, and the signal via spacing is 0.71mm, the chip loss is -0.37dB, the return loss is -13.38dB, and the far-end crosstalk is -18.83dB. When the solder ball diameter is 0.6mm, the ground solder ball spacing is 0.95mm, the signal solder ball spacing is 0.89mm, and the signal via spacing is 0.89mm, the chip loss is -0.48dB, the return loss is -11.69dB, and the far-end crosstalk is -16.89dB. It can be seen that the smaller the solder ball size and the smaller the solder ball and signal via spacing, the better the return loss and far-end crosstalk, verifying the feasibility of the design scheme in this application.

[0087] Furthermore, taking a scheme with a solder ball diameter of 0.5mm, a ground solder ball spacing of 0.95mm, a signal solder ball spacing of 0.76mm, and a signal hole spacing of 0.71mm as an example, modeling and simulation are performed. Figure 9 In the layout shown, if the ground vias and ground balls are not decoupled and a ground via fence is not formed, the far-end crosstalk of the chip is -21.49dB. However, Figure 9 In the layout shown, after decoupling the ground vias and ground solder balls to form a ground via fence, the far-end crosstalk of the chip is -42.76dB. Furthermore, in... Figure 10 In the layout shown, the first and second solder ball rows, as well as the first and second via rows, are alternately arranged. However, if the ground vias and ground solder balls are not decoupled and a ground via fence is not formed, the far-end crosstalk of the chip is -34.04dB. Figure 10 In the layout scheme shown, after decoupling the ground vias and ground solder balls to form a ground via fence, the far-end crosstalk of the chip is -49.75dB.

[0088] Therefore, adding a ground hole fence can effectively improve crosstalk in the vertical direction. Furthermore, combining this with the lateral offset design between differential signal pairs described above not only further improves crosstalk but also has virtually no impact on chip area.

[0089] Furthermore, a comparison between the existing design scheme and the design scheme of this application shows that the insertion loss, return loss, and far-end crosstalk of the chip with a base frequency of 28GHz prepared by the existing design scheme are -0.7dB, -0.39dB, and -41.99dB, respectively; while the insertion loss, return loss, and far-end crosstalk of the chip with a base frequency of 56GHz prepared by the existing design scheme are -8.39dB, -0.83dB, and -31.15dB, respectively. These cannot meet the performance requirements of a chip with a base frequency of 56GHz. The chip with a base frequency of 28GHz fabricated by the design scheme of this application has an insertion loss of -0.70dB, a return loss of -20.17dB, and a far-end crosstalk of -64.24dB, respectively; the chip with a base frequency of 56GHz fabricated by the design scheme of this application has an insertion loss of -1.10dB, a return loss of -13.34dB, and a far-end crosstalk of -49.75dB, respectively, achieving a performance improvement.

[0090] In summary, in the embodiments of this application, by using reasonable ball map layout, ground hole fence, and spherical aperture design, the lateral crosstalk, longitudinal crosstalk, and return loss are improved, so as to achieve a chip BGA design that can support 224Gbps.

[0091] In one embodiment, a PCB circuit board is provided, which is applied to the chip described in any of the above embodiments. The PCB circuit board includes a board body and vias; the layers in the board body are connected by vias; the vias include signal vias and ground vias; the vias are arranged along a first direction to form multiple rows of vias; wherein each row of vias corresponds to a row of solder balls in the ball array layer of the ball grid array package structure corresponding to the PCB circuit board; at least a portion of the first projection of the via rows does not completely overlap with the second projection of the corresponding solder ball rows, the first projection being the vertical projection of the vias in the via rows onto the ball array layer, and the second projection being the vertical projection of the solder balls in the solder ball rows onto the ball array layer; wherein the ball array layer includes multiple solder balls, the solder balls including signal solder balls and ground solder balls; the solder balls are arranged along the first direction to form multiple rows of solder balls.

[0092] For other limitations regarding this PCB circuit board, please refer to the limitations for the chip mentioned above, which will not be repeated here.

[0093] In one embodiment, a ball grid array (BGA) package structure is provided, which is applied to the chip described in any of the above embodiments. The BGA package structure includes a ball array layer, which includes a plurality of solder balls, including signal solder balls and ground solder balls; the solder balls are arranged along a first direction to form multiple rows of solder balls; wherein each row of solder balls corresponds to a via row in a PCB circuit board corresponding to the BGA package structure; the second projection of the solder ball row does not completely overlap with the first projection of the corresponding via row, the first projection being the vertical projection of each via in the via row onto the ball array layer, and the second projection being the vertical projection of each solder ball in the solder ball row onto the ball array layer; wherein the PCB circuit board includes a board body and vias; the layers in the board body are connected by vias; the vias include signal vias and ground vias; the vias are arranged along the first direction to form multiple rows of vias.

[0094] For other limitations regarding this ball grid array packaging structure, please refer to the chip limitations above, which will not be repeated here.

[0095] In one embodiment, a computer system is provided, which includes the chip described in the above embodiments. Optionally, the computer system refers to a system capable of performing computing and data processing tasks, including at least one processor and memory. The system can be a standalone device, such as a server integrated with a smart network card, or a system composed of multiple devices interconnected via a network, such as a data center including switches, servers, and storage devices.

[0096] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A chip, characterized in that, The chip includes a PCB circuit board and a ball grid array package structure; The PCB circuit board includes a board body and vias; the layers in the board body are connected through the vias; the vias include signal vias and ground vias. The vias are arranged along the first direction to form multiple rows of vias; The ball grid array packaging structure includes a ball array layer, the ball array layer includes a plurality of solder balls, the solder balls include signal solder balls and ground solder balls; each of the solder balls is arranged along a first direction to form multiple rows of solder balls; Each via row corresponds to a solder ball row; at least some of the first projections of the via rows do not completely overlap with the second projections of the corresponding solder ball rows, the first projection being the vertical projection of each ground via in the via row onto the ball array layer, and the second projection being the vertical projection of each ground solder ball in the solder ball row onto the ball array layer.

2. The chip according to claim 1, characterized in that, Each of the via rows includes multiple signal vias and multiple ground vias; each of the solder ball rows includes multiple signal solder balls and multiple ground solder balls; Alternatively, in two adjacent rows of vias, the first row of vias includes multiple signal vias and multiple ground vias, and the second row of vias includes multiple ground vias; in two adjacent rows of solder balls, the first row of solder balls includes multiple signal solder balls and multiple ground solder balls, and the second row of solder balls includes multiple ground solder balls; the second row of vias corresponds to the second row of solder balls.

3. The chip according to claim 2, characterized in that, In a via row that includes multiple signal holes and multiple ground holes, two adjacent signal holes form a pair of high-speed signal holes; wherein, at least two ground holes are provided between two adjacent pairs of high-speed signal holes.

4. The chip according to claim 3, characterized in that, The first spacing between a pair of high-speed signal holes is smaller than the second spacing between two other adjacent ground holes; The third spacing between a pair of high-speed signal solder balls corresponding to a pair of high-speed signal holes is smaller than the fourth spacing between the other two adjacent ground solder balls.

5. The chip according to claim 4, characterized in that, The first spacing between a pair of high-speed signal holes is less than the third spacing between the corresponding pair of high-speed signal solder balls.

6. The chip according to claim 5, characterized in that, The first spacing and the third spacing are determined based on the chip's preset loss index and channel crosstalk requirements; the preset loss index includes: return loss, and / or, insertion loss; The preset loss index includes the loss being less than the target loss threshold when the chip supports the target transmission rate; the channel crosstalk requirement includes the crosstalk between signal channels being less than the target crosstalk threshold when the chip indicates the target transmission rate.

7. The chip according to claim 6, characterized in that, The diameter of the signal hole and the diameter of the signal solder ball are determined according to the preset loss index and the channel crosstalk requirements.

8. The chip according to any one of claims 1-7, characterized in that, The two adjacent first solder balls in the first row of solder balls are arranged in a diamond or rectangular pattern with the two adjacent second solder balls in the second row of solder balls; the two second solder balls are closest to the two first solder balls, and the first row of solder balls and the second row of solder balls are adjacent to each other.

9. A PCB circuit board, characterized in that, Applied to the chip as described in any one of claims 1-8, the PCB circuit board includes a board body and vias; the layers in the board body are connected to each other through the vias; the vias include signal vias and ground vias; the vias are arranged along a first direction to form multiple rows of vias; Each via row corresponds to a solder ball row in the ball array layer of the ball grid array package structure corresponding to the PCB circuit board; at least some of the first projections of the via rows and the second projections of the corresponding solder ball rows do not completely overlap, the first projection is the vertical projection of each ground via in the via row onto the ball array layer, and the second projection is the vertical projection of each solder ball in the solder ball row onto the ball array layer; wherein, the ball array layer includes multiple solder balls, the solder balls include signal solder balls and ground solder balls; each solder ball is arranged along a first direction to form multiple rows of solder balls.

10. A ball grid array packaging structure, characterized in that, Applied to the chip as described in any one of claims 1-8, the ball grid array package structure includes a ball array layer, the ball array layer includes a plurality of solder balls, the solder balls including signal solder balls and ground solder balls; each of the solder balls is arranged along a first direction to form multiple rows of solder balls; Each row of solder balls corresponds to a via row in the PCB circuit board corresponding to the ball grid array package structure; the second projection of the solder ball row does not completely overlap with the first projection of the corresponding via row, the first projection being the vertical projection of each ground solder ball in the via row onto the ball array layer, and the second projection being the vertical projection of each ground solder ball in the solder ball row onto the ball array layer; the PCB circuit board includes a board body and vias; the layers in the board body are connected through the vias; the vias include signal vias and ground vias; the vias are arranged along a first direction to form multiple rows of vias.

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