Display device

Abstract

The present application provides display device, have: substrate, it has display area of display image; Lower electrode, it has first metal layer opposite with the substrate, and first conductive oxide layer covering the upper surface of the first metal layer, in the display area is configured above the substrate; Rib layer, it has pixel opening overlapping with the lower electrode, covering the lower electrode, formed by inorganic material; Partition wall, it includes configuration above the rib layer and has lower part of conductive, configuration above the lower part and from the side of the lower part protruding first film and covering the first film and formed by conductive oxide second film; And polarizing plate, it is configured above the partition wall, when observing the polarizing plate from the normal direction of the substrate, the polarizing plate looks as black, when observing the polarizing plate from the oblique direction relative to the normal direction is inclined, polarizing plate looks as blueish black.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2025-045830, filed on March 19, 2025, and invokes all the contents set forth in that Japanese Patent Application. Technical Field

[0002] Embodiments of the present invention relate to display devices. Background Technology

[0003] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. In these devices, aesthetic appeal is important. Summary of the Invention

[0004] In general, according to the embodiments, the display device includes: a substrate having a display area for displaying an image; a lower electrode having a first metal layer opposite to the substrate and a first conductive oxide layer covering the upper surface of the first metal layer, disposed above the substrate in the display area; a rib layer having pixel openings overlapping the lower electrode, covering the lower electrode, and formed of an inorganic material; a partition wall including a lower portion disposed above the rib layer and having conductivity, a first thin film disposed above the lower portion and protruding from the side of the lower portion, and a second thin film covering the first thin film and formed of a conductive oxide; and a polarizing plate disposed above the partition wall, which appears black when viewed from the normal direction of the substrate, and appears bluish-black when viewed from an inclined direction inclined relative to the normal direction.

[0005] According to other embodiments, the display device includes: a substrate having a display area for displaying an image; a lower electrode having a first metal layer opposite to the substrate and a first conductive oxide layer covering the upper surface of the first metal layer, disposed above the substrate in the display area; a rib layer having pixel openings overlapping the lower electrode, covering the lower electrode, and formed of an inorganic material; a partition wall including a lower portion disposed above the rib layer and having conductivity, a first thin film disposed above the lower portion and protruding from the side of the lower portion, and a second thin film covering the first thin film and formed of a conductive oxide; and a polarizing plate disposed above the partition wall, wherein more than 90% of the display area is covered by the lower electrode or the partition wall when viewed from above.

[0006] According to other embodiments, the display device includes: a substrate having a display area for displaying an image; a lower electrode having a first metal layer opposite to the substrate and a first conductive oxide layer covering the upper surface of the first metal layer, disposed above the substrate in the display area; wiring having a second metal layer opposite to the substrate and a second conductive oxide layer covering the upper surface of the second metal layer, disposed between the substrate and the lower electrode in the display area; a rib layer having pixel openings overlapping the lower electrode, covering the lower electrode, and formed of an inorganic material; a partition wall including a lower portion disposed above the rib layer and having conductivity, a first thin film disposed above the lower portion and protruding from the side of the lower portion, and a second thin film covering the first thin film and formed of a conductive oxide; and a polarizing plate disposed above the partition wall.

[0007] According to the implementation method, a display device with good aesthetics can be provided. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating a structural example of the display device according to this embodiment.

[0009] Figure 2 This is a circuit diagram illustrating an example of a structure that can be applied to the pixel circuits that each sub-pixel possesses.

[0010] Figure 3 This is a schematic top view representing an example of the layout of subpixels.

[0011] Figure 4 It is along Figure 3 A schematic cross-sectional view of the display device for the IV-IV lines.

[0012] Figure 5 This is a schematic cross-sectional view of the lower electrode.

[0013] Figure 6 It is a rough cross-sectional view of the partition wall.

[0014] Figure 7 This is a schematic cross-sectional view showing an example of a layer structure that can be applied to circuit layers.

[0015] Figure 8 It is a schematic cross-sectional view of the metal layer.

[0016] Figure 9 This is a diagram showing an example of the structure of transistors included in a circuit layer.

[0017] Figure 10 It is a top view that shows the lower electrode, partition wall, and wiring in a general sense.

[0018] Figure 11 This diagram shows the display device as viewed from both the front and tilted directions.

[0019] Figure 12 It is a coordinate graph representing the chromaticity of the display panel. Detailed Implementation

[0020] Several embodiments are described with reference to the accompanying drawings.

[0021] The disclosed example is merely one instance. Technical solutions that can be readily conceived by those skilled in the art through appropriate modifications while maintaining the spirit of the invention are naturally included within the scope of this invention. Furthermore, to make the description clearer, the drawings may sometimes schematically represent the width, thickness, shape, etc., of various parts compared to the actual situation; however, this is merely an example and does not limit the interpretation of the invention. Additionally, in this specification and the drawings, the same reference numerals are given to constituent elements that perform the same or similar functions as those described in the preceding drawings, and sometimes repeated detailed descriptions are appropriately omitted.

[0022] Furthermore, in the accompanying drawings, for ease of understanding, mutually orthogonal X-axis, Y-axis, and Z-axis are shown. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. Additionally, viewing various elements parallel to the Z-direction is called a top view.

[0023] The display devices involved in each embodiment are organic electroluminescent display devices that have organic light-emitting diodes (OLEDs) as display elements, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet computers, smartphones, mobile phone terminals, and wearable terminals.

[0024] Figure 1 This diagram illustrates a structural example of the display device DSP according to this embodiment. The display device DSP includes a display panel PNL comprising an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 can be glass or a flexible resin film.

[0025] In this embodiment, the substrate 10 is circular when viewed from above. However, the shape of the substrate 10 when viewed from above is not limited to a circle, and may also be other shapes such as a rectangle, a square, or an ellipse.

[0026] The display area DA has multiple pixels PX arranged in a matrix in the X and Y directions. Pixel PX includes multiple sub-pixels SP that display different colors. In this embodiment, it is envisioned that pixel PX includes a green sub-pixel SP1, a blue sub-pixel SP2, and a red sub-pixel SP3. However, pixel PX may also include sub-pixels SP of other colors such as white, either together with or in place of any one of the sub-pixels SP1, SP2, and SP3.

[0027] The display device DSP also includes a terminal section T disposed in the peripheral area SA. For example, a flexible circuit board is connected to the terminal section T to provide voltage and signals for driving the display device DSP.

[0028] Figure 2 This is a circuit diagram illustrating an example of the structure of a pixel circuit PC that can be applied to each of the sub-pixels SP (SP1, SP2, SP3). The pixel circuit PC shown in the diagram includes seven transistors TR1 to TR7 and one holding capacitor Cst.

[0029] In the following description, one of the source and drain electrodes of transistors TR1 to TR7 will be referred to as the first electrode, and the other as the second electrode. Similarly, one electrode of the holding capacitor Cst will be referred to as the first electrode, and the other as the second electrode.

[0030] The first electrode of transistor TR1 is connected to node n3. The second electrode of transistor TR1 is connected to the signal line SL that provides the image signal Sdata. The image signal Sdata is the signal written to the pixels for image display.

[0031] Transistor TR2 is equivalent to a driving transistor that provides current to the display elements DE included in the sub-pixel SP. The first electrode of transistor TR2 is connected to node n1. The second electrode of transistor TR2 is connected to node n3.

[0032] The first electrode of transistor TR3 is connected to node n1. The second electrode of transistor TR3 is connected to node n2.

[0033] The first electrode of transistor TR4 is connected to node n1. The second electrode of transistor TR4 is connected to power line PL1, which provides the power supply voltage VDDEL.

[0034] The first electrode of transistor TR5 is connected to node n3. The second electrode of transistor TR5 is connected to node n4.

[0035] The first electrode of transistor TR6 is connected to node n4. The second electrode of transistor TR6 is connected to the initialization line IL, which provides the initialization voltage Vini.

[0036] The first electrode of transistor TR7 is connected to node n1. The second electrode of transistor TR7 is connected to power line PL2, which provides the power supply voltage VSH.

[0037] Keep the first electrode of capacitor Cst connected to node n2. Keep the second electrode of capacitor Cst connected to node n4.

[0038] The gate electrode of transistor TR1 is connected to scan line GL1, which provides scan signal Sg1. The gate electrodes of transistors TR4, TR5, and TR6 are each connected to scan line GL2, which provides scan signal Sg2. The gate electrode of transistor TR3 is connected to scan line GL3, which provides scan signal Sg3. The gate electrode of transistor TR7 is connected to scan line GL4, which provides scan signal Sg4.

[0039] The anode of the display element DE is connected at node n4. The cathode of the display element DE is connected to power line PL3, which provides the power supply voltage VSSEL. The aforementioned power supply voltage VDDEL is equivalent to the anode voltage supplied to the display element DE, and the power supply voltage VSSEL is equivalent to the cathode voltage supplied to the display element DE.

[0040] Furthermore, the structure of the pixel circuit PC is not limited to Figure 2 The example shown. For instance, the pixel circuit PC may have 6 or fewer transistors, or 8 or more transistors. Additionally, the pixel circuit PC may have multiple holding capacitors Cst.

[0041] Figure 3 This is a schematic top view showing an example of the layout of subpixels SP1, SP2, and SP3. Figure 3 In the example, subpixels SP2 and SP3 are side-by-side with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are side-by-side in the Y direction.

[0042] When sub-pixels SP1, SP2, and SP3 are arranged as described above, the display area DA has columns in which sub-pixels SP2 and SP3 are alternately arranged in the Y direction, and columns in which multiple sub-pixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Furthermore, the layout of sub-pixels SP1, SP2, and SP3 is not limited to... Figure 3 Examples.

[0043] A rib layer 5 is configured in the display area DA. Rib layer 5 has pixel openings AP1, AP2, and AP3 at sub-pixels SP1, SP2, and SP3, respectively. Figure 3 In the example shown, pixel openings AP1 and AP2 are larger than pixel opening AP3. Furthermore, the size and shape of pixel openings AP1, AP2, and AP3 are not limited to the example illustrated.

[0044] Sub-pixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with pixel opening AP1. Sub-pixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with pixel opening AP2. Sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel opening AP3.

[0045] The lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 overlapping with the pixel opening AP1 constitute the display element DE1 of sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 overlapping with the pixel opening AP2 constitute the display element DE2 of sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 overlapping with the pixel opening AP3 constitute the display element DE3 of sub-pixel SP3. Display elements DE1, DE2, and DE3 may further include the cover layer described later. Rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0046] The lower electrode LE1 is connected to the pixel circuit PC of sub-pixel SP1 through contact hole CH1. The lower electrode LE2 is connected to the pixel circuit PC of sub-pixel SP2 through contact hole CH2. The lower electrode LE3 is connected to the pixel circuit PC of sub-pixel SP3 through contact hole CH3.

[0047] A conductive partition wall 6 is disposed in the display area DA. The partition wall 6 is located above the rib layer 5 and overlaps with the rib layer 5 in general. Figure 3 In this example, partition wall 6 has the same planar shape as rib layer 5. That is, partition wall 6 has openings at sub-pixels SP1, SP2, and SP3, respectively. From another viewpoint, rib layer 5 and partition wall 6 appear as a grid when viewed from above, surrounding each display element DE1, DE2, and DE3. Furthermore, partition wall 6 surrounds pixel openings AP1, AP2, and AP3. Partition wall 6 serves as wiring to provide a common voltage to the upper electrodes UE1, UE2, and UE3.

[0048] The partition wall 6 has multiple slots SL6. Figure 3 In this example, each slit SL6 extends in the Y direction. In one example, the slit SL6 reaches both ends of the display area DA in the Y direction, dividing the partition wall 6 into multiple segments. For example, subpixels SP1, SP2, and SP3 constituting a pixel PX are arranged between two adjacent slits SL6 in the X direction. Furthermore, the arrangement of the slits SL6 is not limited to... Figure 3 For example, the gap SL6 does not overlap with the individual lower electrodes LE1, LE2, and LE3.

[0049] Figure 4 It is along Figure 3 A schematic cross-sectional view of the display device DSP with IV-IV lines. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes... Figure 2 The diagram shows various circuits and wiring, including pixel circuit PC, scan lines GL1-GL4, signal lines SL, power lines PL1-PL3, and initialization line IL. Circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarization film to flatten the unevenness caused by circuit layer 11.

[0050] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12 and are separated from each other. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The periphery of the lower electrodes LE1, LE2, and LE3 is covered by the rib layer 5. Although... Figure 4 The cross-section is not shown, but the lower electrodes LE1, LE2, and LE3 are connected to the pixel circuit PC of the circuit layer 11 through contact holes CH1, CH2, and CH3 respectively disposed on the organic insulating layer 12.

[0051] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a wider width than the lower portion 61. As a result, the two ends of the upper portion 62 protrude beyond the sides of the lower portion 61. Such a shape of the partition wall 6 is called an overhang.

[0052] exist Figure 4 In this example, the lower part 61 has a bottom layer 63 disposed above the rib layer 5, and a rod layer 64 disposed above the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the rod layer 64. Figure 4 In this example, the two ends of the bottom layer 63 protrude from the sides of the rod layer 64. Furthermore, when viewed from above, the ends of the bottom layer 63 are located between the ends of the upper layer 62 and the sides of the rod layer 64.

[0053] The upper part 62 is disposed on the rod layer 64. The upper part 62 has films 65 and 66. Film 65 (first film) is disposed on the rod layer 64. Film 66 (second film) is disposed on film 65. For example, films 65 and 66 may have the same width, or the width of film 66 may be slightly smaller than the width of film 65.

[0054] Organic layer OR1 covers lower electrode LE1 through pixel opening AP1. Upper electrode UE1 covers organic layer OR1 and is opposite to lower electrode LE1. Organic layer OR2 covers lower electrode LE2 through pixel opening AP2. Upper electrode UE2 covers organic layer OR2 and is opposite to lower electrode LE2. Organic layer OR3 covers lower electrode LE3 through pixel opening AP3. Upper electrode UE3 covers organic layer OR3 and is opposite to lower electrode LE3. Upper electrodes UE1, UE2, and UE3 are in contact with the side of the lower part 61 of partition wall 6.

[0055] Display element DE1 includes a cover layer CP1 covering the top electrode UE1. Display element DE2 includes a cover layer CP2 covering the top electrode UE2. Display element DE3 includes a cover layer CP3 covering the top electrode UE3. Cover layers CP1, CP2, and CP3 respectively function as optical adjustment layers to improve the extraction efficiency of light emitted by organic layers OR1, OR2, and OR3.

[0056] In the following description, the multilayer comprising organic layer OR1, upper electrode UE1 and capping layer CP1 is referred to as laminated film FL1, the multilayer comprising organic layer OR2, upper electrode UE2 and capping layer CP2 is referred to as laminated film FL2, and the multilayer comprising organic layer OR3, upper electrode UE3 and capping layer CP3 is referred to as laminated film FL3.

[0057] Sub-pixels SP1, SP2, and SP3 are respectively provided with sealing layers SE11, SE12, and SE13 covering the laminated films FL1, FL2, and FL3. Sealing layer SE11 continuously covers display element DE1 and the surrounding partition wall 6. Sealing layer SE12 continuously covers display element DE2 and the surrounding partition wall 6. Sealing layer SE13 continuously covers display element DE3 and the surrounding partition wall 6.

[0058] exist Figure 4 In the example, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the partition wall 6. Additionally, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact above the partition wall 6.

[0059] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. Laminated membranes FL1, FL2, FL3 may also be disposed in at least a portion of these gaps.

[0060] Sealing layers SE11, SE12, and SE13 are covered by resin layer RS1. Resin layer RS1 is covered by sealing layer SE2. Sealing layer SE2 is covered by resin layer RS2. Resin layers RS1, RS2, and sealing layer SE2 are disposed at least continuously throughout the entire display area DA, and a portion of them also extends to the peripheral area SA. The display panel PNL includes the constituent elements between the substrate 10 and resin layer RS2 described above.

[0061] A polarizing plate 15 is disposed above the display panel PNL. The polarizing plate 15 is bonded to the display panel PNL, for example, via an adhesive layer 14 such as OCA (Optical Clear Adhesive). In one example, the polarizing plate 15 is a circular polarizing plate.

[0062] The organic insulating layer 12 is formed of organic insulating materials such as polyimide. The rib layer 5 and sealing layers SE11, SE12, SE13, and SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon nitride oxide (SiON). In one example, the rib layer 5 is formed of silicon nitride oxide, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed, for example, of resin materials (organic insulating materials) such as epoxy resin and acrylic resin.

[0063] The upper electrodes UE1, UE2, and UE3 are formed, for example, from metallic materials such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0064] The capping layers CP1, CP2, and CP3, for example, have a stacked structure comprising multiple overlapping transparent layers. These transparent layers may include layers formed of inorganic materials and layers formed of organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers differ from the refractive indices of the upper electrodes UE1, UE2, and UE3, and the refractive indices of the sealing layers SE11, SE12, and SE13. Additionally, at least one of the capping layers CP1, CP2, and CP3 may be omitted.

[0065] A common voltage is provided to the partition wall 6. This common voltage is provided to the upper electrodes UE1, UE2, and UE3, which are in contact with the sides of the lower part 61. The pixel circuits PC of sub-pixels SP1, SP2, and SP3 respectively provide the lower electrodes LE1, LE2, and LE3 with pixel voltages corresponding to the image signals of the signal line SL.

[0066] In one example, the organic layers OR1, OR2, and OR3 are configured to emit light of different colors. As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may also include a color filter that converts the light emitted by each light-emitting layer of the organic layers OR1, OR2, and OR3 into light of the colors corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may also include a layer comprising quantum dots, which are excited by light emitted from the light-emitting layers to produce light of the colors corresponding to the sub-pixels SP1, SP2, and SP3.

[0067] Figure 5 This is a schematic cross-sectional view of the lower electrodes LE1, LE2, and LE3. Each of the lower electrodes LE1, LE2, and LE3 has a conductive oxide layer L1 (third conductive oxide layer), a metal layer L2 (first metal layer), and a conductive oxide layer L3 (first conductive oxide layer).

[0068] Metal layer L2 has a lower surface LS2 opposite to substrate 10 and an upper surface US2 on the opposite side. Conductive oxide layer L1 covers the lower surface LS2. Conductive oxide layer L3 covers the upper surface US2.

[0069] The metal layer L2 is formed, for example, of a metallic material with excellent light reflectivity, such as silver. The conductive oxide layers L1 and L3 are formed, for example, of transparent conductive oxides such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). In this embodiment, the conductive oxide layers L1 and L3 are formed of ITO.

[0070] The thicknesses of the conductive oxide layer L1, the metal layer L2, and the conductive oxide layer L3 are defined as thicknesses T1, T2, and T3, respectively. In this case, thickness T2 is greater than thicknesses T1 and T3 (T2 > T1 and T3). Conversely, thickness T1 is less than thickness T3 (T1 < T3). In one example, thickness T1 is less than half the thickness T3. Thickness T3 is, for example, 15 nm or more. In another example, thickness T3 is 15–20 nm.

[0071] Figure 6 This is a schematic cross-sectional view of the partition wall 6. As described above, the partition wall 6 includes a lower part 61 and an upper part 62, the lower part 61 including a bottom layer 63 and a rod layer 64, and the upper part 62 including films 65 and 66.

[0072] The bottom layer 63 and the rod layer 64 are formed of metallic materials, for example. For example, molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used as the metallic material for the bottom layer 63. For example, aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used as the metallic material for the rod layer 64. Furthermore, at least one of the bottom layer 63 and the rod layer 64 may have a multi-layered stacked structure. Additionally, the rod layer 64 may also include a layer formed of an insulating material.

[0073] As the metallic material for forming the thin film 65, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloys, or molybdenum-niobium alloys can be used, for example. The thin film 66 is formed of a conductive oxide such as ITO or IZO. In this embodiment, the thin film 66 is formed of ITO.

[0074] The thicknesses of the bottom layer 63, the rod layer 64, and the films 65 and 66 are defined as thicknesses T63, T64, T65, and T66, respectively. In this case, thickness T64 is greater than thicknesses T63, T65, and T66 (T64 > T63, T65, T66). Furthermore, thickness T65 is greater than thicknesses T63 and T66 (T65 > T63, T66). Further, thickness T63 is greater than thickness T66 (T63 > T66). Thickness T66 is greater than... Figure 5 The conductive oxide layer L3 shown has a large thickness T3 (T66 > T3). The thickness T66 is, for example, 45 nm or more. In one example, the thickness T66 is 45–55 nm.

[0075] Figure 7 This is a schematic cross-sectional view showing an example of a layer structure that can be applied to circuit layer 11. Figure 7 In the example shown, circuit layer 11 includes semiconductor layer 31, metal layers 32, 33, 34, 35, inorganic insulating layers 41, 42, 43, 44, 45 and organic insulating layer 46.

[0076] For example, semiconductor layer 31 corresponds to the bottom layer of circuit layer 11. However, an insulating layer may also be disposed below semiconductor layer 31. Inorganic insulating layer 41 covers semiconductor layer 31. Metal layer 32 is disposed on inorganic insulating layer 41. Inorganic insulating layer 42 covers metal layer 32. Inorganic insulating layer 43 covers inorganic insulating layer 42. Metal layer 33 is disposed on inorganic insulating layer 43. Inorganic insulating layer 44 covers metal layer 33. Metal layer 34 is disposed on inorganic insulating layer 44. Inorganic insulating layer 45 covers metal layer 34. Organic insulating layer 46 covers inorganic insulating layer 45. Metal layer 35 is disposed on organic insulating layer 46, by... Figure 4 The organic insulating layer 12 shown is used for covering.

[0077] Semiconductor layer 31 is formed, for example, from polycrystalline silicon, amorphous silicon, or oxide semiconductor. Metal layers 32-35 can be formed using a single-layer structure of metallic materials or a stacked structure using multiple metallic materials. In one example, metal layers 32 and 33 are formed from a molybdenum-tungsten alloy (MoW), and metal layers 34 and 35 are formed from a stacked structure (so-called TAT) consisting of a pair of titanium layers sandwiching an aluminum layer.

[0078] The inorganic insulating layers 41 to 45 are formed, for example, of inorganic insulating materials such as silicon nitride, silicon oxide, or silicon nitride. The organic insulating layer 46 is formed of an organic insulating material such as polyimide and is thicker than the inorganic insulating layers 41 to 45.

[0079] in addition, Figure 2 The signal lines SL, initialization line IL, power lines PL1, PL2, and scan lines GL1 to GL4 shown are formed by any one of metal layers 32 to 35. In one example, scan lines GL1 to GL4 are formed by at least one of metal layers 32 and 33, signal line SL and power line PL1 are formed by metal layer 34, and power line PL2 and initialization line IL are formed by metal layer 35.

[0080] Figure 8 This is a schematic cross-sectional view of metal layer 35. Metal layer 35 has metal layer L4 (second metal layer) and conductive oxide layer L5 (second conductive oxide layer). Metal layer L4 is a stack of thin films L41, L42, L43, and L44.

[0081] Thin film L41 is configured in Figure 7 The organic insulating layer 46 is shown above. Thin film L42 is disposed above thin film L41. Thin film L43 is disposed above thin film L42. Thin film L44 is disposed above thin film L43.

[0082] Metal layer L4 has a lower surface LS4 opposite to substrate 10 and an upper surface US4 on the opposite side. The lower surface LS4 and... Figure 7 The organic insulating layer 46 shown is in contact with the substrate. The upper surface US4 is covered by a conductive oxide layer L5.

[0083] Thin films L41 and L43 are formed, for example, of titanium. Thin film L42 is formed, for example, of aluminum. That is, the stack of thin films L41, L42, and L43 is formed of titanium nitride (TAT). Thin film L44 is formed, for example, of titanium nitride. The conductive oxide layer L5 is formed, for example, of a conductive oxide such as ITO or IZO. In this embodiment, the conductive oxide layer L5 is formed of ITO.

[0084] The thicknesses of thin films L41–L44 and the conductive oxide layer L5 are defined as thicknesses T41, T42, T43, T44, and T5, respectively. In this case, thickness T42 is greater than thicknesses T41, T43, T44, and T5 (T42 > T41, T43, T44, T5). Thicknesses T41 and T43 are greater than T44 and T5 (T41, T43 > T44, T5). In one example, thickness T43 is greater than thickness T41 (T43 > T41). Thickness T5 is greater than thickness T44 (T5 > T44).

[0085] Thickness T5 ratio Figure 5 The conductive oxide layer L3 shown has a greater thickness T3 (T5 > T3). Furthermore, the thickness T5 is greater than... Figure 6 The thickness T66 of the thin film 66 shown is small (T5 < T66). The thickness T5 is, for example, 20 nm or more. In one example, the thickness T5 is 20–30 nm.

[0086] Figure 9 This is a diagram showing an example of the structure of the transistors (TFTs) included in the circuit layer 11. Figure 9 The transistor TR shown includes a semiconductor SC, a gate electrode GE, conductive layers CLs and CLd, a source electrode SO, and a drain electrode DR.

[0087] Semiconductor SC is covered by inorganic insulating layer 41. Gate electrode GE is disposed on inorganic insulating layer 41 and covered by inorganic insulating layer 42. Conductive layers CLs and CLd are separated from each other, disposed on inorganic insulating layer 43 and covered by inorganic insulating layer 44. Source electrode SO and drain electrode DR are separated from each other, disposed on inorganic insulating layer 44 and covered by inorganic insulating layer 45.

[0088] The conductive layer CLs is connected to the semiconductor SC through contact holes CHs1 respectively disposed in the inorganic insulating layers 41, 42, and 43. The conductive layer CLd is connected to the semiconductor SC through contact holes CHd1 respectively disposed in the inorganic insulating layers 41, 42, and 43.

[0089] The source electrode SO is connected to the conductive layer CLs through the contact hole CHs2 provided in the inorganic insulating layer 44. The drain electrode DR is connected to the conductive layer CLd through the contact hole CHd2 provided in the inorganic insulating layer 44. Alternatively, the source electrode SO and the drain electrode DR can also be directly connected to the semiconductor SC through the contact holes respectively provided in the inorganic insulating layers 41 to 44.

[0090] Semiconductor SC is formed from semiconductor layer 31. Gate electrode GE is formed from metal layer 32. Conductive layers CLs and CLd are formed from metal layer 33. Source electrode SO and drain electrode DR are formed from metal layer 34. Wiring TL is formed from metal layer 35. The structure of transistor TR can be applied to... Figure 2The transistors shown are TR1 to TR7.

[0091] The source electrode SO or drain electrode DR is connected to the wiring TL. The wiring TL is disposed on organic insulating layer 46 and covered by organic insulating layer 12. Figure 9 In the example, the wiring TL is connected to the drain electrode DR through contact holes CHt respectively disposed in the inorganic insulating layer 45 and the organic insulating layer 46. The wiring TL, for example, is connected through... Figure 3 The contact holes CH1, CH2, CH3 shown are connected to the lower electrodes LE1, LE2, LE3.

[0092] Figure 10 This is a top view showing the lower electrodes LE1, LE2, LE3, separator 6, and wiring TL. Figure 10 The example shows two pixels of lower electrodes LE1, LE2, LE3, separator 6, and wiring TL arranged in the X direction. The configuration of the lower electrodes LE1, LE2, LE3, and separator 6 is similar to... Figure 3 The example shown is the same. In Figure 10 In the diagram, dotted patterns are used to mark partition wall 6, and diagonal lines are used to mark wiring TL. Lower electrodes LE1, LE2, and LE3 are represented by dashed lines.

[0093] exist Figure 10 In the example, the wiring TL includes a first section TL1 with multiple branches, a second section TL2 in the shape of an island, and a third section TL3 with multiple branches. The first section TL1 and the third section TL3 extend in the X and Y directions, respectively. Figure 10 In the example, the first part TL1 overlaps with the lower electrodes LE1, LE2, and LE3, and the third part TL3 overlaps with LE1 and LE2. The first part TL1 and the third part TL3 are arranged alternately in the X direction. The second part TL2 has, for example, a rectangular or square shape that is longer in the Y direction. Furthermore, the shape and arrangement of the wiring TLs are not limited to the example shown.

[0094] Most of the wiring TL overlaps with the lower electrodes LE1, LE2, LE3 or partition wall 6 in the display area DA. The remaining portion overlaps with the gap SL6. Figure 10 In the example, a portion of the first section TL1 overlaps with the slot SL6. Furthermore, either the second section TL2 or the third section TL3 may also overlap with the slot SL6. The wiring TL does not overlap with the lower electrodes LE1, LE2, LE3, or the separator wall 6 at the slot SL6. Figure 10 In the diagram, dashed lines represent the portions of wiring TL that overlap with the lower electrodes LE1, LE2, LE3 or partition wall 6, while solid lines represent the portions of wiring TL that do not overlap with the lower electrodes LE1, LE2, LE3 or partition wall 6.

[0095] The area covered by the lower electrodes LE1, LE2, and LE3 in display area DA is larger than the area covered by the partition wall 6 and the area covered by the wiring TL in display area DA. Conversely, the area covered by the partition wall 6 in display area DA is smaller than the area covered by the wiring TL in display area DA.

[0096] In one example, the proportion of the area covered by the lower electrodes LE1, LE2, and LE3 in the display area DA is 70-80%. Additionally, the proportion of the area covered by the partition wall 6 in the display area DA is 35-50%. Furthermore, the proportion of the area covered by the wiring TL in the display area DA is 60-70%.

[0097] In the display device DSP according to this embodiment, more than 90% of the display area DA is covered by the lower electrodes LE1, LE2, LE3, the partition wall 6, or the wiring TL. Additionally, there are areas in the display area DA that are not covered by the lower electrodes LE1, LE2, LE3, the partition wall 6, or the wiring TL. Figure 10 In the example, the area in gap SL6 that does not overlap with the lower electrodes LE1, LE2, LE3 and wiring TL belongs to the aforementioned area.

[0098] Furthermore, more than 90% of the display area DA can also be covered by the lower electrodes LE1, LE2, LE3 or the partition wall 6. Alternatively, more than 90% of the display area DA can also be covered by any one of the lower electrodes LE1, LE2, LE3, partition wall 6, and wiring TL.

[0099] Figure 11 This is a diagram showing the display device DSP viewed from both a frontal and tilted perspective. Figure 11 (a) is a diagram showing the display device DSP when viewed from the front. Figure 11 (b) is a diagram showing the display device DSP as viewed from an oblique direction. Here, the front direction corresponds to the normal direction of the substrate 10. That is, the front direction corresponds to a direction parallel to the Z direction. Furthermore, the oblique direction corresponds to a direction oblique to the normal direction of the substrate 10. Figure 11 In example (b), the display device DSP is shown as viewed from a direction tilted towards the Y direction relative to the normal direction. Furthermore, in Figure 11 In the middle, the following was omitted. Figure 1 The terminal portion T shown. The varying shades of the dots marked on the polarizer 15 represent the different densities of black in the polarizer 15.

[0100] like Figure 11 As shown in (a), when the display device DSP according to this embodiment is viewed from the front, the polarizer 15 appears black. However, as the angle at which the display device DSP is viewed increases relative to the normal direction, the color of the light on the shorter wavelength side is highlighted. Therefore, as the angle at which the display device DSP is viewed increases relative to the normal direction, the color of the polarizer 15 appears to change from black to blue. Thus, as... Figure 11 As shown in (b), when the display device DSP of this embodiment is viewed from an oblique direction, the polarizing plate 15 appears as a bluish-black color.

[0101] The polarizing plate 15 is provided to prevent the reflection of external light and generally appears black. The polarizing plate 15 is configured to reduce the reflectivity of light with wavelengths around 550 nm, for example. In this structure, when the display device DSP is viewed from an angle, some light with wavelengths shorter than 550 nm and some with wavelengths longer than 550 nm are sometimes reflected due to differences in wavelength. Therefore, the color of the polarizing plate 15 appears different depending on the angle at which the display device DSP is viewed.

[0102] Here, the principle that the polarizer 15 appears as a bluish-black color when viewed from an angle of tilt will be explained. Figure 12 This is a coordinate graph representing the chromaticity of the PNL (Parallel Color Scale) of the display panel. Figure 12 In the coordinate graph shown, the positive direction of the horizontal axis is defined as +a, and the negative direction as -a. Similarly, the positive direction of the vertical axis is defined as +b, and the negative direction as -b.

[0103] The larger the value of +a (towards the right on the graph), the more prominent the color of the object appears as red. Conversely, the larger the value of -a (towards the left on the graph), the more prominent the color of the object appears as green. Additionally, the larger the value of +b (towards the top of the graph), the more prominent the color of the object appears as yellow. Conversely, the larger the value of -b (towards the bottom of the graph), the more prominent the color of the object appears as blue. As we approach the origin, the color of the object appears as black.

[0104] exist Figure 12Points P1 and P2 are shown in the coordinate graph. Point P1 represents the result obtained by measuring the chromaticity of the display panel PNL involved in the comparative example. In the display panel PNL involved in the comparative example, 50% of the display area DA is covered by the lower electrodes LE1, LE2, LE3, the partition wall 6, or the wiring TL. Point P2 represents the result obtained by measuring the chromaticity of the display panel PNL involved in this embodiment. In the display panel PNL involved in this embodiment, as described above, more than 90% of the display area DA is covered by the lower electrodes LE1, LE2, LE3, the partition wall 6, or the wiring TL. Furthermore, it should be noted that the polarizer 15 is not installed in the display panel PNL.

[0105] These measurements represent the chromaticity when the display panel PNL is viewed from the normal direction. Furthermore, these measurements were performed using the SCI (Specular Component Include) method, which measures all reflected light, including diffuse and specular reflections.

[0106] like Figure 12 As shown in the coordinate graph, the value of +b at point P2 is greater than the value of +b at point P1. Therefore, the display panel PNL at point P2 appears more yellow than the display panel PNL at point P1.

[0107] The color of the display panel PNL varies depending on the proportion of the area covered by ITO. As the proportion of this area increases, the color of the display panel PNL appears more prominently yellow. In the lower electrodes LE1, LE2, and LE3, the conductive oxide layer L3 formed by ITO is located on the top layer. In the separator 6, the thin film 66 formed by ITO is located on the top layer. In the wiring TL, the conductive oxide layer L5 formed by ITO is located on the top layer. Furthermore, in the display panel PNL according to this embodiment, the area of ​​the display region DA covered by the lower electrodes LE1, LE2, LE3, separator 6, or wiring TL is larger than that area of ​​the display panel PNL according to the comparative example. Therefore, the ITO coverage of the display panel PNL according to this embodiment is higher than that of the display panel PNL according to the comparative example. Therefore, the display panel PNL according to this embodiment appears more prominently yellow than the display panel PNL according to the comparative example.

[0108] External light incident on the display device DSP passes through the polarizer 15 and is reflected by the surface of the display panel PNL. Most of the reflected light is absorbed by the polarizer 15, but a portion of the reflected light passes through the polarizer 15. The color of the polarizer 15 mounted on the display panel PNL is affected by the wavelength of the reflected light that has passed through the polarizer 15.

[0109] As described above, the +b value of the display panel PNL in the comparative example is smaller than the +b value of the display panel PNL in this embodiment. Therefore, the yellow component of the reflected light from the display panel PNL of the comparative example is less than that from the display panel PNL of this embodiment. That is, the reflected light from the display panel PNL of the comparative example contains more long-wavelength light. Therefore, when the display device DSP of the comparative example is viewed from an angle, the color of the polarizer 15 sometimes appears as a reddish black.

[0110] The +b value of the display panel PNL in this embodiment is greater than the +b value of the display panel PNL in the comparative example. Therefore, the reflected light from the display panel PNL of this embodiment has more yellow component than the reflected light from the display panel PNL of the comparative example. That is, the reflected light from the display panel PNL of this embodiment contains more short-wavelength light than the comparative example. Therefore, as... Figure 11 As shown in (b), when the display device DSP of this embodiment is viewed from an oblique direction, the color of the polarizing plate 15 appears as a bluish-black.

[0111] In terms of the aesthetics of a display device DSP, blue tends to be better than red. Therefore, by making the color of the polarizing plate 15 close to blue when viewed from an oblique direction, as in the display device DSP according to this embodiment, the aesthetics of the display device DSP can be improved.

[0112] Furthermore, the inventors conducted actual experiments to confirm the color change of the polarizing plate 15 when the proportion of the area covered by the lower electrodes LE1, LE2, LE3, the partition wall 6, or the wiring TL in the display area DA was changed. As a result, it was confirmed that by making this area 90% or more, the polarizing plate 15 appeared as a bluish-black color. Based on this result, it was determined that it is preferable to make this area 90% or more.

[0113] Furthermore, the thicker the ITO film, the more pronounced the yellow hue of the PNL display panel becomes. The more pronounced the yellow hue, the more the red hue of the polarizer 15 in the comparative example is canceled out. Therefore, to highlight the blue hue of the polarizer 15, the thicker the ITO film, the better.

[0114] In this embodiment, the thickness T3 of the conductive oxide layer L3 is thicker than the thickness T1 of the conductive oxide layer L1. This increased thickness T3 further enhances the aesthetics of the display device DSP.

[0115] Any display device that can be implemented by those skilled in the art by making appropriate design changes based on the display device described above as an embodiment of the present invention, as long as it contains the spirit of the present invention, is also within the scope of the present invention.

[0116] Within the scope of this invention, various modifications will be conceived by those skilled in the art, and these modifications are also considered to fall within the scope of this invention. For example, any technical solution obtained by appropriately adding, deleting, or designing constituent elements of the above embodiments, or by adding, omitting, or changing the conditions of processes, as long as the spirit of this invention is present, is also included within the scope of this invention.

[0117] Furthermore, other effects resulting from the technical solutions described in the above embodiments are to be interpreted as effects that are clearly known from the description in this specification, or effects that can be appropriately conceived by those skilled in the art, and are naturally caused by the present invention.

Claims

1. A display device, characterized in that, have: A substrate having a display area for displaying images; The lower electrode has a first metal layer opposite to the substrate and a first conductive oxide layer covering the upper surface of the first metal layer, and is disposed above the substrate in the display area. A rib layer, having pixel openings overlapping the lower electrode and covering the lower electrode, is formed of an inorganic material; A partition wall includes a lower portion disposed on the rib layer and having conductivity, a first film disposed on the lower portion and protruding from the side of the lower portion, and a second film covering the first film and formed of a conductive oxide. as well as A polarizing plate, which is positioned above the partition wall. When viewed from the normal direction of the substrate, the polarizing plate appears black. When viewed from an angled direction relative to the normal direction, the polarizing plate appears as a bluish-black color.

2. The display device according to claim 1, characterized in that, As the angle at which the polarizer is observed relative to the normal direction increases, the polarizer appears to change from black to blue.

3. A display device, characterized in that, have: A substrate having a display area for displaying images; The lower electrode has a first metal layer opposite to the substrate and a first conductive oxide layer covering the upper surface of the first metal layer, and is disposed above the substrate in the display area. A rib layer, having pixel openings overlapping the lower electrode and covering the lower electrode, is formed of an inorganic material; A partition wall includes a lower portion disposed on the rib layer and having conductivity, a first film disposed on the lower portion and protruding from the side of the lower portion, and a second film covering the first film and formed of a conductive oxide. as well as A polarizing plate, which is positioned above the partition wall. More than 90% of the display area is covered by the lower electrode or the partition wall when viewed from above.

4. The display device according to claim 1 or 3, characterized in that, The partition wall has a slit that extends in one direction and does not overlap with the lower electrode.

5. The display device according to claim 1 or 3, characterized in that, It also includes wiring having a second metal layer opposite to the substrate and a second conductive oxide layer covering the upper surface of the second metal layer, disposed between the substrate and the lower electrode in the display area.

6. The display device according to claim 5, characterized in that, The partition wall has a slit that extends in one direction and does not overlap with the lower electrode. The gap overlaps with a portion of the wiring.

7. A display device, characterized in that, have: A substrate having a display area for displaying images; The lower electrode has a first metal layer opposite to the substrate and a first conductive oxide layer covering the upper surface of the first metal layer, and is disposed above the substrate in the display area. The wiring has a second metal layer opposite to the substrate and a second conductive oxide layer covering the upper surface of the second metal layer, and is disposed between the substrate and the lower electrode in the display area; A rib layer, having pixel openings overlapping the lower electrode and covering the lower electrode, is formed of an inorganic material; A partition wall comprising a lower portion disposed above the rib layer and having conductivity, a first thin film disposed above the lower portion and projecting from a side of the lower portion, and a second thin film covering the first thin film and formed of a conductive oxide; and A polarizing plate is disposed above the partition wall.

8. The display device according to claim 7, characterized in that, More than 90% of the display area is covered by the lower electrode, the partition wall, or the wiring when viewed from above.

9. The display device according to claim 7, characterized in that, The partition wall has a slit that extends in one direction and does not overlap with the lower electrode. The gap overlaps with a portion of the wiring.

10. The display device according to claim 1, 3, or 7, characterized in that, The area covered by the lower electrode in the display area is larger than the area covered by the partition wall in the display area.

11. The display device according to claim 7, characterized in that, The area covered by the lower electrode in the display area is larger than the area covered by the wiring in the display area.

12. The display device according to claim 7, characterized in that, The area covered by the partition wall in the display area is smaller than the area covered by the wiring in the display area.

13. The display device according to claim 1, 3, or 7, characterized in that, The lower electrode also has a third conductive oxide layer, which covers the lower surface of the first metal layer and is thinner than the first conductive oxide layer.

14. The display device according to claim 13, characterized in that, The thickness of the third conductive oxide layer is less than half the thickness of the first conductive oxide layer.

15. The display device according to claim 1, 3, or 7, characterized in that, The thickness of the first conductive oxide layer is 15 nm or more.

16. The display device according to claim 1, 3, or 7, characterized in that, The thickness of the second film is 45 nm or more.

17. The display device according to claim 7, characterized in that, The thickness of the second conductive oxide layer is 20 nm or more.

18. The display device according to claim 7, characterized in that, The second metal layer comprises a stack of titanium and aluminum layers.

Images