Inter-chip interconnect verification method, device, storage medium and program product

Abstract

Embodiments of the present application provide a chip-to-chip interconnection verification method, device, storage medium and program product. A chip-to-chip interconnection verification environment includes a first chip side and a second chip side, both of which are configured with a routing intermediate module, a plurality of master devices VIP and a plurality of composite slave devices VIP which have full consistency home node function and slave device response function. The first routing intermediate module decouples the request transaction channel and the snoop transaction channel; receives the request transaction issued by the target first master device VIP, determines the target composite slave device VIP according to the target address and routes; receives the response transaction, the completion data transaction and the snoop transaction generated by the target composite slave device VIP, and routes to the target first master device VIP according to the transaction association identifier through the corresponding routing path; and provides the routed transaction information to the monitor and the score board to obtain the chip-to-chip interconnection verification result. The integrity and accuracy of the on-chip transaction, cross-chip transaction and cache consistency transaction verification are improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design verification technology, and in particular to an inter-chip interconnect verification method, device, storage medium and program product. Background Technology

[0002] With the development of system-on-a-chip (SoC) and multi-chip integration technologies, multiple chips typically interact at high speed via a chip-to-chip (Chip2Chip) bus. The functional correctness and timing consistency of this bus directly determine the performance and reliability of the entire system. To fully verify the inter-chip interconnect logic before tape-out, engineering practices employ verification platforms based on Universal Verification Methodology (UVM). These platforms construct verification environments at both ends of the Design Under Test (DUT) for the inter-chip interconnect, covering scenarios where both sides of the chip simultaneously initiate access, receive returned data, and handle consistent interactions.

[0003] The Verification IP (VIP) is a component in the verification environment used to generate and respond to protocol transactions, and to check protocol behavior. In an inter-chip interconnect verification environment with a cache consistency mechanism, VIPs are typically deployed as Master and Slave devices with a single role. The Master VIP is responsible for initiating requests (Req), receiving responses (Resp) or completion data (CompData) associated with initiated requests, and receiving and processing snoop requests (Snp) from the Fully-Coherent Home Node (HNF). The Slave VIP is responsible for receiving requests and returning responses or data. Additionally, in this verification environment, an HNF component needs to be configured to maintain a consistency directory for shared data and initiate consistency interactions such as snooping, invalidation, and write-back to each Master VIP.

[0004] However, in the aforementioned verification architecture based on a one-way VIP, the transaction processing paths of the master device VIP and the slave device VIP are independent and pre-defined. Furthermore, the HNF component and the slave device VIP belong to different components, lacking a unified interaction and coordination mechanism. When the verification environment needs to simulate real-world scenarios such as concurrent access from multiple master devices on both sides, cross-chip access, and concurrent consistency maintenance by multiple HCFs, the transaction interleaving relationships between VIP instances and the ownership paths of cross-chip transactions are difficult to clearly define and uniformly manage, resulting in insufficient functional verification coverage in concurrent scenarios of inter-chip interconnection. Summary of the Invention

[0005] This application provides an inter-chip interconnect verification method, device, storage medium, and program product to coordinate concurrent interactions between multiple master devices (VIPs), multiple slave devices (VIPs), and multiple HNFs, and to verify the consistency of local and cross-chip transactions.

[0006] In a first aspect, embodiments of this application provide an inter-chip interconnect verification method, applied to a first routing intermediate module in an inter-chip interconnect verification environment; the inter-chip interconnect verification environment is used to verify an inter-chip interconnect design under test including a first chip and a second chip, including a first chip side and a second chip side; the first chip side is configured with a first routing intermediate module, multiple first master device VIPs and multiple first composite slave device VIPs; the second chip side is configured with a second routing intermediate module, multiple second master device VIPs and multiple second composite slave device VIPs; the composite first slave device VIP and the second composite slave device VIP both have fully consistent home node functionality and slave device VIP response functionality; the method includes: The request transaction channel and the eavesdropping transaction channel connected to the first chip side are decoupled to form request transaction routing paths and eavesdropping transaction routing paths respectively; Receive a request transaction sent by a target first master device VIP, determine the target composite slave device VIP corresponding to the request transaction based on the target address of the request transaction, wherein the target first master device VIP is any one of the plurality of first master device VIPs; The request transaction is routed to the target composite slave device VIP via the request transaction routing path; The system receives response transactions, completion data transactions, and probe transactions generated by the target composite slave device VIP, with the target first master device VIP as the target. The response transactions and completion data transactions are generated using the slave device response function of the target composite slave device VIP, and the probe transactions are generated using the fully consistent home node function of the target composite slave device VIP. Based on the transaction association identifier, the response transaction and the completion data transaction are routed to the target first master device VIP through the request transaction routing path, and the eavesdropping transaction is routed to the target first master device VIP through the eavesdropping transaction routing path; The transaction information routed by the first routing intermediate module is provided to the monitor and the scoreboard, so that the monitor and the scoreboard can associate and compare the transactions on the first chip side, the second chip side, and the cross-chip transactions to obtain the inter-chip interconnection verification results.

[0007] Secondly, embodiments of this application provide an inter-chip interconnect verification device, applied to a first routing intermediate module in an inter-chip interconnect verification environment; the inter-chip interconnect verification environment is used to verify an inter-chip interconnect design under test including a first chip and a second chip, including a first chip side and a second chip side; the first chip side is configured with the first routing intermediate module, multiple first master device VIPs and multiple first composite slave device VIPs; the second chip side is configured with the second routing intermediate module, multiple second master device VIPs and multiple second composite slave device VIPs; the composite first slave device VIP and the second composite slave device VIP both have fully consistent home node function and slave device VIP response function; the device includes: The decoupling module is used to decouple the request transaction channel and the eavesdropping transaction channel connected to the first chip side, so as to form request transaction routing paths and eavesdropping transaction routing paths respectively; The processing module is configured to receive a request transaction sent by a target first master device VIP; determine the target composite slave device VIP corresponding to the request transaction based on the target address of the request transaction, wherein the target first master device VIP is any one of the plurality of first master device VIPs; route the request transaction to the target composite slave device VIP through the request transaction routing path; receive response transactions, completion data transactions, and probe transactions generated by the target composite slave device VIP with the target first master device VIP as the target, wherein the response transactions and completion data transactions are generated using the slave device response function of the target composite slave device VIP, and the probe transactions are generated using the fully consistent home node function of the target composite slave device VIP; and route the response transactions and completion data transactions to the target first master device VIP through the request transaction routing path and the probe transactions to the target first master device VIP based on the transaction association identifier. The verification module is used to provide the transaction information routed by the first routing intermediate module to the monitor and the scoreboard, so that the monitor and the scoreboard can associate and compare the transactions on the first chip side, the second chip side, and the cross-chip transactions to obtain the inter-chip interconnection verification results.

[0008] Thirdly, embodiments of this application provide an electronic device, including: a memory, a processor, and a communication interface; wherein, the memory stores a computer program, and when the computer program is executed by the processor, the processor can at least implement the inter-chip interconnection verification method as described in the first aspect.

[0009] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor of an electronic device, enables the processor to at least implement the inter-chip interconnect verification method as described in the first aspect.

[0010] Fifthly, embodiments of this application provide a computer program product, including: a computer program or instructions, which, when executed by a processor of an electronic device, enable the processor to at least implement the inter-chip interconnect verification method as described in the first aspect.

[0011] The inter-chip interconnect verification scheme provided in this application embodiment, in an inter-chip interconnect verification environment including a first chip side and a second chip side, is configured with a routing intermediate module, multiple master device VIPs, and multiple composite slave device VIPs that have both full consistency home node functions and slave device response functions, respectively. The first routing intermediate module decouples the request transaction channel and the probe transaction channel to form independent request transaction routing paths and probe transaction routing paths. It receives request transactions sent by the target first master device VIP, determines the target composite slave device VIP according to the target address of the request transaction, and routes the request transaction to the target composite slave device VIP. Then, it receives response transactions, completion data transactions, and probe transactions generated by the target composite slave device VIP. Based on the transaction association identifier, it sends the response transaction and completion data transaction to the target first master device VIP via the request transaction routing path and the probe transaction via the probe transaction routing path. It also provides the transaction information during the routing process to the monitor and scoreboard for association and comparison. Therefore, in the verification architecture of dual-sided symmetric, multi-master device VIP and multi-composite slave device VIP, request transactions and listening transactions can be clearly distinguished, and the accurate association and routing of request, response, completion data and listening transactions can be realized, thereby improving the verification integrity and verification accuracy of local transactions, cross-chip transactions and cache consistency transactions. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of a scenario for an inter-chip interconnection verification environment provided in an embodiment of this application; Figure 2 A flowchart illustrating an inter-chip interconnect verification method provided in this application embodiment; Figure 3A schematic diagram of a bidirectional concurrent communication verification process provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a VIP extension plugin interface provided in an embodiment of this application; Figure 5 A schematic diagram of an inter-chip interconnection verification device provided in an embodiment of this application; Figure 6 To and Figure 5 The illustrated embodiment provides a schematic diagram of the electronic device corresponding to the inter-chip interconnect verification device. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0015] It should be noted that, in the cases involving user information in the embodiments of this application, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse. In addition, the various models involved in this application (including but not limited to language models or large models) comply with relevant laws and standards.

[0016] Furthermore, the timing of the steps in the following method embodiments is merely an example and not a strict limitation.

[0017] Existing inter-chip interconnect verification environments typically deploy the master device VIP, slave device VIP, and consistency home node as independent components, and mostly adopt a one-sided, unidirectional connection method. When there are multiple master devices and multiple slave devices on both the first chip side and the second chip side, traditional connection methods make it difficult to clearly distinguish between request transactions and eavesdropping transactions, and also make it difficult to support multiple master device VIPs to initiate requests simultaneously.

[0018] To address the aforementioned issues, this embodiment constructs a verification environment for verifying the inter-chip interconnect design under test (UTC) between a first chip and a second chip. This verification environment includes a first chip side and a second chip side. The first chip side is configured with a first routing intermediate module, multiple first master device VIPs, and multiple first composite slave device VIPs; the second chip side is configured with a second routing intermediate module, multiple second master device VIPs, and multiple second composite slave device VIPs.

[0019] The first routing intermediate module and the second routing intermediate module are used to connect the master device VIP, the composite slave device VIP and the inter-chip interconnection design under test on their respective chip sides, and to decouple and route the transaction channels to support the transmission of local transactions and cross-chip transactions.

[0020] The first primary device VIP and the second primary device VIP are used to initiate request transactions, receive response transactions or complete data transactions associated with the request transaction, and handle eavesdropping transactions.

[0021] Both the first and second composite slave VIPs possess both fully consistent home node functionality and slave response functionality. The slave response function receives read or write requests and returns a response transaction or completes a data transaction based on the storage model. The fully consistent home node function maintains address-related consistency and initiates snooping transactions when necessary.

[0022] For ease of understanding, combined with Figure 1 Please provide an explanation. Figure 1 This is a schematic diagram illustrating a scenario for an inter-chip interconnection verification environment provided in an embodiment of this application. For example... Figure 1 As shown, the inter-chip interconnect design under test (DUT) includes a first chip, Chip A, and a second chip, Chip B; the side A where Chip A is located corresponds to the first chip side, and the side B where Chip B is located corresponds to the second chip side.

[0023] Side A is configured with a first routing intermediate module (Router, left), multiple first master device VIPs, and multiple first composite slave device VIPs. The multiple first master device VIPs include first master device VIP#1 to first master device VIP#N, i.e. Figure 1 The diagram illustrates Master VIP #1 to Master VIP #N located on side A; multiple first composite slave VIPs include first composite slave VIP #1 to first composite slave VIP #M, that is... Figure 1 The diagram shows HNF+Slave #1 to HNF+Slave #M located on side A.

[0024] Similar to side A, side B is configured with a second routing intermediate module (Router, right), multiple second master device VIPs, and multiple second composite slave device VIPs. The multiple second master device VIPs include second master device VIP#1 to second master device VIP#N, i.e. Figure 1 The diagram illustrates Master VIP #1 to Master VIP #N located on side B; multiple second composite slave VIPs include second composite slave VIP #1 to second composite slave VIP #M, that is... Figure 1 The diagram shows HNF+Slave #1 to HNF+Slave #M located on side b.

[0025] The first routing intermediate module (left) and the second routing intermediate module (right) are connected to the interfaces on both sides of the design under test, forming a dual-symmetric multi-master device and multi-composite slave device verification topology between Chip A and Chip B.

[0026] In practical applications, the component composition and connection relationship of the first chip side and the second chip side in the verification environment are symmetrical, and the transaction reception, routing forwarding and verification cooperation methods performed by the routing intermediate modules on both sides are the same. Therefore, this application embodiment takes the first routing intermediate module on the first chip side as an example to describe the inter-chip interconnection verification method; the second routing intermediate module can use the same method as the first routing intermediate module to process the transactions on the second chip side.

[0027] Figure 2 A flowchart of an inter-chip interconnection verification method provided in this application embodiment is applied to a first routing intermediate module, such as... Figure 2 As shown, it may include the following steps 201-206: 201. Decouple the request transaction channel and the eavesdropping transaction channel connected to the first chip side to form request transaction routing paths and eavesdropping transaction routing paths respectively.

[0028] In this embodiment, the first routing intermediate module logically divides the transaction channels connected to the first chip side according to the transaction types they carry. Specifically, the request transaction channel is used to transmit request transactions issued by the first master device VIP, as well as corresponding response transactions and completion data transactions; the snooping transaction channel is used to transmit snooping transactions issued by the fully consistent home node function of the composite slave device VIP (including the first composite slave device VIP and the second composite slave device VIP).

[0029] The first routing intermediate module configures independent input interfaces, output interfaces, transaction cache queues, and routing control logic for the request transaction channel and the eavesdropping transaction channel, so that request transactions, response transactions, and completed data transactions only enter the request transaction routing path, and eavesdropping transactions only enter the eavesdropping transaction routing path, thus forming independent request transaction routing paths and eavesdropping transaction routing paths.

[0030] The request transaction routing path refers to the transmission path consisting of the input interface of the request transaction channel, the request transaction buffer queue, the request transaction routing control logic, and the corresponding output interface in sequence; the snooping transaction routing path refers to the transmission path consisting of the input interface of the snooping transaction channel, the snooping transaction buffer queue, the snooping transaction routing control logic, and the corresponding output interface in sequence.

[0031] The request transaction routing control logic is used to send the request transaction to the corresponding first composite slave device VIP, second routing intermediate module, or target first master device VIP based on the target address and transaction association identifier. The snooping transaction routing control logic is used to determine the target first master device VIP corresponding to the snooping transaction based on the transaction association identifier, and send the snooping transaction to the target first master device VIP.

[0032] Through the above decoupling method, request transactions and eavesdropping transactions are processed in their respective cache queues and routing control logic, avoiding confusion between the two types of transactions during the routing process.

[0033] 202. Receive a request transaction sent by the target first master device VIP, determine the target composite slave device VIP corresponding to the request transaction based on the target address of the request transaction, and the target first master device VIP is any one of multiple first master device VIPs.

[0034] In this embodiment, a request transaction refers to a transaction initiated by the target first primary device VIP to access storage resources. This can be a read request transaction, a write request transaction, or other access requests that need to be processed by the slave device VIP. The target first primary device VIP is the primary device VIP that actually issues the current request transaction among multiple primary device VIPs, for example... Figure 1 The Master VIP #1 is located on side A. In practice, different primary master VIPs can issue their respective request transactions at the same or different simulation times. The target composite slave VIP is the composite slave VIP to which the request transaction should reach.

[0035] In the specific implementation process, the first routing intermediate module receives the request transaction sent by the target first master device VIP from the input interface of the request transaction routing path, and parses the request transaction to obtain the initiator identifier, target address and transaction association identifier in the request transaction.

[0036] Among them, the initiator identifier is used to uniquely identify the target first master device VIP; the target address is the address corresponding to the storage unit or storage area to be accessed; the transaction association identifier is the identification information corresponding to the current request transaction, which is used to associate the current request transaction with the response transaction, the completed data transaction and the eavesdropping transaction generated based on the request transaction.

[0037] Optionally, the first routing intermediate module may save the initiator identifier and transaction association identifier along with the request transaction in the request transaction routing path for use in the subsequent return transaction routing.

[0038] In an optional embodiment, an address mapping table can be pre-configured in the first routing intermediate module. This address mapping table records the routing correspondence between target addresses and composite slave device VIPs. Specifically, the address mapping table includes multiple address mapping entries, each including an address range and a composite slave device VIP identifier. The address range is determined by a start address and an end address, or by a base address and an address range; the composite slave device VIP identifier uniquely identifies one of the multiple first composite slave device VIPs and multiple second composite slave device VIPs.

[0039] Optionally, the composite slave device VIP identifier also includes a side identifier, which indicates whether the corresponding composite slave device VIP is located on the first chip side or the second chip side.

[0040] Based on the pre-configured address mapping table, after receiving a request transaction from the target first master device VIP, the first routing intermediate module compares the parsed target address with multiple address ranges corresponding to multiple address mapping entries in the address mapping table.

[0041] When the target address is within the address range of a certain address mapping entry, the address range is determined to be the target address range, the target address matches the address mapping entry corresponding to the target address range, and the composite slave device VIP indicated by the composite slave device VIP identifier in the address mapping entry is determined as the target composite slave device VIP.

[0042] Optionally, if the side identifier indicates that the target composite slave device VIP is located on the first chip side, the subsequent request transaction will be sent to the first composite slave device VIP corresponding to the first chip side; if the side identifier indicates that the target composite slave device VIP is located on the second chip side, the subsequent request transaction will be sent to the inter-chip interconnect design under test to transmit the request transaction to the second routing intermediate module, and then the second routing intermediate module will send the request transaction to the second composite slave device VIP corresponding to the second chip side.

[0043] When the target address does not fall within any address range in the address mapping table, the first routing intermediate module performs a preset hash operation on the target address to obtain a hash result. Then, based on the pre-configured correspondence between the hash result and the composite slave device VIP identifier, it determines the target composite slave device VIP. The hash operation is used to assign target addresses not directly covered by the address mapping table to one of the multiple composite slave device VIPs, ensuring that the first routing intermediate module can still determine a unique route destination for the request transaction.

[0044] In this way, the first routing intermediate module can determine the corresponding target composite slave device VIP and its chip side for any request transaction issued by the first master device VIP, providing a basis for subsequent request transaction routing.

[0045] 203. The request transaction is routed to the target composite slave device VIP via the request transaction routing path.

[0046] As mentioned earlier, the request transaction routing path includes the request transaction input interface, request transaction cache queue, request transaction routing control logic, and multiple request transaction output interfaces of the first routing intermediate module. In specific implementation, the first routing intermediate module selects the corresponding request transaction output interface based on the composite slave VIP identifier and side identifier of the target composite slave device VIP to complete the routing of the request transaction.

[0047] For ease of understanding, combined with Figure 3 Please provide an explanation. Figure 3 This is a schematic diagram of a bidirectional concurrent communication verification process provided in an embodiment of this application. Figure 3 In this context, "HNF+Slave" refers to a composite slave VIP that combines the functions of a fully consistent home node and a slave device response function.

[0048] like Figure 3 As shown, taking the first chip side as side A and the second chip side as side B as an example, the main device VIP of side A to the first routing intermediate module of side A (i.e. Figure 3 The first routing intermediate module (A Router) sends a request transaction; the first routing intermediate module determines the target composite slave device VIP based on the target address of the request transaction, and transmits the request transaction using one of the following two routing methods according to the chip side where the target composite slave device VIP is located.

[0049] In the first routing method, the target composite slave device VIP is one of multiple first composite slave device VIPs, meaning the target composite slave device VIP is located on the first chip side. The first routing intermediate module outputs the request transaction from the request transaction output interface corresponding to the target composite slave device VIP and sends it to the target composite slave device VIP. This routing method corresponds to... Figure 3In path ①, the request transaction is directly routed from the routing intermediate module of side A to the composite slave device VIP of side A, without going through the inter-chip interconnect design under test.

[0050] In the second routing method, the target composite slave device VIP is one of multiple second composite slave device VIPs, meaning the target composite slave device VIP is located on the second chip side. The first routing intermediate module outputs the request transaction from the request transaction output interface connected to the first chip-side interface of the inter-chip interconnect design under test (ICD), and sends it to the ICD. The ICD transmits the request transaction to the second routing intermediate module; the second routing intermediate module sends the request transaction to the target composite slave device VIP using the same address routing method as the first routing intermediate module. This routing method corresponds to... Figure 3 In path ②, the request transaction sequentially passes through the first routing intermediate module, the inter-chip interconnection test design, and the second routing intermediate module to reach the target composite slave device VIP on side B.

[0051] Through the two routing methods described above, the first routing intermediate module can accurately send the request transaction to the target composite slave device VIP on the local chip side or another chip side according to the target address of the request transaction, thereby supporting local access and cross-chip access of the request transaction.

[0052] 204. Receive response transactions, completion data transactions, and probe transactions generated by the target composite slave device VIP with the target first master device VIP as the target. The response transactions and completion data transactions are generated using the slave device response function of the target composite slave device VIP, and the probe transactions are generated using the fully consistent home node function of the target composite slave device VIP.

[0053] After receiving a routed request transaction, the target composite slave device VIP processes the request transaction and generates a response transaction, a completion data transaction, and / or a listening transaction associated with the request transaction.

[0054] In this embodiment, both the first composite slave device VIP and the second composite slave device VIP include a storage model and a consistency directory. The storage model simulates the storage resource corresponding to the target address and stores the address and data content of that storage resource. The consistency directory records the cache consistency status corresponding to the target address, and the cache consistency status includes at least the owner status of the target address and the master device VIP identifier associated with the target address.

[0055] Therefore, after receiving a routing request transaction, the target composite slave device VIP can process read request transactions or write request transactions based on the storage model to realize the slave device response function; and determine the master device VIP associated with the target address and the cache consistency status based on the consistency catalog to realize the fully consistent home node function.

[0056] In practice, the target composite slave device VIP uses the slave device response function to identify the transaction type of the request transaction. When the request transaction is a read request transaction, the slave device response function reads the corresponding data from the storage model according to the target address in the request transaction and generates a completion data transaction carrying the read data; when the request transaction is a write request transaction, the slave device response function updates the data at the corresponding address in the storage model according to the target address and the write data in the request transaction and generates a response transaction to indicate the processing result of the write request transaction.

[0057] Both the response transaction and the completed data transaction carry the same or related transaction association identifier as the request transaction, as well as the initiator identifier corresponding to the target first master device VIP, so that the first routing intermediate module can determine the target first master device VIP of the return transaction in subsequent steps.

[0058] Simultaneously, the target composite slave device VIP uses the fully consistent home node function to query the consistency directory to determine the cache consistency status corresponding to the target address. When the cache consistency status indicates that consistency maintenance needs to be performed, the fully consistent home node function determines the target master device VIP associated with the target address based on the master device VIP identifier recorded in the consistency directory, and generates a snooping transaction targeting the target master device VIP.

[0059] The snooping transaction carries a target address, a transaction association identifier, and a snooping operation identifier. The snooping operation identifier indicates that at least one consistency operation—data retrieval, cache invalidation, or data write-back—is performed on the target address. In this embodiment, the target primary device VIP is the target first primary device VIP, and therefore the snooping transaction targets the target first primary device VIP.

[0060] Furthermore, after receiving the probe response returned by the target first master VIP for the probe transaction, the target composite slave device VIP performs update, invalidation, or write-back processing on the owner status in the consistency catalog according to the data status or processing result indicated in the probe response.

[0061] For example, when a probe response indicates that the target primary master device VIP holds valid cached data for the target address, the target composite slave device VIP can record the target primary master device VIP as the owner of the target address; when a probe response indicates that the target primary master device VIP has invalidated the data corresponding to the target address, the target composite slave device VIP can delete or update the owner status corresponding to the target primary master device VIP in the consistency directory; when a probe response carries write-back data, the target composite slave device VIP writes the write-back data to the storage model and updates the consistency directory.

[0062] In practical applications, when the target composite slave device VIP is the first composite slave device VIP, the first routing intermediate module directly receives the response transactions, completion data transactions, and probe transactions generated by the first composite slave device VIP. When the target composite slave device VIP is the second composite slave device VIP, the second composite slave device VIP sends the response transactions, completion data transactions, and probe transactions to the second routing intermediate module; the second routing intermediate module then transmits these transactions to the first routing intermediate module via the inter-chip interconnection of the design under test.

[0063] Therefore, regardless of whether the target composite slave device VIP is located on the first chip side or the second chip side, the first routing intermediate module can obtain the response transaction, completion data transaction and eavesdropping transaction associated with the request transaction with the target first master device VIP as the target.

[0064] 205. Based on the transaction association identifier, the response transaction and the completed data transaction are routed to the target first primary device VIP through the request transaction routing path, and the probe transaction is routed to the target first primary device VIP through the probe transaction routing path.

[0065] The transaction association identifier is used to identify various transactions within the same request processing process. As mentioned earlier, when the first routing intermediate module receives the request transaction in step 202, the established transaction association record includes the transaction association identifier, the initiator identifier of the target first master device VIP, and the output interface identifier corresponding to the target first master device VIP. The output interface identifier is used to uniquely identify the routing output interface connected to the corresponding first master device VIP.

[0066] Specifically, after receiving a response transaction or a completed data transaction, the first routing intermediate module extracts the transaction association identifier from the response transaction or the completed data transaction, and queries the transaction association record based on the transaction association identifier to obtain the output interface identifier corresponding to the target first master device VIP. Since the response transaction and the completed data transaction are return transactions in the request processing process, the first routing intermediate module writes the response transaction and the completed data transaction into the return transaction cache queue of the request transaction routing path, and the request transaction routing control logic reads the corresponding transaction from the return transaction cache queue and sends it to the target first master device VIP through the output interface corresponding to the output interface identifier. Among them, the response transaction is used to indicate the processing status of the corresponding request transaction, and the completed data transaction is used to return the corresponding read data to the target first master device VIP.

[0067] Correspondingly, after receiving the probe transaction, the first routing intermediate module extracts the transaction association identifier from the probe transaction and queries the transaction association record based on the transaction association identifier to obtain the output interface identifier corresponding to the target first master device VIP. The probe transaction is used to request the target first master device VIP to perform at least one consistency operation on the target address, including data acquisition, cache invalidation, or data write-back. Since the probe transaction is a consistency maintenance transaction, the first routing intermediate module writes the probe transaction into the probe transaction cache queue of the probe transaction routing path, and the probe transaction routing control logic reads the probe transaction from the probe transaction cache queue and sends it to the target first master device VIP through the output interface corresponding to the output interface identifier.

[0068] Therefore, response transactions and completed data transactions are returned through the request transaction routing path, while probe transactions are transmitted through a probe transaction routing path that is independent of the request transaction routing path. The first routing intermediate module can accurately route different types of transactions related to the same request transaction to the corresponding target first master device (VIP) based on the same transaction association identifier.

[0069] 206. Provide the transaction information of the first routing intermediate module to the monitor and the scoreboard, so that the monitor and the scoreboard can associate and compare the transactions on the first chip side, the second chip side and the cross-chip transactions to obtain the inter-chip interconnection verification results.

[0070] When the first routing intermediate module receives, caches, arbitrates, or sends request transactions, response transactions, completed data transactions, and eavesdropping transactions, it generates corresponding transaction information and provides this transaction information to the monitor and scoreboard.

[0071] Optionally, transaction information includes, but is not limited to, transaction type, transaction association identifier, initiator identifier, destination address, target composite slave device VIP identifier, routing direction, and routing time. For example, for a completed data transaction, the transaction information may also include the data content; for a response transaction, the transaction information may also include the response status; for a snooping transaction, the transaction information may also include the snooping operation identifier. The routing direction indicates whether the transaction is a local transaction within the first chip side, or a cross-chip transaction sent from the first chip side to the second chip side or returned from the second chip side to the first chip side.

[0072] Optionally, the first routing intermediate module can set transaction sampling points on both the request transaction routing path and the eavesdropping transaction routing path. When a transaction passes through the corresponding input interface, buffer queue, or output interface, the transaction sampling point collects the transaction information and sends the collected transaction information to the monitor. The monitor samples, parses, and organizes the transaction information, and associates request transactions, response transactions, completed data transactions, and eavesdropping transactions belonging to the same request processing process into a transaction association set based on the transaction association identifier, and sends the transaction association set to the scoreboard.

[0073] The scoring board is used to perform consistency comparisons on transaction association sets. For transactions on the first chip side, the scoring board compares whether the target address, target composite slave device VIP identifier, response status, and completed data content of the request transaction correspond to the routing results of the first routing intermediate module and the processing results of the storage model. For cross-chip transactions on the second chip side, the scoring board compares whether the request transaction corresponding to the same transaction association identifier reaches the second routing intermediate module through the inter-chip interconnect design under test, and whether the response transaction, completed data transaction, and snooping transaction returned by the second chip side return to the target first master device VIP. For snooping transactions, the scoring board compares whether the target address, target first master device VIP, and snooping operation identifier of the snooping transaction correspond to the cache consistency status recorded in the consistency catalog.

[0074] When all transactions in the transaction association set satisfy the preset routing relationship, transaction association relationship, data consistency relationship, and cache consistency relationship, the scoring board generates an inter-chip interconnection verification result indicating that the verification has passed. When there is at least one of the following situations: missing transaction, mismatched transaction association identifier, incorrect route destination, incorrect response status, inconsistent completion data, or eavesdropping processing error, the scoring board records the corresponding abnormal transaction information and generates an inter-chip interconnection verification result indicating that the verification has failed. Thus, unified association and comparison can be performed on transactions on the first chip side, the second chip side, and across chips.

[0075] This application embodiment configures a routing intermediate module, multiple master device VIPs, and multiple composite slave device VIPs that combine slave device response functionality and fully consistent home node functionality on the first chip side and the second chip side, respectively. It decouples the request transaction channel from the probe transaction channel, enabling request transactions, response transactions, and completion data transactions to be transmitted along their corresponding routing paths with probe transactions, avoiding routing confusion between different types of transactions in multi-master concurrent scenarios. The first routing intermediate module determines the target composite slave device VIP based on the target address and supports routing request transactions to the local chip side or to another chip side via inter-chip interconnection, thereby achieving local access and cross-chip access verification under a dual-side symmetrical architecture. The composite slave device VIP further processes access requests based on the storage model and generates probe transactions and maintains cache consistency state based on the consistency catalog, enabling the verification environment to cover the data access and consistency maintenance processes. By accurately routing return transactions and listening transactions based on transaction association identifiers, and by associating and comparing bilateral and cross-chip transactions through monitors and scoreboards, the verification integrity and accuracy of inter-chip interconnect design under test can be improved in scenarios with multiple master devices, multiple composite slave devices, and bidirectional concurrent communication.

[0076] Steps 201 to 206 above use a request transaction issued by a first master device VIP as an example to illustrate the inter-chip interconnection verification method of this application embodiment. In actual verification, multiple first master device VIPs may concurrently issue multiple request transactions at the same or different simulation times; simultaneously, multiple first composite slave device VIPs may also concurrently issue multiple snooping transactions due to performing consistency maintenance operations. Therefore, the first routing intermediate module also needs to arbitrate and schedule multiple transactions to be routed to determine the routing order of each transaction.

[0077] In the specific implementation process, firstly, the first routing intermediate module receives multiple pending routing request transactions issued by multiple first master devices (VIPs), and multiple pending routing probe transactions issued by multiple first composite slave devices (VIPs). The pending routing request transactions are written into the request transaction cache queue of the request transaction routing path, and the pending routing probe transactions are written into the probe transaction cache queue of the probe transaction routing path.

[0078] Among them, pending route request transactions refer to request transactions that have not yet been sent by the first routing intermediate module to the corresponding composite slave device VIP; pending route probe transactions refer to probe transactions that have not yet been sent by the first routing intermediate module to the corresponding first master device VIP.

[0079] Next, the first routing intermediate module parses each pending request transaction and each pending probe transaction to obtain the transaction type, target address, and transaction association identifier of the corresponding transaction. The transaction type distinguishes between request transactions and probe transactions, and can further differentiate between read request transactions, write request transactions, and probe transactions corresponding to different probe operations; the target address determines the target composite slave device VIP corresponding to the pending request transaction, or the consistency maintenance address corresponding to the pending probe transaction; the transaction association identifier identifies related transactions within the same request processing process and is used to determine the target first master device VIP of the pending probe transaction.

[0080] Subsequently, the first routing intermediate module determines the routing order of each pending request transaction and each pending listening transaction based on at least one of the transaction type, target address, and transaction association identifier. Specifically, the first routing intermediate module may prioritize routing pending listening transactions that already have associated request transactions to ensure the transaction association relationship within the same request processing process; it may also sort multiple pending request transactions accessing the same target composite slave device VIP according to the composite slave device VIP corresponding to the target address; and it may also determine the routing order based on a preset transaction type priority when both request and listening transactions are pending routing. The preset transaction type priority is used to limit the priority processing order of different types of transactions to avoid listening or request transactions failing to be routed due to long waiting times.

[0081] After determining the routing order, the first routing intermediate module routes each pending request transaction to the corresponding first composite slave device VIP or second composite slave device VIP via the request transaction routing path, and sends each pending listening transaction to the corresponding first master device VIP determined by the transaction association identifier via the listening transaction routing path.

[0082] During the process of multiple primary master devices (VIPs) issuing request transactions, the first routing intermediate module can also concurrently receive response transactions, completion data transactions, and probe transactions generated by the first composite slave device VIP, as well as response transactions, completion data transactions, and probe transactions generated by the second composite slave device VIP transmitted via inter-chip interconnection under test. Based on the transaction association identifier carried by the above transactions, the first routing intermediate module queries the transaction association record to determine the corresponding primary master device VIP, and sends it to the corresponding primary master device VIP through the request transaction routing path and the probe transaction routing path, respectively.

[0083] Therefore, the first routing intermediate module can achieve orderly routing of request transactions, return transactions, and eavesdropping transactions when multiple first master devices (VIPs) concurrently initiate requests.

[0084] In the above embodiments, bidirectional routing and consistency verification of request transactions, return transactions, and eavesdropping transactions have been achieved through the routing intermediate module, the master device VIP, and the composite slave device VIP. In actual verification, the inter-chip interconnection protocol may also introduce new protocol fields, propose specific boundary timing requirements, or require the construction of protocol violation transactions and exception response transactions. To adapt to the above verification requirements without changing the existing transaction generation and transaction sampling capabilities of each VIP, this application embodiment sets up a VIP extension plug-in interface and at least one VIP extension component in the inter-chip interconnection verification environment.

[0085] Specifically, the VIP extension plugin interface is associated with the transaction generation and transaction sampling ends of the first master device VIP, the second master device VIP, the first composite slave device VIP, and the second composite slave device VIP. The transaction generation end refers to the functional end of the corresponding VIP that generates and outputs request transactions, response transactions, completes data transactions, or listens for transactions; the transaction sampling end refers to the functional end of the corresponding VIP that receives or monitors transactions and obtains transaction fields and transaction transmission times. The VIP extension plugin interface is used to write extended information to the transaction to be generated at the transaction generation end and to obtain the transaction carrying the extended information at the transaction sampling end, so that the extension component can participate in the transaction generation and transaction checking process.

[0086] For ease of understanding, combined with Figure 4 Please provide an explanation. Figure 4 This is a schematic diagram illustrating the structure of a VIP extension plugin interface provided in an embodiment of this application. Figure 4 As shown, the VIP extension plugin interface is located between the basic transaction generation and sampling capabilities of each VIP and the VIP extension components. The VIP extension components can include at least one of the following: protocol field extension components, boundary timing extension components, and error injection rule components. Test cases can select and enable the corresponding VIP extension components based on verification requirements through configuration information.

[0087] The protocol field extension component is used to write extended protocol fields to transactions and parse these fields at the transaction sampling end. Extended protocol fields refer to field information used to characterize extended protocol semantics, in addition to the predefined basic transaction fields in the inter-chip interconnect verification environment. Examples include extended transaction attributes, extended access types, or extended consistency attributes. At the transaction generation end, the protocol field extension component writes extended protocol fields to request transactions, response transactions, completed data transactions, or eavesdropping transactions; at the transaction sampling end, it reads the extended protocol fields and provides them to the monitor and scoreboard for subsequent comparison.

[0088] The boundary timing extension component is used to set boundary timing parameters for transactions and to check these parameters. Boundary timing parameters define the permissible time relationships between related transactions, and may include at least the maximum duration from the issuance of a request transaction to the return of a response transaction, the maximum duration from the issuance of a listener transaction to the return of a listener response, or the minimum interval between adjacent transactions. The boundary timing extension component records the transaction generation time or preset timing requirements at the transaction generation end and obtains the sampling time of the corresponding transaction at the transaction sampling end; based on the generation time, sampling time, and boundary timing parameters, it determines whether the related transactions meet the preset timing constraints.

[0089] The error injection rule component is used to set error injection flags for transactions to generate protocol violation transactions or abnormal response transactions. The error injection flag indicates the type of error to be injected and the corresponding transaction processing method; the error type can include at least one of the following: incorrect transaction field value, missing transaction field, abnormal transaction association flag, abnormal response status, or timing anomaly. Based on the error injection flag, the error injection rule component modifies the corresponding fields or response status of the transaction to be generated, resulting in a protocol violation transaction or abnormal response transaction, and then sends the protocol violation transaction or abnormal response transaction to the corresponding transaction routing path.

[0090] Both the monitor and the scoreboard have the capability to parse extended information corresponding to the VIP extended plug-in interface. The monitor samples and parses the transactions obtained by the transaction sampling terminal to obtain the transaction association identifier and at least one of the following: extended protocol fields, boundary timing parameters, and error injection identifier. The scoreboard associates related transactions based on the transaction association identifier and compares the transaction fields, transaction timing, and error handling results based on the obtained extended information to determine whether the inter-chip interconnect design under test has processed transactions in accordance with the corresponding extended rules.

[0091] By setting up the VIP extension plugin interface, the protocol field extension component, the boundary timing extension component, and the error injection rule component can be selectively connected to the inter-chip interconnection verification environment without changing the basic transaction generation and sampling capabilities of each master device VIP and composite slave device VIP; thereby improving the verification environment's adaptability and reusability to protocol evolution, timing boundary verification, and abnormal scenario verification.

[0092] In summary, this application embodiment constructs a two-sided symmetrical verification environment for inter-chip interconnect design-under-test (DUT). This verification environment configures a routing intermediate module, multiple master device VIPs, and multiple composite slave device VIPs on the first and second chip sides, respectively. The composite slave device VIPs integrate slave device response functionality and fully consistent home node functionality. Taking the first routing intermediate module as an example, it decouples the request transaction channel and the probe transaction channel, determines the target composite slave device VIP based on the target address of the request transaction, and routes the request transaction to the local chip side or via the inter-chip interconnect DUT to the other chip side. The target composite slave device VIP processes read / write requests based on the storage model and generates response transactions or completes data transactions, generates probe transactions based on the consistency directory, and maintains cache consistency status. The first routing intermediate module then sends the response transaction, complete data transaction, and probe transaction to the target first master device VIP via their respective routing paths based on the transaction association identifier. Simultaneously, the verification environment supports arbitration scheduling of multiple pending request transactions and probe transactions, and uses a monitor and scoreboard to associate and compare local transactions, transactions on the other chip side, and cross-chip transactions. In addition, the verification environment accesses the protocol field extension component, boundary timing extension component, and error injection rule component through the VIP extension plugin interface to support the verification of extended protocol fields, timing boundaries, and abnormal transactions.

[0093] The above solution enables clear differentiation and orderly processing of request transactions, return transactions, and eavesdropping transactions in scenarios where multiple master VIPs and multiple composite slave VIPs operate concurrently. It supports unified verification of local chip-side access, cross-chip access, and cache consistency maintenance. Combined with transaction tracing based on transaction association identifiers and two-sided association comparison, it improves the verification accuracy and completeness of inter-chip interconnect designs under test in bidirectional concurrent communication scenarios. Furthermore, by extending the plug-in interface, it can adapt to protocol fields, timing constraints, and error injection requirements without changing the basic transaction generation and sampling capabilities of each VIP, thus improving the reusability and scalability of the verification environment.

[0094] The following describes in detail one or more embodiments of the inter-chip interconnect verification apparatus of this application. Those skilled in the art will understand that these apparatuses can all be configured using commercially available hardware components through the steps taught in this solution.

[0095] Figure 5This is a schematic diagram of an inter-chip interconnect verification device provided in an embodiment of this application, applied to a first routing intermediate module in an inter-chip interconnect verification environment. The inter-chip interconnect verification environment is used to verify an inter-chip interconnect design under test (DUT) including a first chip and a second chip, comprising a first chip side and a second chip side. The first chip side is configured with the first routing intermediate module, multiple first master device VIPs, and multiple first composite slave device VIPs. The second chip side is configured with the second routing intermediate module, multiple second master device VIPs, and multiple second composite slave device VIPs. Both the composite first slave device VIP and the second composite slave device VIP possess both fully consistent home node functionality and slave device VIP response functionality. Figure 5 As shown, the device includes: a decoupling module 11, a processing module 12, and a verification module 13.

[0096] The decoupling module is used to decouple the request transaction channel and the eavesdropping transaction channel connected to the first chip side, so as to form request transaction routing paths and eavesdropping transaction routing paths respectively; The processing module is configured to receive a request transaction sent by a target first master device VIP; determine the target composite slave device VIP corresponding to the request transaction based on the target address of the request transaction, wherein the target first master device VIP is any one of the plurality of first master device VIPs; route the request transaction to the target composite slave device VIP through the request transaction routing path; receive response transactions, completion data transactions, and probe transactions generated by the target composite slave device VIP with the target first master device VIP as the target, wherein the response transactions and completion data transactions are generated using the slave device response function of the target composite slave device VIP, and the probe transactions are generated using the fully consistent home node function of the target composite slave device VIP; and route the response transactions and completion data transactions to the target first master device VIP through the request transaction routing path and the probe transactions to the target first master device VIP based on the transaction association identifier. The verification module is used to provide the transaction information routed by the first routing intermediate module to the monitor and the scoreboard, so that the monitor and the scoreboard can associate and compare the transactions on the first chip side, the second chip side, and the cross-chip transactions to obtain the inter-chip interconnection verification results.

[0097] Figure 5 The device shown can perform the steps described in the foregoing embodiments. For detailed execution process and technical effects, please refer to the description in the foregoing embodiments, which will not be repeated here.

[0098] In one possible design, the above Figure 5 The structure of the inter-chip interconnect verification device shown can be implemented as an electronic device, such as... Figure 6As shown, the electronic device may include: a memory 21, a processor 22, and a communication interface 23. The memory 21 stores a computer program, which, when executed by the processor 22, enables the processor 22 to at least implement the inter-chip interconnect verification method provided in the foregoing embodiments.

[0099] The aforementioned memory 21 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random-Access Memory (SRAM), Electrically Erasable Programmable Read Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0100] Accordingly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, enables the processor to implement the steps in the above-described method embodiments. The computer-readable storage medium includes volatile or non-volatile components, or a combination thereof, and can be removable or non-removable. Examples of computer-readable storage media include, but are not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), flash memory or other memory technologies, CD-ROM, Digital Video Disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium.

[0101] Accordingly, this application also provides a computer program product, which includes a computer program or instructions that, when executed by a processor, cause the processor to implement the steps in the above method embodiments. It should be understood that each step or combination of steps in the above method flow can be implemented by the computer program or instructions. Furthermore, these computer programs or instructions can be applied to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable inter-chip interconnect verification device, enabling the processor of the general-purpose computer, special-purpose computer, embedded processor, or other programmable inter-chip interconnect verification device to function as an apparatus for implementing the corresponding functions in the above method embodiments.

[0102] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0103] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of a necessary general-purpose hardware platform, or by a combination of hardware and software. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a computer product. This application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0104] Finally, it should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0105] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for verifying inter-chip interconnects, characterized in that, A first routing intermediate module is applied in an inter-chip interconnection verification environment; the inter-chip interconnection verification environment is used to verify an inter-chip interconnection design under test including a first chip and a second chip, including a first chip side and a second chip side; the first chip side is configured with the first routing intermediate module, multiple first master device VIPs and multiple first composite slave device VIPs; the second chip side is configured with the second routing intermediate module, multiple second master device VIPs and multiple second composite slave device VIPs; the composite first slave device VIP and the second composite slave device VIP both have fully consistent home node function and slave device VIP response function; the method includes: The request transaction channel and the eavesdropping transaction channel connected to the first chip side are decoupled to form request transaction routing paths and eavesdropping transaction routing paths respectively; Receive a request transaction sent by a target first master device VIP, determine the target composite slave device VIP corresponding to the request transaction based on the target address of the request transaction, wherein the target first master device VIP is any one of the plurality of first master device VIPs; The request transaction is routed to the target composite slave device VIP via the request transaction routing path; The system receives response transactions, completion data transactions, and probe transactions generated by the target composite slave device VIP, with the target first master device VIP as the target. The response transactions and completion data transactions are generated using the slave device response function of the target composite slave device VIP, and the probe transactions are generated using the fully consistent home node function of the target composite slave device VIP. Based on the transaction association identifier, the response transaction and the completion data transaction are routed to the target first master device VIP through the request transaction routing path, and the eavesdropping transaction is routed to the target first master device VIP through the eavesdropping transaction routing path; The transaction information routed by the first routing intermediate module is provided to the monitor and the scoreboard, so that the monitor and the scoreboard can associate and compare the transactions on the first chip side, the second chip side, and the cross-chip transactions to obtain the inter-chip interconnection verification results.

2. The method according to claim 1, characterized in that, The step of routing the request transaction to the target composite slave device VIP through the request transaction routing path includes: If the target composite slave device VIP is included in the plurality of first composite slave device VIPs, then the request transaction is routed to the target composite slave device VIP through the request transaction routing path; If the target composite slave device VIP is included in the plurality of second composite slave device VIPs, the request transaction is sent to the second routing intermediate module through the inter-chip interconnect test design via the request transaction routing path, so that the second routing intermediate module can route the request transaction to the target composite slave device VIP; Specifically, when the target composite slave device VIP is the second composite slave device VIP, the response transaction, the completion data transaction, and the eavesdropping transaction are transmitted to the first routing intermediate module via the second routing intermediate module and the inter-chip interconnection test design.

3. The method according to claim 1, characterized in that, Determining the target composite slave device VIP based on the target address of the requested transaction includes: Based on a pre-configured address mapping table, the target address is matched with multiple address ranges, and the address mapping table includes the correspondence between address ranges and composite slave device VIP identifiers; When the target address matches the target address range in the address mapping table, the composite slave device VIP indicated by the composite slave device VIP identifier corresponding to the target address range is determined as the target composite slave device VIP; When the target address does not match the address mapping table, the target composite slave device VIP is determined based on the hash result of the target address.

4. The method according to claim 1, characterized in that, The method further includes: Receive cross-chip request transactions transmitted from the second routing intermediate module to the first chip side via the inter-chip interconnection design under test, wherein the cross-chip request transactions are sent by the target second master device VIP, and the target second master device VIP is any one of the plurality of second master device VIPs; The cross-chip request transaction is routed to the corresponding target first composite slave device VIP through the request transaction routing path, so that the slave device response function of the target first composite slave device VIP generates the response transaction and completion data transaction corresponding to the cross-chip request transaction, and the full consistency home node function of the target first composite slave device VIP generates the snooping transaction corresponding to the cross-chip request transaction. The system receives the response transaction, completion data transaction, and probe transaction corresponding to the cross-chip request transaction generated by the target first composite slave device VIP, and sends them to the second routing intermediate module through the inter-chip interconnect design under test. The second routing intermediate module then sends the response transaction, completion data transaction, and probe transaction corresponding to the cross-chip request transaction to the target second master device VIP based on the request transaction routing path and probe transaction routing path obtained by decoupling the request transaction channel and probe transaction channel on the second chip side.

5. The method according to claim 1, characterized in that, The method further includes: Receive multiple pending routing request transactions sent by the multiple first master device VIPs, and multiple pending routing snooping transactions sent by the multiple first composite slave device VIPs; Obtain the transaction type, target address, and transaction association identifier for each pending route request transaction and each pending route snooping transaction; The routing order of each pending request transaction and each pending eavesdropping transaction is determined based on at least one of the transaction type, the target address, and the transaction association identifier. According to the routing order, each pending routing request transaction is routed to the corresponding first composite slave device VIP or second composite slave device VIP, and each pending routing snooping transaction is routed to the corresponding first master device VIP; During the process of the multiple first master device VIPs issuing request transactions, the system receives response transactions, completes data transactions and eavesdropping transactions transmitted by the first composite slave device VIP or the design under test via the inter-chip interconnection, and determines the corresponding first master device VIP based on the transaction association identifier.

6. The method according to claim 1, characterized in that, Both the first composite slave device VIP and the second composite slave device VIP include a storage model and a consistency directory; The slave device response function processes read or write requests based on the storage model and generates the response transaction or the completed data transaction. The fully consistent home node function determines the target primary device VIP associated with the target address based on the consistency directory, initiates a snooping transaction to the target primary device VIP, and performs update, invalidation, or write-back processing on the owner status in the consistency directory according to the snooping response.

7. The method according to claim 1, characterized in that, The inter-chip interconnection verification environment also includes a VIP extension plug-in interface and at least one VIP extension component; the VIP extension plug-in interface is associated with the transaction generation end and transaction sampling end of the first master device VIP, the second master device VIP, the first composite slave device VIP, and the second composite slave device VIP; the VIP extension component includes at least one of a protocol field extension component, a boundary timing extension component, and an error injection rule component; The protocol field extension component is used to write extended protocol fields to transactions and parse the extended protocol fields; the boundary timing extension component is used to set boundary timing parameters for transactions and check the boundary timing parameters; the error injection rule component is used to set error injection flags for transactions to generate protocol violation transactions or abnormal response transactions. The monitor and the scoreboard each have extended information parsing capabilities corresponding to the VIP extended plug-in interface, which are used to sample, parse and compare related transactions based on at least one of the extended protocol fields, the boundary timing parameters and the error injection identifier.

8. An electronic device, characterized in that, include: The device includes a memory, a processor, and a communication interface; wherein the memory stores a computer program that, when executed by the processor, causes the processor to perform the inter-chip interconnect verification method as described in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor of an electronic device, causes the processor to perform the inter-chip interconnect verification method as described in any one of claims 1 to 7.

10. A computer program product, characterized in that, include: A computer program or instruction that, when executed by a processor of an electronic device, causes the processor to perform the inter-chip interconnect verification method as described in any one of claims 1 to 7.

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