Mapping method and system for equalizing calculation timing of multi-memristor array under storage logic

Abstract

The application discloses a mapping method and system for logic computation timing equalization of a multi-memristor array, and the method comprises the following steps: performing logic synthesis on a target computation function to obtain a logic netlist; regarding the logic netlist as a directed acyclic graph, performing netlist partitioning on the directed acyclic graph, including: performing layer partitioning and intra-layer graph partitioning based on the layer number N and the intra-layer partition number M given by a current mapping scheme, merging the partitions in adjacent layers, and thus partitioning the logic netlist into a plurality of sub-logic sequences; scheduling and mapping the plurality of sub-logic sequences of the current mapping scheme to each memristor array to obtain an execution scheme composed of sub-execution sequences of each memristor array. The application aims to obtain timing-equalized sub-logic sequences by introducing layer partitioning, obtain a logic execution scheme by scheduling the sub-sequences, and realize execution on a plurality of memristor arrays, so as to fully utilize the parallelism of the memristor array and improve the execution efficiency on the memristor array.

Description

Technical Field

[0001] This invention belongs to the field of digital circuit technology, specifically relating to a mapping method and system for timing balance of in-memory logic computation under a multi-memoryristor array. Background Technology

[0002] Currently, with data transmitted almost unimpeded in high-speed light communication networks, the traditional von Neumann architecture, with its separate processor and memory, necessitates frequent read and write operations from memory. However, memory read / write speeds lag far behind processor processing speeds, creating the infamous "memory wall." This results in idle computing cores, constantly waiting for data transfer, limiting overall system efficiency due to data transmission bottlenecks. In-memory computing architecture breaks the "storage-computing" separation paradigm, potentially overcoming this bottleneck at its root and further driving technological iteration. Memristors, as the basic unit of in-memory computing arrays, possess excellent non-volatility and resistive switching characteristics. Their physical structure changes depending on the amount of charge or current passing through them, macroscopically manifested as changes in resistance. If a high-resistance state is defined as logic '0' and a low-resistance state as logic '1', logical relationships can be established between these states by conditionally switching the device's resistance, thus achieving true in-memory computing. The smallest computational unit on a memristor array is a logic gate; combining logic gates allows for more complex calculations. In recent years, various automated state logic synthesis processes have emerged: In the synthesis phase, complex computations are decomposed into a logical sequence composed of specified complete logic gates, without considering the constraint of the number of array devices; in the mapping phase, the constraint of the number of array devices and the optimization of comprehensive indicators such as throughput, energy efficiency, and reliability are considered. For example, SIMPLER MAGIC aims to maximize multi-instance throughput by compressing each computation instance into a single array row for execution, solving space limitations through memristor reuse; X-MAGIC, LOSSS, and ILOSSS aim to optimize latency and area by introducing more complex logic gates—composite logic gates—effectively reducing operation steps and hardware overhead.

[0003] The implementation of state logic gates in memristor arrays provides a feasible hardware foundation for in-memory computing, significantly reducing the data transfer overhead between data processing and storage units in traditional von Neumann architectures. However, despite the advantages of memristors in integration density and energy efficiency, the execution time of a single computation instance is still difficult to surpass that of mature CMOS combinational logic circuits, which to some extent limits its practical application in high-speed processing scenarios. To overcome this performance bottleneck, an effective strategy is to execute multiple computation instances in parallel across multiple rows of the memristor array, shortening the completion time at the overall task level. This parallel execution method can fully leverage the inherently high parallel computing capabilities of memristor arrays, thereby achieving a significant improvement in system-level throughput while sacrificing the latency of individual tasks. However, current synthesis mapping tools still have the following problems: 1) The logic sequence synthesized from complex computations is difficult to execute on a single row of a single array. For simple computations, a single array row is sufficient to provide the space required for storage and computation; for complex computations, a single array row is insufficient to support the completion of the computation, requiring multiple rows or multiple arrays to collaborate on computation. 2) The parallelism of memristor arrays is not fully utilized. Existing scheduling algorithms have not considered incorporating timing constraints into netlist partitioning, and have failed to obtain a timing-balanced partitioning method. For scheduling logical sequences, they are limited to serial scheduling between arrays. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a mapping method and system for time-balanced in-memory logic computation under multiple memristor arrays, which addresses the above-mentioned problems in the prior art. The present invention aims to obtain time-balanced sub-logic sequences by introducing layer segmentation, and obtain a logic execution scheme by scheduling the sub-sequences to realize execution on multiple memristor arrays, making full use of the parallelism of memristor arrays and improving the execution efficiency on memristor arrays.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A mapping method for timing balance of in-memory logic computation under a multi-memristor array includes the following steps: S101, logically synthesize the target calculation function to obtain a logical netlist; S102, the logical netlist is regarded as a directed acyclic graph, and the directed acyclic graph is partitioned into netlists, including: layer partitioning and intra-layer graph partitioning based on the number of layers N and the number of partitions M given by the current mapping scheme, merging the partitions in adjacent layers, thereby dividing the logical netlist into multiple sub-logical sequences; S103, schedule and map multiple sub-logic sequences of the current mapping scheme onto each memristor array to obtain an execution scheme composed of sub-execution sequences of each memristor array.

[0006] Optionally, when the logical netlist is regarded as a directed acyclic graph in step S102, it includes treating the input and output of each logical operation in the logical netlist as nodes in the directed acyclic graph, and the logical operation itself as an edge or superedge in the directed acyclic graph, thereby obtaining the directed acyclic graph corresponding to the logical netlist.

[0007] Optionally, step S102, which involves performing layer segmentation and intra-layer graph segmentation based on the number of layers N and the number of intra-layer partitions M given by the current mapping scheme, includes: S201, calculate the topological depth of the directed acyclic graph, where the topological depth is the maximum number of edges from a node with an in-degree of 0 to a node with an out-degree of 0; based on the number of layers N given by the current mapping scheme, divide the topological depth of the directed acyclic graph into layers, and the following constraints must be met when dividing the layers: the total number of layers is less than the maximum depth path length of the directed acyclic graph; common nodes with the same topological depth are retained between adjacent layers, where the common nodes are the output nodes of the upper layer and the input nodes of the lower layer; S202, using a preset graph partitioning method, performs a secondary partitioning operation on the subgraph of each layer of the directed acyclic graph based on the number of partitions M within the layer, dividing the subgraph into M groups of nodes, thereby dividing the entire logical netlist into N×M sub-logical sequences.

[0008] Optionally, in step S202, when performing a secondary segmentation operation on the subgraph of each layer of the directed acyclic graph based on the number of intra-layer partitions M using a preset graph segmentation method, the process includes reading the configuration parameters of the graph segmentation. The configuration parameters include, but are not limited to, the segmentation imbalance threshold and the maximum number of subgraphs to be segmented. The imbalance is the size difference between subgraphs within a layer. If the number of nodes in a certain layer is less than or equal to the preset maximum number of subgraphs to be segmented, or the imbalance exceeds the preset imbalance threshold, the original subgraph structure of that layer is maintained, so that the intra-layer graph segmentation result includes one non-empty partition and multiple empty partitions.

[0009] Optionally, merging partitions in adjacent layers in step S102 includes: S301, traverse and obtain a set of adjacent layers obtained by layer segmentation as the current adjacent layer; S302, assign initial array numbers to each partition belonging to the upper and lower layers in the sub-logic sequence obtained by the inner graph segmentation, and record the array positions of the common nodes of the upper and lower layers in the upper and lower layers as upper partition array a and lower partition array b, respectively. S303, calculate the similarity between the upper partition array a and the lower partition array b; S304, construct a set of nodes whose common nodes belong to different array positions in the upper and lower layers respectively for the current adjacent layers. ,in and These are the initial array numbers of the i-th common node in the upper and lower partitions, respectively; S305, Traverse and extract the set One of the elements is used as a swap pair (x, y); S306, replace all elements x in the upper partition array a with elements y, and replace all elements y with elements x, to obtain the new upper partition array a and the lower partition array b after replacement. Calculate the similarity between the new upper partition array a and the lower partition array b as the similarity after replacement. If the similarity after replacement is greater than the similarity before replacement, then the swap pair (x,y) is taken as the best swap pair. S307, Determine the set Has the traversal been completed? If the set is complete... If the traversal has not been completed, jump to step S305 to continue the traversal; otherwise, jump to step S308. S308, determine whether the best swap pair best_swap obtained after traversal is empty. If it is not empty, replace element x in the original upper partition array a with element y according to the best swap pair best_swap, and jump to step S304; otherwise, use the final upper partition array a and lower partition array b as the matching result of the current adjacent layer, and jump to step S309. S309, determine whether the traversal of the adjacent layers has not been completed. If the traversal of the adjacent layers has not been completed, jump to step S301 to continue the traversal; otherwise, start from the top layer of the directed acyclic graph and traverse layer by layer, integrating the partitions of the matching adjacent layers into a sub-logic sequence. The sub-logic sequence is a sequence of multiple logic gates executed serially on the memristor array, thereby obtaining multiple sub-logic sequences obtained by the logical netlist partitioning.

[0010] Optionally, step S103, which involves scheduling and mapping multiple sub-logic sequences of the current mapping scheme onto each memristor array, includes: S401, allocate storage space for the input data; S402, for multiple partitions consisting of multiple sub-logical sequences of the current mapping scheme, traverse one partition of the current mapping scheme as the current partition; S403, determine whether the communication queue is empty. If the communication queue is empty, proceed to step S404; otherwise, write the data to be communicated into the array and proceed to step S408. S404, determine whether the input data for the logical operation to be executed is ready. If not, proceed to step S405; otherwise, execute the logical operation, write the data required by other partitions into the buffer, update the communication queue, and proceed to step S408. S405, determine whether erasure can provide sufficient storage space for logical calculation. If feasible, proceed to step S406; otherwise, allocate a new array for the current partition, update the communication queue, write the data to be communicated into the array, and proceed to step S408. S406, Erase used data; S407, Update the status of the current partition; S408, determine whether the partition has been traversed. If the partition has not been traversed, jump to step S402 to continue traversing; otherwise, jump to step S409. S409, determine whether the calculation is complete. If the calculation is not yet complete, jump to step S402 to continue the calculation; otherwise, end and exit.

[0011] Optionally, it also includes combining multiple different layer divisions N and the number of partitions M within a layer, performing steps S101 to S103 for each combination to obtain multiple mapping schemes, obtaining the performance indicators of each execution scheme, and selecting the execution scheme with the best performance indicators as the final mapping result.

[0012] The present invention also provides a mapping system for timing balance of in-memory logic computation under a multi-memoristant array, comprising a microprocessor and a memory interconnected thereto, wherein the microprocessor is programmed or configured to execute the mapping method for timing balance of in-memory logic computation under the multi-memoristant array.

[0013] The present invention also provides a computer-readable storage medium storing a computer program or instructions that are programmed or configured to execute, by a processor, the mapping method for timing equalization of in-memory logic computation under the multi-memristor array.

[0014] The present invention also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute, via a processor, a mapping method for timing equalization of in-memory logic computation under the multi-memoryristor array.

[0015] Compared with existing technologies, the present invention mainly achieves the following beneficial effects: The method of the present invention includes logically synthesizing the target computation function to obtain a logical netlist; treating the logical netlist as a directed acyclic graph, and partitioning the directed acyclic graph, including: performing layer partitioning and intra-layer graph partitioning based on the layer partitioning number N and the intra-layer partitioning number M given by the current mapping scheme, merging the partitions in adjacent layers, thereby dividing the logical netlist into multiple sub-logical sequences; scheduling and mapping the multiple sub-logical sequences of the current mapping scheme onto each memristor array to obtain an execution scheme composed of the sub-execution sequences of each memristor array. The present invention obtains time-balanced sub-logical sequences by introducing layer partitioning, and obtains a logical execution scheme by scheduling the sub-sequences to achieve execution on multiple memristor arrays, making full use of the parallelism of memristor arrays, and improving the execution efficiency on memristor arrays. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the basic process of the method in an embodiment of the present invention.

[0017] Figure 2 Here is a circuit diagram example of a one-bit full adder in an embodiment of the present invention, where (a) is a one-bit full adder and (b) is the logic gate circuit of the one-bit full adder.

[0018] Figure 3 This is a schematic diagram of a one-bit full adder implemented by cascading logic gates on a memristor array in an embodiment of the present invention.

[0019] Figure 4 This is a schematic diagram illustrating the abstraction of the logical netlist as a directed acyclic graph in an embodiment of the present invention.

[0020] Figure 5 This is a schematic diagram illustrating the abstraction of the logical netlist as a hypergraph in an embodiment of the present invention.

[0021] Figure 6 This is a schematic diagram illustrating the principle of layer partitioning and intra-layer graph partitioning in an embodiment of the present invention, wherein (a) is an example of layer partitioning of a graph, (b) is an example of abstracting each layer node into a graph, (c) is an example of obtaining multiple partitions by intra-layer graph partitioning, and (d) is an example of mapping and executing logical computation on an array.

[0022] Figure 7 This is a schematic diagram of the process of merging inter-layer partitions in an embodiment of the present invention.

[0023] Figure 8 This is a schematic diagram of the partition where the common nodes of adjacent layers are located in an embodiment of the present invention.

[0024] Figure 9 This is a schematic diagram of the process of scheduling and mapping onto each memristor array in an embodiment of the present invention.

[0025] Figure 10 This is a schematic diagram of the structure of a multi-memristor array in an embodiment of the present invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0027] like Figure 1 As shown, the mapping method for timing balance of in-memory logic computation under a multi-memristor array in this embodiment includes the following steps: S101, logically synthesize the target calculation function to obtain a logical netlist; S102, the logical netlist is regarded as a directed acyclic graph, and the directed acyclic graph is partitioned into netlists, including: layer partitioning and intra-layer graph partitioning based on the number of layers N and the number of partitions M given by the current mapping scheme, merging the partitions in adjacent layers, thereby dividing the logical netlist into multiple sub-logical sequences; S103, schedule and map multiple sub-logic sequences of the current mapping scheme onto each memristor array to obtain an execution scheme composed of sub-execution sequences of each memristor array.

[0028] In step S101 of this embodiment, the logical netlist obtained by logically synthesizing the target calculation function can be achieved using existing logical synthesis tools as needed. Figure 2 Taking the one-bit full adder shown in (a) as an example, it takes two one-bit binary numbers a and b as input, and a carry-in cin_0 as input, calculates a + b + cin_0, and outputs the sum s and the carry-out c. In step S101 of this embodiment, a logic synthesis tool is used to synthesize the one-bit full adder as the target calculation function to obtain a logic netlist. The above function can be implemented using the following logic sequence: n7 = AND(a, b); n6 = NOR(a, b); n8 = NOR(n6, n7); n9 = AND(n8, cin_0); c = OR(n7, n9); n10 = NOR(n8, cin_0); s=NOR(n10, n9); The first step is to perform a bitwise AND operation on the two input addends (binary numbers a and b) to obtain n7. The second step is to perform a bitwise OR operation on the two input addends to obtain n6. The third step is to perform a bitwise OR operation on n6 and n7 to obtain n8. The fourth step is to perform a bitwise AND operation on n8 and the carry-in cin_0 to obtain n9. The fifth step is to perform a bitwise OR operation on n7 and n9 to obtain the carry-in c. The sixth step is to perform a bitwise OR operation on n8 and the carry-in cin_0 to obtain n10. The seventh step is to perform a bitwise OR operation on n10 and n9 to obtain the sum s, which corresponds to... Figure 2 The logic circuit shown in (b) is further illustrated. Furthermore, the logic gates corresponding to the logic sequence of a one-bit full adder can be sequentially mapped onto a single row of a memristor array, resulting in the following... Figure 3 As shown. The above logical sequence can be abstracted into a directed acyclic graph as follows. Figure 4 As shown, the nodes are categorized into three types: computational inputs, intermediate nodes, and computational outputs. The arrows between nodes indicate the relationship between input and output nodes in a logical operation, for example... Figure 4 Both nodes a and b point to node n7, and the two edges together represent the logical operation n7=AND(a, b), and so on.

[0029] In step S102 of this embodiment, when the logical netlist is regarded as a directed acyclic graph, it includes treating the input and output of each logical operation in the logical netlist as nodes in the directed acyclic graph, and the logical operation itself as an edge or superedge in the directed acyclic graph, thereby obtaining the directed acyclic graph corresponding to the logical netlist. Figure 5 As shown, a hyperedge can connect two or more nodes. The AND dashed box contains nodes a, b, and n7, which means that the logical operation n7 = AND(a, b).

[0030] like Figure 6 As shown, in step S102 of this embodiment, layer partitioning and intra-layer graph partitioning are performed based on the number of layers N and the number of partitions M given by the current mapping scheme. The nodes in the graph are uniformly divided into N layers according to the topological depth, as follows: Figure 6 As shown in (a) above, this example includes two layers, layer 1 and layer 2 (N=2). Then, each layer's nodes are treated as a graph, as follows: Figure 6 As shown in (b), the graph is partitioned into M groups of nodes using the graph partitioning method, as follows: Figure 6 As shown in (c), the entire logical netlist is divided into N×M sub-logical sequences, and finally the sub-logical sequences are mapped to each array (array 0 to array 2) for execution, as follows. Figure 6 As shown in (d) in the figure. In this embodiment, layer segmentation and intra-layer graph segmentation specifically include: S201, calculate the topological depth of the directed acyclic graph, where the topological depth is the maximum number of edges from a node with an in-degree of 0 to a node with an out-degree of 0; based on the number of layers N given by the current mapping scheme, divide the topological depth of the directed acyclic graph into layers, and the following constraints must be met when dividing the layers: the total number of layers is less than the maximum depth path length of the directed acyclic graph; common nodes with the same topological depth are retained between adjacent layers, where the common nodes are the output nodes of the upper layer and the input nodes of the lower layer; S202, using a preset graph partitioning method, performs a secondary partitioning operation on the subgraph of each layer of the directed acyclic graph based on the number of partitions M within the layer, dividing the subgraph into M groups of nodes, thereby dividing the entire logical netlist into N×M sub-logical sequences.

[0031] In step S202 of this embodiment, when performing a secondary segmentation operation on the subgraph of each layer of the directed acyclic graph based on the preset graph segmentation method and the number of intra-layer segmentation partitions M, the process includes reading the configuration parameters of the graph segmentation. These configuration parameters include, but are not limited to, a segmentation imbalance threshold and a maximum number of segmented subgraphs. The imbalance of each layer is calculated, where the imbalance is the size difference between subgraphs within a layer. If the number of nodes in a certain layer is less than or equal to the preset maximum number of segmented subgraphs, or if the imbalance exceeds the preset imbalance threshold, the original subgraph structure of that layer is maintained. This ensures that the intra-layer graph segmentation result includes one non-empty partition and multiple empty partitions, avoiding computational redundancy introduced by over-segmentation. Through this method, closely related and frequently interacting nodes can be aggregated into the same partition, while sparsely connected and relatively independent nodes can be distributed to different partitions, reducing cross-partition communication overhead and redundant dependencies. The preset graph partitioning method can employ various graph partitioning methods as needed. For example, the shmetis graph partitioning method from the hMETIS series can be used to partition nodes. In addition to specifying the target number of partitions, the maximum load imbalance k of each partition during the recursive binary search process can be selected. The latter's value ranges from 1 to 49. Assuming the layer contains n vertices (each vertex has a unit weight), let the imbalance be b. a When performing a binary search operation, i.e., when the target number of partitions is 2, the number of vertices in the two partitions will be between [a certain value]. Between. For example, when b a When the value is 5, the system allows a bipartition ratio of 45% to 55%, meaning the number of vertices in each partition is between 0.45n and 0.55n. The graph abstracted from the logical sequence has a vertex and edge weight of 1. For this case of uniform vertex weights, a smaller imbalance can be chosen, such as 1 to 10, to ensure the partitioning results are as balanced as possible.

[0032] In step S102 of this embodiment, the partitions in adjacent layers are merged to integrate N×M sub-logic sequences into M sub-logic sequences. Based on the outputs of each sub-logic sequence in the upper layer and the inputs of each sub-logic sequence in the lower layer, sub-logic sequences with similar common nodes in the upper and lower layers are merged. This layer-by-layer integration yields the M-segmentation result of the entire graph. Specifically, as follows... Figure 7 As shown, in this embodiment, step S102, merging the partitions in adjacent layers includes: S301, traverse and obtain a set of adjacent layers obtained by layer segmentation as the current adjacent layer; S302, assign initial array numbers to each partition belonging to the upper and lower layers in the sub-logic sequence obtained by the inner graph segmentation, and record the array positions of the common nodes of the upper and lower layers in the upper and lower layers as upper partition array a and lower partition array b, respectively. S303, Calculate the similarity between the upper-level partition array a and the lower-level partition array b: ; Where n is the number of common nodes in the current adjacent layers. and This is the index of the initial array containing the i-th common node of the upper partition array a and the lower partition array b; S304, construct a set of nodes whose common nodes belong to different array positions in the upper and lower layers respectively for the current adjacent layers. ,in and These are the initial array numbers of the i-th common node in the upper and lower partitions, respectively; S305, Traverse and extract the set One of the elements is used as a swap pair (x, y); S306, replace all elements x in the upper partition array a with elements y, and replace all elements y with elements x, to obtain the new upper partition array a and the lower partition array b after replacement. Calculate the similarity between the new upper partition array a and the lower partition array b as the similarity after replacement. If the similarity after replacement is greater than the similarity before replacement, then the swap pair (x,y) is taken as the best swap pair. S307, Determine the set Has the traversal been completed? If the set is complete... If the traversal has not been completed, jump to step S305 to continue the traversal; otherwise, jump to step S308. S308, determine whether the best swap pair best_swap obtained after traversal is empty. If it is not empty, replace element x in the original upper partition array a with element y according to the best swap pair best_swap, and jump to step S304; otherwise, use the final upper partition array a and lower partition array b as the matching result of the current adjacent layer, and jump to step S309. S309, determine whether the traversal of the adjacent layers has not been completed. If the traversal of the adjacent layers has not been completed, jump to step S301 to continue the traversal; otherwise, start from the top layer of the directed acyclic graph and traverse layer by layer, integrating the partitions of the matching adjacent layers into a sub-logic sequence. The sub-logic sequence is a sequence of multiple logic gates executed serially on the memristor array, thereby obtaining multiple sub-logic sequences obtained by the logical netlist partitioning.

[0033] like Figure 8 As shown, the current common nodes are denoted as N1-N8. Only node N8 is obtained as an output node in the upper layer and participates in the lower layer calculation as an input node, so the node distribution similarity is 12.5%. Swapping the arrays where partitions are located changes the array number of the nodes, increasing the similarity of common nodes in the array distribution, which reduces the communication requirements between arrays. Therefore, by comparing the overall similarity of the array positions of the output nodes in the upper layer and the input nodes in the lower layer, the array allocation result with the highest similarity is retained. Value swapping operations are repeatedly applied to gradually improve the matching degree of the two subsequences until no swapping operation that can improve the similarity can be found. Finally, the corresponding result of the final upper-layer partition array a and the lower-layer partition array b is taken as the matching result of the upper and lower layers of partitions.

[0034] In step S103, the M sub-logic sequences of the complex computational netlist are mapped to M sets of memristor memory arrays to obtain the state logic gate execution sequence, the operation of which is implemented through a scheduler. For example... Figure 9 As shown, step S103, which schedules and maps multiple sub-logic sequences of the current mapping scheme onto each memristor array, includes: S401, allocate storage space for the input data; S402, for multiple partitions consisting of multiple sub-logical sequences of the current mapping scheme, traverse one partition of the current mapping scheme as the current partition; S403, determine whether the communication queue is empty. If the communication queue is empty, proceed to step S404; otherwise, write the data to be communicated into the array and proceed to step S408. S404, determine whether the input data for the logical operation to be executed is ready. If not, proceed to step S405; otherwise, execute the logical operation, write the data required by other partitions into the buffer, update the communication queue, and proceed to step S408. S405, determine whether erasure can provide sufficient storage space for logical calculation. If feasible, proceed to step S406; otherwise, allocate a new array for the current partition, update the communication queue, write the data to be communicated into the array, and proceed to step S408. S406, Erase used data; S407, Update the status of the current partition; S408, determine whether the partition has been traversed. If the partition has not been traversed, jump to step S402 to continue traversing; otherwise, jump to step S409. S409, determine whether the calculation is complete. If the calculation is not yet complete, jump to step S402 to continue the calculation; otherwise, end and exit.

[0035] During data storage and array allocation, arrays are allocated first for input data, followed by arrays for logical operation partitions. Regarding task parallelism, an execution model of inter-partition parallelism and intra-partition serial execution is adopted: logical operations belonging to different partitions can be executed in parallel on their respective allocated arrays; while logical operations within the same partition, due to data dependencies, are executed serially on a single array. First, storage space is allocated for input data, storing input nodes sequentially on a single row of the array. Based on the characteristics of in-memory computation, each computation is completed and stored after the input nodes are ready. Therefore, when the total number of input nodes is not divisible by the array width, there is still space available after the last part of the input nodes are stored in a single array. Partitions more closely related to these input nodes are placed closer to the input nodes (i.e., the last input array) to complete the computation, reducing array resource consumption. Then, arrays are allocated to other partitions sequentially. Initially, the system allocates only one physical array to each partition. As the computation task progresses, when the existing array storage space is insufficient and erasure cannot meet the demand, new arrays are dynamically allocated to the partitions. This on-demand allocation strategy avoids resource idleness while ensuring the smooth execution of computation tasks.

[0036] When other arrays obtain the required results through logical operations, they are written to a buffer, and a ready signal is sent through the control path for the target array to read. This buffer-based asynchronous communication mechanism eliminates the need for the source array to engage in blocking communication with the receiving array in additional cycles. The calculation results are written to the buffer in the latter half of the cycle after the calculation is completed, and the receiving array reads the data as needed during the data reading cycle.

[0037] Data transfer from the source array to the target array must be relayed through an intermediate shared buffer, rather than establishing a direct point-to-point connection between the two arrays. Each physical memristor array has both storage and computation capabilities, connected to the global buffer via a dedicated interface. The scheduler needs to determine which computation results need to be transferred across arrays based on the data dependencies between logical operations. When one array needs computation results from another array, data waiting and inter-array communication become involved. For scenarios where other arrays require the computation results from this array, a time-sliced ​​execution model can be adopted: each execution cycle is divided into a first half and a second half. In the first half, the array performs logical computation operations; in the second half, the results calculated in this cycle and needed by other arrays are written to the buffer, and a data ready signal is sent to the global controller through the control path. This mechanism allows computation and data writing to be completed within the same cycle, without requiring additional independent communication cycles. The buffer maintains metadata for each data item, including the source array identifier, target array identifier, data validity bits, and ready status. When data is written to the buffer, its status is updated to ready, indicating that the target array can read it. If the logical operations of other arrays require the computation results from this array, but the corresponding logical operations have not yet been executed, the other arrays can only wait until the data is completed and transmitted to the target array through the buffer.

[0038] Once the external input data required for an operation to be executed in the memristor array is ready in the buffer, the scheduler will schedule a data transfer cycle in the cycle preceding the operation to write the required data from the buffer to the target array. Specifically, at the beginning of each cycle, the scheduler checks if there is data in the buffer waiting to be written to the array. If so, it enters the data transfer cycle and writes the data from the buffer to the array. If not, it checks if the current cycle can execute a logical operation: if all input data for an operation is ready and there is sufficient storage space, the operation is executed in the current cycle; if there is no currently executable operation, it waits. The scheduler can free up array space by erasing intermediate results that are no longer used by subsequent operations. The criteria for erasing include: whether the intermediate result has been used by all operations that depend on it; whether the current array is facing storage space pressure; and whether the erased result can provide sufficient storage space for the upcoming operation. The erase operation itself occupies clock cycles, so the scheduler must weigh the space gain and time overhead of erasing, prioritizing erasure when space is scarce and erasure can avoid the allocation of a new array. Multiple intermediate results can be erased in a single execution cycle. After the erase operation is completed, the freed-up storage space can be used for subsequent logic operations. Finally, the structure of the multi-memristor array obtained in this embodiment is as follows: Figure 10As shown in the figure, memristor arrays #1 to #4 form a 2×2 memristor array matrix, where each memristor array is used to execute an execution scheme consisting of a sub-execution sequence.

[0039] Furthermore, this embodiment also includes combining multiple different layer divisions, the number of layers N, and the number of partitions M within each layer. For each combination, steps S101 to S103 are executed to obtain multiple mapping schemes. Performance indicators of each execution scheme are obtained, such as a weighted average of one or more of latency, energy consumption, and system throughput. The execution scheme with the best performance indicators is selected as the final mapping result.

[0040] In summary, the purpose of this embodiment is to achieve a highly efficient synthesis mapping from complex combinational logic functions to state logic gate execution sequences. It uses a variety of simple logic function sets to synthesize netlists with different structures, introduces layer segmentation to obtain time-balanced sub-logic sequences, and obtains a logic execution scheme by scheduling the sub-sequences to achieve execution on multiple memristor arrays. This fully utilizes the parallelism of memristor arrays and improves the execution efficiency on memristor arrays.

[0041] Furthermore, this embodiment also provides a mapping system for timing balancing of in-memory logic computation under a multi-memoristant array, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute the mapping method for timing balancing of in-memory logic computation under a multi-memoristant array. This embodiment also provides a computer-readable storage medium storing a computer program or instructions, which is programmed or configured to execute the mapping method for timing balancing of in-memory logic computation under a multi-memoristant array via a processor. This embodiment also provides a computer program product, including a computer program or instructions, which is programmed or configured to execute the mapping method for timing balancing of in-memory logic computation under a multi-memoristant array via a processor.

[0042] Those skilled in the art will understand that the technical solutions provided by this invention may take the form of a method, system, or computer program product. Therefore, this invention may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this invention may take the form of a computer program product embodied on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, produce an implementation of the flowchart... Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0043] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A mapping method for time-balanced in-memory logic computation under a multi-memristor array, characterized in that, Includes the following steps: S101, logically synthesize the target calculation function to obtain a logical netlist; S102, the logical netlist is regarded as a directed acyclic graph, and the directed acyclic graph is partitioned into netlists, including: layer partitioning and intra-layer graph partitioning based on the number of layers N and the number of partitions M given by the current mapping scheme, merging the partitions in adjacent layers, thereby dividing the logical netlist into multiple sub-logical sequences; S103, schedule and map multiple sub-logic sequences of the current mapping scheme onto each memristor array to obtain an execution scheme composed of sub-execution sequences of each memristor array.

2. The mapping method for timing balance of in-memory logic computation under a multi-memristor array according to claim 1, characterized in that, In step S102, when the logical netlist is regarded as a directed acyclic graph, the input and output of each logical operation in the logical netlist are regarded as nodes in the directed acyclic graph, and the logical operation itself is regarded as an edge or superedge in the directed acyclic graph, thereby obtaining the directed acyclic graph corresponding to the logical netlist.

3. The mapping method for timing balance of in-memory logic computation under a multi-memristor array according to claim 1, characterized in that, Step S102, which involves performing layer segmentation and intra-layer graph segmentation based on the number of layers N and the number of intra-layer partitions M given by the current mapping scheme, includes: S201, calculate the topological depth of the directed acyclic graph, where the topological depth is the maximum number of edges from a node with an in-degree of 0 to a node with an out-degree of 0; based on the number of layers N given by the current mapping scheme, divide the topological depth of the directed acyclic graph into layers, and the following constraints must be met when dividing the layers: the total number of layers is less than the maximum depth path length of the directed acyclic graph; common nodes with the same topological depth are retained between adjacent layers, where the common nodes are the output nodes of the upper layer and the input nodes of the lower layer; S202, using a preset graph partitioning method, performs a secondary partitioning operation on the subgraph of each layer of the directed acyclic graph based on the number of partitions M within the layer, dividing the subgraph into M groups of nodes, thereby dividing the entire logical netlist into N×M sub-logical sequences.

4. The mapping method for timing balance of in-memory logic computation under a multi-memristor array according to claim 3, characterized in that, In step S202, when performing a secondary segmentation operation on the subgraph of each layer of the directed acyclic graph based on the number of intra-layer partitions M using a preset graph segmentation method, the process includes reading the configuration parameters of the graph segmentation. The configuration parameters include, but are not limited to, the segmentation imbalance threshold and the maximum number of subgraphs to be segmented. The imbalance is calculated for each layer, where the imbalance is the size difference between subgraphs within the layer. If the number of nodes in a certain layer is less than or equal to the preset maximum number of subgraphs to be segmented, or the imbalance exceeds the preset imbalance threshold, the original subgraph structure of that layer is maintained, so that the intra-layer graph segmentation result includes one non-empty partition and multiple empty partitions.

5. The mapping method for timing balance of in-memory logic computation under a multi-memristor array according to claim 1, characterized in that, Step S102, merging partitions in adjacent layers, includes: S301, traverse and obtain a set of adjacent layers obtained by layer segmentation as the current adjacent layer; S302, assign initial array numbers to each partition belonging to the upper and lower layers in the sub-logic sequence obtained by the inner graph segmentation, and record the array positions of the common nodes of the upper and lower layers in the upper and lower layers as upper partition array a and lower partition array b, respectively. S303, calculate the similarity between the upper partition array a and the lower partition array b; S304, construct a set of nodes whose common nodes belong to different array positions in the upper and lower layers respectively for the current adjacent layers. ,in and These are the initial array numbers of the i-th common node in the upper and lower partitions, respectively; S305, Traverse and extract the set One of the elements is used as a swap pair (x, y); S306, replace all elements x in the upper partition array a with elements y, and replace all elements y with elements x to obtain the new upper partition array a and the lower partition array b after replacement. Calculate the similarity between the new upper partition array a and the lower partition array b as the similarity after replacement. If the similarity after replacement is greater than the similarity before replacement, then the swap pair (x, y) is taken as the best swap pair. S307, Determine the set Has the traversal been completed? If the set is complete... If the traversal has not been completed, jump to step S305 to continue the traversal; otherwise, jump to step S308. S308, determine whether the best swap pair best_swap obtained after traversal is empty. If it is not empty, replace element x in the original upper partition array a with element y according to the best swap pair best_swap, and jump to step S304; otherwise, use the final upper partition array a and lower partition array b as the matching result of the current adjacent layer, and jump to step S309. S309, determine whether the traversal of the adjacent layers has not been completed. If the traversal of the adjacent layers has not been completed, jump to step S301 to continue the traversal; otherwise, start from the top layer of the directed acyclic graph and traverse layer by layer, integrating the partitions of the matching adjacent layers into a sub-logic sequence. The sub-logic sequence is a sequence of multiple logic gates executed serially on the memristor array, thereby obtaining multiple sub-logic sequences obtained by the logical netlist partitioning.

6. The mapping method for timing balance of in-memory logic computation under a multi-memristor array according to claim 1, characterized in that, Step S103, which schedules and maps multiple sub-logic sequences of the current mapping scheme to each memristor array, includes: S401, allocate storage space for the input data; S402, for multiple partitions consisting of multiple sub-logical sequences of the current mapping scheme, traverse one partition of the current mapping scheme as the current partition; S403, determine whether the communication queue is empty. If the communication queue is empty, proceed to step S404; otherwise, write the data to be communicated into the array and proceed to step S408. S404, determine whether the input data for the logical operation to be executed is ready. If not, proceed to step S405; otherwise, execute the logical operation, write the data required by other partitions into the buffer, update the communication queue, and proceed to step S408. S405, determine whether erasure can provide sufficient storage space for logical calculation. If feasible, proceed to step S406; otherwise, allocate a new array for the current partition, update the communication queue, write the data to be communicated into the array, and proceed to step S408. S406, Erase used data; S407, Update the status of the current partition; S408, determine whether the partition has been traversed. If the partition has not been traversed, jump to step S402 to continue traversing; otherwise, jump to step S409. S409, determine whether the calculation is complete. If the calculation is not yet complete, jump to step S402 to continue the calculation; otherwise, end and exit.

7. The mapping method for timing balance of in-memory logic computation under a multi-memristor array according to claim 1, characterized in that, It also includes combining the number of layers N and the number of partitions M within a layer in various different layer divisions, executing steps S101 to S103 for each combination to obtain execution schemes for multiple mapping schemes, obtaining the performance indicators of each execution scheme, and selecting the execution scheme with the best performance indicators as the final mapping result.

8. A timing-balanced mapping system for in-memory logic computation under a multi-memristor array, comprising interconnected microprocessors and memory, characterized in that, The microprocessor is programmed or configured to perform the mapping method for timing equalization of in-memory logic computation under any one of claims 1 to 7.

9. A computer-readable storage medium storing a computer program or instructions, characterized in that, The computer program or instructions are programmed or configured to execute, via a processor, the mapping method for timing equalization of in-memory logic computation under any one of claims 1 to 7.

10. A computer program product, comprising a computer program or instructions, characterized in that, The computer program or instructions are programmed or configured to execute, via a processor, the mapping method for timing equalization of in-memory logic computation under any one of claims 1 to 7.

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