Data path synthesis optimization method, system, medium, terminal and program product based on boundary fusing

Abstract

The application provides a boundary-fusing-based data path comprehensive optimization method, system, medium, terminal and program product, comprising: performing syntax analysis on an RTL design file to construct an abstract syntax tree and identify a plurality of data path operator nodes; performing bidirectional traversal on the data path operator nodes to generate a data flow graph; identifying intermediate signal variables for connecting adjacent data path operator nodes in the data flow graph, and performing data flow node connectivity fusion by eliminating the intermediate signal variables to generate a maximum arithmetic connectivity subgraph; performing algebraic expression reconstruction on the maximum arithmetic connectivity subgraph to generate an arithmetic expression model, and performing numerical domain analysis on the arithmetic expression model to obtain a corresponding minimum effective bit width; and taking the minimum effective bit width as a bit width constraint and returning it to the maximum arithmetic connectivity subgraph to generate a data path abstract graph model with a bit width constraint. The application can reduce the global delay of a circuit.

Description

Technical Field

[0001] This application relates to the field of data path comprehensive optimization technology, and in particular to a data path comprehensive optimization method, system, medium, terminal and program product based on boundary circuit breaking. Background Technology

[0002] Hardware simulation systems can automate and accelerate the simulation and debugging of complete chip designs, and are widely used in the early stages of RTL functional verification in large-scale SoC design. The synthesizer, as the entry point software of the hardware simulation system, is responsible for implementing the circuits designed by chip design companies using SystemVerilog with real FPGA resources, and is a core component of the hardware simulation system. In modern VLSI design, the core of digital signal processing, microprocessors, and various microcontrollers typically involves a large number of arithmetic operations, such as addition, multiplication, multiply-accumulate, and comparison. These circuits are collectively referred to as the datapath. As chip technology evolves towards more advanced nanometer-scale (e.g., 3nm and below), the performance of the datapath in terms of timing, area, and power consumption directly determines the core competitiveness of the entire chip, which is also a problem that our domestic hardware simulation synthesizers currently need to solve.

[0003] In traditional standard cell circuit synthesis processes, synthesis tools primarily rely on the syntax structure of hardware description languages ​​to perform gate-level logic mapping line by line. However, existing data path processing technologies have the following limitations:

[0004] 1. Limited by syntax and module boundaries, trapped in local optima: For the sake of code readability, reusability, or modularity, chip designers often break down complex arithmetic chains in RTL into multiple always blocks, multi-line statements, and define a large number of intermediate variables (wire or reg). Traditional synthesis tools instantiate independent arithmetic IP cores (e.g., independent adders, independent multipliers) for each line of code. This leads to the fragmentation of connections between various arithmetic modules, making it impossible to perform global algebraic simplification across statements and modules.

[0005] 2. Costly Carry Propagation Delay Cannot Be Eliminated Globally: In digital arithmetic circuits, the most significant factor affecting timing is the "carry propagation delay" caused by the cascading wait of adders from low to high bits during computation. While existing high-level arithmetic optimizations (such as Wallace Trees) can eliminate intermediate-level carry waits using "carry-preserving representations," traditional synthesis tools, unable to cross line boundaries of RTL code, can only implement carry preservation within a single multiplier or adder. For example, when calculating A+B+C+D, the traditional approach is: first perform A+B (generating carry wait), obtain the result, then add C (generating carry wait again), and then add D. However, expensive "carry-propagating adders" are still necessary for binary data interfacing between modules. This results in a large number of redundant carry waits on the chip's global critical path, severely limiting the chip's maximum operating frequency.

[0006] 3. Ineffective power switching caused by redundant bit width: When writing RTL, designers often subjectively increase the bit width of intermediate variables to prevent data overflow (for example, assigning the result of adding two 8-bit numbers to a 16-bit variable). Traditional synthesis techniques lack fine-grained static value range analysis across the entire arithmetic chain, resulting in the generation of a large number of redundant high-bit hardware circuits, which leads to severe dynamic glitches and ineffective switching power consumption during chip operation.

[0007] Therefore, it is necessary to provide a comprehensive optimization method, system, medium, terminal, and program product for data paths based on boundary circuit breaking to solve the above-mentioned problems in the prior art. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a data path comprehensive optimization method, system, medium, terminal and program product based on boundary circuit breaking, so as to solve the above-mentioned problems existing in the prior art.

[0009] To achieve the above and other related objectives, a first aspect of this application provides a data path synthesis optimization method based on boundary circuit breaking. The method includes: acquiring an RTL design file and performing syntax parsing to construct an abstract syntax tree; traversing the abstract syntax tree and identifying several data path operator nodes based on preset operator semantic features; performing bidirectional traversal of the input and output directions of the data path operator nodes based on data dependencies until a hard boundary of the data path is identified; combining the data path operator nodes and signal connections within the hard boundary of the data path to generate a data flow graph; identifying intermediate signal variables in the data flow graph used to connect adjacent data path operator nodes, and performing data flow node connectivity fusion by eliminating the intermediate signal variables to generate a maximum arithmetic connected subgraph; reconstructing the maximum arithmetic connected subgraph using an algebraic expression to generate an arithmetic expression model, and performing numerical domain analysis on the arithmetic expression model to obtain the corresponding minimum effective bit width; and using the minimum effective bit width as a bit width constraint back-indexed to the maximum arithmetic connected subgraph to generate a data path abstract graph model with bit width constraints.

[0010] In some embodiments of the first aspect of this application, the input and output directions of the data path operator nodes are bidirectionally traversed based on data dependencies. The specific process includes: selecting a starting node based on the plurality of data path operator nodes; performing graph traversal from the input direction of the starting node according to data dependencies; when a data path operator node is identified, adding the data path operator node to the current data flow graph, and continuing traversal based on the input of the data path operator node until a hard boundary of the data path is identified; performing graph traversal from the output direction of the starting node according to data dependencies; when a data path operator node is identified, adding the data path operator node to the current data flow graph, and continuing traversal based on the output of the data path operator node until a hard boundary of the data path is identified; reselecting a starting node from the data path operator nodes that have never been added to any data flow graph, and repeating the above data flow graph construction until all data path operator nodes are added to their corresponding data flow graphs.

[0011] In some embodiments of the first aspect of this application, the hard boundary of the data path includes: a trigger input terminal, a trigger output terminal, a chip main input terminal, a chip main output terminal, a fixed constant node, and a control logic decision node.

[0012] In some embodiments of the first aspect of this application, the process of performing data flow node connectivity fusion by eliminating the intermediate signal variable specifically includes: identifying the intermediate node corresponding to the intermediate signal variable in the abstract syntax tree; substituting the definition expression of the intermediate signal variable into the input item of the subsequent data path operator node that references the intermediate signal variable; and deleting the intermediate node while maintaining data dependency and bit width semantic consistency.

[0013] In some embodiments of the first aspect of this application, the process of reconstructing the algebraic representation of the maximum arithmetic connected subgraph to generate an arithmetic representation model specifically includes: converting the shift operators in the maximum arithmetic connected subgraph into constant multiplication expressions; converting the comparison operators in the maximum arithmetic connected subgraph into implicit subtraction expressions and using carry output or sign bit as the comparison result; and mapping the addition operators, subtraction operators, multiplication operators, shift operators, comparison operators, and selector nodes into a unified algebraic representation structure to obtain an arithmetic representation model.

[0014] In some embodiments of the first aspect of this application, the minimum effective bit width is used as a bit width constraint back-indexed to the maximum arithmetic connected subgraph. The specific process includes: performing numerical range analysis on the intermediate product terms, addition terms, and output terms in the arithmetic expression model to obtain the maximum range of positive and negative values ​​that the arithmetic expression model can mathematically achieve; determining the minimum effective bit width based on the maximum range of positive and negative values; comparing the minimum effective bit width with the original defined bit width of the corresponding signal in the RTL design file; if the original defined bit width is greater than the minimum effective bit width, marking the high bits exceeding the minimum effective bit width as constant bits or sign extension bits, and deleting the corresponding redundant hardware interconnects; otherwise, keeping the original defined bit width unchanged.

[0015] To achieve the above and other related objectives, a second aspect of this application provides a data path comprehensive optimization system based on boundary circuit breaking. The system includes: a preprocessing module for acquiring an RTL design file and performing syntax parsing to construct an abstract syntax tree (AST), traversing the AST, and identifying several data path operator nodes based on preset operator semantic features; and a data flow graph construction module for bidirectionally traversing the input and output directions of the data path operator nodes based on data dependencies until a hard boundary of the data path is identified, and grouping the data path operator nodes and signal connection groups within the hard boundary of the data path. The system generates a data flow graph; a boundary circuit breaking module is used to identify intermediate signal variables in the data flow graph that connect adjacent data path operator nodes, and to merge data flow nodes by eliminating the intermediate signal variables to generate a maximum arithmetic connected subgraph; a bit width acquisition module is used to reconstruct the maximum arithmetic connected subgraph using an algebraic expression, generate an arithmetic expression model, and perform numerical domain analysis on the arithmetic expression model to obtain the corresponding minimum effective bit width; a model construction module is used to back-index the minimum effective bit width as a bit width constraint to the maximum arithmetic connected subgraph to generate a data path abstract graph model with bit width constraints.

[0016] To achieve the above and other related objectives, a third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data path integration optimization method based on boundary circuit breaking.

[0017] To achieve the above and other related objectives, a fourth aspect of this application provides a computer program product comprising computer program code, which, when executed on a computer, enables the computer to implement the data path integration optimization method based on boundary circuit breaking.

[0018] To achieve the above and other related objectives, a fifth aspect of this application provides an electronic terminal, including a memory, a processor, and a computer program stored in the memory; the processor executes the computer program to implement the data path comprehensive optimization method based on boundary circuit breaking.

[0019] As described above, the data path comprehensive optimization method, system, medium, terminal, and program product based on boundary circuit breaking of this application have the following beneficial effects:

[0020] (1) Significantly reduce global circuit delay: By extracting the maximum arithmetic connected subgraph, the subsequent optimization stage can carry out bit width pruning throughout the entire link within the maximum arithmetic connected subgraph. It reduces the carry propagation delay in multi-level addition / multiplication chains to the minimum limit, and only performs carry propagation once at the final output, thereby significantly increasing the operating frequency of the standard unit circuit.

[0021] (2) Significantly reduce chip area: It breaks the line limit of RTL code, allowing the arithmetic logic hidden between different statements to be exposed in the same maximum arithmetic connected subgraph, thereby triggering effects such as common subexpression sharing (CSE) and algebraic simplification of sum-to-sum, directly reducing the number of hardware instantiations of multipliers and adders from the mathematical source.

[0022] (3) Effectively reduce dynamic power consumption and glitches: By eliminating unnecessary intermediate carry propagation within the maximum arithmetic connected subgraph, dynamic glitches caused by inconsistent signal arrival times are greatly reduced; at the same time, fine bit width clipping directly eliminates the power consumption waste caused by high-bit redundant flipping.

[0023] (4) Enhance the flexibility of the synthesis tool: It provides a high degree of freedom for the subsequent "context-driven generator". The tool can freely switch between area-first or time-first representation within the maximum arithmetic connected subgraph according to different temporal constraints, so as to achieve the optimality under multi-objective constraints. Attached Figure Description

[0024] Figure 1 The diagram shown is a flowchart of a data path comprehensive optimization method based on boundary circuit breaking in one embodiment of this application.

[0025] Figure 2 The diagram shown is a schematic representation of constructing a data flow graph in one embodiment of this application.

[0026] Figure 3 The diagram shown is a structural schematic of a data path comprehensive optimization method based on boundary circuit breaking in one embodiment of this application.

[0027] Figure 4 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of this application. Detailed Implementation

[0028] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0029] In the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" do not necessarily imply that they are different.

[0030] It should be noted that, in the embodiments of this application, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0031] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0032] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0033] <1> RTL design files: Register-transfer level hardware description files.

[0034] <2> Data path operator nodes: In the abstract syntax tree, these are the operator nodes that participate in data path operations, such as addition, subtraction, multiplication, shifting, comparison, or selection.

[0035] <3> Data flow graph: A graph structure formed by combining data path operator nodes and their signal connections based on data dependencies.

[0036] <4> Abstract Syntax Tree (AST): A tree-structured representation of an RTL design file obtained after syntax parsing.

[0037] The technical solutions of this application can be applied to various communication systems, such as: Long Term Evolution (LTE) systems, LTE Frequency Division Duplex (FDD) systems, future 5th Generation (5G) communication systems, new radio access technology (NR), LTE Time Division Duplex (TDD), Worldwide Interoperability for Microwave Access (WiMAX), Universal Mobile Telecommunication System (UMTS), and vehicle-to-XV2X. V2X can include vehicle to network (V2N), vehicle to vehicle (V2V), vehicle to infrastructure (V2I), vehicle to pedestrian (V2P), Long Term Evolution-Vehicle (LTE-V), vehicle-to-everything (V2X), machine-type communication (MTC), Internet of Things (IoT), Long Term Evolution-Machine (LTE-M), and machine to machine (M2M).

[0038] To facilitate understanding of the embodiments of this application, firstly, in conjunction with Figure 1 Detailed explanation. Figure 1 This document illustrates a flowchart of a data path integration optimization method based on boundary circuit breaking, as described in an embodiment of the present invention. The data path integration optimization method based on boundary circuit breaking in this embodiment mainly includes the following steps:

[0039] Step S11: Obtain the RTL design file and perform syntax parsing to construct an abstract syntax tree. Traverse the abstract syntax tree and identify several data path operator nodes based on preset operator semantic features.

[0040] It should be noted that an RTL design file refers to a digital circuit design file written in a register-transfer-level hardware description language. It describes the registers, combinational logic, data paths, control logic, and the transmission relationships between signals in a chip circuit. The RTL design file can include source files in hardware description languages ​​such as Verilog, SystemVerilog, or VHDL. For hardware simulation synthesizers, the RTL design file serves as a front-end input file and needs to be parsed and converted into an abstract syntax tree (AST) to facilitate subsequent identification of arithmetic operations, signal dependencies, and register boundaries.

[0041] Furthermore, lexical and syntactic analysis is performed on the RTL design file to identify module definitions, port declarations, signal declarations, continuous assignment statements, procedural assignment statements, conditional statements, selection statements, and operational expressions. Based on the identification results, an abstract syntax tree (AST) corresponding to the RTL design file is constructed. The AST includes multiple syntax nodes corresponding to modules, statements, signals, constants, operators, and expressions, and the hierarchical structure of the syntax in the RTL design file is represented by the parent-child relationships between nodes. By constructing the AST, the original text-based RTL design file can be converted into a structured intermediate representation, thus providing a foundation for subsequent identification of data path operator nodes, analysis of signal dependencies, and determination of hard boundaries of data paths. Preferably, existing hardware description language parsing tools such as Verific can be used to parse the RTL design file to obtain the standard AST.

[0042] Furthermore, based on the connection relationship of the multiple syntax nodes, the abstract syntax tree is traversed to identify several syntax nodes that contain preset arithmetic semantic features as data path operator nodes; wherein the preset arithmetic semantic features include arithmetic operation features such as addition, subtraction, multiplication, shift, comparison, and relational operators >, <, ==.

[0043] In another embodiment of this application, the preset arithmetic semantic features include not only arithmetic operation features such as addition, subtraction, multiplication, shifting, and comparison, but also selection operation features that have data connection relationships with data path operator nodes. Specifically, for the multi-way selection statement node in the abstract syntax tree, the multi-way selection statement node includes a selector node formed by a case statement or a conditional selection expression; it is detected whether each branch input of the selector node is connected to an identified data path operator node. If at least one branch input is connected to an identified data path operator node, it is determined that the selector node participates in the selection and transmission of the data path result, and the selector node is marked as a data path associated operator node. Thus, when constructing the data flow graph subsequently, the selector node and its connected arithmetic operator nodes can be included in the data path scope, thereby maintaining the conditional selection semantics and avoiding the truncation of the data path arithmetic chain due to the selection statement.

[0044] Step S12: Perform bidirectional traversal of the input and output directions of the data path operator nodes based on data dependencies until the hard boundary of the data path is identified, and combine the data path operator nodes and signal connections within the hard boundary of the data path to generate a data flow graph.

[0045] In one embodiment of this application, as Figure 2 As shown, the input and output directions of the data path operator nodes are traversed bidirectionally based on data dependencies. The specific process includes: selecting a starting node based on the data path operator nodes; performing graph traversal from the input direction of the starting node according to data dependencies; when a data path operator node is identified, adding it to the current data flow graph and continuing traversal based on the input of the data path operator node until a hard boundary of the data path is identified; performing graph traversal from the output direction of the starting node according to data dependencies; when a data path operator node is identified, adding it to the current data flow graph and continuing traversal based on the output of the data path operator node until a hard boundary of the data path is identified; reselecting a starting node from the data path operator nodes that have never been added to any data flow graph, and repeating the above data flow graph construction until all data path operator nodes are added to their corresponding data flow graphs.

[0046] It should be noted that not all of the data path operator nodes are connected, and multiple data flow graphs may be constructed from the same RTL design file; furthermore, one data path operator node is randomly selected from the several data path operator nodes as the starting node, and bidirectional traversal is performed on the starting node.

[0047] Furthermore, for traversal in the input direction, the source of operands is traced backwards from the input of the current data path operator node. When an operand originates from the output of another data path operator node, that other data path operator node is added to the current data flow graph, and the tracing continues upstream along the input of that other data path operator node until a hard boundary of the data path is encountered, such as a trigger output, a chip main input, or a fixed constant node. For traversal in the output direction, the subsequent use of the operation result is traced along the output of the current data path operator node. When the operation result is used as input by another data path operator node, that other data path operator node is added to the current data flow graph, and the tracing continues downstream along the output of that other data path operator node until a hard boundary of the data path is encountered, such as a trigger input, a chip main output, or a control logic decision node. Thus, multiple data path operator nodes and their signal connections interconnected by signal dependencies within the same hard boundary of a data path can be aggregated into the same data flow graph. For data path operator nodes that are not added to any data flow graph, they are reselected as new starting nodes and the above bidirectional traversal process is repeated to avoid missing multiple data path regions that are not connected to each other.

[0048] In one embodiment of this application, the hard boundary of the data path includes: a trigger input terminal, a trigger output terminal, a chip main input terminal, a chip main output terminal, a fixed constant node, and a control logic determination node.

[0049] Specifically, the hard boundary of the data path refers to the boundary node that is no longer crossed during bidirectional traversal of the data path, used to limit the fusion range of the data path operator nodes. Among them, the flip-flop output and the chip main input typically serve as the upstream data source boundary of the data path, representing the input starting point of the current combined data path; the flip-flop input and the chip main output typically serve as the downstream result output boundary of the data path, representing the output ending point of the current combined data path; fixed constant nodes represent constant inputs participating in arithmetic operations, which no longer have upstream data sources that can be traced; control logic decision nodes represent the location of control logic such as conditional jumps, state machine decisions, or selection controls, which mainly determine the selection of data path results or the flow direction, and should not be further merged with arithmetic data paths. By setting the above-mentioned hard boundaries of the data path, while preserving register timing boundaries, chip port boundaries, and control logic semantics, only the internal syntax boundaries formed by intermediate signal variables or statement structures within the hard boundary can be circuit-broken.

[0050] Step S13: Identify the intermediate signal variables used to connect adjacent data path operator nodes in the data flow graph, and perform data flow node connectivity fusion by eliminating the intermediate signal variables to generate the maximum arithmetic connectivity subgraph.

[0051] Specifically, the signal connections between each data path operator node are traversed in the data flow graph to determine the signal variables located between the output of the previous data path operator node and the input of the next data path operator node. If the signal variable is not a trigger input, trigger output, chip main input, chip main output, or control logic decision node, but is only used to receive the operation result of the previous data path operator node and serve as the input of the next data path operator node, then the signal variable is identified as an intermediate signal variable. The intermediate signal variable may include temporary signal variables declared by wire, reg, or logic in the RTL design file, which are typically used to pass intermediate operation results between multiple lines of statements, multiple assignment statements, or multiple code blocks. By identifying the intermediate signal variables, the internal syntax boundaries formed by the code writing style in the data flow graph can be determined, providing a basis for subsequently eliminating intermediate signal variables and merging adjacent data path operator nodes.

[0052] In one embodiment of this application, the process of performing data flow node connectivity fusion by eliminating the intermediate signal variable specifically includes: identifying the intermediate node corresponding to the intermediate signal variable in the abstract syntax tree; substituting the definition expression of the intermediate signal variable into the input item of the subsequent data path operator node that references the intermediate signal variable; and deleting the intermediate node while maintaining the consistency of data dependency and bit width semantics.

[0053] In one specific embodiment, the RTL design file includes the following data path description:

[0054] temp1 = A + B;

[0055] temp2 = temp1 + C;

[0056] Y = temp2 + D.

[0057] Where A, B, C, and D are the data path input signals, Y is the data path output signal, and temp1 and temp2 are intermediate signal variables used in the RTL design file to receive intermediate calculation results.

[0058] After parsing the RTL design file, multiple addition operator nodes corresponding to the "+" operation and intermediate nodes corresponding to temp1 and temp2 can be identified in the abstract syntax tree. Since temp1 is only used to connect the previous addition operator "A+B" and the next addition operator "temp1+C", and temp2 is only used to connect the previous addition operator "temp1+C" and the next addition operator "temp2+D", and neither temp1 nor temp2 belongs to the flip-flop terminal, the chip's main input / output terminal, or the control logic decision node, temp1 and temp2 are identified as intermediate signal variables.

[0059] When eliminating intermediate signal variables, firstly, the definition expression "A+B" of temp1 is substituted into the input of the subsequent addition operator node referencing temp1, transforming the expression "temp1+C" into "(A+B)+C". Then, the definition expression "(A+B)+C" of temp2 is substituted into the input of the subsequent addition operator node referencing temp2, transforming the expression "temp2+D" into "((A+B)+C)+D". During this substitution process, the data dependencies between the input signals remain unchanged, and the bit width semantics are kept consistent based on the symbol attributes and bit width definitions of temp1 and temp2 in the RTL design file. After the substitution is complete, the intermediate nodes corresponding to temp1 and temp2 in the abstract syntax tree are deleted, allowing the multiple addition operator nodes, originally separated by intermediate signal variables, to be directly connected in the data flow graph, thus merging to form the maximum arithmetic connected subgraph corresponding to "A+B+C+D".

[0060] Furthermore, if the intermediate signal variable is not only used as the input to the next-level data path operator node, that is, it is also used as the input to at least another data path operator node, then the intermediate signal variable will not be eliminated, in order to prevent the corresponding data path operator node, which is used as input, from losing input and causing logical errors in the data flow graph.

[0061] Step S14: Reconstruct the algebraic representation of the maximum arithmetic connected subgraph to generate an arithmetic representation model, and perform numerical domain analysis on the arithmetic representation model to obtain the corresponding minimum effective bit width.

[0062] In one embodiment of this application, the process of reconstructing the algebraic representation of the maximum arithmetic connected subgraph to generate an arithmetic representation model includes: converting the shift operators in the maximum arithmetic connected subgraph into constant multiplication expressions; converting the comparison operators in the maximum arithmetic connected subgraph into implicit subtraction expressions and using carry output or sign bit as the comparison result; and mapping the addition operators, subtraction operators, multiplication operators, shift operators, comparison operators, and selector nodes into a unified algebraic representation structure to obtain the arithmetic representation model.

[0063] Specifically, if a shift operator appears in the maximum arithmetic connected subgraph, it will be converted into a constant multiplication expression. For example, the shift operator (A << N) is converted into a constant multiplication expression A×2. N Where A is the main input of the chip, and N is the number of bits to be shifted.

[0064] If a comparison operator appears in the maximum arithmetic connected subgraph, it is converted into an implicit subtraction expression. When the comparison expression "A>B" is identified, it is converted into the binary two's complement subtraction expression "A+(~B)+1" to represent "A-B", where "~B" represents bitwise inversion of B, and "+1" represents carry compensation in two's complement subtraction. This conversion does not require the complete difference of "A-B" as the final output, but rather determines the comparison result based on the operation state of the implicit subtraction expression. For unsigned comparisons, the carry output of the highest bit can be used to determine whether a borrow occurred during subtraction, and the comparison result can be determined by combining this with whether the difference is zero. For signed comparisons, the comparison result can be determined based on the sign bit of the difference and the overflow state. Thus, comparison operators can be mapped to an algebraic expression structure consistent with arithmetic operators such as addition and subtraction, thereby incorporating comparison logic into a unified arithmetic expression model while maintaining the original comparison semantics.

[0065] Furthermore, the maximal arithmetic connected subgraph after the above transformation is mapped to the same algebraic expression to construct an arithmetic expression model.

[0066] Furthermore, based on the original bit width, sign attribute, and constant values ​​of each input signal in the arithmetic expression model, numerical ranges are derived along the algebraic operation relationships in the arithmetic expression model to obtain the maximum and minimum negative value ranges that the intermediate product terms, addition terms, subtraction terms, and output terms can mathematically reach. The minimum number of binary bits required to represent the corresponding signal without overflow is determined based on these maximum and minimum negative value ranges, and this minimum number of binary bits is defined as the minimum effective bit width of the corresponding signal. This avoids retaining redundant high-order bits solely according to the user-declared original bit width in the RTL design file, thus providing a basis for subsequent bit width constraint backscaling and redundant hardware interconnect deletion.

[0067] Step S15: Use the minimum effective bit width as a bit width constraint back index to the maximum arithmetic connected subgraph to generate a data path abstract graph model with bit width constraints.

[0068] In one embodiment of this application, the minimum effective bit width is used as a bit width constraint back-indexed to the maximum arithmetic connected subgraph. The specific process includes: performing numerical range analysis on the intermediate product terms, addition terms, and output terms in the arithmetic expression model to obtain the maximum range of positive and negative values ​​that the arithmetic expression model can mathematically achieve; determining the minimum effective bit width based on the maximum range of positive and negative values; comparing the minimum effective bit width with the original defined bit width of the corresponding signal in the RTL design file; if the original defined bit width is greater than the minimum effective bit width, then marking the high bits exceeding the minimum effective bit width as constant bits or sign extension bits, and deleting the corresponding redundant hardware interconnects; otherwise, keeping the original defined bit width unchanged.

[0069] Specifically, the minimum effective bit widths of each input, intermediate operation, and output term obtained through numerical domain analysis are associated with the corresponding data path operator nodes, signal edges, or output nodes in the maximum arithmetic connected subgraph.

[0070] Furthermore, the bit width attribute of the corresponding node or signal edge is updated according to the minimum effective bit width, and redundant high bits that exceed the minimum effective bit width are marked with constant bits, sign extension bits, or deletion bits.

[0071] After completing the bit-width constraint back-indexing, the arithmetic operator connections, input-output boundary relationships, and data dependencies in the maximum arithmetic connected subgraph are retained, forming a data path abstract graph model with bit-width attributes, sign attributes, and redundant bit pruning markers. This data path abstract graph model serves as an intermediate representation for subsequent gate-level netlist generation or FPGA resource mapping, enabling the subsequent synthesis process to generate the corresponding hardware circuit based on the pruned effective bit width.

[0072] In one specific embodiment, for the adder node "Y=A+B" in the maximum arithmetic connected subgraph, if the numerical domain analysis determines that the minimum effective bit width of Y is 9 bits, while the original defined bit width of Y in the RTL design file is 16 bits, then "9 bits" is used as the bit width constraint of the corresponding output edge of Y and back-indexed to the maximum arithmetic connected subgraph, and bits 10 to 16 are marked as redundant high bits. After the back-indexing is completed, the adder node and its output edge carry the effective bit width constraint, and the subsequent netlist generator can use this to avoid generating invalid hardware interconnects corresponding to the redundant high bits.

[0073] Figure 3 This is a schematic block diagram of a data path comprehensive optimization system 300 based on boundary circuit breaking provided in an embodiment of this application. Figure 3 As shown, the device includes a preprocessing module 301, a data flow graph construction module 302, a boundary circuit breaking module 303, a bit width acquisition module 304, and a model construction module 305.

[0074] The preprocessing module 301 is used to acquire the RTL design file and perform syntax parsing to construct an abstract syntax tree, traverse the abstract syntax tree, and identify several data path operator nodes based on preset operator semantic features.

[0075] The data flow graph construction module 302 is used to perform bidirectional traversal of the input and output directions of the data path operator nodes based on data dependencies until the hard boundary of the data path is identified, and to combine the data path operator nodes and signal connections within the hard boundary of the data path to generate a data flow graph.

[0076] Boundary circuit breaking module 303 is used to identify intermediate signal variables used to connect adjacent data path operator nodes in the data flow graph, and to perform data flow node connectivity fusion by eliminating the intermediate signal variables to generate a maximum arithmetic connectivity subgraph;

[0077] The bit width acquisition module 304 is used to perform algebraic expression reconstruction on the maximum arithmetic connected subgraph, generate an arithmetic expression model, and perform numerical domain analysis on the arithmetic expression model to obtain the corresponding minimum effective bit width.

[0078] The model building module 305 is used to back-index the minimum effective bit width as a bit width constraint to the maximum arithmetic connected subgraph to generate a data path abstract graph model with bit width constraints.

[0079] It should be understood that the specific process of each module performing the above-mentioned corresponding steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0080] It should also be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0081] Figure 4 This is a schematic block diagram of the electronic terminal provided in an embodiment of this application. Figure 4 As shown, the electronic terminal 400 includes at least one processor 401, a memory 402, at least one network interface 403, and a user interface 405. The various components in the electronic terminal 400 are coupled together via a bus system 404. It is understood that the bus system 404 is used to implement communication between these components. In addition to a data bus, the bus system 404 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in… Figure 4 The general will label all buses as bus systems.

[0082] The user interface 405 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0083] It is understood that memory 402 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0084] In this embodiment of the invention, the memory 402 is used to store various types of data to support the operation of the electronic terminal 400. Examples of this data include: any executable program for operation on the electronic terminal 400, such as the operating system 4021 and application programs 4022; the operating system 4021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 4022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The method for implementing the boundary circuit breaker-based data path comprehensive optimization method provided in this embodiment of the invention can be included in the application program 4022.

[0085] The methods disclosed in the above embodiments of the present invention can be applied to processor 401, or implemented by processor 401. Processor 401 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 401 or by instructions in the form of software. The processor 401 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 401 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 401 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in a memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0086] In an exemplary embodiment, the electronic terminal 400 may be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs) to execute the aforementioned method.

[0087] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code, which, when run on a computer, causes the computer to execute the data path integration optimization method based on boundary circuit breaking in any of the above embodiments.

[0088] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing program code, which, when run on a computer, causes the computer to execute the data path integration optimization method based on boundary circuit breaking in any of the above embodiments.

[0089] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0090] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0091] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0092] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0093] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0094] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0095] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0096] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0097] In summary, this application provides a data path comprehensive optimization method, system, medium, terminal, and program product based on boundary circuit breaking, including: parsing the RTL design file to construct an abstract syntax tree and identify several data path operator nodes; performing bidirectional traversal on the data path operator nodes to generate a data flow graph; identifying intermediate signal variables in the data flow graph used to connect adjacent data path operator nodes, and performing data flow node connectivity fusion by eliminating the intermediate signal variables to generate a maximum arithmetic connected subgraph; reconstructing the maximum arithmetic connected subgraph using an algebraic expression to generate an arithmetic expression model, and performing numerical domain analysis on the arithmetic expression model to obtain the corresponding minimum effective bit width; and using the minimum effective bit width as a bit width constraint back-indexed to the maximum arithmetic connected subgraph to generate a data path abstract graph model with bit width constraints. This application can reduce the global delay of the circuit. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0098] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A data path comprehensive optimization method based on boundary circuit breaking, characterized in that, include: The RTL design file is obtained and its syntax is parsed to construct an abstract syntax tree. The abstract syntax tree is traversed, and several data path operator nodes are identified based on preset operator semantic features. The input and output directions of the data path operator nodes are bidirectionally traversed based on data dependencies until the hard boundary of the data path is identified. The data path operator nodes and signal connections within the hard boundary of the data path are combined to generate a data flow graph. Identify intermediate signal variables used to connect adjacent data path operator nodes in the data flow graph, and perform data flow node connectivity fusion by eliminating the intermediate signal variables to generate a maximum arithmetic connectivity subgraph; The maximum arithmetic connected subgraph is reconstructed using an algebraic representation to generate an arithmetic representation model, and the arithmetic representation model is subjected to numerical domain analysis to obtain the corresponding minimum effective bit width. The minimum effective bit width is used as a bit width constraint back-indexed to the maximum arithmetic connected subgraph to generate a data path abstract graph model with bit width constraints.

2. The data path comprehensive optimization method based on boundary circuit breaking according to claim 1, characterized in that, The data path operator nodes are traversed bidirectionally in both input and output directions based on data dependencies. The specific process includes: The starting node is selected based on the aforementioned data path operator nodes; The graph is traversed from the input direction of the originating node according to the data dependency relationship. When a data path operator node is identified, the data path operator node is added to the current data flow graph, and the traversal continues based on the input of the data path operator node until a hard boundary of the data path is identified. The graph is traversed from the output direction of the originating node according to the data dependency relationship. When a data path operator node is identified, the data path operator node is added to the current data flow graph, and the traversal continues based on the output of the data path operator node until a hard boundary of the data path is identified. Reselect the starting node from the data path operator nodes that have never been added to any data flow graph, and repeat the above data flow graph construction until all data path operator nodes have been added to their corresponding data flow graphs.

3. The data path comprehensive optimization method based on boundary circuit breaking according to claim 2, characterized in that, The hard boundary of the data path includes: the input terminal of the trigger, the output terminal of the trigger, the main input terminal of the chip, the main output terminal of the chip, the fixed constant node, and the control logic decision node.

4. The data path comprehensive optimization method based on boundary circuit breaking according to claim 1, characterized in that, The specific process of achieving data stream node connectivity fusion by eliminating the intermediate signal variables includes: Identify the intermediate nodes corresponding to the intermediate signal variables in the abstract syntax tree; The definition expression of the intermediate signal variable is substituted into the input of the subsequent data path operator node that references the intermediate signal variable, and the intermediate node is deleted while maintaining the consistency of data dependency and bit width semantics.

5. The data path comprehensive optimization method based on boundary circuit breaking according to claim 1, characterized in that, The specific process of reconstructing the algebraic representation of the maximal arithmetic connected subgraph to generate an arithmetic representation model includes: Convert the shift operator in the maximally arithmetic connected subgraph into a constant multiplication expression; The comparison operators in the maximal arithmetic connected subgraph are converted into implicit subtraction expressions and the carry output or the sign bit is used as the comparison result. Addition, subtraction, multiplication, shift, comparison, and selector nodes are mapped to a unified algebraic representation structure to obtain an arithmetic representation model.

6. The data path comprehensive optimization method based on boundary circuit breaking according to claim 1, characterized in that, The specific process of using the minimum effective bit width as a bit width constraint back-indexing to the maximum arithmetic connected subgraph includes: Numerical range analysis is performed on the intermediate product term, addition term, and output term in the arithmetic expression model to obtain the maximum range of positive and negative values ​​that the arithmetic expression model can mathematically achieve, and the minimum effective bit width is determined based on the maximum range of positive and negative values. Compare the minimum effective bit width with the original defined bit width of the corresponding signal in the RTL design file; If the original defined bit width is greater than the minimum effective bit width, the high-order bits exceeding the minimum effective bit width are marked as constant bits or sign extension bits, and the corresponding redundant hardware interconnects are deleted; otherwise, the original defined bit width remains unchanged.

7. A data path comprehensive optimization system based on boundary circuit breaking, characterized in that, include: The preprocessing module is used to acquire RTL design files and perform syntax parsing to construct an abstract syntax tree, traverse the abstract syntax tree, and identify several data path operator nodes based on preset operator semantic features. The data flow graph construction module is used to perform bidirectional traversal of the input and output directions of the data path operator nodes based on data dependencies until the hard boundary of the data path is identified, and to combine the data path operator nodes and signal connections within the hard boundary of the data path to generate a data flow graph. The boundary circuit breaking module is used to identify intermediate signal variables in the data flow graph that are used to connect adjacent data path operator nodes, and to perform data flow node connectivity fusion by eliminating the intermediate signal variables to generate the maximum arithmetic connectivity subgraph. The bit width acquisition module is used to reconstruct the algebraic expression of the maximum arithmetic connected subgraph, generate an arithmetic expression model, and perform numerical domain analysis on the arithmetic expression model to obtain the corresponding minimum effective bit width. The model building module is used to back-index the minimum effective bit width as a bit width constraint to the maximum arithmetic connected subgraph, thereby generating a data path abstract graph model with bit width constraints.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the data path comprehensive optimization method based on boundary circuit breaking as described in any one of claims 1 to 6.

9. A computer program product, characterized in that, The computer program product includes computer program code, which, when run on a computer, enables the computer to implement the data path integration optimization method based on boundary circuit breaking as described in any one of claims 1 to 6.

10. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the data path integration optimization method based on boundary circuit breaking as described in any one of claims 1 to 6.

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