A polyphase interpolation and digital up-conversion cooperative stream processing method and architecture

Abstract

The application discloses a kind of polyphase interpolation and digital up-conversion collaborative stream processing method and architecture, method includes: obtaining input signal and prototype filter;With the commutability of complex multiplication and convolution operation, mix frequency converter is from the high-speed domain after interpolation to the low-speed domain before interpolation;Under the condition that interpolation coefficient is equal to polyphase factor, prototype filter is decomposed into phase polyphase structure, and polyphase complex filter coefficient is defined;In the sampling rate rate domain, input signal is multiplied with low-frequency fundamental signal to obtain pre-mixing signal;Pre-mixing signal is sent into polyphase complex interpolation filter group and is carried out interpolation filtering processing, each phase filter coefficient is the complex coefficient after offline calculation and quantization, and the sample point after each phase interpolation and up-conversion is output;Synthetic sampling rate data stream.The application prepositions mix frequency converter to low-speed domain, and the number of multiplier is reduced, power consumption and timing pressure are reduced.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing and digital front-end technology, specifically relating to a multiphase interpolation and digital upconversion collaborative stream processing method. By combining mixer pre-processing and filter coefficient compensation, the multiphase interpolation filter and multiphase digital mixer are collaboratively optimized in stream processing architecture, thereby significantly reducing the number of high-speed domain multipliers, reducing power consumption, and maintaining system spectrum performance. This method and hardware architecture can be widely applied in software-defined radio, digital beamforming, distributed coherent signal sources, 5G / 6G baseband front-ends, and high-speed test and measurement instruments. Background Technology

[0002] Digital upconversion (DUC) is the core processing link in modern communication and radar digital front-ends. Its basic task is to upsample the low-sampling-rate complex baseband signal to a high rate through multi-stage interpolation, and then digitally mix it with the local oscillator signal generated by a numerically controlled oscillator (NCO) to achieve precise frequency shifting at a specified mid / high frequency range (digital downconversion, DDC, is the reverse process). To achieve high-rate sampling rate conversion on hardware platforms such as FPGAs and ASICs, polyphase filters have become the industry standard. Essentially, a high-speed FIR filter is decomposed into multiple parallel sub-filters operating at low rates, thereby significantly reducing the operating frequency of multiply-accumulate operations. However, in existing typical DUC implementations, interpolation filtering and digital mixing are often designed as two relatively independent modules: first, the baseband signal is upsampled to the interpolated high rate using a polyphase interpolation filter. Then, with the carrier generated by the high-speed NCO Performing complex multiplication to shift the spectrum, such as... Figure 1 As shown. This series design has the following inherent drawbacks:

[0003] 1. Waste of computational resources: Mixing operations are complex multiplications, which must be performed at high data rates after interpolation. Meanwhile, the multipliers inside the multiphase interpolation filter also operate at a high speed. The two independently accumulate hardware overhead, which is particularly significant in multi-channel / multi-link systems.

[0004] 2. High-speed NCO is costly: To ensure the spectral purity and phase continuity of the carrier wave, At high speeds, NCOs require high-bit-width phase accumulators and large-capacity sine / cosine lookup tables (or high-precision CORDICs), consuming considerable BRAM / LUTs and dynamic power.

[0005] 3. Timing convergence and placement and routing pressure: Complex multipliers and their data paths in the high-speed clock domain have stringent timing convergence requirements, especially in FPGAs where they often become critical paths, limiting the improvement of system clock frequency.

[0006] 4. Failure to fully exploit the synergistic potential of multiphase structures: There is a strong coupling relationship between the multiple parallel low-speed branches of multiphase interpolation filters and the phase rotation operation required for multiphase mixing, but the existing architecture does not make full use of this relationship.

[0007] Furthermore, even if the interpolator factor is... With mixer multiphase factor Assuming they are equal, current designs typically still treat them as separate pipelined cascaded modules, lacking multiplier multiplexing, coefficient fusion, and pipeline merging strategies from the perspective of the entire link. This particularly limits integration and energy efficiency in broadband, high-precision, multi-channel applications (such as large-scale phased arrays, distributed phased coherent signal sources, and software-defined radio broadband transmitters).

[0008] To address the aforementioned problems, this invention proposes a multiphase interpolation and digital upconversion processing method and its architecture. Summary of the Invention

[0009] This invention provides a multiphase interpolation and digital upconversion coordinated flow processing method to solve the above-mentioned technical problems, specifically adopting the following technical solution:

[0010] A multiphase interpolation and digital upconversion coordinated flow processing method includes the following steps:

[0011] Acquire input signal and prototype filter The length of the zero-padded filter Interpolation coefficients multiples of integers, let ,in Determine the target carrier frequency based on the number of taps per phase. Sampling rate before interpolation and the interpolated sampling rate ;

[0012] By leveraging the commutativity of complex multiplication and convolution operations, the mixer is moved from the interpolated high-speed domain to the pre-interpolated low-speed domain, and the complex filter coefficients are defined. , so that the output signal Satisfies identity transformation:

[0013]

[0014] ;

[0015] In interpolation coefficients With multiphase factors Under equal conditions, the prototype filter Decomposed into Multiphase structure, the first Phase coefficient is Define the coefficients of a polyphase complex filter. ,in … ;

[0016] At sampling rate In the rate domain, the input signal Multiplying it by the low-frequency fundamental signal yields the premixed signal. Low-frequency fundamental frequency ,in express The closest integer;

[0017] premixed signal The input is fed into a multiphase complex interpolation filter bank for interpolation filtering. The filter coefficients for each phase are complex coefficients calculated offline and quantized. Output the interpolated samples of each phase and the samples after up-conversion. ;

[0018] Let the complex filter coefficients of each phase Then the first Phase output satisfies ,in ;

[0019] The output samples of each phase are combined into a sampling rate in order of phase number. The data stream completes the digital up-conversion.

[0020] Furthermore, the implementation of the multiphase complex interpolation filter bank is based on the interpolated sampling rate. With system clock frequency The size relationship is determined when: At that time, a serial multiphase filter structure with time-division multiplexed multipliers and delay units is adopted. Each multiplier operates at Convolution operations are performed at a low speed, with one multiplier operating at [speed value missing]. Premixing is completed at a certain speed; when At that time, a parallel multiphase filter structure is adopted, in which each phase independently uses delay units and multipliers. The branch circuits are synchronously outputting water.

[0021] Furthermore, the complex filter coefficients and polyphase complex filter coefficients The phase compensation calculation is performed offline by the processor. After being quantized to a fixed-point format compatible with the hardware multiplier, it is downloaded to the phase coefficient registers or memory of the programmable logic terminal via the bus interface.

[0022] Furthermore, when the digital up-conversion link adopts Multiphase interpolation cascade with interpolation factors for each stage as follows: In this process, the mixer pre-processing method is applied iteratively step by step: starting from the last stage, the pre-processed mixer is combined with the polyphase interpolation filter of the previous stage and pre-processed again before the previous stage. The filter coefficients of this stage are multiplied by the new phase compensation factor accordingly. This process continues until the original high-speed domain mixer is pre-processed as a low-speed mixer in the lowest input rate domain. The phase compensation generated by each pre-processing stage is absorbed into the corresponding polyphase interpolation filter coefficients, or the low-speed mixer is retained before the selected intermediate stage.

[0023] Furthermore, in the step-by-step iterative preprocessing, the filter coefficients of each stage are recalculated and downloaded offline on the processor, and the iteration endpoint is flexibly selected according to the system flexibility and resource requirements to achieve multi-level collaborative optimization.

[0024] Furthermore, the low-frequency fundamental signal is generated by operating at... The low-speed numerically controlled oscillator at a given rate is generated, or provided by a low-frequency fundamental frequency generation module, which is used to generate the low-frequency fundamental frequency in... The frequency generated at the speed is The complex fundamental wave.

[0025] Furthermore, the prototype filter The original length is ;when no When the length is an integer multiple of the given length, zeros are added to the end to make the equivalent length after zero-padding. ,in ⌈ ⌉, to ensure that each phase branch has One tap.

[0026] Furthermore, during dynamic carrier frequency switching, only the low-frequency fundamental frequency needs to be updated via the bus interface. The corresponding numerically controlled oscillator frequency word and the complex coefficients of the polyphase filter This completes the carrier frequency. The dynamic switching is performed frame by frame, without affecting the pipeline processing of existing samples.

[0027] A multiphase interpolation and digital upconversion collaborative stream processing architecture includes: a coefficient generation and configuration module, used to generate and configure coefficients based on the target carrier frequency. and prototype filter Generate and distribute Phase complex filter coefficients Low-speed complex mixer, used in The rate domain will input signal With frequency Multiplying the complex fundamental frequency yields the premixed signal. ,in , express The closest integer; Phase complex interpolation filter bank, used to respectively use complex interpolation filter banks to respectively right Perform convolution and output ; and a sample synthesis module, used to synthesize samples according to phase sequence Phase output synthesized into sampling rate Data stream; where , , .

[0028] Furthermore, when ≤ At that time, the multiphase complex interpolation filter bank adopts a serial structure of time-division multiplexed multipliers and delay units; when At that time, a parallel structure with independently configured delay units and multipliers for each phase is adopted. The branch circuits are synchronously outputting water.

[0029] Furthermore, the coefficient generation and configuration module is located on the processor side and is used for offline calculation and quantization of the multiphase complex filter coefficients, and downloads them to the phase coefficient registers or memory of the programmable logic side through the bus interface.

[0030] Furthermore, when the digital up-conversion link adopts When multiple phase interpolation stages are cascaded, the original high-speed domain mixer is pre-processed as a low-speed mixer in the selected input rate domain, and the phase compensation generated by each pre-processor stage is absorbed into the coefficients of the corresponding multiphase interpolation filter.

[0031] The advantage of this invention lies in utilizing the commutativity of complex multiplication and convolution operations to move the mixer from the high-speed domain after interpolation to the low-speed domain before interpolation, thereby reducing the number of multipliers. Down to Eliminate high-speed domain independent complex multipliers; mixer operating speed is reduced from Down to This reduces critical path latency and dynamic power consumption; high-speed NCO is replaced with low-speed NCO, reducing BRAM / LUT resources; and multi-level interpolation is supported for iterative pre-processing and dynamic carrier frequency switching, while keeping the system spectrum indicators unchanged. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 The basic structure is based on traditional interpolation plus mixing;

[0034] Figure 2 This is the basic structure of traditional multi-stage interpolation and mixing;

[0035] Figure 3 This is the basic structure of the optimized multi-stage interpolation and mixing of the present invention; the sampling rate after each interpolation stage in the figure is calculated according to the corresponding interpolation factor and... Understanding the product.

[0036] Figure 4 This is a basic single-stage interpolation and mixing structure for the preamplifier stage;

[0037] Figure 5 Implementation details for the optimized serial multiphase mixer architecture;

[0038] Figure 6 For optimization Implementation details of the parallel multiphase mixer architecture. Detailed Implementation

[0039] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0040] The core idea of ​​this invention is to utilize the commutativity and distributive law of complex multiplication and convolution operations to perform an equivalent mathematical transformation on the multiphase interpolation-multiphase mixing link, moving the mixer from after interpolation to before interpolation; further, in the multiphase structure, the phase factor required for multiphase mixing is absorbed into the branch coefficients of the multiphase interpolation filter, forming a complex filter. The specific derivation and architecture are as follows.

[0041] (1) Derivation of the preamplifier for a single-phase general form mixer.

[0042] Let the input signal be Low-pass FIR filter Length is The digital upconversion frequency is Sampling rate In traditional architectures, the mixer is placed after the filter, and the output... satisfy:

[0043]

[0044] The summation range on the right-hand side of the above equation is: Multiply by using identity transformation And rearrange the convolution terms and define the compensation factor. With complex filter coefficients:

[0045]

[0046] The formula can then be equivalently rewritten in the form of a mixer preamp:

[0047]

[0048] At this point, the mixer is equivalently pre-positioned before the filter, and the operating speed decreases to [missing value]. The low-pass filter is made of It became a complex filter .

[0049] (2) Derivation of the preamplifier for multiphase mixers.

[0050] In interpolation coefficients With multiphase factors Assuming they are equal, let the input signal be... Filter length , No. Phase coefficient The sampling rate before interpolation is After interpolation, it becomes The target carrier frequency is Then the first Phase output satisfy:

[0051]

[0052] Similarly, we introduce the identity transformation and define a polyphase complex filter:

[0053]

[0054] Then the first The phase output can be equivalently rewritten as a multiphase mixer preamp expression:

[0055]

[0056] In other words, the mixer preamp is also applicable to multiphase structures.

[0057] (3) Step-by-step pre-iteration optimization in multi-level interpolation links.

[0058] When the DUC link adopts Multiphase interpolation cascade (interpolation factors for each stage are respectively) When ), the present invention applies the above-mentioned pre-processing method iteratively step by step: The first... The preamplifier mixer further combines the first stage with the second stage. The multiphase interpolation filter of the first stage is then pre-filtered to the second stage. Before each stage, the filter coefficients of that stage are multiplied by a new phase compensation factor; this process continues until the original high-speed domain mixer is pre-processed as a low-speed mixer in the lowest input rate domain. The phase compensation generated by each pre-processing stage is absorbed into the corresponding polyphase interpolation filter coefficients, or the low-speed mixer is retained before the selected intermediate stage. The traditional multi-stage structure and the multi-stage structure optimized by this invention are shown in Figures 2 and 3, respectively.

[0059] (4) Collaborative stream processing architecture.

[0060] Based on the above derivation, the collaborative stream processing hardware architecture proposed in this invention is as follows: Figure 4 As shown, it includes: ① Working in A single-channel low-speed complex mixer at a given rate (essentially a low-speed NCO + complex multiplier, or directly provided by the low-frequency fundamental wave module from another aspect of this invention, "High-Frequency Digital Carrier Signal Generation Method Based on Multiphase Parallel Structure") generates a frequency of... The low-frequency fundamental wave and the input Multiplication; ② Multiphase complex interpolation filter bank The coefficients are those of the original real coefficient filter. With phase compensation factor Pointwise multiplication supports both serial and parallel implementations; ③ Filter coefficients are calculated offline and dynamically loaded by the PS terminal, supporting carrier frequency agility.

[0061] (5) Serial and parallel implementation conditions.

[0062] When the interpolated sampling rate satisfies At that time, a serial multiphase filter structure with time-division multiplexed multipliers and delay units is adopted, and the multipliers operate at full efficiency; the theoretical number of multipliers in the overall architecture is... ,in Each multiplier operates at At a certain speed, it is used for convolution operations, with one multiplier operating at [speed value missing]. This is used for pre-mixing. The serial implementation details are shown in Figure 5.

[0063] when At that time, a parallel multiphase filter structure with independent flow in each phase is adopted, and the filter length is... If not integers Alignment can be achieved by padding with zeros, which can save up to [number] zeros. There are multiple multipliers. The details of the parallel implementation are shown in Figure 6. In both implementations, the filter coefficients must be configurable.

[0064] (6) Resource comparison.

[0065] With parallelism as Taking real-time computing scenarios as an example, the number of multipliers required for the three schemes are as follows: , and The number of adders is 1. In both traditional architecture and co-optimization (mixer not pre-positioned), the mixer operates at... After the mixer is pre-amplified, its operating speed drops to The detailed comparison of the three scenarios is shown in the table below:

[0066] Table 1 Comparison of Adder and Multiplier Usage in Various Situations

[0067]

[0068] Beneficial effects:

[0069] Completely eliminate high-speed domain-independent complex multipliers: Traditional architectures operating in... rate One mixer multiplier is removed or absorbed entirely, and the total number of multipliers after co-optimization is reduced from [previous value]. Down to Further reduction to the mixer preamplifier solution Significant resource savings are achieved.

[0070] Reduce critical path and system power consumption: The operating speed of the pre-mixer is reduced from Down to High-speed complex multiplication on the critical path is replaced by low-speed multiplication, which significantly reduces the dynamic power consumption and timing convergence pressure of the FPGA.

[0071] Simplified high-speed NCO design: Traditional high-speed, high-precision NCOs are replaced with those operating in... The low-speed NCO (or the low-speed fundamental wave module proposed in the "multiphase carrier generation method" of this invention) reduces ROM / LUT storage resources and phase truncation error simultaneously.

[0072] Supports iterative optimization of multi-stage and multi-phase interpolation: the mixer can be moved forward step by step along the multi-stage interpolation link, and the final landing point (e.g., the lowest rate stage) can be flexibly selected to maximize resource savings, or it can be kept in the intermediate stage as needed to adapt to system flexibility.

[0073] The system performance remains unchanged: all transformations are mathematical identities, and the passband flatness, stopband rejection, and system spectrum shifting accuracy of the filter are equivalent to those of the traditional architecture, without introducing additional distortion or phase noise.

[0074] CPU+FPGA heterogeneous implementation is user-friendly: filter coefficients The phase compensation calculation can be completed offline by the PS (ARM) side and loaded into the PL side via AXI-Lite or DMA without increasing the computing resources of the FPGA side during runtime.

[0075] High architectural regularity: The optimized stream processing unit consists of a single type of complex FIR branches, with a highly regular parallel structure, which facilitates pipeline mapping, placement and routing, and multi-channel multiplexing for FPGA / ASIC.

[0076] Based on the above derivation, this application discloses a multiphase interpolation and digital upconversion coordinated flow processing method, comprising the following steps:

[0077] Acquire input signal and prototype filter The length of the zero-padded filter Interpolation coefficients multiples of integers, let ,in Determine the target carrier frequency based on the number of taps per phase. Sampling rate before interpolation and the interpolated sampling rate ;

[0078] By leveraging the commutativity of complex multiplication and convolution operations, the mixer is moved from the interpolated high-speed domain to the pre-interpolated low-speed domain, and the complex filter coefficients are defined. , so that the output signal Satisfies identity transformation:

[0079]

[0080] ;

[0081] In interpolation coefficients With multiphase factors Under equal conditions, the prototype filter Decomposed into Multiphase structure, the first Phase coefficient is Define the coefficients of a polyphase complex filter. ,in … ;

[0082] At sampling rate In the rate domain, the input signal Multiplying it by the low-frequency fundamental signal yields the premixed signal. Low-frequency fundamental frequency ,in express The closest integer;

[0083] premixed signal The input is fed into a multiphase complex interpolation filter bank for interpolation filtering. The filter coefficients for each phase are complex coefficients calculated offline and quantized. Output the interpolated samples of each phase and the samples after up-conversion. ;

[0084] Let the complex filter coefficients of each phase Then the first Phase output satisfies ,in ;

[0085] The output samples of each phase are combined into a sampling rate in order of phase number. The data stream completes the digital up-conversion.

[0086] In the embodiments of this application, the implementation of the multiphase complex interpolation filter bank is based on the interpolated sampling rate. With system clock frequency The size relationship is determined when: At that time, a serial multiphase filter structure with time-division multiplexed multipliers and delay units is adopted. Each multiplier operates at Convolution operations are performed at a low speed, with one multiplier operating at [speed value missing]. Premixing is completed at a certain speed; when At that time, a parallel multiphase filter structure is adopted, in which each phase independently uses delay units and multipliers. The branch circuits are synchronously outputting water.

[0087] In embodiments of this application, the complex filter coefficients and polyphase complex filter coefficients The phase compensation calculation is performed offline by the processor. After being quantized to a fixed-point format compatible with the hardware multiplier, it is downloaded to the phase coefficient registers or memory of the programmable logic terminal via the bus interface.

[0088] In the embodiments of this application, when the digital up-conversion link adopts Multiphase interpolation cascade with interpolation factors for each stage as follows: In this process, the mixer pre-processing method is applied iteratively step by step: starting from the last stage, the pre-processed mixer is combined with the polyphase interpolation filter of the previous stage and pre-processed again before the previous stage. The filter coefficients of this stage are multiplied by the new phase compensation factor accordingly. This process continues until the original high-speed domain mixer is pre-processed as a low-speed mixer in the lowest input rate domain. The phase compensation generated by each pre-processing stage is absorbed into the corresponding polyphase interpolation filter coefficients, or the low-speed mixer is retained before the selected intermediate stage.

[0089] In the embodiments of this application, during the step-by-step iterative preprocessing, the filter coefficients of each stage are recalculated and downloaded offline on the processor, and the iteration endpoint is flexibly selected according to the system flexibility and resource requirements to achieve multi-level collaborative optimization.

[0090] In embodiments of this application, the low-frequency fundamental signal is generated by a device operating at... The low-speed numerically controlled oscillator at a given rate is generated, or provided by a low-frequency fundamental frequency generation module, which is used to generate the low-frequency fundamental frequency in... The frequency generated at the speed is The complex fundamental wave.

[0091] In embodiments of this application, the prototype filter The original length is ;when no When the length is an integer multiple of the given length, zeros are added to the end to make the equivalent length after zero-padding. ,in ⌈ ⌉, to ensure that each phase branch has One tap.

[0092] In the embodiments of this application, when the carrier frequency is dynamically switched, only the low-frequency fundamental frequency needs to be updated through the bus interface. The corresponding numerically controlled oscillator frequency word and the complex coefficients of the polyphase filter This completes the carrier frequency. The dynamic switching is performed frame by frame, without affecting the pipeline processing of existing samples.

[0093] This application also discloses a multiphase interpolation and digital upconversion collaborative stream processing architecture, including: a coefficient generation and configuration module, used to generate and configure coefficients based on the target carrier frequency. and prototype filter Generate and distribute Phase complex filter coefficients Low-speed complex mixer, used in The rate domain will input signal With frequency Multiplying the complex fundamental frequency yields the premixed signal. ,in , express The closest integer; Phase complex interpolation filter bank, used to respectively use complex interpolation filter banks to respectively right Perform convolution and output ; and a sample synthesis module, used to synthesize samples according to phase sequence Phase output synthesized into sampling rate Data stream; where , , .

[0094] In the embodiments of this application, when ≤ At that time, the multiphase complex interpolation filter bank adopts a serial structure of time-division multiplexed multipliers and delay units; when At that time, a parallel structure with independently configured delay units and multipliers for each phase is adopted. The branch circuits are synchronously outputting water.

[0095] In the embodiments of this application, the coefficient generation and configuration module is located on the processor side and is used to calculate and quantize the coefficients of the multiphase complex filter offline, and download them to the phase coefficient registers or memory of the programmable logic side through the bus interface.

[0096] In the embodiments of this application, when the digital up-conversion link adopts When multiple phase interpolation stages are cascaded, the original high-speed domain mixer is pre-processed as a low-speed mixer in the selected input rate domain, and the phase compensation generated by each pre-processor stage is absorbed into the coefficients of the corresponding multiphase interpolation filter.

[0097] The following describes the specific implementation using a CPU+FPGA heterogeneous coherent signal source transmission link as an example. The system consists of three parts: PS-end (ARM) parameter configuration and filter coefficient calculation, PL-end (FPGA) polyphase interpolation and pre-mixer stream processing, and a JESD204B / C interface high-speed DAC. The complete link starts from the baseband signal input. Output of radio frequency analog signal.

[0098] (1) Overall parameter design. Based on the target carrier frequency Determine the interpolation factor based on the baseband signal bandwidth and DAC sampling rate. and multiphase factors (This invention takes) ), and the rate before interpolation Interpolated rate With FPGA system clock The size relationship determines whether to use a serial or parallel multiphase filter architecture.

[0099] (2) Prototype filter design. Design a real-coefficient low-pass FIR prototype filter using traditional methods. ,length for Integer multiples of (if not satisfied, pad with zeros to align) It meets frequency domain specifications such as passband ripple, stopband suppression, and transition bandwidth.

[0100] (3) Calculation of compensation factor and complex filter coefficients (completed offline at PS end). For the target carrier frequency... According to the formula Calculate the coefficients of the complex multiphase filter point by point ( The data is quantized to a fixed-point format compatible with the FPGA multiplier and downloaded to the phase coefficient registers / BRAM at the PL end via AXI-Lite or DMA.

[0101] (4) Implemented by a pre-amplifier low-speed mixer. At the PL end... Instantiate a low-speed complex mixer in the rate domain ,in The low-speed NCO can be implemented using a traditional DDS, or directly provided by the low-frequency fundamental wave module of the multiphase method in another invention, "High-Frequency Digital Carrier Signal Generation Method Based on Multiphase Parallel Structure".

[0102] (5) Implementation of a multiphase complex interpolation filter. Feed into multiphase complex interpolation filter bank :when At that time, a serial structure of a time-division multiplexed multiplier is adopted (see...). Figure 5 Each clock cycle switches one phase output. Multiple multipliers work together to perform convolution; when At that time, a parallel structure is adopted in which each phase uses its own delay unit and multiplier (see [link]). Figure 6 ), The branch synchronous flow output, the output of each phase is the interpolated and frequency-converted first phase. Phase point .

[0103] (6) Parallel-to-serial conversion and DAC interface. The outputs of each branch are combined in order of phase number to form the sampling rate. The data stream is fed into a high-speed DAC via a JESD204B / C or LVDS interface to generate the target RF carrier frequency. The simulated output.

[0104] (7) Step-by-step pre-interpolation of multi-level interpolation (optional). When the system adopts... During multi-phase interpolation, according to the step-by-step iterative pre-processing method of the present invention, starting from the last stage, the mixer coefficients combined with the multi-phase filter coefficients of the previous stage are further pre-processed; the filter coefficients of each stage are recalculated and downloaded offline at the PS end, and the iteration endpoint can be flexibly selected according to the system flexibility and resource requirements.

[0105] (8) Dynamic carrier frequency switching. Updates only require AXI-Lite. The corresponding low-speed NCO frequency words and complex coefficients of the polyphase filter This completes the carrier frequency. Dynamic switching; the process can be performed in frames without affecting the pipeline processing of existing samples.

[0106] (9) Indicator verification. Functional equivalence simulation and actual measurement were performed on the link before and after optimization to verify that the passband flatness, stopband suppression, SFDR, EVM and other indicators are consistent; at the same time, Vivado / synthesis tool was used to count the resource consumption of multipliers, adders, BRAM, DSP Slice and Fmax timing margin to confirm the quantitative benefits brought by the collaborative optimization.

[0107] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any way, and all technical solutions obtained by equivalent substitution or equivalent transformation fall within the protection scope of the present invention.

Claims

1. A method for multiphase interpolation and digital upconversion co-processing, characterized in that, Includes the following steps: Acquire input signal and prototype filter The length of the zero-padded filter Interpolation coefficients Multiples of integers, let ,in Determine the target carrier frequency based on the number of taps per phase. Sampling rate before interpolation and the interpolated sampling rate ; By leveraging the commutativity of complex multiplication and convolution operations, the mixer is moved from the interpolated high-speed domain to the pre-interpolated low-speed domain, and the complex filter coefficients are defined. , so that the output signal Satisfies identity transformation: ； In interpolation coefficients With multiphase factors Under equal conditions, the prototype filter Decomposed into Multiphase structure, the first Phase coefficient is Define the coefficients of a polyphase complex filter. ,in … ; At sampling rate In the rate domain, the input signal Multiplying it by the low-frequency fundamental signal yields the premixed signal. Low-frequency fundamental frequency ,in express The closest integer; premixed signal The input is fed into a multiphase complex interpolation filter bank for interpolation filtering. The filter coefficients for each phase are complex coefficients calculated offline and quantized. Output the interpolated samples of each phase and the samples after up-conversion. ; Let the complex filter coefficients of each phase Then the first Phase output satisfies ,in ; The output samples of each phase are combined into a sampling rate in order of phase number. The data stream completes the digital up-conversion.

2. The multiphase interpolation and digital upconversion collaborative flow processing method according to claim 1, characterized in that, The implementation of the multiphase complex interpolation filter bank is based on the sampling rate after interpolation. With system clock frequency The size relationship is determined when: At that time, a serial multiphase filter structure with time-division multiplexed multipliers and delay units is adopted. Each multiplier operates at Convolution operations are performed at a low speed, with one multiplier operating at [speed value missing]. Premixing is completed at a certain speed; when At that time, a parallel multiphase filter structure is adopted, in which each phase independently uses delay units and multipliers. The branch circuits are synchronously outputting water.

3. The multiphase interpolation and digital upconversion collaborative flow processing method according to claim 1, characterized in that, The complex filter coefficients and polyphase complex filter coefficients The phase compensation calculation is performed offline by the processor. After being quantized to a fixed-point format compatible with the hardware multiplier, it is downloaded to the phase coefficient registers or memory of the programmable logic terminal via the bus interface.

4. The multiphase interpolation and digital upconversion collaborative flow processing method according to claim 1, characterized in that, When the digital up-conversion link is adopted Multiphase interpolation cascade with interpolation factors for each stage as follows: In this process, the mixer pre-processing method is applied iteratively step by step: starting from the last stage, the pre-processed mixer is combined with the polyphase interpolation filter of the previous stage and pre-processed again before the previous stage. The filter coefficients of this stage are multiplied by the new phase compensation factor accordingly. This process continues until the original high-speed domain mixer is pre-processed as a low-speed mixer in the lowest input rate domain. The phase compensation generated by each pre-processing stage is absorbed into the corresponding polyphase interpolation filter coefficients, or the low-speed mixer is retained before the selected intermediate stage.

5. The multiphase interpolation and digital upconversion collaborative flow processing method according to claim 4, characterized in that, In the step-by-step iterative preprocessing, the filter coefficients of each stage are recalculated and downloaded offline on the processor. The iteration endpoint is flexibly selected according to the system flexibility and resource requirements to achieve multi-level collaborative optimization.

6. The multiphase interpolation and digital upconversion collaborative flow processing method according to claim 1, characterized in that, The low-frequency fundamental wave signal is operated by... The low-speed numerically controlled oscillator at a given rate is generated, or provided by a low-frequency fundamental frequency generation module, which is used to generate the low-frequency fundamental frequency in... The frequency generated at the speed is The complex fundamental wave.

7. The multiphase interpolation and digital upconversion collaborative flow processing method according to claim 1, characterized in that, The prototype filter The original length is ;when no When the length is an integer multiple of the given length, zeros are added to the end to make the equivalent length after zero-padding. ,in ⌈ ⌉, to ensure that each phase branch has One tap.

8. The multiphase interpolation and digital upconversion collaborative flow processing method according to claim 1, characterized in that, When the carrier frequency is dynamically switched, only the low-frequency fundamental frequency needs to be updated through the bus interface. The corresponding numerically controlled oscillator frequency word and the complex coefficients of the polyphase filter This completes the carrier frequency. The dynamic switching is performed frame by frame, without affecting the pipeline processing of existing samples.

9. A multiphase interpolation and digital upconversion collaborative stream processing architecture, characterized in that, include: The coefficient generation and configuration module is used to generate and configure coefficients based on the target carrier frequency. and prototype filter Generate and distribute Phase complex filter coefficients ; Low-speed complex mixer, used in The rate domain will input signal With frequency Multiplying the complex fundamental frequency yields the premixed signal. ,in , express The closest integer; Phase complex interpolation filter bank, used to respectively use complex interpolation filter banks to respectively right Perform convolution and output ; and a sample synthesis module, used to synthesize samples according to phase sequence Phase output synthesized into sampling rate Data stream; where , , .

10. The collaborative stream processing architecture according to claim 9, characterized in that, when ≤ At that time, the multiphase complex interpolation filter bank adopts a serial structure of time-division multiplexed multipliers and delay units; when At that time, a parallel structure with independently configured delay units and multipliers for each phase is adopted. The branch circuits are synchronously outputting water.

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