Self-test circuit and integrated circuit (IC) device

Abstract

The utility model provides a self-test circuit and an integrated circuit (IC) device. A self-test circuit includes: a first analog-to-digital converter (ADC) configured to be coupled to a respective one of first sensors; a first multiplexer (MUX) coupled to an output terminal of the first ADC; a second MUX configured to be coupled to a second sensor, the second sensor being a redundant sensor of the first sensor; a second ADC coupled to an output terminal of a second MUX, the first MUX and the second MUX being controlled by the select signal; a first checker circuit configured to compare first data at an output terminal of the first MUX with second data at an output terminal of the second ADC; and a plurality of switches coupled between respective ones of the input terminals of the second MUX and a reference voltage node.

Description

Technical Field

[0001] The present disclosure generally relates to self-test circuits for a device or system having multiple input channels with redundant sensors in the input channels. Background Art

[0002] Due to the strict safety requirements of automotive applications, redundancy is used for many key devices or systems. For example, in the transmission control unit of an automobile, the key block is the valve driver for driving the solenoid load, which is a typical load of the automatic transmission system. The accuracy of the current in the valve driver of the transmission control unit is greatly affected by temperature. The transmission control unit can be implemented as an integrated circuit (IC) device with multiple input channels and multiple output channels, with a thermal sensor in each input channel, and a valve driver (e.g., a high-side driver and a low-side driver) for driving the load in each output channel. The output of the thermal sensor in each input channel is used by a calibration algorithm (e.g., an interpolation algorithm) to remove the current error at different current levels. Since the thermal sensor should be protected from single-point failures due to the safety requirements of automotive applications, redundant thermal sensors are used in each input channel.

[0003] The transmission control unit is typically formed as an IC device to achieve high integration, low power consumption, and low cost. The IC device is tested in a manufacturing facility before being shipped to the customer, for example, using automatic test equipment (ATE). Throughout the life cycle of the IC device, periodic functional tests can be performed to ensure that the device is functioning properly. For an IC device having multiple redundant input channels (e.g., multiple input channels, each with a main sensor and a redundant sensor), testing all sensors in all input channels may be very time-consuming. In addition, in addition to testing sensors, it may be advantageous to test other components of the IC device (such as a multiplexer in the IC for selecting different input channels). There is a need in the art for a circuit that performs efficient self-testing on an IC having multiple input channels. Utility Model Content

[0004] In some embodiments, a self-test circuit includes: a first plurality of analog-to-digital converters ADC configured to be coupled to corresponding sensors in a first plurality of sensors; a first multiplexer MUX, wherein an input terminal of the first MUX is coupled to corresponding output terminals of the first plurality of ADCs; a second MUX, wherein an input terminal of the second MUX is configured to be coupled to corresponding sensors in a second plurality of sensors, wherein each sensor in the second plurality of sensors is a redundant sensor for a corresponding sensor in the first plurality of sensors; a second ADC coupled to an output terminal of the second MUX, wherein the first MUX and the second MUX are controlled by a selection signal; a first checker circuit, wherein a first input terminal of the first checker circuit is coupled to an output terminal of the first MUX, and a second input terminal of the first checker circuit is coupled to an output terminal of the second ADC, wherein the first checker circuit is configured to compare first data at a first input terminal of the first checker circuit with second data at a second input terminal of the first checker circuit; and a third plurality of switches coupled between corresponding ones of the input terminals of the second MUX and a reference voltage node.

[0005] For example, the first MUX and the second MUX are controlled by a selection signal so that during a self-test process of the self-test circuit, a first ADC output of a first sensor among the first plurality of sensors is output at an output terminal of the first MUX, and a second ADC output of a second sensor among the second plurality of sensors is output at an output terminal of the second ADC, wherein the second sensor is a redundant sensor of the first sensor.

[0006] For example, each switch of the third plurality of switches is controlled by a corresponding control signal having a first value or a second value, wherein the control signal having the first value is configured to close the switch and connect the corresponding input terminal of the second MUX to the reference voltage node, and wherein the control signal having the second value is configured to open the switch and disconnect the corresponding input terminal of the second MUX from the reference voltage node.

[0007] For example, the reference voltage node is configured to be connected to electrical ground.

[0008] For example, the self-test circuit further comprises a cycle counter, wherein the cycle counter is configured to repeatedly count from 0 to N-1, wherein N is the number of sensors in the first plurality of sensors, wherein during a self-test process of the self-test circuit, after a predetermined time period T has elapsed, an output of the cycle counter is incremented by one, wherein the output of the cycle counter is a selection signal.

[0009] For example, the self-test circuit also includes: a first counter, configured to generate a pulse after a predetermined time period N×T has passed; a second counter, configured to count the number of pulses generated by the first counter; and a decoder, coupled to the second counter, wherein the decoder is configured to generate a plurality of control signals based on an output of the second counter, wherein each of the plurality of control signals has a first value or a second value, wherein each of the plurality of control signals is configured to control a corresponding switch among a third plurality of switches.

[0010] For example, the second counter counts from 0 to N-1.

[0011] For example, the decoder is configured to, when the output of the second counter has the value m When m =0, 1, ..., or N-1: is the first ( m+1 ) control signals to assign a first value; and assign a second value to other control signals in the plurality of control signals.

[0012] For example, the second counter repeatedly counts from 0 to 1.

[0013] For example, the decoder is configured to: when the output signal of the second counter is zero, assign a first value and a second value to the odd-indexed control signals among the multiple control signals and the even-indexed control signals among the multiple signals, respectively; and when the output signal of the second counter is one, assign a second value and a first value to the odd-indexed control signals among the multiple control signals and the even-indexed control signals among the multiple signals, respectively.

[0014] For example, the decoder is configured to: assign a first value to the plurality of control signals when the output signal of the second counter is zero; and assign a second value to the plurality of control signals when the output signal of the second counter is one.

[0015] For example, the self-test circuit further includes a second checker circuit coupled to the first checker circuit, wherein the second checker circuit is configured to compare the output of the first checker circuit with an expected output of the first checker circuit.

[0016] In some embodiments, an integrated circuit IC device having multiple input channels includes: a first multiplexer MUX configured to receive a first output from a first plurality of analog-to-digital converters ADC coupled to a plurality of main sensors; a second MUX configured to receive a second output from a plurality of redundant sensors, wherein each redundant sensor of the plurality of redundant sensors and a corresponding main sensor of the plurality of main sensors are deployed in the same input channel of the plurality of input channels and are configured to sense the same physical phenomenon; a second ADC coupled to an output terminal of the second MUX; a first checker circuit configured to compare a first output of the first MUX with a second output of the second ADC, wherein during a self-test process of the integrated circuit IC device, the first MUX and the second MUX are configured to be synchronized so that the first output of the first MUX and the second output of the second ADC are digital samples from the same input channel; and a plurality of switches, wherein each of the plurality of switches is coupled between a corresponding input terminal of the second MUX and a reference voltage node.

[0017] For example, the integrated circuit IC device further includes a first plurality of ADCs.

[0018] For example, the reference voltage node is configured to be coupled to electrical ground, wherein each switch of the plurality of switches is configured to force a voltage at a corresponding input terminal of the second MUX to be electrical ground when closed.

[0019] For example, the integrated circuit IC device also includes: a circuit configured to generate a plurality of control signals for controlling corresponding switches of the plurality of switches, wherein the plurality of control signals have a first set of values ​​during a first time period and a second set of values ​​different from the first set of values ​​during a second time period; and a second checker circuit, wherein the second checker circuit is configured to receive an output of the first checker circuit during the first time period and the second time period, and is configured to compare the output of the first checker circuit with an expected output of the first checker circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the present disclosure will become apparent from the description and drawings, and from the claims. In the drawings, identical reference numerals (e.g., 101) or labels (e.g., "Sensor_0") generally represent identical components in various views, and for the sake of brevity, they will generally not be re-described. For a more complete understanding of the present disclosure, reference is now made to the following description in conjunction with the drawings, in which:

[0021] Figure 1 A block diagram of a system having multiple input channels with redundancy in an embodiment is illustrated.

[0022] Figure 2 The embodiment is shown in the figure Figure 1 A block diagram of the system, but with more details;

[0023] Figure 3 The embodiment is shown in the figure Figure 1 a block diagram of a portion of a system having details of a self-test circuit;

[0024] Figure 4 Another embodiment is shown Figure 1 a block diagram of a portion of a system with details of the self-test circuit; and

[0025] Figure 5 A flow chart of a method for testing a device having multiple input channels in an embodiment is illustrated. DETAILED DESCRIPTION

[0026] The making and use of the currently preferred embodiments are discussed in detail below. However, it should be appreciated that the present disclosure provides many applicable concepts that can be implemented in a variety of specific environments. The specific embodiments discussed are merely to illustrate the specific ways to make and use the present disclosure and do not limit the scope of the present disclosure.

[0027] The present disclosure will be described with reference to exemplary embodiments in a specific context, namely, a self-test circuit for a system having multiple input channels with redundancy.

[0028] Figure 1 FIG. 1 is a block diagram of a system 100 having multiple input channels with redundancy in an embodiment. The system 100 may be, for example, a transmission control unit of an automobile having multiple input channels, each of which has a thermal sensor. The system 100 may also have multiple output channels ( Figure 1 Not shown, but Figure 2 ), each output channel has a driver circuit (e.g., a high-side driver and a low-side driver) for driving a corresponding external load (e.g., a solenoid load). In some embodiments, the sensor (e.g., a main sensor and a redundant sensor) in each input channel is placed (e.g., formed) to be adjacent to the driver circuit of the corresponding output channel so as to measure the temperature of the driver circuit in the output channel. The interpolator uses the temperature measurement to generate an estimated error of the current of the driver circuit at the measured temperature. The estimated error indicates the deviation of the value of the current of the driver circuit from the target current value. The system 100 can then compensate for the estimated error in the current value so that the driver circuit of the output channel has a target current value. More details will be discussed below.

[0029] like Figure 1As shown in , system 100 includes multiple input channels (also may be referred to as channels or sensor channels), labeled as CH0, CH1, . . . and so on. Figure 1 The number of channels shown in is merely a non-limiting example, and any other suitable number of channels is possible and is fully intended to be included within the scope of the present disclosure.

[0030] Each channel of the system 100 includes a sensor (e.g., a thermal sensor), an analog-to-digital converter (ADC), and a redundant sensor (e.g., another thermal sensor used as a redundancy for the sensor). For example, channel CH0 has a sensor labeled Sensor_0, an ADC labeled ADC_0, and a redundant sensor labeled Sensor_RED_0. For ease of discussion and clarity, the sensors (e.g., Sensor_0, Sensor_1, ...) are also referred to as primary sensors in the discussion herein. In addition, the primary sensors (e.g., Sensor_0, Sensor_1, ...) and the redundant sensors (e.g., Sensor_RED_0, Sensor_RED_1, ...) are collectively referred to as sensors of the system 100.

[0031] In some embodiments, each sensor of the system 100 is used to sense a physical phenomenon having an analog value (e.g., temperature) and to generate an analog value (e.g., voltage) indicating (e.g., proportional to) the analog value of the measured physical phenomenon. In an embodiment, the sensor in the input channel of the system 100 is a thermal sensor for sensing temperature. The ADC in each input channel converts the output of the main sensor into a digital value. The ADC outputs from all ADCs in all input channels are sent to the main logic block 120 for further processing. The details of the processing performed by the main logic block 120 are discussed below.

[0032] The outputs of the redundant sensors in all input channels are sent to a block 110, which includes a multiplexer (MUX) and an ADC labeled ADC_RED (which may also be referred to as a redundant ADC). The outputs of the redundant sensors are sent to the input terminals of the MUX, and the redundant ADC is coupled to the output terminals of the MUX. The MUX in block 110 is controlled to select one of its input signals and output the selected input signal at the output terminal of the MUX. The redundant ADC then converts the selected input signal of the MUX into a digital value, which is sent to the main logic block 120 for further processing. In some embodiments, during normal operation of the system 100, if the main sensor in an input channel is determined to be defective, the MUX in block 110 may select the output of the corresponding redundant sensor in that input channel as the output of the MUX, and the output of the redundant ADC of block 110 may be used to replace the ADC output of the defective main sensor of that input channel.

[0033] Figure 2 In the embodiment shown Figure 1 100 , but with more details. For simplicity, Figure 2 Not all features of system 100 are shown. Figure 2 , the primary sensor in each channel is labeled as primary sensor 101 , the redundant sensor in each channel is labeled as redundant sensor 103 , and the ADC in each channel is labeled as ADC 105 . Figure 1 The box 110 in Figure 2 MUX 109 and Figure 2 The selection signal 108 of MUX 109 selects which input signal of MUX 109 is sent as the output of MUX 109. Note that MUX 109 accepts an analog input signal (eg, voltage) and outputs the selected analog signal, and therefore, may also be referred to as an analog MUX. Figure 2 As shown in FIG. 1 , the primary sensor 101 in each channel has a dedicated ADC 105 . In contrast, all redundant sensors 103 share a redundant ADC 107 by using a MUX 109 .

[0034] Still reference Figure 2 , the output of ADC 105 is sent to processing blocks 113 and 115. Figure 2 Further illustrated is a driver circuit for one of the output channels, which includes a high-side switch 121 and a low-side switch 123. The high-side switch 121 and the low-side switch 123 are coupled in series to a voltage source 125 (eg, having a voltage of +V DD The resistor 127 may be coupled between the low-side switch 123 and the reference voltage 126. To avoid confusion, Figure 2 Only one output channel is illustrated in FIG. 1 , but it is understood that a plurality of output channels are formed in the system 100 for driving a plurality of external loads.

[0035] exist Figure 2In the example of , for each output channel, the processing block 113 receives a temperature measurement from the main sensor 101 in the corresponding input channel and calculates an estimated current error (e.g., an estimated error in current) of the drive current of the high-side switch 121 at the measured temperature. The processing block 113 may include an interpolator that performs an interpolation operation to generate an estimated current error. For example, different current errors corresponding to different temperature values ​​may be predetermined (e.g., by simulation, calculation, or measurement) and stored in a lookup table (LUT). If the measured temperature matches one of the temperatures in the LUT, the corresponding current error in the LUT is used as the estimated current error. If the measured temperature does not match any temperature stored in the LUT, an interpolation operation (e.g., linear interpolation) is performed to generate an estimate of the current error for the measured temperature. Therefore, the processing block 113 (or 115) may also be referred to as an interpolator. In some embodiments, after calculating the estimated current error for each output channel, processing block 113 generates a drive current 114 (which has been corrected for the estimated current error) and feeds the drive current 114 to a control terminal 117 (eg, a gate terminal) of a high-side switch 121 in the output channel.

[0036] Processing block 115 performs the same processing as processing block 113 to calculate an estimated current error of the low-side driver 123 in each output channel and generate a drive current 116 for the low-side driver 123 in each output channel.

[0037] like Figure 2 As shown in FIG, a load 129 (e.g., a solenoid load) is coupled to an output terminal 128 of each output channel of the system 100, which is coupled to a node between the high-side switch 121 and the low-side switch 123. Note that the load 129 is shown to illustrate the operation of the system 100 and may not be considered part of the system 100.

[0038] Figure 2 Also illustrated are MUX 111 and self-test circuit 150. The output of ADC 105 is sent to the input terminal of MUX 111, and the output of MUX 111 is sent to self-test circuit 150. In addition, the output of redundant ADC 107 is also sent to self-test circuit 150. Self-test circuit 150 is configured to perform self-tests on sensors 101 / 103 and MUX 109 / MUX 111, details of which are discussed below. Note that MUX 111 is controlled by the same select signal 108 as MUX 109, such that during self-test, MUX 111 is synchronized with MUX 109 (e.g., selects a respective input signal from the same input channel as its respective output). In some embodiments, Figure 1The main logic block 120 includes a MUX 111, processing blocks 113 / 115, and a self-test circuit 150. In some embodiments, the main logic block 120 may additionally include a high-side switch 121 and a low-side switch 123.

[0039] Figure 3 The embodiment is shown in the figure Figure 1 A block diagram of a portion of a system 100 having Figure 2 Details of the self-test circuit 150. In some embodiments, Figure 2 The self-test circuit 150 and Figure 3 The circuit within the dashed box 153 and Figure 3 In some embodiments, Figure 3 Portions of the system 100 used in the self-test process and the electrical connections between the various components of the system 100 used in the self-test process are illustrated.

[0040] exist Figure 3 In the example, Figure 2 Each ADC (e.g., 105 or 107) in the system 100 is implemented as a Σ-Δ modulator (105A or 107A) followed by a conversion circuit (105B or 107B). The Σ-Δ modulator generates a one-bit data stream for its analog input signal. The conversion circuit includes (one or more) low-pass filters and (one or more) decimators (e.g., for reducing the sampling rate) for out-of-band noise suppression and for generating a multi-bit ADC output from the one-bit data stream. The Σ-Δ modulator and the corresponding conversion circuit are also collectively referred to as Σ-Δ ADC. Σ-Δ ADCs are known in the art and the details are not discussed here. Note that the Σ-Δ ADC is used as a non-limiting example of an ADC used in the system 100, and other types of ADCs may also be used in the system 100 as will be readily appreciated by those skilled in the art.

[0041] like Figure 3 As shown in , the output of the redundant sensor 103 in each input channel is coupled to a first load path terminal (e.g., drain terminal) of a corresponding switch 155 (e.g., N-MOS transistor), and a second load path terminal (e.g., source terminal) of the switch 155 is coupled to a reference voltage (e.g., electrical ground). The control terminal (e.g., gate terminal) of the switch 155 is coupled to a corresponding control signal (labeled as Ctrl_0, Ctrl_1, ..., or Ctrl_N-1) of each input channel.

[0042] The control signals Ctrl_0, Ctrl_1, ..., and Ctrl_N-1 are used during the self-test process to inject a fault condition into the corresponding redundant sensor 103. Details are discussed below. In the illustrated embodiment, for each input channel, when the control signal closes the switch 155 for that channel (e.g., by turning on a transistor used as a switch), the output terminal of the redundant sensor 103 is coupled to (e.g., directly coupled to) a reference voltage (e.g., electrical ground). This forces the output of the redundant sensor 103 (or equivalently, the corresponding input of the MUX 109) to have a zero voltage, thereby introducing or injecting a fault condition into the redundant sensor 103 in that channel. Conversely, when the control signal opens the switch 155 (e.g., by turning off the transistor), the output terminal of the redundant sensor 103 is decoupled (e.g., disconnected) from the reference voltage (e.g., electrical ground), and the redundant sensor 103 operates normally.

[0043] like Figure 3 As shown in FIG. 1 , the ADC output of the primary sensor 101 is sent to MUX 111, and the output of the redundant sensor 103 is sent to MUX 109. The output of MUX 109 is then converted into digital samples by a Σ-Δ ADC (e.g., Σ-Δ modulator 107A and conversion circuit 107B). Both MUX 111 and MUX 109 are controlled by a selection signal 108, so that MUX 111 is synchronized with the output of MUX 109. In other words, MUX 111 and MUX 109 select input signals from the same input channel (but from different sensors in the same input channel) as their respective outputs.

[0044] Figure 3 The cycle counter 131 in is used to generate the selection signal 108. In some embodiments, during the conversion period of the ADC (eg, Σ-Δ ADC), T After the elapse of time, the output of the cycle counter 131 is incremented by one, wherein the conversion period T is the time required by the ADC to convert the analog input signal into digital data. In some embodiments, the output of the cycle counter 131 changes repeatedly from 0 to N-1 and is used as the selection signal 108. For example, the output of the cycle counter 131 can start from zero and count to N-1. Then, in the next conversion period T After the time has elapsed, the output of the cycle counter 131 returns to zero, and the cycle counter 131 counts from zero to N-1 again. In some embodiments, the cycle counter 131 is responsive to the system clock signal. M The system clock signal is counted in cycles. M The duration of the clock cycle is equal to or greater than the conversion period T . In the system clock signal MAfter N clock cycles have passed, the output of loop counter 131 is incremented by one, or wraps around to zero if the previous output of loop counter 131 was N-1. Thus, in some embodiments, it takes N× T seconds or N× M The ADC outputs of the primary sensor 101 and the redundant sensor 103 of all N input channels are compared with each other within the duration of 1 system clock cycles.

[0045] The output of the MUX 111, which is the ADC output of the main sensor 101 in the selected channel, is sent to a first input terminal of a first checker 133 (also referred to as a first checker circuit or a first comparison circuit). And the output of the conversion circuit 107B, which is the ADC output of the redundant sensor 103 in the selected channel, is sent to a second input terminal of the first checker 133. The first checker 133 compares the digital data at the first input terminal with the digital data at the second input terminal. If there is a mismatch, an error flag is set for the corresponding selected channel.

[0046] exist Figure 3 In the example of N Output signals 134 are provided, each output signal 134 being used for one of the input channels. For example, if an error flag is set for an input channel, the output signal 134 for that input channel may have a value of 1, otherwise, the output signal 134 for that input channel may have a value of 0. As an example, a mismatch between two digital data at the first input terminal and the second input terminal of the first checker 133 may be defined as the two digital data being different, or may be defined as the difference between the two digital data being greater than a predetermined threshold (e.g., differing by more than one least significant bit (LSB)). The output signal 134 of the first checker 133 is sent to the second checker 139 for further processing, details of which are discussed below. The output signal 134 may also be stored in, for example, a memory area (such as a register map of a self-test circuit) for further processing.

[0047] exist Figure 3 In the embodiment shown in , the cycle counter 131 generates a control signal 106, which is sent to the first checker 133 to control (eg, enable) the operation of the first checker 133. In an embodiment, the control signal 106 is equivalent to delaying the conversion period T The delay between the control signal 106 and the select signal 108 ensures that the first checker 133 compares the ADC output only after the ADC conversion is completed.

[0048] Still reference Figure 3, the self-test circuit further includes a first counter 135, a second counter 137 and a decoder circuit 141. In some embodiments, after N× T duration, for example, when counting N× M After a system clock cycle, the first counter 135 generates a pulse (e.g., with a rising edge and a falling edge) at its output terminal. The second counter 137 counts the number of pulses generated by the first counter 135. The output of the second counter 137 is sent to the decoder circuit 141. The decoder circuit 141 generates a control signal 142 (e.g., Ctrl_0, Ctrl_1, ..., and Ctrl_N-1) at its output terminal according to the output of the second counter 137. In an embodiment, when the decoder circuit 141 receives the value from the second counter 137, i ( i =0, 1, 2... or N-1), the decoder circuit 141 will be used for the first ( i+1 ) input channels (labeled Ctrl_ i ) is set to one, and all other control signals 142 are set to zero. In some embodiments, the cycle counter 131, the first counter 135, and the second counter 137 are configured to be set to an initial value (e.g., zero) after power-on, after reset, or at the start of a self-test process. In some embodiments, the cycle counter 131, the first counter 135, and the second counter 137 are driven by the same system clock, so that the cycle counter 131 and the first counter 135 start counting at the same time (e.g., at the same system clock edge after the start of the self-test process).

[0049] In some embodiments, Figure 2 and Figure 3 The system 100 shown in FIG. 1 (excluding the load 129) is implemented as an integrated circuit (IC) device 100 formed on a semiconductor substrate (e.g., a silicon substrate). In some embodiments, the sensors (101 and 103) are not included in the IC device 100 to allow flexibility in the selection of external sensors used. In some embodiments, the sensors (101 and 103) and the power switches (121 and 123) are not included in the IC device 100 to provide additional flexibility in the selection of the power switches.

[0050] Now discuss the details about the self-test process. In some embodiments, the purpose of the self-test process is to check the main sensor 101 and the redundant sensor 103 in all input channels, and to check the MUX 109 and MUX 111 to detect component failures in the input channels. In the illustrated embodiment, the sensor is a thermal sensor, and the self-test is performed at a known temperature, such as room temperature, high temperature (higher than room temperature, such as 150°C), and low temperature (lower than room temperature, such as -40°C). Compare the ADC output of the main sensor in the same input channel with the ADC output of the redundant sensor. The mismatch of the ADC output indicates that the (one or more) components in the tested channel are defective. The self-test process can be performed as a quality control process during the manufacture of the equipment in the factory using automatic test equipment (ATE) to identify defective equipment, or can be performed periodically or on demand in the field (for example, after the equipment is deployed) to test the functionality of the equipment. Error detection or error reduction actions can be performed based on the results of the self-test process. For example, after identifying a faulty main sensor, a redundant sensor can be used to replace the faulty main sensor. As another example, if an input channel is determined to be defective, then depending on the application and safety requirements, the system 100 may perform self-test again at a later time to determine whether the error in the input channel is temporary, may stop driving the load at the corresponding output channel, or may instruct the system 100 to enter a safe mode once a defect is detected in the input channel.

[0051] In an embodiment, at the beginning of the self-test process, the cycle counter 131, the first counter 135 and the second counter 137 are reset to an initial value, such as zero. The first counter 135 is configured to count the N×N× T The total duration is counted and at each N× T After the duration of N×1 elapses, a pulse is generated, causing the output of the second counter 137 to increase from, for example, 0 to N-1 (and then wrap around to 0). Note that the output of the second counter 137 (or equivalently, the control signal 142) is incremented for each N×1. TThe duration of remains unchanged, which allows the loop counter 131 to sequentially select each of the N input channels for comparison by the first checker 133 while the control signal 142 remains unchanged. For example, at the beginning of the self-test process, the output value of the counter 137 is zero, and the decoder circuit 141 sets the control signal 142 (labeled as Ctrl_0) for the first input channel to one and sets all other control signals 142 to zero. Therefore, the switch 155 (e.g., an N-MOS transistor) connected to the first redundant sensor 103 (labeled as Sensor_RED_0) in the first input channel is turned on, thereby forcing the output of the first redundant sensor 103 to be zero (e.g., having zero voltage), while the other redundant sensors 103 operate normally (e.g., no fault condition is injected and have a non-zero output voltage corresponding to the measured temperature). The loop counter 131 sequentially selects the ADC outputs of the main sensor 101 and the redundant sensor 103 from one of the input channels for comparison by the first checker 133. Assuming that the primary sensor 101 and the redundant sensor 103 are not defective, the fault condition injected at the redundant sensor 103 of the first input channel causes a mismatch at the first checker 133, and the first checker 133 sets an error flag (e.g., sets a value of 1) for the output signal 134 corresponding to the first input channel. Since no fault condition is injected into the other input channels, the ADC outputs of the primary sensor 101 and the redundant sensor 103 from the other input channels should match, and the first checker 133 sets, for example, a value of 0 for the output signal corresponding to the other input channels.

[0052] In the first duration N× T Thereafter, the value of the output signal 134 may be represented by a row vector V1 of length N and may be represented by [1 0 0 ... 0], where the first element in the vector corresponds to the error flag for the first input channel, the second element in the vector corresponds to the error flag for the second input channel, and so on. Therefore, the value of the first element of the vector V1 is 1, and the values ​​of all other elements in the vector V1 are 0. In the next N× T During the duration, the decoder circuit 141 sets the control signal 142 for the second input channel to one and sets all other control signals 142 to zero, thereby injecting a fault condition in the second input channel (e.g., forcing the output of the redundant sensor Sensor_RED_1 to zero), while no fault condition is injected into other input channels. The loop counter 131 sequentially selects the ADC output from each input channel for comparison by the first checker 133, and the first checker 133 generates an output vector V2 of length N that can be represented by [0 1 0...0]. This process is repeated N times in total, so that in each N× TDuring the duration, only one of the control signals 142 is set to one, while the other control signals 142 are set to zero. The output row vectors V1, V2, ... VN can be stacked together to form a matrix M1 of size N x N. Note that when there is no defect in the primary sensor 101, the redundant sensor 103, or the MUX 109 / MUX 111, the matrix M1 is an identity matrix, where the values ​​of the diagonal elements of the matrix are 1, and the values ​​of all other elements are 0.

[0053] In some embodiments, the second checker 139 converts the output (eg, N×N× T The output signal 134 collected after the duration of, or equivalently, the output vector V1, V2 ... VN) is compared with the expected output. In some embodiments, the expected output is the identity matrix, and the second checker 139 stacks the output vectors V1, V2 ... VN generated by the first checker 133 into the matrix M1 and compares the matrix M1 with the identity matrix. If there is no mismatch between the two matrices, the second checker 139 declares that the self-test has passed and all sensors (e.g., 101 / 103) and multiplexers (e.g., 109 / 111) are working properly. If a particular column of the matrix M1 deviates from the expected value (e.g., the corresponding column of the identity matrix), then there is a defect in that input channel and the self-test fails. In other words, in some embodiments, in order to pass the self-test, the output signal 134 corresponding to the particular input channel should only set the error flag (e.g., have a value of 1) when a fault condition is injected into that input channel, and the error flag should not be set when no fault condition is injected into that input channel. In the illustrated embodiment, the output signal 151 generated by the second checker 139 has N different signals, each signal indicating whether a corresponding input channel has a defective component.

[0054] The matrix M1 formed by the output signals 134 can be used to provide more insight into the cause of a self-test failure. For example, if one of the redundant sensors in a particular channel is not functioning properly or its connecting network is open / shorted, then the self-test will fail even without an injected fault condition. A possible symptom of such a defective redundant sensor is that the error flag for the output signal 134 corresponding to this particular channel is set, regardless of the state of the switch 155 for that particular channel.

[0055] Reference above Figure 3 The self-test process described provides good coverage to detect defects in the circuit. The total time required to perform the self-test is N × N × T For example, for a system 100 having 10 input channels, the self-test process may take approximately 25 ms. Figure 4An alternative self-test circuit is provided which has a much shorter self-test time.

[0056] Figure 4 Another embodiment is shown Figure 1 A block diagram of a portion of the system, with details of the self-test circuitry. Figure 4 The circuit in Figure 3 The circuit in FIG. 1 is similar, but the second counter 137 is replaced by an even / odd selector 138. In some embodiments, each time the first counter 135 generates an output pulse (e.g., at each N× T After a duration of N× 1, the output of the even / odd selector 138 switches (e.g., alternates) between an even number (e.g., 0) and an odd number (e.g., 1). T The duration is even, and then in the subsequent N× T The even / odd selector 138 may be implemented as a one-bit counter that repeatedly counts between zero and one. For example, the one-bit counter counts from 0 to 1, then wraps around to 0 and counts to 1 again.

[0057] In some embodiments, Figure 4 The decoder circuit 141 sets the control signal 142 of the odd index (e.g., Ctrl_1, Ctrl_3, etc.) to 1, and sets the control signal 142 of the even index (e.g., Ctrl_0, Ctrl_2, etc.) to zero. In addition, when the output of the even / odd selector 138 is an even number, Figure 4 The decoder circuit 141 sets the odd-indexed control signal 142 to 0 and the even-indexed control signal 142 to 1. For example, after the self-test process starts, in the first N× T During the duration of N×, the output of even / odd selector 138 is zero (even). Therefore, assuming that there is no defective component in system 100, the output of redundant sensor 103 in the even-indexed input channel is forced to zero to introduce a fault condition, and the output signal 134 corresponding to the even-indexed input channel should set the error flag. TDuring the duration of , assuming that there are no defective components in the system 100, the output of the even / odd selector 138 is one (odd), and the output of the redundant sensor 103 in the odd-indexed input channel is forced to zero to introduce a fault condition, and the output signal 134 corresponding to the odd-indexed input channel should set an error flag. In other words, if the error flag of the output signal 134 corresponding to the odd-indexed channel is set when the output of the even / odd selector 138 is odd, and if the error flag of the output signal 134 corresponding to the even-indexed channel is set when the output of the even / odd selector 138 is even, then the self-test passes. Those skilled in the art will readily recognize that in alternative embodiments, the decoder 143 can set the odd-indexed control signal 142 and the even-indexed control signal 142 in a manner opposite to that described above, and the pass-fail criteria for the self-test should be adjusted accordingly. This modification is straightforward for those skilled in the art, so the details are not described here.

[0058] In another embodiment, when the output of the even / odd selector 138 has a first value (eg, an even value), Figure 4 The decoder circuit 141 sets all control signals 142 to one, and sets all control signals 142 to zero when the output of the even / odd selector 138 has a second value (e.g., an odd value). Therefore, when the even / odd selector 138 has a first value, a fault condition is injected into all input channels, and when the even / odd selector 138 has a second value, no fault condition is injected into any input channel. Thus, if the error flags for the output signals 134 of all input channels are set when the output of the even / odd selector 138 has a first value, and if the error flags for the output signals 134 of all input channels are not set when the output of the even / odd selector 138 has a second value, then the self-test passes.

[0059] Figure 4 The total self-test time of the system 100 is 2×N× T For the above example of a system 100 with 10 input channels, as an example, Figure 4 The self-test process can be reduced to about 5ms. Figure 4 The self-test process shortens the self-test time, but at the expense of the ability to detect defective components.

[0060] Figure 5 The flowchart of the method of testing a device with multiple input channels in an embodiment is illustrated. It should be appreciated that Figure 5The embodiment methods shown in are merely examples of many possible embodiment methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, or repeated. Figure 5 The steps shown in .

[0061] refer to Figure 5 , at block 1010, converting a first output of a primary sensor in a plurality of input channels into a first plurality of digital samples using a first plurality of analog-to-digital converters (ADCs), wherein each of the plurality of input channels has a primary sensor and a redundant sensor. At block 1020, injecting a fault condition at a redundant sensor in a first input channel of the plurality of input channels, wherein a second output of the redundant sensor in the plurality of input channels is coupled to an input terminal of a multiplexer (MUX). At block 1030, after the injection of the fault condition, converting the second output of the redundant sensor in the plurality of input channels into a second plurality of digital samples includes: sequentially selecting each of the second outputs of the redundant sensor as an output of the MUX; and converting each sequentially selected output of the MUX into a corresponding digital sample using a second ADC, wherein the digital samples of the sequentially selected output of the MUX form a second plurality of digital samples. At block 1040, comparing each of the first plurality of digital samples with a corresponding digital sample in a second plurality of digital samples from the same input channel using a first checker circuit.

[0062] Embodiments can achieve advantages. For example, the disclosed self-test circuit and method cover sensors (e.g., main sensors and redundant sensors) and multiplexers (e.g., analog MUX 109 and digital MUX 111), which may not be achievable for existing self-test methods. In addition, by analyzing the output of the first checker 133 and comparing the output of the first checker 133 with the expected output, the second checker 139 can not only detect defective components in different input channels, but also provide more granularity into the failure mechanism. Note that the disclosed self-test process can be performed without the need for an external control signal. Therefore, the self-test process can be performed in the background, for example, in parallel during the calibration process of the system 100. Therefore, in an embodiment where the calibration time is longer than the self-test time, the time used for the self-test process is invisible to the system because the self-test process runs in the background in parallel with the calibration process and is completed before the calibration process. This greatly reduces the ATE test time in the IC device test phase and reduces manufacturing costs.

[0063] Example embodiments of the present disclosure are summarized here. Other embodiments may also be understood from the entire specification and claims submitted herein.

[0064] Example 1. In an embodiment, a circuit includes: a first plurality of analog-to-digital converters (ADCs) configured to be coupled to corresponding sensors in a first plurality of sensors; a first multiplexer (MUX), wherein an input terminal of the first MUX is coupled to corresponding output terminals of the first plurality of ADCs; a second MUX, wherein an input terminal of the second MUX is configured to be coupled to corresponding sensors in a second plurality of sensors, wherein each sensor in the second plurality of sensors is a redundant sensor for a corresponding sensor in the first plurality of sensors; a second ADC coupled to an output terminal of the second MUX, wherein the first MUX and the second MUX are controlled by a selection signal; a first checker circuit, wherein a first input terminal of the first checker circuit is coupled to an output terminal of the first MUX, and a second input terminal of the first checker circuit is coupled to an output terminal of the second ADC, wherein the first checker circuit is configured to compare first data at a first input terminal of the first checker circuit with second data at a second input terminal of the first checker circuit; and a third plurality of switches coupled between corresponding ones of the input terminals of the second MUX and a reference voltage node.

[0065] Example 2. The circuit of Example 1, wherein the first MUX and the second MUX are controlled by a selection signal such that during a self-test process of the circuit, a first ADC output of a first sensor among the first plurality of sensors is output at an output terminal of the first MUX, and a second ADC output of a second sensor among the second plurality of sensors is output at an output terminal of the second ADC, wherein the second sensor is a redundant sensor of the first sensor.

[0066] Example 3. The circuit of Example 2, wherein each switch of the third plurality of switches is controlled by a corresponding control signal having a first value or a second value, wherein the control signal having the first value is configured to close the switch and connect the corresponding input terminal of the second MUX to a reference voltage node, and wherein the control signal having the second value is configured to open the switch and disconnect the corresponding input terminal of the second MUX from the reference voltage node.

[0067] Example 4. The circuit of Example 3, wherein the reference voltage node is configured to be connected to electrical ground.

[0068] Example 5. The circuit of Example 3, further comprising a loop counter, wherein the loop counter is configured to repeatedly count from 0 to N-1, where N is the number of sensors in the first plurality of sensors, wherein during a self-test process of the circuit, after a predetermined time period T has elapsed, an output of the loop counter is incremented by one, wherein the output of the loop counter is a selection signal.

[0069] Example 6. The circuit of Example 5 further includes: a first counter configured to generate a pulse after a predetermined time period N×T has passed; a second counter configured to count the number of pulses generated by the first counter; and a decoder coupled to the second counter, wherein the decoder is configured to generate a plurality of control signals based on an output of the second counter, wherein each of the plurality of control signals has a first value or a second value, wherein each of the plurality of control signals is configured to control a corresponding switch in a third plurality of switches.

[0070] Example 7. The circuit of Example 6, wherein the second counter counts from 0 to N-1.

[0071] Example 8. The circuit of Example 7, wherein the decoder is configured to, when the output of the second counter has a value m (in m =0, 1... or N-1): the first of multiple control signals ( m+1 ) assigns a first value to a control signal; and assigns a second value to other control signals in the plurality of control signals.

[0072] Example 9. The circuit of Example 6, wherein the second counter repeatedly counts from 0 to 1.

[0073] Example 10. The circuit of Example 9, wherein the decoder is configured to: when the output signal of the second counter is zero, assign a first value and a second value to a control signal with an odd index among the multiple control signals and a control signal with an even index among the multiple signals, respectively; and when the output signal of the second counter is one, assign a second value and a first value to a control signal with an odd index among the multiple control signals and a control signal with an even index among the multiple signals, respectively.

[0074] Example 11. The circuit of Example 9, wherein the decoder is configured to: assign a first value to the plurality of control signals when the output signal of the second counter is zero; and assign a second value to the plurality of control signals when the output signal of the second counter is one.

[0075] Example 12. The circuit of Example 6, further comprising a second checker circuit coupled to the first checker circuit, wherein the second checker circuit is configured to compare the output of the first checker circuit to an expected output of the first checker circuit.

[0076] Example 13. In an embodiment, an integrated circuit (IC) device having multiple input channels includes: a first multiplexer (MUX) configured to receive a first output from a first plurality of analog-to-digital converters (ADCs) coupled to a plurality of primary sensors; a second MUX configured to receive a second output from a plurality of redundant sensors, wherein each redundant sensor of the plurality of redundant sensors and a corresponding primary sensor of the plurality of primary sensors are disposed in a same input channel of the plurality of input channels and are configured to sense the same physical phenomenon; a second ADC coupled to an output terminal of the second MUX; a first checker circuit configured to compare a first output of the first MUX with a second output of the second ADC, wherein during a self-test process of the IC device, the first MUX and the second MUX are configured to be synchronized so that the first output of the first MUX and the second output of the second ADC are digital samples from the same input channel; and a plurality of switches, wherein each of the plurality of switches is coupled between a corresponding input terminal of the second MUX and a reference voltage node.

[0077] Example 14. The IC device of Example 13, further comprising a first plurality of ADCs.

[0078] Example 15. The IC device of Example 13, wherein the reference voltage node is configured to be coupled to electrical ground, wherein each switch of the plurality of switches is configured to force a voltage at a corresponding input terminal of the second MUX to electrical ground when closed.

[0079] Example 16. The IC device of Example 15, further comprising: a circuit configured to generate a plurality of control signals for controlling corresponding switches of a plurality of switches, wherein the plurality of control signals have a first set of values ​​during a first time period and a second set of values ​​different from the first set of values ​​during a second time period; and a second checker circuit, wherein the second checker circuit is configured to receive an output of the first checker circuit during the first time period and the second time period, and is configured to compare the output of the first checker circuit with an expected output of the first checker circuit.

[0080] Example 17. In an embodiment, a method of testing a device having multiple input channels includes: converting a first output of a primary sensor in the multiple input channels into a first plurality of digital samples using a first plurality of analog-to-digital converters (ADCs), wherein each of the multiple input channels has a primary sensor and a redundant sensor; injecting a fault condition at a redundant sensor in a first input channel of the multiple input channels, wherein a second output of the redundant sensor in the multiple input channels is coupled to an input terminal of a multiplexer (MUX); and converting the second output of the redundant sensor in the multiple input channels into a second plurality of digital samples after the fault condition is injected, including: sequentially selecting each of the second outputs of the redundant sensors as an output of the MUX; and converting each sequentially selected output of the MUX into a corresponding digital sample using a second ADC, wherein the digital samples of the sequentially selected output of the MUX form a second plurality of digital samples. The method also includes comparing each of the first plurality of digital samples with a corresponding digital sample in a second plurality of digital samples from the same input channel using a first checker circuit.

[0081] Example 18. The method of Example 17, further comprising, in response to detecting a mismatch between the first plurality of digital samples and the second plurality of digital samples, setting, by the first checker circuit, an error flag for the input channel having the mismatch.

[0082] Example 19. The method of Example 18, further comprising comparing, using a second checker circuit, an output of the first checker circuit to an expected output of the first checker circuit.

[0083] Example 20. The method of Example 17, further comprising, after comparing each digital sample in the first plurality of digital samples with a corresponding digital sample in the second plurality of digital samples: injecting another fault condition at a redundant sensor in a second input channel of the plurality of input channels; after injecting the another fault condition, converting a second output of the redundant sensor in the plurality of input channels into a third plurality of digital samples; and comparing each digital sample in the first plurality of digital samples with a corresponding digital sample in the third plurality of digital samples from the same input channel using a first checker circuit.

[0084] Although the present disclosure has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. With reference to this description, various modifications and combinations of the illustrative embodiments and other embodiments of the present disclosure will be apparent to those skilled in the art. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A self-test circuit, characterized in that: The self-test circuit comprises: a first plurality of analog-to-digital converters ADC configured to be coupled to respective sensors of the first plurality of sensors; a first multiplexer MUX, wherein input terminals of the first MUX are coupled to respective output terminals of the first plurality of ADCs; a second MUX, wherein input terminals of the second MUX are configured to be coupled to corresponding sensors of a second plurality of sensors, wherein each sensor of the second plurality of sensors is a redundant sensor for a corresponding sensor of the first plurality of sensors; a second ADC coupled to an output terminal of a second MUX, wherein the first MUX and the second MUX are controlled by a selection signal; a first checker circuit, wherein a first input terminal of the first checker circuit is coupled to an output terminal of the first MUX, and a second input terminal of the first checker circuit is coupled to an output terminal of the second ADC, wherein the first checker circuit is configured to compare first data at the first input terminal of the first checker circuit with second data at the second input terminal of the first checker circuit; and A third plurality of switches are coupled between corresponding ones of the input terminals of the second MUX and a reference voltage node.

2. The self-test circuit of claim 1 , wherein the first MUX and the second MUX are controlled by a selection signal so that during a self-test process of the self-test circuit, a first ADC output of a first sensor among the first plurality of sensors is output at an output terminal of the first MUX, and a second ADC output of a second sensor among the second plurality of sensors is output at an output terminal of the second ADC, wherein the second sensor is a redundant sensor of the first sensor.

3. The self-test circuit of claim 2 , wherein each switch of the third plurality of switches is controlled by a corresponding control signal having a first value or a second value, wherein the control signal having the first value is configured to close the switch and connect the corresponding input terminal of the second MUX to a reference voltage node, and wherein the control signal having the second value is configured to open the switch and disconnect the corresponding input terminal of the second MUX from the reference voltage node.

4. The self-test circuit of claim 3, wherein the reference voltage node is configured to be connected to electrical ground.

5. The self-test circuit of claim 3 , further comprising a cycle counter, wherein the cycle counter is configured to repeatedly count from 0 to N-1, wherein N is the number of sensors in the first plurality of sensors, wherein during a self-test process of the self-test circuit, after a predetermined time period T has elapsed, an output of the cycle counter is incremented by one, wherein the output of the cycle counter is a selection signal.

6. The self-test circuit of claim 5 , further comprising: a first counter configured to generate a pulse after a predetermined time period N×T has elapsed; a second counter configured to count the number of pulses generated by the first counter; as well as A decoder is coupled to the second counter, wherein the decoder is configured to generate a plurality of control signals based on an output of the second counter, wherein each control signal of the plurality of control signals has a first value or a second value, wherein each control signal of the plurality of control signals is configured to control a corresponding switch of the third plurality of switches.

7. The self-test circuit of claim 6, wherein the second counter counts from 0 to N-1.

8. The self-test circuit of claim 7 , wherein the decoder is configured to, when the output of the second counter has a value m When m =0, 1, ..., or N-1: is the first ( m+1 ) a control signal assigning a first value; and Other control signals in the plurality of control signals are assigned second values.

9. The self-test circuit of claim 6, wherein the second counter repeatedly counts from 0 to 1.

10. The self-test circuit of claim 9, wherein the decoder is configured to: assigning a first value and a second value to an odd-indexed control signal of the plurality of control signals and an even-indexed control signal of the plurality of signals, respectively, when the output signal of the second counter is zero; and When the output signal of the second counter is one, odd-indexed control signals among the plurality of control signals and even-indexed control signals among the plurality of signals are assigned a second value and a first value, respectively.

11. The self-test circuit of claim 9, wherein the decoder is configured to: assigning a first value to the plurality of control signals when the output signal of the second counter is zero; and When the output signal of the second counter is one, the plurality of control signals are assigned a second value.

12. The self-test circuit of claim 6, further comprising a second checker circuit coupled to the first checker circuit, wherein the second checker circuit is configured to compare the output of the first checker circuit with an expected output of the first checker circuit.

13. An integrated circuit IC device, characterized in that: The integrated circuit IC device has a plurality of input channels, and the integrated circuit IC device comprises: a first multiplexer MUX configured to receive first outputs from a first plurality of analog-to-digital converters ADC coupled to the plurality of primary sensors; a second MUX configured to receive a second output from a plurality of redundant sensors, wherein each redundant sensor of the plurality of redundant sensors and a corresponding primary sensor of the plurality of primary sensors are disposed in a same input channel of the plurality of input channels and are configured to sense a same physical phenomenon; a second ADC coupled to an output terminal of the second MUX; a first checker circuit configured to compare a first output of the first MUX with a second output of the second ADC, wherein during a self-test process of the integrated circuit IC device, the first MUX and the second MUX are configured to be synchronized so that the first output of the first MUX and the second output of the second ADC are digital samples from the same input channel; and A plurality of switches, wherein each switch of the plurality of switches is coupled between a corresponding input terminal of the second MUX and a reference voltage node.

14. The integrated circuit (IC) device of claim 13, further comprising a first plurality of ADCs.

15. The integrated circuit (IC) device of claim 13, wherein the reference voltage node is configured to be coupled to electrical ground, wherein each switch of the plurality of switches is configured to force a voltage at a corresponding input terminal of the second MUX to be electrical ground when closed.

16. The integrated circuit IC device of claim 15, further comprising: circuitry configured to generate a plurality of control signals for controlling respective switches of the plurality of switches, wherein the plurality of control signals have a first set of values ​​during a first time period and a second set of values ​​different from the first set of values ​​during a second time period; as well as A second checker circuit, wherein the second checker circuit is configured to receive an output of the first checker circuit during a first time period and a second time period and is configured to compare the output of the first checker circuit to an expected output of the first checker circuit.

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