Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device. The display substrate comprises a driving structure layer and a light-emitting structure layer which are arranged on a substrate, the driving structure layer comprises a plurality of circuit repeating units, and the light-emitting structure layer comprises a plurality of first light-emitting devices; the circuit repeating unit comprises M first circuit units and one second circuit unit, each first circuit unit at least comprises a first pixel driving circuit, the first pixel driving circuit is connected with the first light-emitting device, the second circuit unit at least comprises a second pixel driving circuit, and the second pixel driving circuit is not connected with the first light-emitting device; the driving structure layer further comprises a first insertion line, a second insertion line and a power connecting line, the second insertion line is connected with the data signal line through the first insertion line, the power connecting line is connected with the first power line, the second insertion line is arranged in the first circuit unit, and the power connecting line is arranged in the second circuit unit. The circuit difference between the first circuit unit and the second circuit unit can be reduced.

Description

Technical Field

[0001] The present invention relates to but is not limited to the field of display technology, and specifically to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] Currently, existing OLED display devices have problems such as circuit differences. Utility Model Content

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the present disclosure is to provide a display substrate and a display device to solve the problems such as circuit differences in existing display devices.

[0006] On the one hand, the present disclosure provides a display substrate, including a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate; the driving structure layer includes a plurality of circuit repetition units, and the light-emitting structure layer includes a plurality of first light-emitting devices; at least one circuit repetition unit includes M first circuit units and 1 second circuit unit, M is a positive integer greater than or equal to 3, the first circuit unit includes at least a first pixel driving circuit, the first pixel driving circuit is respectively connected to a data signal line, a first power line and the first light-emitting device, the second circuit unit includes at least a second pixel driving circuit, the second pixel driving circuit is respectively connected to the data signal line and the first power line, but is not connected to the first light-emitting device; the driving structure layer also includes at least one first insertion line extending along a first direction, at least one second insertion line extending along a second direction, and at least one power connection line extending along the second direction, the first direction and the second direction intersect; the second insertion line is connected to the data signal line through the first insertion line, the power connection line is connected to the first power line, the second insertion line is arranged in the first circuit unit, and the power connection line is arranged in the second circuit unit.

[0007] In an exemplary embodiment, M is equal to four.

[0008] In an exemplary embodiment, at least one first insertion line includes a first data connection line and a first power line arranged in sequence along the first direction, and a first break is arranged between the first data connection line and the first power line; at least one second insertion line includes a second data connection line and a second power line arranged in sequence along the second direction, and a second break is arranged between the second data connection line and the second power line; the second data connection line is connected to the data signal line through the first data connection line.

[0009] In an exemplary embodiment, an orthographic projection of at least one first break on the display substrate plane at least partially overlaps with an orthographic projection of the first power line on the display substrate plane, and / or an orthographic projection of at least one second break on the display substrate plane at least partially overlaps with an orthographic projection of the first power line on the display substrate plane.

[0010] In an exemplary embodiment, in at least one second circuit unit, the power connection line is connected to the first power routing line to form a mesh connection structure.

[0011] In an exemplary embodiment, at least one first circuit unit further includes a data connection block, and the second data connection line is connected to the first data connection line through the data connection block; at least one first circuit unit further includes a dummy connection block, and the second power line is connected to the dummy connection block; the position and shape of the data connection block in one first circuit unit are the same as the position and shape of the dummy connection block in another first circuit unit.

[0012] In an exemplary embodiment, the first pixel driving circuit and the second pixel driving circuit each include at least a storage capacitor, a first initialization transistor and a first light emission control transistor, the first electrode of the first initialization transistor is connected to the fifth connection electrode, the second electrode of the first initialization transistor is connected to the first electrode plate of the storage capacitor through the first connection electrode, and the first electrode of the first light emission control transistor is connected to the second electrode plate of the storage capacitor through the third connection electrode; in at least one first circuit unit, the first connection electrode, the third connection electrode and the fifth connection electrode are arranged in isolation; in at least one second circuit unit, the first connection electrode is respectively connected to the third connection electrode and the fifth connection electrode to form the power connection line.

[0013] In an exemplary embodiment, the first power line is connected to the third connection electrode.

[0014] In an exemplary embodiment, the first circuit unit and the second circuit unit both include a first initial signal line extending along the first direction; in at least one first circuit unit, the fifth connecting electrode is respectively connected to the first electrode of the first initialization transistor and the first initial signal line; in at least one second circuit unit, the fifth connecting electrode is connected to the first electrode of the first initialization transistor and is not connected to the first initial signal line.

[0015] In an exemplary embodiment, in at least one second circuit unit, the data signal line is connected to the first power line.

[0016] In an exemplary embodiment, the display substrate includes a display area, a binding area located on one side of the display area, and a frame area located on the other side of the display area, the display area includes at least a first display area and a second display area, the first display area at least partially surrounds the second display area, the first display area is configured to display images, and the second display area is configured to display images and transmit light; the driving structure layer of the first display area includes a plurality of circuit repeating units, and the light-emitting structure layer of the first display area includes a plurality of first light-emitting devices.

[0017] In an exemplary embodiment, at least one circuit repetition unit includes M first circuit units and 1 third circuit unit, and at least one third circuit unit includes at least a third pixel driving circuit; the light-emitting structure layer of the second display area includes a plurality of second light-emitting devices, and the third pixel driving circuit is connected to the second light-emitting device.

[0018] In an exemplary embodiment, the driving structure layer includes at least a first source-drain metal layer, a second source-drain metal layer arranged on a side of the first source-drain metal layer away from the substrate, and a third source-drain metal layer arranged on a side of the second source-drain metal layer away from the substrate; the power connection line and the first insertion line are arranged in the first source-drain metal layer, the first power line is arranged in the second source-drain metal layer, and the data signal line and the second insertion line are arranged in the third source-drain metal layer.

[0019] In an exemplary embodiment, the border area at least includes an upper border area located on a side of the display area away from the binding area, the upper border area includes a plurality of dummy repeating units, at least one dummy repeating unit includes M first dummy units and 1 second dummy unit, the first dummy unit includes at least a first dummy pixel circuit, the second dummy unit includes at least a second dummy pixel circuit, and neither the first dummy pixel circuit nor the second dummy pixel circuit is connected to the light-emitting device; the driving structure layer also includes a passivation layer arranged between the first source and drain metal layer and the second source and drain metal layer, and in at least one first dummy unit, at least one via is arranged on the passivation layer to connect the first source and drain metal layer with the second source and drain metal layer; in at least one second dummy unit, no via is arranged on the passivation layer.

[0020] In an exemplary embodiment, at least one first dummy cell is provided with the second source-drain metal layer, and at least one second dummy cell is not provided with the second source-drain metal layer.

[0021] In an exemplary embodiment, at least one power connection line is connected to a binding power trace of the binding area, and the binding power trace is configured to transmit a first power signal.

[0022] In an exemplary embodiment, at least one power connection line is connected to a frame power trace of the frame area, and the frame power trace is configured to transmit a first power signal.

[0023] In an exemplary embodiment, at least one second insertion line includes a second power trace, the second power trace is connected to a power lead of the frame area or the binding area, and the power lead is configured to transmit a second power signal.

[0024] On the other hand, the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0025] The present disclosure provides a display substrate and a display device. By setting a second insertion line in a first circuit unit and a power connection line in a second circuit unit, the circuit difference between the first circuit unit and the second circuit unit can be reduced, the load difference of the data signal caused by the circuit difference can be avoided, and the display quality is improved.

[0026] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0028] Figure 1 is a structural schematic diagram of a display device;

[0029] Figure 2 It is a structural schematic diagram of a display substrate;

[0030] Figure 3 is a schematic diagram of a planar structure of a first display area in a display area;

[0031] Figure 4 is a schematic diagram of a cross-sectional structure of a first display area in a display region;

[0032] Figure 5 is an equivalent circuit diagram of a pixel driving circuit;

[0033] Figure 6 It is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] Figure 7 The structure of the circuit repeating unit of the embodiment of the present disclosure;

[0035] Figure 8 is the structure of the light-emitting repeating unit of the embodiment of the present disclosure;

[0036] Fig. 9 This is a schematic diagram of the connection between a pixel driving circuit and a light-emitting device according to an embodiment of the present disclosure;

[0037] Fig.10 It is a structural schematic diagram of an insertion line of an exemplary embodiment of the present disclosure;

[0038] Fig.11 A schematic structural diagram of a first display area of ​​an exemplary embodiment of the present disclosure;

[0039] Fig.12 This is a schematic diagram of the structure of the first insertion line and the second insertion line according to an embodiment of the present disclosure;

[0040] Fig.13 It is a schematic diagram of a semiconductor layer pattern formed according to an embodiment of the present disclosure;

[0041] Fig.14A and Fig. 14B It is a schematic diagram after forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0042] Fig.15A and Fig. 15B It is a schematic diagram after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0043] Fig.16 It is a schematic diagram after forming a fourth insulating layer pattern according to an embodiment of the present disclosure;

[0044] Fig.17A and Fig. 17B It is a schematic diagram after forming a third conductive layer pattern according to an embodiment of the present disclosure;

[0045] Fig. 17C It is a plan view of the third conductive layer at the junction of the display area and the binding area;

[0046] Fig.17D It is a plan view of the third conductive layer at the junction of the display area and the upper frame area;

[0047] Fig.18 It is a schematic diagram after forming the fifth insulating layer and the first planar layer pattern according to the embodiment of the present disclosure;

[0048] Fig.19A and Fig.19B It is a schematic diagram after forming a fourth conductive layer pattern according to an embodiment of the present disclosure;

[0049] Fig.19C A schematic plan view of the fourth conductive layer at the junction of the display area and the upper frame area;

[0050] Fig. 20 It is a schematic diagram after forming a second planar layer pattern according to an embodiment of the present disclosure;

[0051] Fig.21A and Fig.21B It is a schematic diagram after forming the fifth conductive layer pattern according to the embodiment of the present disclosure.

[0052] Description of reference numerals:

[0053] 11—first active layer; 12—second active layer; 13—third active layer;

[0054] 14—fourth active layer; 15—fifth active layer; 16—sixth active layer;

[0055] 17—seventh active layer; 21—first scanning signal line; 22—second scanning signal line;

[0056] 23—luminous signal line; 31—first electrode plate; 32—second electrode plate;

[0057] 33—opening; 34—plate connection bar; 41—first initial signal line;

[0058] 42—second initial signal line; 43—first shielding electrode; 44—second shielding electrode;

[0059] 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode;

[0060] 54—fourth connecting electrode; 55—fifth connecting electrode; 56—sixth connecting electrode;

[0061] 61—eleventh connecting electrode; 62—twelfth connecting electrode; 63—thirteenth connecting electrode;

[0062] 64—fourteenth connecting electrode; 70—power connection line; 71—first power line;

[0063] 72—data signal line; 73—first data connection electrode; 74—first anode connection electrode;

[0064] 75—second data connection electrode; 76—second anode connection electrode; 77—dummy electrode;

[0065] 81—first data connection line; 82—second data connection line; 83—data connection bar;

[0066] 84—data connection block; 91—first power supply wiring; 92—second power supply wiring;

[0067] 93—virtual connection bar; 94—virtual connection block; 100—display area;

[0068] 101 - substrate; 102 - driving structure layer; 103 - light emitting structure layer;

[0069] 104—package structure layer; 200—binding area; 201—lead-out area;

[0070] 202—bending area; 210—binding power supply wiring; 300—border area;

[0071] 310—Frame power routing. DETAILED DESCRIPTION

[0072] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0073] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0074] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0075] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0076] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0077] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0078] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0079] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0080] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0081] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0082] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not strictly defined, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc., and may have some small deformations caused by tolerances, chamfers, curved edges and deformations, etc. "About" in this disclosure means that the limits are not strictly defined, and the values ​​within the range of process and measurement errors are allowed.

[0083] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal suitable for the specification of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specification of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0084] For products such as smart terminals, it is usually necessary to set up hardware such as front cameras, fingerprint sensors or light sensors. In order to increase the screen-to-body ratio, display devices usually use a method of opening holes on the display substrate to form an under-display camera area (UDC) using the openings, and place sensors such as cameras in the under-display camera area of ​​the display substrate to achieve full display with camera (FDC) technology. The under-display camera area not only has a certain transmittance, but also has a display function.

[0085] Figure 2 Schematic diagram of the structure of a display substrate. Figure 2 As shown, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area, including a plurality of sub-pixels Pxij constituting a pixel array, and the plurality of sub-pixels Pxij are configured to display dynamic pictures or still images, and the display area 100 may be referred to as an active area (ActiveArea, referred to as AA). In an exemplary embodiment, the display substrate may be a flexible substrate, so that the display substrate may be deformable, such as curling, bending, folding or rolling up.

[0086] In an exemplary embodiment, the display area 100 may include at least a first display area 110 and a second display area 120, and the first display area 110 may at least partially surround the second display area 120. The first display area 110 is configured to display an image and may be referred to as a normal display area. The second display area 120 is configured to display an image and transmit light, and the transmitted light is received by an optical device, and may be referred to as an under-screen camera display area or a light-transmitting display area, and the position of the second display area 120 may correspond to the position of the optical device.

[0087] In an exemplary embodiment, the binding area 200 may include a lead area 201, a bending area 202, a driver chip area and a binding pin area arranged in sequence along a direction away from the display area, and the lead area 201 is connected to the display area 100 and includes at least a data lead. The bending area 202 is connected to the lead area 201 and may include at least a composite insulating layer provided with a groove, and the groove is configured to bend the binding area to the back of the display area. The driver chip area may include an integrated circuit (IC), which is configured to be connected to a plurality of data lead lines. The binding pin area may include a binding pad (Bonding Pad), which is configured to be bound and connected to an external flexible printed circuit (Flexible Printed Circuit, FPC).

[0088] In an exemplary embodiment, the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100. The circuit area is connected to the display area 100 and may include at least a gate drive circuit, which is connected to the scanning signal line and the light-emitting signal line in the display area 100. The power line area is connected to the circuit area and may include at least a frame power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100. The crack dam area is connected to the power line area and may include at least a plurality of cracks arranged on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least a cutting groove arranged on the composite insulating layer, and the cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment cuts along the cutting groove respectively.

[0089] In an exemplary embodiment, the lead line area in the binding area 200 and the power line area in the border area 300 may be provided with an isolation dam, which may extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100, and the edge of the display area is the edge of one side of the display area binding area or the border area.

[0090] Figure 3 FIG. 1 is a schematic diagram of a planar structure of a first display area in a display area. Figure 3 As shown, the first display area may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal line, the light-emitting signal line, and the data signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0091] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 and the fourth sub-pixel P4 may be green sub-pixels (G) emitting green light, and the third sub-pixel P3 may be a blue sub-pixel (B) emitting blue light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the four sub-pixels may be arranged in an RGBG manner.

[0092] In other exemplary embodiments, the pixel unit P may include three sub-pixels, and the three sub-pixels may be arranged in parallel horizontally or vertically, etc., which is not limited in the present disclosure.

[0093] Figure 4 FIG. 1 is a schematic diagram of a cross-sectional structure of a first display area in a display region. Figure 4 As shown, on a plane perpendicular to the display substrate, the first display area may include a driving structure layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the first display area may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.

[0094] In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, and the light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0095] Figure 5 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Figure 5 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 7 signal lines (first scanning signal line S1, second scanning signal line S2, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, data signal line DATA and first power line VDD).

[0096] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is respectively connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, the second node N2 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, and the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0097] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1, and a second end of the storage capacitor C is connected to the first power line VDD.

[0098] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the second scan signal line S2 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor is connected to the first node N1 .

[0099] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first scan signal line S1 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0100] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0101] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1 , a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0102] In an exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0103] In an exemplary embodiment, a gate electrode of the sixth transistor T6 is connected to the light emitting signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3 , and a second electrode of the sixth transistor T6 is connected to the fourth node N4 .

[0104] In an exemplary embodiment, a gate electrode of the seventh transistor T7 is connected to the first scan signal line S1 , a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2 , and a second electrode of the seventh transistor T7 is connected to the fourth node N4 .

[0105] In an exemplary embodiment, a first electrode of the light emitting device EL is connected to the fourth node N4, and a second electrode of the light emitting device EL is connected to the second power supply line VSS. The light emitting device EL may be an OLED including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode).

[0106] In an exemplary embodiment, the first power line VDD is configured to provide a constant first power signal to the pixel driving circuit, the second power line VSS is configured to provide a constant second power signal to the light emitting device, and the first power signal is a high level signal, and the second power signal is a low level signal. The first initial voltage signal and the second initial voltage signal may be constant voltage signals, which is not limited in the present disclosure.

[0107] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 in the pixel driving circuit may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0108] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS for short), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current. The low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0109] With the development of display technology, consumers have higher and higher requirements for the display effect and display quality of display products. Products such as full screen and narrow bezel have gradually become the development trend of display products with their large screen-to-body ratio and ultra-narrow bezel. Therefore, the narrowing of the bezel or even the bezel-free design has been paid more and more attention in the design of OLED display products. In a display substrate, since the data signal of the integrated circuit in the binding area needs to be introduced into the wider display area through the data lead-out line in a fan-out manner, the lead-out line area occupies a large space, resulting in a larger width of the lower bezel. In addition, since the gate drive circuit and power lead need to be set in the bezel area, and the gate drive circuit and power lead occupy a large space, the width of the left and right bezels is large.

[0110] In order to reduce the width of the lower frame, the exemplary embodiment of the present disclosure provides a display substrate, which adopts a fanout in panel (FIP) structure, a plurality of data connection lines are arranged in the display area, one end of the plurality of data connection lines is correspondingly connected to the plurality of data signal lines in the display area, and the other end of the plurality of data connection lines extends to the binding area, and is correspondingly connected to the integrated circuit through the plurality of lead wires in the lead wire area. Since the lead wire area does not need to be provided with fan-shaped oblique lines, the width of the lead wire area is reduced, thereby reducing the width of the lower frame.

[0111] An exemplary embodiment of the present disclosure provides a display substrate, comprising a driving structure layer disposed on a substrate and a light emitting structure layer disposed on a side of the driving structure layer away from the substrate; the driving structure layer comprises a plurality of circuit repetition units, and the light emitting structure layer comprises a plurality of first light emitting devices; at least one circuit repetition unit comprises M first circuit units and 1 second circuit unit, M being a positive integer greater than or equal to 3, the first circuit unit comprises at least a first pixel driving circuit, the first pixel driving circuit is respectively connected to a data signal line, a first power line and the first light emitting device, the second circuit unit comprises at least a second pixel driving circuit, the second pixel driving circuit is respectively connected to the data signal line and the first power line, but is not connected to the first light emitting device; the driving structure layer further comprises at least one first insertion line extending along a first direction, at least one second insertion line extending along a second direction, and at least one power connection line extending along the second direction, the first direction and the second direction intersect; the second insertion line is connected to the data signal line through the first insertion line, the power connection line is connected to the first power line, the second insertion line is arranged in the first circuit unit, and the power connection line is arranged in the second circuit unit.

[0112] In an exemplary embodiment, M is equal to four.

[0113] In an exemplary embodiment, at least one first insertion line includes a first data connection line and a first power line arranged in sequence along the first direction, and a first break is arranged between the first data connection line and the first power line; at least one second insertion line includes a second data connection line and a second power line arranged in sequence along the second direction, and a second break is arranged between the second data connection line and the second power line; the second data connection line is connected to the data signal line through the first data connection line.

[0114] In an exemplary embodiment, in at least one second circuit unit, the power connection line is connected to the first power routing line to form a mesh connection structure.

[0115] In an exemplary embodiment, the first pixel driving circuit and the second pixel driving circuit each include at least a storage capacitor, a first initialization transistor and a first light emission control transistor, the first electrode of the first initialization transistor is connected to the fifth connection electrode, the second electrode of the first initialization transistor is connected to the first electrode plate of the storage capacitor through the first connection electrode, and the first electrode of the first light emission control transistor is connected to the second electrode plate of the storage capacitor through the third connection electrode; in at least one first circuit unit, the first connection electrode, the third connection electrode and the fifth connection electrode are arranged in isolation; in at least one second circuit unit, the first connection electrode is respectively connected to the third connection electrode and the fifth connection electrode to form the power connection line.

[0116] In an exemplary embodiment, in at least one second circuit unit, the data signal line is connected to the first power line.

[0117] In an exemplary embodiment, the display substrate includes a display area, a binding area located on one side of the display area, and a frame area located on the other side of the display area, the display area includes at least a first display area and a second display area, the first display area at least partially surrounds the second display area, the first display area is configured to display images, and the second display area is configured to display images and transmit light; the driving structure layer of the first display area includes multiple circuit repetition units.

[0118] In an exemplary embodiment, the display substrate includes a display area, a binding area located on one side of the display area, and a frame area located on the other side of the display area, the display area includes at least a first display area and a second display area, the first display area at least partially surrounds the second display area, the first display area is configured to display images, and the second display area is configured to display images and transmit light; the driving structure layer of the first display area includes a plurality of circuit repeating units, and the light-emitting structure layer of the first display area includes a plurality of first light-emitting devices.

[0119] In an exemplary embodiment, at least one circuit repetition unit includes M first circuit units and 1 third circuit unit, and at least one third circuit unit includes at least a third pixel driving circuit; the light-emitting structure layer of the second display area includes a plurality of second light-emitting devices, and the third pixel driving circuit is connected to the second light-emitting device.

[0120] Figure 6 FIG. 1 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure. Figure 6 As shown, in a plane parallel to the display substrate, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. The display area 100 may include at least a first display area 110 and a second display area 120, the first display area 110 may at least partially surround the second display area 120, the first display area 110 is configured to display an image, and the second display area 120 is configured to display an image and transmit light. In a direction perpendicular to the display substrate, the display area may include at least a driving structure layer disposed on the substrate and a light emitting structure layer disposed on a side of the driving structure layer away from the substrate.

[0121] In an exemplary embodiment, the driving structure layer of the first display area 110 may include a plurality of pixel driving circuits, the driving structure layer of the second display area 120 is not provided with a pixel driving circuit, the light-emitting structure layer of the first display area 110 may include a plurality of first light-emitting devices, the light-emitting structure layer of the second display area 120 may include a plurality of second light-emitting devices, and the plurality of pixel driving circuits of the first display area 110 are configured to provide driving signals to the first light-emitting devices in the first display area 110 and the second light-emitting devices in the second display area 120, respectively, so as to drive the corresponding first light-emitting devices and the second light-emitting devices to emit light.

[0122] In an exemplary embodiment, the driving structure layer of the first display area 110 may include a plurality of circuit repeating units. The circuit repeating unit is a basic unit constituting the driving structure layer of the first display area 110, and the driving structure layer of the first display area 110 may be constituted by repeating and continuously arranging the circuit repeating unit along the first direction X and the second direction Y. The light emitting structure layer of the first display area 110 may include a plurality of light emitting repeating units. The light emitting repeating unit is a basic unit constituting the light emitting structure layer of the first display area 110, and the light emitting structure layer of the first display area 110 may be constituted by repeating and continuously arranging the light emitting repeating unit along the first direction X and the second direction Y.

[0123] In an exemplary embodiment, in the first display area 110, the positions of the plurality of circuit repetition units and the plurality of light-emitting repetition units may be substantially corresponding, the orthographic projection of at least one circuit repetition unit on the substrate has a first area, the orthographic projection of at least one light-emitting repetition unit on the substrate has a second area, and the ratio of the first area to the second area may be approximately 0.95 to 1.05, that is, the area of ​​the orthographic projection of the circuit repetition unit on the substrate and the area of ​​the orthographic projection of the light-emitting repetition unit on the substrate may be substantially the same.

[0124] In an exemplary embodiment, the size of at least one circuit repeating unit in the first direction X and the size of at least one light emitting repeating unit in the first direction X may be substantially the same, and the size of at least one circuit repeating unit in the second direction Y and the size of at least one light emitting repeating unit in the second direction Y may be substantially the same.

[0125] In an exemplary embodiment, at least one circuit repetition unit may include M+1 circuit units sequentially arranged along the first direction X, and the circuit unit may include at least a pixel driving circuit. At least one light emitting repetition unit may include M first light emitting units sequentially arranged along the first direction X, and the first light emitting unit may include at least a first light emitting device. The area of ​​the positive projection of the M+1 pixel driving circuits on the substrate may be substantially the same as the area of ​​the positive projection of the M first light emitting devices on the substrate.

[0126] In an exemplary embodiment, the circuit unit mentioned in the present disclosure refers to an area divided according to a pixel driving circuit, and the light-emitting unit mentioned in the present disclosure refers to an area divided according to a light-emitting device. In an exemplary embodiment, the position of the orthogonal projection of the light-emitting unit on the substrate may correspond to the position of the orthogonal projection of the circuit unit on the substrate, or the position of the orthogonal projection of the light-emitting unit on the substrate may not correspond to the position of the orthogonal projection of the circuit unit on the substrate.

[0127] In an exemplary embodiment, a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row, a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column, a plurality of unit rows and a plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X intersects the second direction Y.

[0128] In an exemplary embodiment, in at least one circuit repetition unit, the sizes of the multiple pixel driving circuits may be substantially the same. In at least one light-emitting repetition unit, the sizes of the multiple first light-emitting devices may be substantially the same. In the present disclosure, the size of the pixel driving circuit refers to the size of the orthographic projection of the pixel driving circuit on the substrate, and the size of the light-emitting device refers to the size of the orthographic projection of the light-emitting device on the substrate. When the orthographic projections of the pixel driving circuit and the light-emitting device on the substrate are rectangular, the size may include any one or more of the following: the length of the orthographic projection in the first direction X, the length of the orthographic projection in the second direction Y, and the area of ​​the orthographic projection. When the orthographic projections of the pixel driving circuit and the light-emitting device on the substrate are circular or elliptical, the size may include any one or more of the following: the radius of the orthographic projection, the major axis and minor axis of the orthographic projection, and the area of ​​the orthographic projection.

[0129] In an exemplary embodiment, in the first display area 110, the driving structure layer may be arranged in a compressed manner to set the circuit unit (pixel driving circuit), while the light emitting structure layer is arranged in a normal (non-compressed) manner to set the first light emitting unit (first light emitting device). For example, in a normal manner, M circuit units may be arranged in one circuit repeating unit, and M first light emitting units may be arranged in one light emitting repeating unit. In a compressed manner, the number of circuit units arranged in the circuit repeating unit may be increased by adopting lateral compression, and one circuit unit may be inserted into the area where the M circuit units were previously arranged, so that M+1 circuit units may be arranged in one circuit repeating unit. Since the light emitting structure layer adopts a normal manner, M first light emitting devices are still arranged in the light emitting repeating unit, and the area occupied by the M+1 circuit units is substantially the same as the area occupied by the M first light emitting units. In an exemplary embodiment, M may be a positive integer greater than or equal to 3.

[0130] In an exemplary embodiment, for an RGBG pixel arrangement, M may be an integer multiple of 4, such as 4, 8 or 12. In the embodiment of the present disclosure, M is equal to 4, that is, the display substrate of the embodiment of the present disclosure adopts a 4-in-1 structure.

[0131] In some possible implementations, when the pixel arrangement is an RGB arrangement, M may be an integer multiple of 3, such as 3, 6, or 9.

[0132] In an exemplary embodiment, the driving structure layer of the second display area 120 may include a plurality of insulating layers, the light emitting structure layer of the second display area 120 may include a plurality of second light emitting units, and the second light emitting unit may include at least a second light emitting device, that is, the second display area 120 is not provided with a pixel driving circuit, but only with a light emitting device. Since the second display area 120 is not provided with a pixel driving circuit, the second light emitting device of the second display area 120 needs to be connected to the pixel driving circuit in the first display area 110 through an anode connection line.

[0133] In an exemplary embodiment, the size of the second light-emitting device in the second display area 120 may be substantially the same as the size of the first light-emitting device in the first display area 110, and the arrangement of the plurality of second light-emitting devices in the second display area 120 may be substantially the same as the arrangement of the plurality of first light-emitting devices in the first display area 110.

[0134] In an exemplary embodiment, in at least one circuit repetition unit, M+1 circuit units may include M first circuit units and 1 second circuit unit, or may include M first circuit units and 1 third circuit unit. The first circuit unit may include at least a first pixel driving circuit, the second circuit unit may include at least a second pixel driving circuit, and the third circuit unit may include at least a third pixel driving circuit, the first pixel driving circuit is configured to provide a driving signal to a first light-emitting device in the first display area 110, the second pixel driving circuit is used as a dummy pixel circuit, and the third pixel driving circuit is configured to provide a driving signal to a second light-emitting device in the second display area 120.

[0135] Figure 7 The structure of the circuit repeating unit of the embodiment of the present disclosure. Figure 7 As shown, the driving structure layer in the first display area 110 may include a plurality of circuit repetition units 110A, at least one circuit repetition unit 110A may include four first circuit units and one second circuit unit sequentially arranged along the first direction X, or may include four first circuit units and one third circuit unit sequentially arranged along the first direction X, the first circuit unit may include at least a first pixel driving circuit Q1, the second circuit unit may include at least a second pixel driving circuit Q2, and the third circuit unit may include at least a first pixel driving circuit Q3.

[0136] Figure 8 is the structure of the luminescent repeating unit of the embodiment of the present disclosure. Figure 8 As shown, the light emitting structure layer of the first display area 110 may include a plurality of light emitting repeating units 110B, at least one light emitting repeating unit 110B may include four first light emitting devices F1 sequentially arranged along the first direction X, and the light emitting structure layer of the second display area 120 may include a plurality of second light emitting devices F2.

[0137] like Figure 7 and Figure 8 As shown, at least one first pixel driving circuit Q1 in the first display area 110 is connected to at least one first light-emitting unit F1 in the first display area 110, and the orthographic projection of at least one first pixel driving circuit Q1 on the substrate at least partially overlaps with the orthographic projection of at least one first light-emitting device F1 on the substrate, and the first pixel driving circuit Q1 is configured to provide a driving signal to the connected first light-emitting device F1 to drive the corresponding first light-emitting device F1 to emit light. In some examples, the relationship between multiple first pixel driving circuits Q1 and multiple first light-emitting devices F1 can be one-to-one, that is, one first pixel driving circuit Q1 can be connected to one first light-emitting device F1 and is configured to drive the connected first light-emitting device F1 to emit light; or, the relationship between multiple first pixel driving circuits Q1 and multiple first light-emitting devices F1 can be one-to-many, that is, one first pixel driving circuit Q1 can be connected to multiple first light-emitting devices F1 and is configured to drive the connected multiple first light-emitting devices F1 to emit light; or, the relationship between multiple first pixel driving circuits Q1 and multiple first light-emitting devices F1 can be many-to-one, that is, multiple first pixel driving circuits Q1 can be connected to one first light-emitting device F1 and are configured to drive the first light-emitting device F1 to emit light.

[0138] In an exemplary embodiment, at least one third pixel driving circuit Q3 in the first display area 110 is connected to at least one second light-emitting device F2 in the second display area 120 through an anode connecting line, and the orthographic projection of at least one third pixel driving circuit Q3 on the substrate does not overlap with the orthographic projection of at least one second light-emitting device F2 on the substrate, and the third pixel driving circuit Q3 is configured to provide a driving signal to the connected second light-emitting device F2 to drive the corresponding second light-emitting device F2 to emit light. In some examples, the relationship between multiple third pixel driving circuits Q3 and multiple second light-emitting devices F2 can be one-to-one, that is, one third pixel driving circuit Q3 can be connected to one second light-emitting device F2 and is configured to drive the connected second light-emitting device F2 to emit light; or, the relationship between multiple third pixel driving circuits Q3 and multiple second light-emitting devices F2 can be one-to-many, that is, one third pixel driving circuit Q3 can be connected to multiple second light-emitting devices F2 and is configured to drive the connected multiple second light-emitting devices F2 to emit light; or, the relationship between multiple third pixel driving circuits Q3 and multiple second light-emitting devices F2 can be many-to-one, that is, multiple third pixel driving circuits Q3 can be connected to one second light-emitting device F2 and are configured to drive the second light-emitting device F2 to emit light.

[0139] In an exemplary embodiment, the sizes of the first pixel driving circuit Q1 , the second pixel driving circuit Q2 , and the third pixel driving circuit Q3 may be substantially the same, and the sizes of the first light emitting device F1 and the second light emitting device F2 may be substantially the same.

[0140] Fig. 9 FIG. 1 is a schematic diagram showing the connection between a pixel driving circuit and a light emitting device according to an embodiment of the present disclosure. Fig. 9 As shown, at least one first light-emitting device F1 in the first display area 110 can be connected to at least one first pixel driving circuit Q1 in the first display area 110, and at least one second light-emitting device F2 in the second display area 120 can be connected to at least one third pixel driving circuit Q3 in the first display area 110 through the anode connection line AL.

[0141] In an exemplary embodiment, the circuit repetition unit in the first display area 110 may include four first pixel driving circuits Q1 and one third pixel driving circuit Q3 (or second pixel driving circuit Q2), the four first pixel driving circuits Q1 may be arranged sequentially along the first direction X, and one third pixel driving circuit Q3 (or second pixel driving circuit Q2) may be arranged on one side of the first direction X of the four first pixel driving circuits Q1.

[0142] In an exemplary embodiment, the light emitting repeating units in the first display area 110 may each include four first light emitting devices F1. The four first light emitting devices F1 may be a red light emitting device, a first green light emitting device, a blue light emitting device, and a second green light emitting device sequentially arranged along the first direction X.

[0143] In an exemplary embodiment, the second display area 120 may include a plurality of second light emitting devices F2, which may include red light emitting devices, first green light emitting devices, blue light emitting devices, and second green light emitting devices periodically disposed along the first direction X.

[0144] In an exemplary embodiment, the position of a circuit repetition unit in the first display area 110 may substantially correspond to the position of a light-emitting repetition unit, and in the corresponding circuit repetition unit and the light-emitting repetition unit, at least one first light-emitting device F1 is directly connected to at least one first pixel driving circuit Q1, and the orthographic projection of at least one first light-emitting device F1 on the substrate at least partially overlaps with the orthographic projection of at least one first pixel driving circuit Q1 on the substrate, and the first pixel driving circuit Q1 is configured to provide a driving signal to the connected first light-emitting device F1 to drive the corresponding first light-emitting device F1 to emit light.

[0145] In an exemplary embodiment, at least one second light-emitting device F2 in the second display area 120 is connected to at least one third pixel driving circuit Q3 in the first display area 110 through an anode connecting line AL, and the orthographic projection of the at least one second light-emitting device F2 on the substrate does not overlap with the orthographic projection of the at least one third pixel driving circuit Q3 on the substrate, and the third pixel driving circuit Q3 is configured to provide a driving signal to the connected second light-emitting device F2 to drive the corresponding second light-emitting device F2 to emit light.

[0146] In an exemplary embodiment, the first circuit unit may be referred to as a normal circuit unit, and the second circuit unit and the third circuit unit may be referred to as an insertion circuit unit. The first pixel driving circuit in the first circuit unit provides a driving signal to the first light-emitting device in the first display area, and may be referred to as a normal pixel circuit, the second pixel driving circuit in the second circuit unit is neither connected to the first light-emitting device nor to the second light-emitting device, and may be referred to as a dummy pixel circuit, and the third pixel driving circuit in the third circuit unit provides a driving signal to the second light-emitting device in the second display area, and may be referred to as an insertion pixel circuit.

[0147] In an exemplary embodiment, a plurality of first circuit units arranged sequentially along the second direction Y may be referred to as a normal unit column, a plurality of second circuit units (or a plurality of second circuit units and at least one third circuit unit) arranged sequentially along the second direction Y may be referred to as an insertion unit column, and four normal unit columns may be arranged between two adjacent insertion unit columns in the first direction X to form a 4-in-1 structure.

[0148] In an exemplary embodiment, the plurality of third circuit units may be disposed at a position close to the second display area, and the plurality of second circuit units may be disposed at a position far from the second display area, which is not limited in the present disclosure.

[0149] In an exemplary embodiment, the position of the second display area 120 in the first display area 110 is not limited, and may be located in the upper area or the lower area of ​​the first display area 110, or may be located at the edge of the first display area 110. The resolutions of the first display area 110 and the second display area 120 may be the same or different, and the present disclosure does not limit this.

[0150] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the second display area 120 may be any one or more of the following: rectangular, polygonal, circular, and elliptical, and the optical device may be a fingerprint recognition device, a camera device, or an optical sensor such as 3D imaging. When the shape of the second display area 120 is circular, the diameter of the circle may be approximately 3 mm to 5 mm, and when the shape of the second display area 120 is rectangular, the side length of the rectangle may be approximately 3 mm to 5 mm, which is not limited in the present disclosure.

[0151] like Figure 6 As shown, the driving structure layer of the first display area 110 may also include a plurality of data signal lines 72, a plurality of first data connection lines 81 and a plurality of second data connection lines 82. The shape of the first data connection line 81 may be a straight line or a broken line extending along the first direction X, and the shape of the data signal line 72 and the second data connection line 82 may be a straight line or a broken line extending along the second direction Y.

[0152] In an exemplary embodiment, a plurality of data signal lines 72 are sequentially arranged at set intervals in the first direction X, at least one data signal line 72 is connected to a plurality of pixel driving circuits in a unit column, and the data signal line 72 is configured to provide data signals to the connected pixel driving circuits. A first end of at least one first data connection line 81 is connected to a data signal line 72, and a second end is connected to one end of a second data connection line 82, and the other end of the second data connection line 82 is connected to a data lead-out line 80 after extending to the binding area, so that the data signal line 72 in the display area is connected to the data lead-out line 80 in the binding area 200 through the first data connection line 81 and the second data connection line 82, forming a FIP structure (also referred to as a FIAA structure). In an exemplary embodiment, the first data connection line 81 and the second data connection line 82 may be collectively referred to as a data connection line.

[0153] In an exemplary embodiment, the binding area 200 may include a lead area 201, a bending area, a driver chip area, and a binding pin area sequentially arranged in a direction away from the display area, the lead area 201 is connected to the display area 100, and the bending area is connected to the lead area 201. The lead area 201 may be provided with a plurality of data lead lines 80, the plurality of data lead lines 80 extend in a direction away from the display area, the first ends of a portion of the data lead lines 80 are correspondingly connected to the second data connection line 82 in the display area 100, the first ends of another portion of the data lead lines 80 are correspondingly connected to the data signal line 72 in the display area 100, and the second ends of all the data lead lines 80 extend along the second direction Y and then cross the bending area to connect to the integrated circuit of the driver chip area, so that the integrated circuit applies the data signal to the data signal line through the data lead line and the data connection line. Since the first data connection line 81 and the second data connection line 82 are arranged in the display area, the length of the second direction Y of the lead area can be effectively reduced, the width of the lower frame can be greatly reduced, the screen ratio is improved, and it is conducive to achieving full-screen display.

[0154] In an exemplary embodiment, the number of data connection lines in the display area may be the same as the number of data signal lines, and each data signal line is connected to a corresponding lead line through a data connection line. Alternatively, the number of data connection lines in the display area may be less than the number of data signal lines, and a portion of the data signal lines in the display area are connected to the corresponding lead lines through the data connection lines, and another portion of the data signal lines are directly connected to the lead lines, which is not limited in the present disclosure.

[0155] Fig.10 FIG. 1 is a schematic diagram of a structure of an insertion line according to an exemplary embodiment of the present disclosure. Fig.10 As shown, the driving structure layer of the first display area 110 may further include a plurality of first power lines 91 and a plurality of second power lines 92, the first power lines 91 may be in the shape of a straight line or a folded line extending along the first direction X, the plurality of first power lines 91 may be arranged sequentially along the second direction Y, the second power lines 92 may be in the shape of a straight line or a folded line extending along the second direction Y, and the plurality of second power lines 92 may be arranged sequentially along the first direction X. In an exemplary embodiment, the first power lines 91 and the second power lines 92 may be collectively referred to as power lines.

[0156] In an exemplary embodiment, the first data connection line 81 and the first power supply line 91 can be arranged in the same layer and formed simultaneously by the same patterning process. A first break K1 is arranged between the first data connection line 81 and the first power supply line 91 arranged in the same cell row, and the first break K1 is configured to achieve mutual insulation between the first data connection line 81 and the first power supply line 91.

[0157] In an exemplary embodiment, the second data connection line 82 and the second power supply line 92 can be arranged in the same layer and formed simultaneously by the same patterning process. A second break K2 is arranged between the second data connection line 82 and the second power supply line 92 arranged in the same unit column, and the second break K2 is configured to achieve mutual insulation between the second data connection line 82 and the second power supply line 92.

[0158] In an exemplary embodiment, the first data connection line 81 may be referred to as a lateral connection line (lateral FIP line), and the first power line 91 may be referred to as a lateral dummy connection line (lateral Dummy FIP line). The lateral connection line and the lateral dummy connection line are formed synchronously using the same film layer and the same patterning process (such as the first source and drain metal layer), and the two are disconnected. In an exemplary embodiment, the first data connection line 81 and the first power line 91 may both be referred to as first insertion lines. In some cell rows, the first insertion line may include the first data connection line 81 and the first power line 91 sequentially arranged along the first direction X. In other cell rows, the first insertion line may include only the first power line 91.

[0159] In an exemplary embodiment, the second data connection line 82 can be referred to as a vertical connection line (vertical FIP line), and the second power line 92 can be referred to as a vertical dummy connection line (vertical Dummy FIP line). The vertical connection line and the vertical dummy connection line are formed synchronously using the same film layer and the same patterning process (such as the third source and drain metal layer), and the two are disconnected. In an exemplary embodiment, the second data connection line 82 and the second power line 92 can both be referred to as second insertion lines. In some unit columns, the second insertion line may include the second data connection line 82 and the second power line 92 sequentially arranged along the second direction Y. In other unit columns, the second insertion line may only include the second power line 92.

[0160] In a direction perpendicular to the display substrate, the driving structure layer of the first display area 110 may include a plurality of conductive layers. The data signal line 72 and the first data connection line 81 may be arranged in different conductive layers, and the first data connection line 81 and the second data connection line 82 may be arranged in different conductive layers. The first end of the first data connection line 81 is connected to the data signal line 72 through the first connection hole VK1, and the second end of the first data connection line 81 is connected to the first end of the second data connection line 82 through the second connection hole VK2 after extending along the first direction X or the opposite direction of the first direction X, and the second end of the second data connection line 82 is extended along the second direction Y toward the binding area.

[0161] In an exemplary embodiment, since the data connection line is provided in a partial area of ​​the display area, the driving structure layer of the first display area can be divided into a first area 110-1 and a second area 110-2 according to the presence or absence of the data connection line. The first area 110-1 can be an area where the first data connection line 81 and the second data connection line 82 are provided ( Fig.10 The second area 110-2 may be an area where the first data connection line 81 and the second data connection line 82 are not provided ( Fig.10In an exemplary embodiment, the first area 110 - 1 may be referred to as a FIP area, and the second area 110 - 2 may be referred to as a non-FIP area or a SIP area.

[0162] Fig.11 This is a schematic diagram of the structure of a first display area of ​​an exemplary embodiment of the present disclosure, illustrating the structure of 16 circuit units in two unit rows (the Mth unit row and the M+1th unit row) and eight unit columns (the Nth unit column to the N+7th unit column) in the first display area. Among them, the Nth unit column, the N+2th unit column to the N+5th unit column, and the N+7th unit column are normal unit columns, and the circuit units in these unit columns are first circuit units, and the N+1th unit column and the N+6th unit column are inserted unit columns, and the circuit units in these unit columns are second circuit units.

[0163] like Fig.11 As shown, in a plane parallel to the display substrate, the driving structure layer of the first display area may include a plurality of first circuit units and a plurality of second circuit units, at least one first circuit unit may include a first pixel driving circuit, at least one second circuit unit may include a second pixel driving circuit, and the first pixel driving circuit and the second pixel driving circuit may be connected to the first scanning signal line 21, the second scanning signal line 22, the light emitting signal line 23, the first initial signal line 41, the second initial signal line 42, the first power line 71 and the data signal line 72, respectively. The first scanning signal line 21, the second scanning signal line 22 and the light emitting signal line 23 are configured to provide the first scanning signal, the second scanning signal and the light emitting control signal to the first pixel driving circuit, respectively, the first initial signal line 41 and the second initial signal line 42 are configured to provide the first initial signal and the second initial signal to the first pixel driving circuit, respectively, the first power line 71 is configured to provide the first power signal to the first pixel driving circuit, and the data signal line 72 is configured to provide the data signal to the first pixel driving circuit. Among them, the multiple signal lines connected to the first pixel driving circuit and the second pixel driving circuit may be located in the corresponding circuit units.

[0164] In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the light-emitting signal line 23, the first initial signal line 41 and the second initial signal line 42 can be straight lines or folded lines with the main parts extending along the first direction X, and the shapes of the first power line 71 and the data signal line 72 can be straight lines or folded lines with the main parts extending along the second direction Y.

[0165] In the present disclosure, A extends along the B direction, which means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along the B direction, and the length of the main part extending along the B direction is greater than the length of the secondary part extending along other directions. In the following description, "A extends along the B direction" means "the main part of A extends along the B direction". In an exemplary embodiment, the first direction X may be a unit row direction, and the second direction Y may be a unit column direction.

[0166] In an exemplary embodiment, the first pixel driving circuit and the second pixel driving circuit may include at least a storage capacitor and a plurality of transistors. The plurality of transistors may include a first transistor T1 as a first reset transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emission control transistor, a sixth transistor T6 as a second light emission control transistor, and a seventh transistor T7 as a second reset transistor, and the storage capacitor may include a first plate and a second plate stacked.

[0167] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line 22, the first electrode of the first transistor T1 is connected to the first initial signal line 41, and the second electrode of the first transistor T1 is respectively connected to the first electrode and the first electrode plate of the second transistor T2 (also the gate electrode of the third transistor T3). The gate electrode of the second transistor T2 is connected to the first scan signal line 21, and the second electrode of the second transistor T2 is respectively connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, the first electrode of the fourth transistor T4 is connected to the data signal line 72, and the second electrode of the fourth transistor T4 is respectively connected to the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5. The gate electrode of the fifth transistor T5 is connected to the light emitting signal line 23, and the first electrode of the fifth transistor T5 is connected to the first power supply line 71. The gate electrode of the sixth transistor T6 is connected to the light emitting signal line 23, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. A gate electrode of the seventh transistor T7 is connected to the first scanning signal line 21 , and a first electrode of the seventh transistor T7 is connected to the second initial signal line 42 .

[0168] Fig.12 FIG. 1 is a schematic diagram of the structure of the first insertion line and the second insertion line of the exemplary embodiment of the present disclosure. Fig.11 and Fig.12As shown, the driving structure layer of the first display area may further include at least one first insertion line and at least one second insertion line. The shape of the first insertion line may be a straight line or a broken line extending along the first direction X, and the shape of the second insertion line may be a straight line or a broken line extending along the second direction Y.

[0169] In an exemplary embodiment, at least one first insertion line may include a first data connection line 81 and a first power supply line 91 that are arranged in the same unit row and sequentially arranged along the first direction X, and a first break K1 is provided between the first data connection line 81 and the first power supply line 91, and the first break K1 cuts off the first data connection line 81 and the first power supply line 91. In other unit rows, the first insertion line may include only the first power supply line 91.

[0170] In an exemplary embodiment, at least one second insertion line may include a second data connection line 82 and a second power supply line 92 that are arranged in the same unit column and sequentially arranged along the second direction Y, and a second break K2 is provided between the second data connection line 82 and the second power supply line 92, and the second break K2 cuts off the second data connection line 82 and the second power supply line 92. In other unit columns, the second insertion line may include only the second power supply line 92.

[0171] In an exemplary embodiment, the second data link line 82 may be connected to the first data link line 81 through a via, and the first data link line 81 may be connected to the data signal line 72 through a via, that is, the second data link line 82 is connected to the data signal line 72 through the first data link line 81 .

[0172] In an exemplary embodiment, the driving structure layer of the first display area may further include at least one power connection line 70 . The power connection line 70 may be in the shape of a folded line extending along the second direction Y. The power connection line 70 is configured to be connected to the first power line 71 .

[0173] In an exemplary embodiment, the second data connection line 82 and the second power supply line 92 can be set only in the first circuit unit, and the power connection line 70 can be set only in the second circuit unit, that is, the power connection line 70 is not set in the normal unit column (first circuit unit), and the second insertion line is not set in the insertion unit column (second circuit unit), so as to reduce the circuit difference between the first circuit unit and the second circuit unit, avoid the load difference of the data signal caused by the circuit difference, and improve the display quality.

[0174] In an exemplary embodiment, at least one circuit unit (including a first circuit unit and a second circuit unit) may include at least a first connection electrode 51, a third connection electrode 53 and a fifth connection electrode 55, the first connection electrode 51 may be respectively connected to the second electrode of the first transistor T1 and the first electrode plate of the storage capacitor, the third connection electrode 53 may be respectively connected to the first electrode of the fifth transistor T5 and the second electrode plate of the storage capacitor, and the fifth connection electrode 55 may be connected to the first electrode of the first transistor T1.

[0175] In an exemplary embodiment, in at least one first circuit unit, the first connection electrode 51, the third connection electrode 53 and the fifth connection electrode 55 can be isolated, that is, not connected. In at least one second circuit unit, the first connection electrode 51 can be connected to the third connection electrode 53 and the fifth connection electrode 55, respectively, to form a power connection line 70 extending along the second direction Y.

[0176] In an exemplary embodiment, in at least one second circuit unit, the third connection electrode 53 and the fifth connection electrode 55 are both connected to the first power line 91, so that the power connection line 70 forms a mesh connection structure with the first power line 91. In at least another second circuit unit, the third connection electrode 53 and the fifth connection electrode 55 are not connected to the first data connection line 81.

[0177] In an exemplary embodiment, at least one of the first circuit units is further provided with a data connection bar 83 and a data connection block 84. The data connection bar 83 may be in a bar shape extending along the second direction Y, and the data connection block 84 may be in a block shape (such as a rectangle). The first end of the data connection bar 83 is connected to the first data connection line 81, and the second end of the data connection bar 83 is connected to the second data connection line 82, that is, the first data connection line 81 is connected to the second data connection line 82 through the data connection bar 83 and the data connection block 84.

[0178] In an exemplary embodiment, at least one of the first circuit units is further provided with a dummy connection bar 93 and a dummy connection block 94. The dummy connection bar 93 may be in the shape of a bar extending along the second direction Y, and the dummy connection block 94 may be in the shape of a block (such as a rectangle). The first end of the dummy connection bar 93 is located on one side of the first power supply line 91, and the second end of the dummy connection bar 93 is connected to the dummy connection block 94, and the dummy connection block 94 is connected to the second power supply line 92.

[0179] In an exemplary embodiment, the position and shape of the data connection bar 83 in one first circuit unit are the same as the position and shape of the dummy connection bar 93 in another first circuit unit, and the position and shape of the data connection block 84 in one first circuit unit are the same as the position and shape of the dummy connection block 94 in another first circuit unit.

[0180] In an exemplary embodiment, in a direction perpendicular to the display substrate, the driving structure layer may include a plurality of conductive layers, and the plurality of conductive layers may include at least a first source-drain metal layer (third conductive layer), a second source-drain metal layer (fourth conductive layer) disposed on a side of the first source-drain metal layer away from the substrate, and a third source-drain metal layer (fifth conductive layer) disposed on a side of the second source-drain metal layer away from the substrate. The power connection line 70, the first data connection line 81, and the first power wiring 91 may be disposed in the first source-drain metal layer, the first power line 71 may be disposed in the second source-drain metal layer, and the data signal line 72, the second data connection line 82, and the second power wiring 92 may be disposed in the third source-drain metal layer.

[0181] The following is an exemplary explanation of the preparation process of the substrate shown in this exemplary embodiment. The "patterning process" mentioned in the present disclosure includes deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0182] In an exemplary embodiment, taking 16 circuit units of 2 unit rows (Mth unit row and M+1th unit row) and 8 unit columns (Nth unit column to N+7th unit column) as an example, the preparation process of the display substrate of this embodiment may include the following operations. Among them, the Nth unit column, the N+2th unit column to the N+5th unit column, and the N+7th unit column are normal unit columns, and the circuit units in these unit columns are first circuit units, and the N+1th unit column and the N+6th unit column are inserted unit columns, and the circuit units in these unit columns are second circuit units.

[0183] (11) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer disposed on the substrate, and a semiconductor layer pattern disposed on the first insulating layer, such as Fig.13 shown.

[0184] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit (including the first circuit unit and the second circuit unit) in the first display area may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 17 may be an integrated structure connected to each other.

[0185] In an exemplary embodiment, in the second direction Y, the first active layer 11, the second active layer 12, and the fourth active layer 14 may be located on a side of the third active layer 13 in the opposite direction of the second direction Y, and the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may be located on a side of the third active layer 13 in the second direction Y.

[0186] In an exemplary embodiment, the third active layer 13 may be shaped like an "Ω", the first active layer 11 may be shaped like an "n", the second active layer 12, the fifth active layer 15, and the sixth active layer 16 may be shaped like an "L", and the fourth active layer 14 and the seventh active layer 17 may be shaped like an "I".

[0187] In an exemplary embodiment, the first to seventh active layers 11 to 17 may each include a first region, a second region, and a channel region between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be connected to each other, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be connected to each other, and the first region 13-1 of the third active layer may serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer at the same time. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be connected to each other, and the second region 12-2 of the second active layer may serve as the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer at the same time. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be connected to each other, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer may be separately provided.

[0188] In an exemplary embodiment, the first region 17-1 of the seventh active layer in the present circuit unit may be disposed in the circuit unit of the next unit row. For example, the first region 17-1 of the seventh active layer of the circuit unit in the M-1th unit row may be disposed in the circuit unit of the Mth unit row. For another example, the first region 17-1 of the seventh active layer of the circuit unit in the Mth unit row may be disposed in the circuit unit of the M+1th unit row.

[0189] In an exemplary embodiment, positions and shapes of semiconductor layers in a plurality of circuit cells in one cell row may be substantially the same, and positions and shapes of semiconductor layers in a plurality of circuit cells in one cell column may be substantially the same.

[0190] In an exemplary embodiment, in this process, the semiconductor layer in the second display area is etched away to form a first insulating layer disposed on the substrate.

[0191] In an exemplary embodiment, the semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the third transistor to the seventh transistor are LTPS transistors. In an exemplary embodiment, patterning the semiconductor film by a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, dehydrogenating the amorphous silicon film, and crystallizing the amorphous silicon film after the dehydrogenation to form a polycrystalline silicon film. Subsequently, the polycrystalline silicon film is patterned to form a semiconductor layer pattern.

[0192] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer, and a first conductive layer pattern disposed on the second insulating layer, such as Fig.14A and Fig. 14B As shown, Fig. 14B for Fig.14A In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0193] In an exemplary embodiment, the first conductive layer pattern of each circuit unit (including the first circuit unit and the second circuit unit) in the first display area may include at least a first scan signal line 21, a second scan signal line 22, a light emitting signal line 23 and a first plate 31 of a storage capacitor.

[0194] In an exemplary embodiment, the shape of the first electrode plate 31 of the storage capacitor can be rectangular, and the corners of the rectangle can be provided with chamfers or grooves. The orthographic projection of the first electrode plate 31 on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate. The first electrode plate 31 can simultaneously serve as the lower electrode plate of the storage capacitor and the gate electrode of the third transistor T3.

[0195] In an exemplary embodiment, the first scan signal line 21 may be in the shape of a straight line or a folded line extending along the first direction X, and may be disposed on the side of the first electrode plate 31 opposite to the second direction Y. A gate block 21-1 is disposed on the first scan signal line 21 of each circuit unit, and the gate block 21-1 may be in the shape of a strip extending along the second direction Y. A first end of the gate block 21-1 is connected to a side of the first scan signal line 21 close to the first electrode plate 31, and a second end of the gate block 21-1 extends in a direction close to the first electrode plate 31. The region where the first scan signal line 21 and the gate block 21-1 overlap with the second active layer may serve as the gate electrode of the second transistor T2 of the dual-gate structure, and the region where the first scan signal line 21 overlaps with the fourth active layer may serve as the gate electrode of the fourth transistor T4.

[0196] In an exemplary embodiment, in at least one unit row, the first scan signal line 21 and the gate blocks 21 - 1 of the plurality of circuit units may be an integral structure connected to each other.

[0197] In an exemplary embodiment, the second scan signal line 22 may be in the shape of a straight line or a folded line extending along the first direction X, and may be arranged on the side of the first scan signal line 21 away from the first electrode plate 31. The area where the second scan signal line 22 overlaps with the first active layer in the present circuit unit may be used as the gate electrode of the first transistor T1 of the double-gate structure in the present circuit unit, and the area where the second scan signal line 22 overlaps with the seventh active layer in the previous circuit unit may be used as the gate electrode of the seventh transistor T7 in the previous circuit unit, that is, the seventh transistor T7 of the circuit unit in the M-1th unit row is controlled by the second scan signal line 22 of the Mth unit row, and the seventh transistor T7 of the circuit unit in the Mth unit row is controlled by the second scan signal line 22 of the M+1th unit row. The present circuit unit refers to the circuit unit of the present unit row, and the previous circuit unit refers to the circuit unit of the previous unit row. In terms of timing control, the second scan signal line of the next unit row is equivalent to the first scan signal line of the present unit row, and thus is equivalent to the seventh transistor T7 of the circuit unit in the Mth unit row being controlled by the first scan signal line of the Mth unit row.

[0198] In an exemplary embodiment, the shape of the light emitting signal line 23 may be a straight line or a folded line extending along the first direction X, and may be disposed on one side of the first electrode plate 31 in the second direction Y. The region where the light emitting signal line 23 overlaps with the fifth active layer may serve as the gate electrode of the fifth transistor T5, and the region where the light emitting signal line 23 overlaps with the sixth active layer may serve as the gate electrode of the sixth transistor T6.

[0199] In an exemplary embodiment, positions and shapes of first conductive layers in a plurality of circuit cells in one cell row may be substantially the same, and positions and shapes of first conductive layers in a plurality of circuit cells in one cell column may be substantially the same.

[0200] In an exemplary embodiment, in this process, the first conductive layer in the second display area is etched away to form a second insulating layer disposed on the first insulating layer.

[0201] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate having the aforementioned pattern, patterning the second conductive film through a patterning process to form a third insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the third insulating layer, such as Fig.15A and Fig. 15B As shown, Fig. 15B for Fig.15A In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0202] In an exemplary embodiment, the second conductive layer pattern of each circuit unit (including the first circuit unit and the second circuit unit) in the first display area includes at least: a second plate 32 of the storage capacitor, a first initial signal line 41, a second initial signal line 42, a first shielding electrode 43 and a second shielding electrode 44.

[0203] In an exemplary embodiment, the outline of the second electrode plate 32 of the storage capacitor can be rectangular, and the corners of the rectangle can be provided with chamfers or grooves. The orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate. The second electrode plate 32 can serve as the upper electrode plate of the storage capacitor, and the first electrode plate 31 and the second electrode plate 32 constitute a storage capacitor.

[0204] In an exemplary embodiment, an opening 33 is provided on the second electrode plate 32. The opening 33 may be rectangular and may be located in the middle region of the second electrode plate 32, so that the second electrode plate 32 forms a ring shape. The opening 33 exposes the third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 on the substrate includes the orthographic projection of the opening 33 on the substrate. In an exemplary embodiment, the opening 33 is configured to accommodate a seventh via hole formed subsequently. The seventh via hole is located in the opening 33 and exposes the first electrode plate 31, so that the first connecting electrode formed subsequently is connected to the first electrode plate 31.

[0205] In an exemplary embodiment, the second electrode plate 32 may be provided with a plate connection bar 34. The plate connection bar 34 may be in the shape of a bar extending along the first direction X, and the plate connection bar 34 may be provided on one side of the second electrode plate 32 in the first direction X or on the side opposite to the first direction X, and the first end of the plate connection bar 34 is connected to the second electrode plate 32 in the current circuit unit, and the second end of the plate connection bar 34 is connected to the second electrode plate 32 in the adjacent circuit unit in the first direction X.

[0206] In an exemplary embodiment, the second plates 32 and the plate connection bars 34 in two adjacent circuit units in a unit row may be interconnected integral structures. For example, the second plates 32 of the Nth unit column and the second plates 32 of the N+1th unit column are interconnected through the plate connection bars 34 to form an interconnected integral structure. Since the second plates 32 in each circuit unit are connected to the first power line formed subsequently, by forming the second plates 32 of adjacent circuit units into an integral structure interconnected, the second plates of the integral structure can be reused as a lateral power signal line, which can ensure that multiple second plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0207] In an exemplary embodiment, the first initial signal line 41 may be in the shape of a straight line or a folded line extending along the first direction X, and may be disposed between the first scan signal line 21 and the second scan signal line 22. A first initial connection block 41-1 may be disposed on the first initial signal line 41, and the shape of the first initial connection block 41-1 may be in the shape of a block (such as a rectangle), a first end of the first initial connection block 41-1 is connected to a side of the first initial signal line 41 away from the second electrode plate 32, a second end of the first initial connection block 41-1 extends in a direction away from the second electrode plate 32, and the first initial connection block 41-1 is configured to be connected to the first region of the first active layer through a fifth connection electrode formed subsequently.

[0208] In an exemplary embodiment, in at least one cell row, the first preliminary signal line 41 and the first preliminary connection block 41 - 1 may be an integral structure connected to each other.

[0209] In an exemplary embodiment, the second initial signal line 42 may be in a straight line or a folded line extending along the first direction X, and may be disposed on a side of the second scan signal line 22 away from the first scan signal line 21. A second initial connection block 42-1 may be disposed on the second initial signal line 42, and the second initial connection block 42-1 may be in a block shape (such as a rectangle), connected to the second initial signal line 42, and the second initial connection block 42-1 is configured to be connected to the first region of the seventh active layer through a sixth connection electrode formed subsequently.

[0210] In an exemplary embodiment, the positive projection of the second initial signal line 42 on the substrate at least partially overlaps with the positive projection of the first active layer between the two gate electrodes in the first transistor T1 on the substrate. The second initial signal line 42 can shield the node between the two gate electrodes in the first transistor T1, avoid the influence of the data voltage jump on the first transistor T1, reduce the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0211] In an exemplary embodiment, in at least one unit row, the second preliminary signal line 42 and the second preliminary connection block 42 - 1 may be an integral structure connected to each other.

[0212] In an exemplary embodiment, the shape of the first shielding electrode 43 may be a block shape (such as a rectangle), and may be disposed on a side of the second electrode plate 32 close to the first scan signal line 21. A first end of the first shielding electrode 43 is connected to a side of the second electrode plate 32 close to the first scan signal line 21, and a second end of the first shielding electrode 43 extends in a direction close to the first scan signal line 21. The positive projection of the first shielding electrode 43 on the substrate at least partially overlaps with the positive projection of the second active layer between the two gate electrodes in the second transistor T2 on the substrate. In an exemplary embodiment, the first shielding electrode 43 is configured to shield the node between the two gate electrodes in the second transistor T2, avoid the influence of the data voltage jump on the second transistor T2, reduce the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0213] In an exemplary embodiment, in at least one circuit unit, the second electrode plate 32 and the first shielding electrode 43 may be an integral structure connected to each other.

[0214] In an exemplary embodiment, the second shielding electrode 44 may be block-shaped (such as a rectangle) and may be disposed on a side of the first initial signal line 41 close to the first scanning signal line 21. The first end of the second shielding electrode 44 is connected to a side of the first initial signal line 41 close to the first scanning signal line 21, and the second end of the second shielding electrode 44 extends in a direction close to the first scanning signal line 21. In the first direction X, the second shielding electrode 44 may be located between the first region of the second active layer (also the second region of the first active layer) and the first region of the fourth active layer. In an exemplary embodiment, the second shielding electrode 44 is configured to serve as a shielding bar between the second transistor T2 and the fourth transistor T4, isolating the influence of the data voltage jump of the fourth transistor T4 on the first electrode of the second transistor T2 (the first node of the pixel driving circuit), reducing the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improving the display effect. Shielding

[0215] In an exemplary embodiment, in at least one circuit unit, the first initial signal line 41 and the second shielding electrode 44 may be an integral structure connected to each other.

[0216] In an exemplary embodiment, positions and shapes of the second conductive layers in a plurality of circuit cells in one cell row may be substantially the same, and positions and shapes of the second conductive layers in a plurality of circuit cells in one cell column may be substantially the same.

[0217] In an exemplary embodiment, in this process, the second conductive layer in the second display area is etched away to form a third insulating layer disposed on the second insulating layer.

[0218] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of via holes are disposed on the fourth insulating layer, such as Fig.16 shown.

[0219] In an exemplary embodiment, the plurality of vias of at least one circuit unit in the first display area may include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9 and a tenth via V10.

[0220] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed fifth connecting electrode to the first region of the first active layer through the via hole.

[0221] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the first active layer (also the first area of ​​the second active layer) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the second via hole V2 are etched away to expose the surface of the second area of ​​the first active layer (also the first area of ​​the second active layer), and the second via hole V2 is configured to connect a subsequently formed first connecting electrode to the second area of ​​the first active layer (also the first area of ​​the second active layer) through the via hole.

[0222] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the third via hole V3 are etched away to expose the surface of the first area of ​​the fourth active layer, and the third via hole V3 is configured to connect a subsequently formed second connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0223] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first area of ​​the fifth active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fourth via hole V4 are etched away to expose the surface of the first area of ​​the fifth active layer, and the fourth via hole V4 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fifth active layer through the via hole.

[0224] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fifth via hole V5 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the fifth via hole V5 is configured to connect a subsequently formed fourth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0225] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the sixth via hole V6 are etched away to expose the surface of the first region of the seventh active layer, and the sixth via hole V6 is configured to connect a subsequently formed sixth connecting electrode to the first region of the seventh active layer through the via hole.

[0226] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the opening 33 on the substrate, the third insulating layer and the fourth insulating layer in the seventh via hole V7 are etched away to expose the surface of the first electrode plate 31, and the seventh via hole V7 is configured to connect a subsequently formed first connecting electrode to the first electrode plate 31 through the via hole.

[0227] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the second electrode plate 32 on the substrate, the fourth insulating layer in the eighth via hole V8 is etched away to expose the surface of the second electrode plate 32, and the eighth via hole V8 is configured to connect the subsequently formed third connecting electrode to the second electrode plate 32 through the via hole.

[0228] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the first initial connection block 41-1 of the first initial signal line 41 on the substrate, the fourth insulating layer in the ninth via hole V9 is etched away to expose the surface of the first initial connection block 41-1, and the ninth via hole V9 is configured to connect the subsequently formed fifth connection electrode to the first initial connection block 41-1 through the via hole.

[0229] In an exemplary embodiment, since a power connection line is formed in the second circuit unit in a subsequent process and the power connection line is connected to the first power line, the second circuit unit is not provided with a ninth via V9, that is, the fifth connection electrode of the second circuit unit formed subsequently is not connected to the first initial signal line.

[0230] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second initial connection block 42-1 of the second initial signal line 42 on the substrate, the fourth insulating layer in the tenth via hole V10 is etched away to expose the surface of the second initial connection block 42-1, and the tenth via hole V10 is configured to connect the subsequently formed sixth connection electrode to the second initial connection block 42-1 through the via hole.

[0231] In an exemplary embodiment, in this process, the second display region forms a fourth insulating layer disposed on the third insulating layer.

[0232] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, such as Fig.17A and Fig. 17B As shown, Fig. 17B for Fig.17A In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0233] In an exemplary embodiment, the third conductive layer of each circuit unit (including the first circuit unit and the second circuit unit) in the first display area includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55 and a sixth connection electrode 56.

[0234] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip having a main portion extending along the second direction Y, a first end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) through a second via hole V2, and a second end of the first connection electrode 51 is connected to the first electrode plate 31 through a seventh via hole V7. Since the first electrode plate 31 serves as the gate electrode of the third transistor T3, the first connection electrode 51 realizes the interconnection between the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3 and the first electrode plate 31 of the storage capacitor, thereby forming a first node N1 of the pixel driving circuit.

[0235] In an exemplary embodiment, the second connection electrode 52 may be block-shaped (eg, rectangular) and connected to the first region of the fourth active layer through the third via hole V3. The second connection electrode 52 is configured to be connected to a first data connection electrode formed subsequently.

[0236] In an exemplary embodiment, the third connection electrode 53 may be in the shape of a strip extending along the second direction Y, a first end of the third connection electrode 53 is connected to the first region of the fifth active layer through a fourth via hole V4, a second end of the third connection electrode 53 is connected to the second electrode plate 32 through an eighth via hole V8, and the third connection electrode 53 is configured to be connected to a first power line formed subsequently. In an exemplary embodiment, the third connection electrode 53 realizes the mutual connection between the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor, and the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor have the same potential.

[0237] In an exemplary embodiment, the shape of the fourth connection electrode 54 can be block-shaped (such as rectangular), and the fourth connection electrode 54 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fifth via V5, and the fourth connection electrode 54 is configured to be connected to the first anode connection electrode formed subsequently.

[0238] In an exemplary embodiment, the fifth connection electrode 55 may be in the shape of a strip extending along the first direction X. In the first circuit unit, the first end of the fifth connection electrode 55 is connected to the first region of the first active layer through the first via hole V1, and the second end of the fifth connection electrode 55 is connected to the first initial connection block 41-1 through the ninth via hole V9. Since the first initial connection block 41-1 is connected to the first initial signal line 41, the fifth connection electrode 55 enables the first initial signal line 41 to write the first initial signal to the first electrode of the first transistor T1. In the second circuit unit, the first end of the fifth connection electrode 55 is connected to the first region of the first active layer through the first via hole V1, and the second end of the fifth connection electrode 55 is not connected to the first initial connection block 41-1.

[0239] In an exemplary embodiment, a connection bar 55-1 may be provided on the fifth connection electrode 55. The connection bar 55-1 may be in an "n" shape and may be provided on a side of the fifth connection electrode 55 away from the second electrode plate 32, a first end of the connection bar 55-1 is connected to a first end of the fifth connection electrode 55, and a second end of the connection bar 55-1 is connected to a second end of the fifth connection electrode 55, so that the fifth connection electrode 55 and the connection bar 55-1 form a ring shape.

[0240] In an exemplary embodiment, the sixth connection electrode 56 may be in a strip shape extending along the second direction Y, a first end of the sixth connection electrode 56 is connected to the first region of the seventh active layer through a sixth via hole V6, and a second end of the sixth connection electrode 56 is connected to the second initial connection block 42-1 through a tenth via hole V10. Since the second initial connection block 42-1 is connected to the second initial signal line 42, the sixth connection electrode 56 enables the second initial signal line 42 to write the second initial signal into the first electrode of the seventh transistor T7.

[0241] In an exemplary embodiment, the third conductive layer of at least one circuit unit in the first display area may further include a first inserted line, which may be in the shape of a straight line or a broken line extending along the first direction X, and may be located between the light-emitting signal line 23 of the current unit row and the second initial signal line 42 of the next unit row.

[0242] In an exemplary embodiment, at least one first insertion line may include at least a first data connection line 81 and a first power line 91, the first data connection line 81 may be arranged in the first area (FIP area), and the first power line 91 may be arranged in the second area (non-FIP area or SIP area).

[0243] In an exemplary embodiment, in the second region (non-FIP region or SIP region), the first insertion line may include only the first power trace 91 .

[0244] In an exemplary embodiment, a first break K1 may be provided between the first data connection line 81 and the first power line 91 in the same unit row, and the first break K1 may cut off the first data connection line 81 located in the FIP area from the first power line 91 located in the non-FIP area, so that the first data connection line 81 and the first power line 91 on both sides of the first break K1 are insulated from each other.

[0245] In an exemplary embodiment, an end of the first data connection line 81 away from the first break K1 is configured to be connected to a subsequently formed data signal line, and an end of the first data connection line 81 close to the first break K1 is configured to be connected to a subsequently formed second data connection line.

[0246] In an exemplary embodiment, in at least one first circuit unit of the first region (FIP region), a data connection bar 83 and a data connection block 84 may be provided on the first data connection line 81. The data connection bar 83 may be in a bar shape extending along the second direction Y, and the data connection block 84 may be in a block shape (such as a rectangle). The data connection bar 83 and the data connection block 84 may be provided on a side of the first data connection line 81 close to the first scan signal line 21. A first end of the data connection bar 83 is connected to a side of the first data connection line 81 close to the first scan signal line 21, and a second end of the data connection bar 83 is connected to the data connection block 84 after extending in the direction of the first scan signal line 21. The data connection block 84 is configured to be connected to a second data connection line formed subsequently.

[0247] In an exemplary embodiment, the first circuit unit in which the data connection bar 83 and the data connection block 84 are provided may be the first circuit unit close to the first break K1 .

[0248] In an exemplary embodiment, in at least one first circuit unit, the first data connection line 81 , the data connection bar 83 , and the data connection block 84 may be an integral structure connected to each other.

[0249] In an exemplary embodiment, at least one first circuit unit of the first display area may further be provided with a dummy connection bar 93 and a dummy connection block 94. The dummy connection bar 93 may be in the shape of a bar extending along the second direction Y, and the dummy connection block 94 may be in the shape of a block (such as a rectangle). The dummy connection bar 93 and the dummy connection block 94 may be provided on a side of the first power supply line 91 (or the first data connection line 81) close to the first scan signal line 21. The first end of the dummy connection bar 93 is located on a side of the first power supply line 91 (or the first data connection line 81) close to the first scan signal line 21, and the second end of the dummy connection bar 93 is extended in the direction of the first scan signal line 21 and connected to the dummy connection block 94, and the dummy connection block 94 is configured to be connected to the second power supply line formed subsequently.

[0250] In an exemplary embodiment, in at least one first circuit unit, the dummy connection bar 93 and the dummy connection block 94 may be an integral structure connected to each other.

[0251] In an exemplary embodiment, the position and shape of the dummy connection bar 93 in one first circuit unit and the data connection bar 83 in another first circuit unit can be substantially the same, and the position and shape of the dummy connection block 94 in one first circuit unit and the data connection block 84 in another first circuit unit can be substantially the same, except that the data connection bar 83 is connected to the first data connection line 81, while the dummy connection bar 93 is not connected to the first power supply line 91 (or the first data connection line 81). The present disclosure sets the data connection bar and the dummy connection bar, the data connection block and the dummy connection block to present the same morphology and via connection structure, and the same design of the transfer area can not only improve the uniformity of the subsequent etching process, but also achieve the same display effect in different areas under transmitted and reflected light, realize shadow elimination, effectively avoid the poor appearance of the display substrate and the occurrence of off-screen watermarks (mura), and improve the display quality and display quality.

[0252] In an exemplary embodiment, since the second data connection line and the second power supply line formed subsequently are only disposed in the first circuit unit but not in the second circuit unit, the dummy connection block and the data connection block may be disposed only in the first circuit unit.

[0253] In an exemplary embodiment, the first region (FIP region) may include a plurality of first circuit units and a plurality of second circuit units. The third conductive layer of at least one second circuit unit in the first region may further include an eleventh connection electrode 61 and a twelfth connection electrode 62 .

[0254] In an exemplary embodiment, the eleventh connection electrode 61 may be shaped as a strip extending along the second direction Y, and may be disposed between the first connection electrode 51 and the fifth connection electrode 55 , with the first end of the eleventh connection electrode 61 being connected to the first connection electrode 51 , and the second end of the eleventh connection electrode 61 being connected to the fifth connection electrode 55 .

[0255] In an exemplary embodiment, the shape of the twelfth connection electrode 62 can be a strip shape extending along the first direction X, and can be arranged between the first connection electrode 51 and the third connection electrode 53, the first end of the twelfth connection electrode 62 is connected to the first connection electrode 51, and the second end of the twelfth connection electrode 62 is connected to the third connection electrode 53.

[0256] In an exemplary embodiment, in at least one second circuit unit of the first area (FIP area), the first connecting electrode 51, the third connecting electrode 53, the fifth connecting electrode 55, the eleventh connecting electrode 61 and the twelfth connecting electrode 62 can be an integrated structure connected to each other, and a power connection line extending along the second direction Y is formed in the second circuit unit.

[0257] In an exemplary embodiment, since the third connecting electrode 53 is configured to be connected to the first power line formed subsequently, the power connection line can be reused as a vertical power signal line, forming a double-layer routing structure together with the first power line, which can effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0258] In an exemplary embodiment, the second region (non-FIP region or SIP region) may include a plurality of first circuit units and a plurality of second circuit units. The third conductive layer of at least one second circuit unit of the second region may further include an eleventh connection electrode 61, a twelfth connection electrode 62, a thirteenth connection electrode 63, and a fourteenth connection electrode 64. The structures of the eleventh connection electrode 61 and the twelfth connection electrode 62 in the first region and the second region are substantially the same.

[0259] In an exemplary embodiment, the thirteenth connection electrode 63 may be in the shape of a strip extending along the second direction Y, and may be disposed between the third connection electrode 53 and the first power supply wiring 91. A first end of the thirteenth connection electrode 63 is connected to the third connection electrode 53, and a second end of the thirteenth connection electrode 63 is connected to the first power supply wiring 91 of the current unit row. In an exemplary embodiment, the thirteenth connection electrode 63 realizes the connection between the third connection electrode 53 and the first power supply wiring 91.

[0260] In an exemplary embodiment, the fourteenth connection electrode 64 may be in the shape of a strip extending along the second direction Y, and may be disposed between the connection bar 55-1 and the first power supply wiring 91, a first end of the fourteenth connection electrode 64 is connected to the connection bar 55-1, and a second end of the fourteenth connection electrode 64 is connected to the first power supply wiring 91 of the previous unit row. In an exemplary embodiment, since the connection bar 55-1 is connected to the fifth connection electrode 55, the fourteenth connection electrode 64 realizes the connection between the fifth connection electrode 55 and the first power supply wiring 91.

[0261] In the exemplary embodiment, since the first connection electrode 51, the third connection electrode 53, the fifth connection electrode 55, the eleventh connection electrode 61 and the twelfth connection electrode 62 in the second circuit unit are interconnected as an integrated structure, the thirteenth connection electrode 63 and the fourteenth connection electrode 64 not only realize the interconnection between the power connection line and the first power wiring 91, but also realize the interconnection between multiple power connection lines in one unit column. In this way, the first power wiring 91 extending along the first direction X and the power connection line extending along the second direction Y form a meshed connection structure for transmitting power signals.

[0262] In an exemplary embodiment, since the first insertion line in the FIP region is the first data connection line 81, the power connection line of the second circuit unit in the FIP region is arranged at intervals, and in one unit column, the power connection lines of the second circuit unit on both sides of the first data connection line 81 in the second direction Y are disconnected (i.e., not connected). Since the first insertion line in the non-FIP region is the first power wiring 91, the power connection line of the second circuit unit in the non-FIP region is arranged continuously, and in one unit column, the power connection lines of the second circuit unit on both sides of the first power wiring 91 in the second direction Y are connected to each other through the first power wiring 91.

[0263] Fig. 17C FIG. 1 is a plan view of the third conductive layer at the junction of the display area and the binding area. Fig. 17C As shown, the display substrate may include a display area 100 and a binding area 200 located on one side of the second direction Y of the display area 100. The binding area 200 may include at least a binding power line 210. The binding power line 210 is configured to transmit a constant first power signal and is connected to the first power line of the display area.

[0264] In an exemplary embodiment, the power connection line in the second circuit unit can extend to the binding area and connect to the binding power line 210, so that the power connection line transmits a constant first power signal, which can effectively prevent the occurrence of process static electricity.

[0265] Fig.17D FIG. 1 is a plan view of the third conductive layer at the junction of the display area and the upper frame area. Fig.17D As shown, the display substrate may include a display area 100, a frame area 300 located on both sides of the display area 100 in a first direction X, and a frame area 300 located on the opposite side of the display area 100 in a second direction Y. The frame area 300 located on the opposite side of the second direction Y of the display area 100 may be referred to as an upper frame area, and the upper frame area may include at least a frame power line 310, which is configured to transmit a constant first power signal and is connected to the first power line of the display area.

[0266] In an exemplary embodiment, the power connection line in the second circuit unit can extend to the upper frame area and connect to the frame power line 310, so that the power connection line transmits a constant first power signal, which can effectively prevent the occurrence of process static electricity.

[0267] In an exemplary embodiment, since the first display area adopts a compression method to set the circuit unit, the wiring density of the pixel driving circuit is large, and the static electricity generated in the process is easy to accumulate, resulting in damage and short circuit of the transistor in the pixel driving circuit. For example, the first scanning signal line, the second scanning signal line and the light-emitting signal line in the first conductive layer, and the first initial signal line and the second initial signal line in the second conductive layer are all relatively long signal lines. Since there is no way to transfer other signal lines, static electricity is easy to accumulate on these relatively long signal lines. When the connecting electrode of the third conductive layer is connected to the second conductive layer and the semiconductor layer through vias, the resistance of the channel region of the semiconductor layer changes from small resistance to large resistance, and static electricity is easily released at the resistance change point of the channel region, thereby damaging the transistor. In the embodiment of the present disclosure, by forming a power connection line in the second circuit unit, the power connection line is connected to the first power signal at the upper frame and the binding area, so that the static electricity of the relatively long signal lines in the first conductive layer and the second conductive layer can be transferred to the third conductive layer, and the static electricity is led out from the display area to the upper frame and the binding area through the mesh connection structure, which effectively eliminates the accumulation of static electricity generated in the process, effectively avoids the damage and short circuit of the transistor in the pixel driving circuit, and improves the product quality.

[0268] In an exemplary embodiment, the first power line 91 extending along the first direction X and the power connection line extending along the second direction Y form a mesh-like mesh connection structure for transmitting the first power signal, which can not only effectively reduce the resistance of the first power line, reduce the voltage drop of the first power signal, effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality, but also can greatly reduce the width of the binding power line in the binding area and the frame power line in the frame area, greatly reduce the width of the upper and lower frames, improve the screen-to-body ratio, and facilitate the realization of full-screen display.

[0269] In an exemplary embodiment, in this process, the third conductive layer in the second display area is etched away.

[0270] (16) Forming a fifth insulating layer and a first planar layer pattern. In an exemplary embodiment, forming the fifth insulating layer and the first planar layer pattern may include: first depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the fifth insulating film and the first planar film using a patterning process to form a fifth insulating layer covering the third conductive layer pattern and a first planar layer disposed on the fifth insulating layer, and a plurality of via holes are disposed on the fifth insulating layer and the first planar layer, such as Fig.18 shown.

[0271] In an exemplary embodiment, the plurality of via holes in each circuit unit (including the first circuit unit and the second circuit unit) in the first display area includes at least a twenty-first via hole V21 , a twenty-second via hole V22 , and a twenty-third via hole V23 .

[0272] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second connecting electrode 52 on the substrate, the first flat layer and the fifth insulating layer in the twenty-first via hole V21 are removed to expose the surface of the second connecting electrode 52, and the twenty-first via hole V21 is configured to connect the subsequently formed first data connecting electrode to the second connecting electrode 52 through the via hole.

[0273] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer and the fifth insulating layer in the twenty-second via hole V22 are removed to expose the surface of the third connecting electrode 53, and the twenty-second via hole V22 is configured to connect a subsequently formed first power line to the third connecting electrode 53 through the via hole.

[0274] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer and the fifth insulating layer in the twenty-third via hole V23 are removed to expose the surface of the fourth connecting electrode 54, and the twenty-third via hole V23 is configured to connect the subsequently formed first anode connecting electrode to the fourth connecting electrode 54 through the via hole.

[0275] In an exemplary embodiment, at least one first circuit unit may further include a twenty-fourth via hole V24. The orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the data connection block 84 on the substrate, the first flat layer and the fifth insulating layer in the twenty-fourth via hole V24 are removed, and the surface of the data connection block 84 is exposed, and the twenty-fourth via hole V24 is configured to connect the second data connection line formed subsequently to the data connection block 84 through the via hole.

[0276] In an exemplary embodiment, at least one first circuit unit may further include a twenty-fifth via hole V25. The orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the dummy connection block 94 on the substrate, the first flat layer and the fifth insulating layer in the twenty-fifth via hole V25 are removed, exposing the surface of the dummy connection block 94, and the twenty-fifth via hole V25 is configured to connect the second power supply line (or the second data connection line) formed subsequently to the dummy connection block 94 through the via hole.

[0277] In an exemplary embodiment, the twenty-fourth via hole V24 and the twenty-fifth via hole V25 may be provided only in the first circuit unit.

[0278] In an exemplary embodiment, in this process, the second display region forms a fifth insulating layer disposed on the fourth insulating layer and a first planarization layer disposed on the fifth insulating layer.

[0279] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the first planar layer, such as Fig.19A and Fig.19B As shown, Fig.19B for Fig.19A In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0280] In an exemplary embodiment, the fourth conductive layer of each circuit unit (including the first circuit unit and the second circuit unit) in the first display area includes at least a first power supply line 71 , a first data connection electrode 73 and a first anode connection electrode 74 .

[0281] In an exemplary embodiment, the shape of the first power line 71 may be a straight line or a folded line with the main portion extending along the second direction Y, and the first power line 71 is connected to the third connection electrode 53 through the twenty-second via hole V22. Since the third connection electrode 53 is respectively connected to the first region and the second electrode plate 32 of the fifth active layer through the via hole, the first power line 71 can write the first power signal into the second electrode plate 32 of the storage capacitor and the first electrode of the fifth transistor T5 respectively.

[0282] In an exemplary embodiment, the first power line 71 may be a folded line with a variable width, and the orthographic projection of the first power line 71 on the substrate at least partially overlaps the orthographic projection of the first connection electrode 51 on the substrate. Since the first connection electrode 51 serves as the first node N1 of the pixel driving circuit, the first power line 71 with a constant potential may shield the first node N1, thereby preventing the influence of the data voltage jump on the first node N1, improving the working stability of the pixel driving circuit, and improving the display effect.

[0283] In an exemplary embodiment, the orthographic projection of the first break K1 on the substrate can be located within the range of the orthographic projection of the first power line 71 on the substrate, so that the first power line 71 can block the first break K1 from above, which can effectively eliminate the film layer differences in different areas, facilitate shadow elimination, and avoid poor appearance of the display substrate.

[0284] In an exemplary embodiment, since the second circuit unit is formed with a power connection line, the first power line is connected to the third connection electrode so that the power connection line in the second circuit unit and the first power line together form a double-layer routing structure, which can effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0285] In an exemplary embodiment, the first data connection electrode 73 may be block-shaped (eg rectangular), connected to the second connection electrode 52 through the twenty-first via hole V21, and configured to be connected to a subsequently formed data signal line.

[0286] In an exemplary embodiment, in at least one second circuit unit, a power connection block 73-1 may be provided on the first data connection electrode 73, the power connection block 73-1 may be in a block shape (such as a rectangle), and may be provided between the first power line 71 and the first data connection electrode 73, the first end of the power connection block 73-1 is connected to the first data connection electrode 73, and the second end of the power connection block 73-1 is connected to the first power line 71. Since the second pixel driving circuit in the second circuit unit is not connected to the light-emitting device, the data signal line connected to the second pixel driving circuit has no data signal. The present disclosure can avoid floating of the data signal line of the second circuit unit by setting the data signal line of the second circuit unit to be connected to the first power line 71 through the first data connection electrode 73 and the power connection block 73-1.

[0287] In an exemplary embodiment, since the third pixel driving circuit in a plurality of third circuit units close to the second display area is connected to the second light-emitting device in the second display area, no power connection block 73-1 is provided in the third circuit unit, that is, there is no connection between the first data connection electrode 73 in the third circuit unit and the first power line 71.

[0288] In an exemplary embodiment, the shape of the first anode connection electrode 74 can be block-shaped (such as rectangular), the first anode connection electrode 74 is connected to the fourth connection electrode 54 through the twenty-third via V23, and the first anode connection electrode 74 is configured to be connected to the second anode connection electrode formed subsequently.

[0289] In an exemplary embodiment, the fourth conductive layer of at least one first circuit unit may further include a second data connection electrode 75. The second data connection electrode 75 may be in a block shape (e.g., rectangular) and connected to the data connection block 84 through the twenty-fourth via hole V24. The second data connection electrode 75 is configured to be connected to a second data connection line formed subsequently.

[0290] In an exemplary embodiment, the fourth conductive layer of at least one first circuit unit may further include a dummy electrode 77. The dummy electrode 77 may be in a block shape (e.g., rectangular) and connected to the dummy connection block 94 through the twenty-fifth via hole V25. The dummy electrode 77 is configured to be connected to a second power supply line (or a second data connection line) formed subsequently.

[0291] Fig.19C FIG. 3 is a schematic plan view of the fourth conductive layer at the junction of the display area and the upper frame area. In an exemplary embodiment, the frame area 300 may include an upper frame area located on the side of the display area 100 away from the binding area and left and right frame areas located on both sides of the display area 100 in the first direction X. Fig.19C As shown, the upper frame area in the frame area 300 may include at least a plurality of dummy repeating units, and at least one dummy repeating unit may include 4 first dummy units and 1 second dummy unit. The first dummy unit may include at least a first dummy pixel circuit, and the second dummy unit may include at least a second dummy pixel circuit. In an exemplary embodiment, the first dummy pixel circuit has substantially the same structure as the first pixel driving circuit in the display area 100, except that the first dummy pixel circuit is not connected to the light emitting device. The second dummy pixel circuit has substantially the same structure as the second pixel driving circuit in the display area 100, and neither of them is connected to the light emitting device.

[0292] In an exemplary embodiment, a plurality of first dummy units arranged in sequence along the second direction Y may be referred to as first dummy columns, a plurality of second dummy units arranged in sequence along the second direction Y may be referred to as second dummy columns, four first dummy columns may be provided between two adjacent second dummy columns in the first direction X, and the position of the first dummy column in the upper border area corresponds to the position of the normal unit column in the display area, and the position of the second dummy column in the upper border area corresponds to the position of the inserted unit column in the display area.

[0293] In an exemplary embodiment, the structures and connection relationships of the fourth conductive layer in the first dummy unit in the upper frame area and the first circuit unit in the display area may be substantially the same, and the first dummy unit may include at least structures such as a first power line, a first data connection electrode, and a first anode connection electrode, while in the second dummy unit in the upper frame area, neither corresponding vias nor a fourth conductive layer structure are provided on the fifth insulating layer and the first flat layer.

[0294] In an exemplary embodiment, the fifth insulating layer may be referred to as a passivation layer (PVX), and the vias provided on the fifth insulating layer may be referred to as passivation layer vias. Considering that static electricity is easily introduced into the position of the passivation layer vias, the present disclosure can effectively reduce the generation of static electricity by eliminating the PVX vias in the second dummy unit and the fourth conductive layer in the second dummy unit, and can effectively improve the efficiency of the power connection line in the second circuit unit in deriving static electricity, effectively eliminate the accumulation of static electricity generated in the process, effectively avoid damage and short circuit of transistors in the pixel driving circuit, and improve product quality.

[0295] In an exemplary embodiment, in this process, the fourth conductive layer in the second display area is etched away.

[0296] (18) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fourth conductive layer pattern, wherein a plurality of via holes are disposed on the second planar layer, such as Fig. 20 shown.

[0297] In an exemplary embodiment, the plurality of via holes in each circuit unit (including the first circuit unit and the second circuit unit) in the first display area includes at least a thirty-first via hole V31 and a thirty-second via hole V32.

[0298] In an exemplary embodiment, the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the first data connection electrode 73 on the substrate, the second flat layer in the thirty-first via hole V31 is removed to expose the surface of the first data connection electrode 73, and the thirty-first via hole V31 is configured to connect a subsequently formed data signal line to the first data connection electrode 73 through the via hole.

[0299] In an exemplary embodiment, the orthographic projection of the thirty-second via hole V32 on the substrate is within the range of the orthographic projection of the first anode connecting electrode 74 on the substrate, the second flat layer in the thirty-second via hole V32 is removed to expose the surface of the first anode connecting electrode 74, and the thirty-second via hole V32 is configured to connect a subsequently formed second anode connecting electrode to the first anode connecting electrode 74 through the via hole.

[0300] In an exemplary embodiment, at least one circuit unit may further include a thirty-third via hole V33. The orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the second data connection electrode 75 on the substrate, the second flat layer in the thirty-third via hole V33 is removed, and the surface of the second data connection electrode 75 is exposed, and the thirty-third via hole V33 is configured to connect the second data connection line 82 formed subsequently to the second data connection electrode 75 through the via hole.

[0301] In an exemplary embodiment, at least one circuit unit may further include a thirty-fourth via hole V34. The orthographic projection of the thirty-fourth via hole V34 on the substrate is located within the range of the orthographic projection of the dummy electrode 77 on the substrate, the second flat layer in the thirty-fourth via hole V34 is removed, exposing the surface of the dummy electrode 77, and the thirty-fourth via hole V34 is configured to connect a second power supply line (or a second data connection line) formed subsequently to the dummy electrode 77 through the via hole.

[0302] In an exemplary embodiment, in this process, the second display area forms a second planar layer disposed on the first planar layer.

[0303] (19) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern, patterning the fourth conductive film using a patterning process, and forming a fifth conductive layer disposed on the first planar layer, such as Fig.21A and Fig. 21B As shown, Fig. 21B for Fig.21A In an exemplary embodiment, the fifth conductive layer may be referred to as a third source-drain metal (SD3) layer.

[0304] In an exemplary embodiment, the fifth conductive layer of each circuit unit (including the first circuit unit and the second circuit unit) in the first display area includes at least: a data signal line 72 and a second anode connection electrode 76 .

[0305] In an exemplary embodiment, the shape of the data signal line 72 may be a straight line or a folded line with the main part extending along the second direction Y, and the data signal line 72 is connected to the first data connection electrode 73 through the thirty-first via hole V31. In the first circuit unit, since the first data connection electrode 73 is connected to the second connection electrode 52 through the via hole, and the second connection electrode 52 is connected to the first region of the fourth active layer through the via hole, the data signal line 72 can write the data signal to the first electrode of the fourth transistor T4. In the second circuit unit, since the first data connection electrode 73 is connected to the first power line 71 through the power connection block 73-1, the data signal line 72 has the potential of the first power line, which effectively avoids the floating of the data signal line of the second circuit unit.

[0306] In an exemplary embodiment, the second anode connection electrode 76 may be in a block shape (e.g., a rectangular shape), and the second anode connection electrode 76 is connected to the first anode connection electrode 74 through the thirty-second via hole V32, and the second anode connection electrode 76 is configured to be connected to the subsequently formed anode. Since the first anode connection electrode 74 is connected to the fourth connection electrode 54 through the via hole, and the fourth connection electrode 54 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the via hole, the pixel driving circuit can output a driving current to the light-emitting device.

[0307] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit in the first display area may further include a second inserted line, which may be in the shape of a straight line or a broken line extending along the second direction Y and may be located on the side opposite to the first direction X of the data signal line 72.

[0308] In an exemplary embodiment, at least one second insertion line may include at least a second data connection line 82 and a second power line 92 arranged in sequence along the second direction Y, the second data connection line 82 may be arranged in the first area (FIP area), and the second power line 92 may be arranged in the second area (non-FIP area or SIP area).

[0309] In an exemplary embodiment, in the second region (non-FIP region or SIP region), the second insertion line may include only the second power trace 92 .

[0310] In an exemplary embodiment, a second break K2 may be provided between the second data connection line 82 and the second power supply line 92 in the same unit column, and the second break K2 may cut off the second data connection line 82 located in the FIP area from the second power supply line 92 located in the non-FIP area, so that the second data connection line 82 and the second power supply line 92 on both sides of the second break K2 are insulated from each other.

[0311] In an exemplary embodiment, the end of the second data connection line 82 away from the second break K2 is extended to the binding area and then connected to the data lead-out line, and the end of the second data connection line 82 close to the second break K2 is connected to the second data connection electrode 75 through the thirty-third via hole V33. Since the second data connection electrode 75 is connected to the data connection block 84 through the via hole, the data connection block 84 is connected to the first data connection line 81 through the data connection bar 83, and the first data connection line 81 is configured to be connected to the data signal line in the display area, the first data connection line 81 extending along the first direction X of the main part and the second data connection line 82 extending along the second direction Y of the main part are mutually connected, and the data lead-out line in the binding area is connected to the data signal line in the display area through the first data connection line 81 and the second data connection line 82.

[0312] In an exemplary embodiment, in at least one circuit unit, the second data link line 82 may be connected to the dummy electrode 77 through the thirty-fourth via hole V34 .

[0313] In an exemplary embodiment, the first display area (including the FIP area and the non-FIP area) may include a plurality of first circuit units and a plurality of second circuit units, the second insertion line may be provided only in the first circuit unit, and the second circuit unit is not provided with the second data connection line 82 and the second power supply line 92. Since the SD1 layer of the second circuit unit is provided with a power supply connection line, there is a certain difference in the circuit structure between the first circuit unit and the second circuit unit. The present disclosure can reduce the circuit difference between the first circuit unit and the second circuit unit by providing the second insertion line only in the first circuit unit, avoid the load difference of the data signal caused by the circuit difference, and improve the display quality.

[0314] In an exemplary embodiment, the positive projection of the second data connection line 82 on the substrate at least partially overlaps with the positive projection of the first power line on the substrate. The first power line with a constant potential can shield the influence of the data voltage jump of the second data connection line 82 on the key nodes of the pixel driving circuit, thereby improving the working stability of the pixel driving circuit and improving the display effect.

[0315] In an exemplary embodiment, the orthographic projection of the second break K2 on the substrate can be within the range of the orthographic projection of the first power line on the substrate, so that the first power line can raise the second break K2 from the bottom, which can effectively eliminate the film layer differences in different areas, facilitate shadow elimination, and avoid poor appearance of the display substrate.

[0316] In an exemplary embodiment, the second power supply line 92 can be connected to the dummy electrode 77 through the thirty-fourth via V34, so that the display area has basically the same transfer area structure, which improves the uniformity of the etching process, and different areas can achieve the same display effect under transmitted and reflected light, realizing shadow elimination, effectively avoiding the poor appearance of the display substrate and the occurrence of off-screen watermarks, and improving the display quality.

[0317] In an exemplary embodiment, the second power line 92 can be connected to the power lead that transmits the second power signal through the border area or the binding area, thereby realizing a second power line located in the panel (VSS in Panel, referred to as SIP) structure. This can not only effectively reduce the resistance of the second power line, reduce the voltage drop of the second power signal, effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality, but also can greatly reduce the width of the border power lead, greatly reduce the width of the left and right borders, and improve the screen-to-body ratio, which is conducive to achieving full-screen display.

[0318] In some possible implementations, the second power line may be connected to the first power line, or may be connected to the first initial signal line, or may be connected to the second initial signal line, which is not limited in the present disclosure.

[0319] In an exemplary embodiment, in this process, the fifth conductive layer in the second display area is etched away.

[0320] The subsequent preparation process may include forming a third flat layer, on which an anode via is provided, the anode via exposes the surface of the second anode connection electrode, and the anode via is configured to connect a subsequently formed anode to the second anode connection electrode through the via.

[0321] At this point, the driving structure layer of this embodiment is prepared on the substrate. In a plane parallel to the display substrate, the driving structure layer may include a first display area and a second display area, the first display area may at least partially surround the second display area, the first display area may include a plurality of circuit units, at least one circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving structure layer of the first display area may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first flat layer, a fourth conductive layer, a second flat layer, a fifth conductive layer, and a third flat layer sequentially arranged on the substrate. The semiconductor layer may include at least an active layer of multiple transistors, the first conductive layer may include at least a first scanning signal line, a second scanning signal line, a light-emitting signal line and a first electrode plate of a storage capacitor, the second conductive layer may include at least a first initial signal line, a second initial signal line and a second electrode plate of a storage capacitor, the third conductive layer may include at least a first data connection line, a first power supply line and multiple connection electrodes, the fourth conductive layer may include at least a first power supply line, and the fifth conductive layer may include at least a data signal line, a second data connection line and a second power supply line.

[0322] In an exemplary embodiment, the substrate may be a flexible substrate, or may be a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and one or more of textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si).

[0323] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer may be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo), etc., or may be made of alloy materials composed of metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc., and may be a single layer structure, or may be a multilayer composite structure, such as Ti / Al / Ti, etc. The first planar layer, the second planar layer and the third planar layer may be made of organic materials, such as resin or polyimide.

[0324] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer may be prepared on the driving structure layer, and an encapsulation structure layer may be prepared on the light emitting structure layer, which will not be described in detail here.

[0325] An exemplary embodiment of the present disclosure provides a display substrate, which, by inserting a circuit unit, a FIP and a SIP structure design, not only ensures the normal operation of the under-screen camera area, but also eliminates the differences in pixel driving circuits in various areas, avoids the defects such as screen-off watermarks caused by differences in pixel driving circuits, and achieves an integrated black display effect.

[0326] The disclosed embodiment adopts a 4-in-1 design in the first display area. The first pixel driving circuit drives the light-emitting device in the first display area, the third pixel driving circuit drives the light-emitting device in the second display area, and the second pixel driving circuit is used as a dummy pixel circuit. This can not only ensure the display effects of the bright and dark states of the second display area, but also ensure that there is no obvious difference between the first display area and the second display area.

[0327] The disclosed embodiment realizes a FIP structure by setting a first data connection line and a second data connection line in the display area, and connecting the data lead line in the binding area to the data signal line through the first data connection line and the second data connection line. This makes it unnecessary to set a fan-shaped oblique line in the lead line area, effectively reduces the length of the lead line area, greatly reduces the width of the lower frame, improves the screen-to-body ratio, and is conducive to achieving full-screen display.

[0328] The disclosed embodiment effectively reduces the circuit difference between the first circuit unit and the second circuit unit by setting the second insertion line in the first circuit unit and the power connection line in the second circuit unit, thereby avoiding the load difference of the data signal caused by the circuit difference and improving the display quality.

[0329] The embodiment of the present disclosure forms a power connection line in the second circuit unit, and the power connection line is connected to the first power signal at the upper frame and the binding area, thereby effectively eliminating the static electricity accumulation generated in the process, effectively avoiding transistor damage and short circuit in the pixel driving circuit, and improving product quality.

[0330] The disclosed embodiment can effectively reduce the generation of static electricity by eliminating the PVX via of the second dummy unit in the upper frame area and the fourth conductive layer in the second dummy unit, effectively improve the efficiency of the power connection line in the second circuit unit in conducting static electricity, and effectively eliminate the accumulation of static electricity generated in the process.

[0331] The disclosed embodiment forms a power connection line in the second circuit unit, and the power connection line and the first power line form a mesh-like interconnected structure for transmitting the first power signal. This can not only effectively reduce the resistance of the first power line, reduce the voltage drop of the first power signal, and effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality, but also can greatly reduce the width of the binding power line in the binding area and the frame power line in the frame area, greatly reduce the width of the upper and lower frames, improve the screen-to-body ratio, and facilitate the realization of full-screen display.

[0332] The disclosed embodiment realizes a SIP structure by setting a second power line to transmit a second power signal, which can not only effectively reduce the resistance of the second power line, reduce the voltage drop of the second power signal, effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality, but also can greatly reduce the width of the frame power lead, greatly reduce the left and right frame widths, improve the screen-to-body ratio, and facilitate the realization of full-screen display.

[0333] The disclosed embodiment utilizes the first power line to cover the first break on the first data connection line from above, and utilizes the first power line to support the second break on the second data connection line from below, which can effectively eliminate the difference in film layers in different areas, is beneficial to eliminating shadows, avoids poor appearance of the display substrate, and improves display quality.

[0334] The disclosed embodiments provide dummy connecting strips, dummy connecting blocks and dummy electrodes so that the display area has substantially the same transfer area structure, thereby improving the uniformity of the etching process. Different areas can achieve the same display effect under transmitted and reflected light, thus achieving shadow elimination, effectively avoiding the poor appearance of the display substrate and the occurrence of off-screen watermarks, and improving the display quality.

[0335] In the embodiment of the present disclosure, by arranging the data signal line of the second circuit unit to be connected to the first power line, it is possible to avoid floating of the data signal line in the second circuit unit and reduce the impact on the pixel driving circuit.

[0336] The preparation process of the embodiment of the present disclosure is well compatible with the existing preparation process, and the process is simple to realize, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0337] The structure and preparation process shown in the above disclosure are merely exemplary. In the exemplary implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the first power supply line can be connected to the second power supply signal. For another example, the second power supply line can be connected to the first power supply signal, which is not limited in the present disclosure.

[0338] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0339] The present disclosure also provides a method for preparing a display substrate to manufacture the display substrate provided in the above embodiment. In an exemplary embodiment, the preparation method may include:

[0340] forming a driving structure layer on the substrate, and forming a light-emitting structure layer on the driving structure layer;

[0341] The driving structure layer includes a plurality of circuit repetition units, and the light-emitting structure layer includes a plurality of first light-emitting devices; at least one circuit repetition unit includes M first circuit units and 1 second circuit unit, the first circuit unit includes at least a first pixel driving circuit, the first pixel driving circuit is respectively connected to a data signal line, a first power line and the first light-emitting device, the second circuit unit includes at least a second pixel driving circuit, the second pixel driving circuit is respectively connected to the data signal line and the first power line, but is not connected to the first light-emitting device; the driving structure layer also includes at least one first insertion line extending along a first direction, at least one second insertion line extending along a second direction, and at least one power connection line extending along a second direction, the first direction and the second direction intersect; the second insertion line is connected to the data signal line through the first insertion line, the power connection line is connected to the first power line, the second insertion line is arranged in the first circuit unit, and the power connection line is arranged in the second circuit unit.

[0342] The present disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.

[0343] Although the embodiments disclosed in the present disclosure are as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions or omissions may be made to the forms and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: It comprises a driving structure layer arranged on a substrate and a light emitting structure layer arranged on a side of the driving structure layer away from the substrate; the driving structure layer comprises a plurality of circuit repeating units, and the light emitting structure layer comprises a plurality of first light emitting devices; At least one circuit repetition unit includes M first circuit units and 1 second circuit unit, M is a positive integer greater than or equal to 3, the first circuit unit includes at least a first pixel driving circuit, the first pixel driving circuit is respectively connected to the data signal line, the first power line and the first light-emitting device, the second circuit unit includes at least a second pixel driving circuit, the second pixel driving circuit is respectively connected to the data signal line and the first power line, but is not connected to the first light-emitting device; the driving structure layer also includes at least one first insertion line extending along the first direction, at least one second insertion line extending along the second direction, and at least one power connection line extending along the second direction, the first direction and the second direction intersect; The second inlet line is connected to the data signal line through the first inlet line, the power connection line is connected to the first power line, the second inlet line is arranged in the first circuit unit, and the power connection line is arranged in the second circuit unit.

2. The display substrate according to claim 1, characterized in that: M is equal to 4.

3. The display substrate according to claim 1, characterized in that: At least one first insertion line includes a first data connection line and a first power line arranged in sequence along the first direction, and a first break is arranged between the first data connection line and the first power line; at least one second insertion line includes a second data connection line and a second power line arranged in sequence along the second direction, and a second break is arranged between the second data connection line and the second power line; the second data connection line is connected to the data signal line through the first data connection line.

4. The display substrate according to claim 3, characterized in that: The orthographic projection of at least one first break on the display substrate plane at least partially overlaps with the orthographic projection of the first power line on the display substrate plane, and / or the orthographic projection of at least one second break on the display substrate plane at least partially overlaps with the orthographic projection of the first power line on the display substrate plane.

5. The display substrate according to claim 3, characterized in that: In at least one second circuit unit, the power connection line is connected to the first power line to form a mesh connection structure.

6. The display substrate according to claim 3, characterized in that: At least one first circuit unit also includes a data connection block, and the second data connection line is connected to the first data connection line through the data connection block; at least one first circuit unit also includes a dummy connection block, and the second power line is connected to the dummy connection block; the position and shape of the data connection block in one first circuit unit are the same as the position and shape of the dummy connection block in another first circuit unit.

7. The display substrate according to claim 1, characterized in that: The first pixel driving circuit and the second pixel driving circuit each include at least a storage capacitor, a first initialization transistor and a first light-emitting control transistor, wherein the first electrode of the first initialization transistor is connected to the fifth connection electrode, the second electrode of the first initialization transistor is connected to the first electrode plate of the storage capacitor through the first connection electrode, and the first electrode of the first light-emitting control transistor is connected to the second electrode plate of the storage capacitor through the third connection electrode; in at least one first circuit unit, the first connection electrode, the third connection electrode and the fifth connection electrode are arranged in isolation; in at least one second circuit unit, the first connection electrode is respectively connected to the third connection electrode and the fifth connection electrode to form the power connection line.

8. The display substrate according to claim 7, characterized in that: The first power line is connected to the third connection electrode.

9. The display substrate according to claim 7, characterized in that: Both the first circuit unit and the second circuit unit include a first initial signal line extending along the first direction; in at least one first circuit unit, the fifth connecting electrode is respectively connected to the first electrode of the first initialization transistor and the first initial signal line; in at least one second circuit unit, the fifth connecting electrode is connected to the first electrode of the first initialization transistor and is not connected to the first initial signal line.

10. The display substrate according to claim 1, characterized in that: At least one second circuit unit, the data signal line is connected to the first power line.

11. The display substrate according to any one of claims 1 to 10, characterized in that: The display substrate includes a display area, a binding area located on one side of the display area, and a frame area located on the other side of the display area, the display area includes at least a first display area and a second display area, the first display area at least partially surrounds the second display area, the first display area is configured to display images, and the second display area is configured to display images and transmit light; the driving structure layer of the first display area includes a plurality of circuit repeating units, and the light-emitting structure layer of the first display area includes a plurality of first light-emitting devices.

12. The display substrate according to claim 11, characterized in that: At least one circuit repetition unit includes M first circuit units and 1 third circuit unit, and at least one third circuit unit includes at least a third pixel driving circuit; the light-emitting structure layer of the second display area includes multiple second light-emitting devices, and the third pixel driving circuit is connected to the second light-emitting device.

13. The display substrate according to claim 11, characterized in that: The driving structure layer includes at least a first source-drain metal layer, a second source-drain metal layer arranged on a side of the first source-drain metal layer away from the substrate, and a third source-drain metal layer arranged on a side of the second source-drain metal layer away from the substrate; the power connection line and the first insertion line are arranged in the first source-drain metal layer, the first power line is arranged in the second source-drain metal layer, and the data signal line and the second insertion line are arranged in the third source-drain metal layer.

14. The display substrate according to claim 13, characterized in that: The frame area at least includes an upper frame area located on a side of the display area away from the binding area, the upper frame area includes a plurality of dummy repeating units, at least one dummy repeating unit includes M first dummy units and 1 second dummy unit, the first dummy unit includes at least a first dummy pixel circuit, the second dummy unit includes at least a second dummy pixel circuit, and the first dummy pixel circuit and the second dummy pixel circuit are not connected to the light-emitting device; the driving structure layer also includes a passivation layer arranged between the first source-drain metal layer and the second source-drain metal layer, and in at least one first dummy unit, the passivation layer is provided with at least one via hole connecting the first source-drain metal layer with the second source-drain metal layer; In at least one second dummy unit, no via hole is disposed on the passivation layer.

15. The display substrate according to claim 14, characterized in that: The second source-drain metal layer is disposed in at least one first dummy unit, and the second source-drain metal layer is not disposed in at least one second dummy unit.

16. The display substrate according to claim 11, characterized in that: At least one power connection line is connected to a binding power line of the binding area, and the binding power line is configured to transmit a first power signal.

17. The display substrate according to claim 11, characterized in that: At least one power connection line is connected to a frame power line in the frame area, and the frame power line is configured to transmit a first power signal.

18. The display substrate according to claim 11, characterized in that: At least one second insertion line includes a second power line, and the second power line is connected to a power lead in the frame area or the binding area, and the power lead is configured to transmit a second power signal.

19. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 18.

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