Display device

Abstract

The display device includes: a pixel electrode; a pixel defining layer on the pixel electrode and having an opening exposing at least a portion of the pixel electrode; a bank layer on the pixel defining layer; a suspended layer on the bank layer; an intermediate layer on the pixel electrode; and an opposing electrode on the intermediate layer. The overhang layer includes a tip portion protruding toward the pixel electrode from a point where a bottom surface of the overhang layer and a side surface of the bank layer facing the pixel electrode meet each other, and a height from an upper surface of the pixel defining layer to an upper surface of the bank layer is different from a height from the upper surface of the pixel defining layer to a bottom surface of the tip portion of the overhang layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0039059 filed on March 24, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0055657 filed on April 27, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0003] Various aspects of one or more embodiments of the present disclosure are directed to a display device having improved reliability and a method of manufacturing the display device. Background Art

[0004] Recently, the use of display devices has become diversified. In addition, as the thickness of the display device becomes smaller and the weight of the display device becomes lighter, the use range of the display device has become wider.

[0005] Typically, a display device includes a plurality of pixels for emitting light by receiving an electrical signal to display an image. The pixels of an organic light emitting display (OLED) device include an organic light emitting diode as a display element and a drive circuit for controlling the electrical signal applied to the display element. The drive circuit includes a thin film transistor (TFT), a storage capacitor, and a plurality of circuits. The plurality of circuits provide a data signal, a drive voltage, a common voltage, etc. to the drive circuit of each pixel.

[0006] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art. Utility Model Content

[0007] In a comparative example, the display device may have difficulty in achieving high resolution, or may have low emission efficiency due to structural and process limitations.

[0008] One or more embodiments of the present disclosure relate to a display device that displays high-quality images. However, the present disclosure is not limited to the above aspects and features.

[0009] Additional aspects and features will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of one or more of the presented embodiments of the disclosure.

[0010] According to one or more embodiments of the present disclosure, a display device includes: a pixel electrode; a pixel defining layer on the pixel electrode and having an opening exposing at least a portion of the pixel electrode; a bank layer on the pixel defining layer; an overhang layer on the bank layer; an intermediate layer on the pixel electrode; and an opposing electrode on the intermediate layer. The overhang layer includes a tip protruding toward the pixel electrode from a point where a bottom surface of the overhang layer and a side surface of the bank layer facing the pixel electrode meet each other, and a height from an upper surface of the pixel defining layer to an upper surface of the bank layer is different from a height from an upper surface of the pixel defining layer to a bottom surface of the tip of the overhang layer.

[0011] In an embodiment, the tip of the overhang layer may have an opening overlapping the pixel electrode; the bank layer may have an opening overlapping the pixel electrode; and a width of the opening of the tip may be smaller than a width of the opening of the bank layer.

[0012] In an embodiment, a height from an upper surface of the pixel defining layer to a bottom surface of the tip of the overhang layer may be greater than a height from an upper surface of the pixel defining layer to an upper surface of the bank layer.

[0013] In an implementation, the opposite electrode may be electrically connected to the bank layer.

[0014] In an embodiment, the counter electrode may be electrically connected to the overhanging layer.

[0015] In an embodiment, the overhanging layer may include a conductive material.

[0016] In an embodiment, a height from an upper surface of the pixel defining layer to a bottom surface of the tip of the overhang layer may be smaller than a height from an upper surface of the pixel defining layer to an upper surface of the bank layer.

[0017] In an implementation, the opposite electrode may be electrically connected to the bank layer.

[0018] In an implementation, the overhanging layer may include an organic insulating material or an inorganic insulating material.

[0019] In an embodiment, the counter electrode may be electrically connected to the overhanging layer.

[0020] In an embodiment, the overhanging layer may include a conductive material.

[0021] In an embodiment, the display device may further include: an encapsulation layer on the overhanging layer and the opposite electrode; a dummy intermediate layer on the overhanging layer; and a dummy opposite electrode on the dummy intermediate layer. The dummy intermediate layer and the dummy opposite electrode may be located between the overhanging layer and the encapsulation layer; the dummy intermediate layer may include the same material as that of the intermediate layer; and the dummy opposite electrode may include the same material as that of the opposite electrode.

[0022] According to one or more embodiments of the present disclosure, a method for manufacturing a display device includes: forming a pixel electrode on a substrate; forming a pixel defining layer having an opening exposing at least a portion of the pixel electrode; forming a preliminary bank layer on the pixel defining layer and the pixel electrode; forming a bank layer having an opening overlapping the opening of the pixel defining layer by patterning the preliminary bank layer; forming a preliminary sacrificial layer to fill the opening of the pixel defining layer and the opening of the bank layer and cover the bank layer; forming a sacrificial layer by patterning the preliminary sacrificial layer; forming a preliminary overhang layer on the bank layer and the sacrificial layer; forming an overhang layer having an opening overlapping the opening of the pixel defining layer and the opening of the bank layer by patterning the preliminary overhang layer; and removing the sacrificial layer. Forming the overhang layer includes removing a portion of the overhang layer so that the width of the opening of the overhang layer is smaller than the width of the opening of the bank layer.

[0023] In an implementation, the preliminary sacrificial layer may be formed of a material including a photosensitive compound.

[0024] In an embodiment, forming the sacrificial layer may include removing the preliminary sacrificial layer so that a height from an upper surface of the pixel defining layer to an upper surface of the sacrificial layer may be greater than a height from an upper surface of the pixel defining layer to an upper surface of the bank layer.

[0025] In an embodiment, the method may further include: forming an intermediate layer on the pixel electrode; and forming an opposing electrode on the intermediate layer. The opposing electrode may be formed to be electrically connected to the overhanging layer.

[0026] In an embodiment, forming the sacrificial layer may include removing the preliminary sacrificial layer so that a height from an upper surface of the pixel defining layer to an upper surface of the sacrificial layer may be less than a height from an upper surface of the pixel defining layer to an upper surface of the bank layer.

[0027] In an embodiment, the method may further include: forming an intermediate layer on the pixel electrode; and forming an opposing electrode on the intermediate layer. The opposing electrode may be formed to be electrically connected to the bank layer.

[0028] In an embodiment, the counter electrode may be formed to be electrically connected to the overhanging layer.

[0029] In an implementation, forming the bank layer may include removing the preliminary bank layer by dry etching.

[0030] The above and other aspects and features of the present disclosure will become more apparent by referring to the detailed description with reference to the accompanying drawings, the claims and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings, in which:

[0032] Figure 1is a perspective view schematically showing a display device according to an embodiment;

[0033] Figure 2 It is schematically shown Figure 1 A cross-sectional view of a display device taken along line AA';

[0034] Figure 3 is a plan view schematically showing a display panel of a display device according to an embodiment;

[0035] Figure 4 and Figure 5 is an equivalent circuit diagram schematically showing a pixel of a display device according to one or more embodiments;

[0036] Figure 6 and Figure 7 is a cross-sectional view schematically showing a display device according to one or more embodiments;

[0037] Figure 8 and Fig. 9 is a cross-sectional view schematically showing a display device according to one or more embodiments;

[0038] Figures 10 to 17 are cross-sectional views sequentially showing some processes of a method for manufacturing a display device according to an embodiment;

[0039] Figures 18 to 24 are cross-sectional views sequentially showing some processes of a method of manufacturing a display device according to an embodiment; and

[0040] Fig.25 is a cross-sectional view showing a stack structure of a light emitting diode according to an embodiment. DETAILED DESCRIPTION

[0041] Hereinafter, each embodiment will be described in more detail with reference to the accompanying drawings, wherein the same reference numerals refer to the same elements. However, the present disclosure can be implemented in a variety of different forms, and should not be construed as being limited to the embodiments shown herein. More specifically, these embodiments are provided as examples so that the present disclosure will be comprehensive and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, unnecessary processes, elements and techniques for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, in all drawings and written descriptions in their entirety, the same reference numerals refer to the same elements, and therefore, their redundant descriptions will not be repeated.

[0042] When a certain embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two processes described in succession can be performed simultaneously or substantially simultaneously or in the reverse order of the described order.

[0043] In the accompanying drawings, for clarity, the relative size, thickness and ratio of elements, layers and regions may be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "below", "below", "below", "below", "above", "on" may be used herein to describe the relationship between an element or feature and another element (multiple elements) or feature (multiple features) as shown in the figure. It should be understood that, in addition to the orientation depicted in the accompanying drawings, spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, the element described as being "below" or "below" or "below" of other elements or features will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0044] In the accompanying drawings, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other or substantially perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0045] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer or first part described below may be referred to as the second element, second component, second region, second layer or second part.

[0046] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intervening elements or layers. For example, when described as "component B is directly disposed on component A," this may mean that there is no separate adhesive layer or adhesive member between component A and component B. In this case, after component A is formed, component B may be formed on the base surface provided by component A by a continuous process. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it may be directly electrically connected to the other layer, region, or element, and / or may be indirectly electrically connected with one or more intervening layers, regions, or elements between the two. In addition, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0047] As used in the present disclosure, the phrase "A and B overlap each other" may mean that in a direction (e.g., the z-axis direction) and in a plane view (e.g., an xy plane view) perpendicular to or substantially perpendicular to the direction, at least a portion of A and at least a portion of B overlap each other.

[0048] The terms used herein are used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, as used herein, the singular forms "a" and "an" are intended to also include plural forms. It will be further understood that when used in this specification, the terms "comprises", "comprising", "includes", "including", "has", "having" and "have" specify the existence of the features, wholes, steps, operations, elements and / or parts described, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or their combinations. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. For example, "A and / or B" means A or B or A and B. When located after a list of elements, expressions such as "at least one of..." modify the elements of the entire list rather than modifying the individual elements in the list. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0049] As used herein, the terms "substantially," "approximately," and similar terms are used as approximate terms rather than as terms of degree, and are intended to allow for inherent deviations in measurements or calculations that will be recognized by those of ordinary skill in the art. For example, "approximately" may represent values ​​within the range of ±30%, ±20%, ±10%, or ±5% of any stated number. In addition, "may" used in describing embodiments of the present disclosure means "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be understood as synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0051] Figure 1 is a perspective view schematically showing a display device according to an embodiment.

[0052] Reference Figure 1 The display panel of the display device 1 may include a display area DA and a non-display area NDA outside the display area DA. The display panel including the display area DA may be understood as a substrate 100 of the display panel (for example, referring to Figure 3 ) includes a display area DA. Hereinafter, for convenience, the substrate 100 will be described in more detail as having a display area DA and a non-display area NDA.

[0053] The display area DA may display an image through the pixels P arranged in the display area DA. The non-display area NDA is arranged outside the display area DA and does not display an image. For example, the non-display area NDA may completely surround the display area DA (e.g., near the periphery of the display area DA). A driver or the like for providing an electrical signal or power to the display area DA may be arranged in the non-display area NDA. A pad may be arranged in the non-display area NDA, and the pad is an area to which an electronic device or a printed circuit board can be electrically connected.

[0054] In an embodiment, Figure 1The display area DA is shown to have a polygonal shape (e.g., a rectangular shape) whose length in the x direction is less than that in the y direction, but the present disclosure is not limited thereto. In another embodiment, the display area DA may have various suitable shapes such as a polygon with N sides (where N is a natural number of 3 or more), a circle, or an ellipse. Figure 1 It is illustrated that the corner portion of the display area DA has a shape including a vertex where sides (eg, straight lines) meet, but in another embodiment, the corner portion of the display area DA may be a polygonal shape with a rounded corner portion.

[0055] In the following, for convenience, the case where the display device 1 is an electronic device such as a smartphone will be described in more detail, but the present disclosure is not limited thereto. The display device 1 can be a portable electronic device such as a mobile phone, a smartphone, a desktop personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an ultra-mobile PC (UMPC), etc., and can also be used in various suitable products such as televisions, notebook computers, monitors, billboards, Internet of Things (IoT) devices, etc. In addition, the display device 1 according to the embodiment can also be used as a wearable device such as a smart watch, a watch phone, a glasses display or a head-mounted display (HMD). In addition, the display device 1 according to the embodiment can also be applied to the dashboard of a vehicle, the central panel of a vehicle or a central information display (CID) set on the dashboard, a rearview mirror display replacing the side mirror of the vehicle, or a display screen set on the rear surface of the front seat as an entertainment device for passengers in the rear seat of the vehicle.

[0056] Figure 2 It is schematically shown Figure 1 2 is a cross-sectional view of a section of the display device 1 taken along line AA′.

[0057] Reference Figure 2 The display device 1 may include a display panel DP, an input sensing layer 40 disposed on the display panel DP, and an optical function layer 50. The display panel DP, the input sensing layer 40, and the optical function layer 50 may be covered by a window 60.

[0058] The display panel DP may display an image. The display panel DP includes pixels arranged in a display area DA. The pixels may include a display element and a pixel circuit connected to the display element. The display element may include an organic light emitting diode, a quantum dot organic light emitting diode, and the like.

[0059] The input sensing layer 40 may obtain coordinate information according to an external input (e.g., a touch event). The input sensing layer 40 may include a sensing electrode (or a touch electrode) and a trace connected to the sensing electrode. The input sensing layer 40 may be disposed on the display panel DP. The input sensing layer 40 may sense an external input by a mutual capacitance method and / or a self-capacitance method.

[0060] The input sensing layer 40 may be formed directly on the display panel DP, or may be formed separately and then connected to (e.g., attached to or bonded to) the display panel DP via an adhesive layer (e.g., such as an optically transparent adhesive). For example, the input sensing layer 40 may be formed continuously after the process of forming the display panel DP. In this case, the input sensing layer 40 may be understood as part of the display panel DP, and no adhesive layer may be provided between the input sensing layer 40 and the display panel DP. Figure 2 The input sensing layer 40 is shown between the display panel DP and the optical functional layer 50 , but in another embodiment the input sensing layer 40 may be disposed above the optical functional layer 50 .

[0061] The optical function layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (e.g., external light) incident from the outside through the window 60 toward the display panel DP. In an embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged according to the color of each light emitted in the pixels of the display panel DP.

[0062] In another embodiment, the anti-reflection layer may include a retarder and a polarizer. The retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type polarizer may include a stretched synthetic resin film, and the liquid crystal coating type polarizer may include liquid crystals arranged in a suitable arrangement (e.g., a specific or predetermined arrangement). The retarder and the polarizer may further include a protective film. The protective film of the retarder and the polarizer may be defined as a base layer of the anti-reflection layer.

[0063] In another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer arranged at different layers from each other (e.g., in different layers or on different layers). The first reflected light and the second reflected light reflected from the first reflective layer and the second reflective layer, respectively, may destructively interfere with each other, and thus the reflectivity of the external light may be reduced.

[0064] In an embodiment, the optical function layer 50 may be continuously formed after the process of forming the display panel DP and / or the input sensing layer 40. In this case, an adhesive layer may not be provided between the optical function layer 50 and the input sensing layer 40 and / or between the input sensing layer 40 and the display panel DP.

[0065] In certain embodiments, a layer including an optically transparent adhesive or an optically transparent resin may be further disposed between the window 60 and the optical functional layer 50 .

[0066] Figure 3 is a plan view schematically showing a display panel of a display device according to an embodiment.

[0067] The display device according to the embodiment may include a display panel DP. Figure 3 It may be understood as a view (eg, a plan view) of the substrate 100 of the display panel DP.

[0068] Reference Figure 3 , the display panel DP includes a display area DA and a non-display area NDA outside the display area DA. The display area DA is a portion where an image is displayed, and a plurality of pixels P may be arranged in the display area DA. Figure 3 The display area DA is shown to have a rectangular or substantially rectangular shape with rounded corners, but the present disclosure is not limited thereto. As described above, the display area DA may have various suitable shapes such as a polygon with N sides (where N is a natural number of 3 or more), a circle, or an ellipse.

[0069] Each pixel P may refer to a sub-pixel and may include a display element such as an organic light emitting diode (OLED). Each pixel P may emit, for example, red light, green light, blue light, white light, or the like.

[0070] The non-display area NDA may be outside the display area DA. External circuits for driving the pixels P may be arranged in the non-display area NDA. For example, the first scan drive circuit 11, the second scan drive circuit 12, the emission control drive circuit 13, the terminal 14, the drive power line 15, and the common power line 16 may be arranged in the non-display area NDA.

[0071] The first scan driving circuit 11 may provide a scan signal to the pixel P through the scan line SL. The second scan driving circuit 12 may be arranged in parallel with the first scan driving circuit 11, and the display area DA is located between the first scan driving circuit 11 and the second scan driving circuit 12. Some of the pixels P in the display area DA may be electrically connected to the first scan driving circuit 11, and the other remaining pixels P may be connected to the second scan driving circuit 12. When necessary, the second scan driving circuit 12 may be omitted, and all the pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit 11.

[0072] The emission control driving circuit 13 may be disposed on one side of the first scanning driving circuit 11, and may provide an emission control signal to the pixel P through the emission control line EL. Figure 3 The emission control driving circuit 13 is shown to be arranged only on one side of the display area DA, but similar to the arrangement of the first scan driving circuit 11 and the second scan driving circuit 12, the emission control driving circuit 13 can also be arranged on the opposite side of the display area DA.

[0073] In an embodiment, the non-display area NDA may include a curved area extending toward one side of the display area DA (e.g., in the -y direction). The curved area is curved toward the rear surface of the display area DA, thereby reducing the area of ​​the non-display area NDA visible when viewed from the front surface of the display device.

[0074] The driving chip 20 may be disposed in the non-display area NDA. The driving chip 20 may include an integrated circuit that drives the display panel DP. The integrated circuit may be a data driving integrated circuit that generates a data signal, but the present disclosure is not limited thereto.

[0075] The terminal 14 may be disposed in the non-display area NDA. The terminal 14 may be exposed by not being covered by the insulating layer to be electrically connected to the printed circuit board 30. The terminal 34 of the printed circuit board 30 may be electrically connected to the terminal 14 of the display panel DP.

[0076] The printed circuit board 30 transmits a signal or power of the controller to the display panel DP. The control signal generated by the controller can be transmitted to each of the first scan driving circuit 11, the second scan driving circuit 12 and the emission control driving circuit 13 through the printed circuit board 30. In addition, the controller can Figure 4 ) is transmitted to the driving power supply line 15, and the common voltage ELVSS (reference Figure 4) is provided to the common power line 16. The driving voltage ELVDD may be delivered to each pixel P through the driving voltage line PL connected to the driving power line 15, and the common voltage ELVSS may be delivered to the opposite electrode of each pixel P. The driving power line 15 may have a shape extending from the lower side of the display area DA in one direction (e.g., x direction). The common power line 16 may have a ring shape with one side opening to partially surround the display area DA (e.g., near the periphery of the display area DA).

[0077] The controller may generate a data signal. The generated data signal may be transmitted to the input line IL through the driving chip 20, and transmitted to the pixel P through the data line DL connected to the input line IL. For reference, "line" may refer to "wiring". The various embodiments described in more detail below may be similar to the embodiments described above, and modified examples thereof will be described in more detail below.

[0078] Figure 4 and Figure 5 is an equivalent circuit diagram schematically showing a pixel of a display device according to one or more embodiments.

[0079] Reference Figure 4 The light emitting diode ED may be electrically connected to the pixel circuit PC. The pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0080] The second transistor T2 is configured to transfer the data signal Dm input through the data line DL to the first transistor T1 according to the scan signal Sgw input through the scan line GW.

[0081] The storage capacitor Cst is connected to the second transistor T2 and the driving voltage line PL, and stores a voltage corresponding to a difference between a voltage received from the second transistor T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0082] The first transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and may control the driving current I flowing from the driving voltage line PL to the light emitting diode ED according to the voltage value stored in the storage capacitor Cst. d The opposite electrode (eg, cathode) of the light emitting diode ED may receive the common voltage ELVSS. The light emitting diode ED may be driven by the driving current I d Light having a desired brightness (eg, a specific or predetermined brightness) is emitted.

[0083] Figure 4 It is shown that the pixel circuit PC includes two transistors and one storage capacitor, but the present disclosure is not limited thereto.

[0084] For example, refer to Figure 5 , the pixel circuit PC may include seven transistors and two capacitors.

[0085] In an embodiment, the pixel circuit PC may include first to seventh transistors T1, T2, T3, T4, T5, T6 and T7, a storage capacitor Cst and a boosting capacitor Cbt. In another embodiment, the pixel circuit PC may not include the boosting capacitor Cbt.

[0086] Some of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be n-channel metal oxide semiconductor field effect transistors (MOSFETs) (NMOS), and the remaining transistors may be p-channel MOSFETs (PMOS). In another embodiment, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be NMOS transistors, and the remaining transistors may be PMOS transistors.

[0087] The first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, the storage capacitor Cst, and the boost capacitor Cbt may be connected to the signal line. The signal line may include a scan line GW, an emission control line EM, a compensation gate line GC, a first initialization gate line Gl1, a second initialization gate line Gl2, and a data line DL. For example, the pixel circuit PC may be electrically connected to a voltage line such as a driving voltage line PL, a first initialization voltage line VL1, and a second initialization voltage line VL2.

[0088] The first transistor T1 may be a driving transistor. The first gate electrode of the first transistor T1 may be connected to the storage capacitor Cst. The first electrode of the first transistor T1 may be electrically connected to the driving voltage line PL via the fifth transistor T5, and the second electrode of the first transistor T1 may be electrically connected to the pixel electrode (e.g., anode) of the light emitting diode ED via the sixth transistor T6. One of the first electrode and the second electrode of the first transistor T1 may be a source electrode, and the other may be a drain electrode. The first transistor T1 may supply a driving current I to the light emitting diode ED according to the switching operation of the second transistor T2. d .

[0089] The second transistor T2 may be a switching transistor. The second gate electrode of the second transistor T2 may be connected to the scan line GW, the first electrode of the second transistor T2 may be connected to the data line DL, and the second electrode of the second transistor T2 may be electrically connected to the drive voltage line PL via the fifth transistor T5 and to the first electrode of the first transistor T1. One of the first electrode and the second electrode of the second transistor T2 may be a source electrode, and the other may be a drain electrode. The second transistor T2 may be turned on according to the scan signal Sgw received through the scan line GW, and may perform a switching operation of transferring the data signal Dm transmitted to the data line DL to the first electrode of the first transistor T1.

[0090] The third transistor T3 may be a compensation transistor for compensating the threshold voltage of the first transistor T1. The third gate electrode of the third transistor T3 is connected to the compensation gate line GC. The first electrode of the third transistor T3 is connected to the lower electrode CE1 of the storage capacitor Cst and the first gate electrode of the first transistor T1 through the node connection line 166. The first electrode of the third transistor T3 may be connected to the fourth transistor T4. The second electrode of the third transistor T3 is electrically connected to the second electrode of the first transistor T1 and is electrically connected to the pixel electrode (e.g., anode) of the light emitting diode ED via the sixth transistor T6. One of the first electrode and the second electrode of the third transistor T3 may be a source electrode, and the other may be a drain electrode.

[0091] The third transistor T3 is turned on according to the compensation signal Sgc received through the compensation gate line GC to electrically connect the first gate electrode and the second electrode (eg, drain electrode) of the first transistor T1 to each other, and thus, the first transistor T1 may be diode-connected.

[0092] The fourth transistor T4 may be a first initialization transistor that initializes the first gate electrode of the first transistor T1. The fourth gate electrode of the fourth transistor T4 is connected to the first initialization gate line Gl1. The first electrode of the fourth transistor T4 is connected to the first initialization voltage line VL1. The second electrode of the fourth transistor T4 may be connected to the lower electrode CE1 of the storage capacitor Cst, the first electrode of the third transistor T3, and the first gate electrode of the first transistor T1. One of the first electrode and the second electrode of the fourth transistor T4 may be a source electrode, and the other may be a drain electrode. The fourth transistor T4 may be turned on according to the first initialization signal Sgi1 received through the first initialization gate line Gl1 to transfer the first initialization voltage Vint to the first gate electrode of the first transistor T1, and thus, an initialization operation of initializing the voltage of the first gate electrode of the first transistor T1 may be performed.

[0093] The fifth transistor T5 may be an operation control transistor. A fifth gate electrode of the fifth transistor T5 is connected to the emission control line EM, a first electrode of the fifth transistor T5 is connected to the driving voltage line PL, and a second electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1 and the second electrode of the second transistor T2. One of the first electrode and the second electrode of the fifth transistor T5 may be a source electrode, and the other may be a drain electrode.

[0094] The sixth transistor T6 may be an emission control transistor. A sixth gate electrode of the sixth transistor T6 is connected to the emission control line EM, a first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1 and the second electrode of the third transistor T3, and a second electrode of the sixth transistor T6 is electrically connected to the second electrode of the seventh transistor T7 and a pixel electrode (e.g., an anode) of the light emitting diode ED. One of the first electrode and the second electrode of the sixth transistor T6 may be a source electrode, and the other may be a drain electrode.

[0095] According to the emission control signal Sem received through the emission control line EM, the fifth transistor T5 and the sixth transistor T6 are turned on simultaneously or substantially simultaneously to allow the driving voltage ELVDD to be transferred to the light emitting diode ED, and thus, the driving current I d can flow through the light emitting diode ED.

[0096] The seventh transistor T7 may be a second initialization transistor for initializing a pixel electrode (e.g., an anode) of the light emitting diode ED. The seventh gate electrode of the seventh transistor T7 is connected to the second initialization gate line Gl2. The first electrode of the seventh transistor T7 is connected to the second initialization voltage line VL2. The second electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6 and the pixel electrode (e.g., an anode) of the light emitting diode ED. The seventh transistor T7 is turned on according to the second initialization signal Sgi2 received through the second initialization gate line Gl2, and may transfer the second initialization voltage Vaint to the pixel electrode (e.g., an anode) of the light emitting diode ED to initialize the pixel electrode of the light emitting diode ED.

[0097] In an embodiment, the second initialization gate line Gl2 may be a subsequent scan line. For example, the second initialization gate line Gl2 connected to the seventh transistor T7 of the pixel circuit PC arranged in the i-th row (where i is a natural number) may correspond to the scan line of the pixel circuit PC arranged in the (i+1)-th row. In another embodiment, the second initialization gate line Gl2 may be an emission control line EM. For example, the emission control line EM may be electrically connected to the fifth to seventh transistors T5, T6, and T7.

[0098] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2. The lower electrode CE1 of the storage capacitor Cst is connected to the first gate electrode of the first transistor T1, and the upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL. The storage capacitor Cst can store charges corresponding to the difference between the voltage of the first gate electrode of the first transistor T1 and the driving voltage ELVDD.

[0099] The boost capacitor Cbt includes a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 may be connected to the second gate electrode of the second transistor T2 and the scan line GW, and the fourth electrode CE4 may be connected to the first electrode of the third transistor T3 and the node connection line 166. When the scan signal Sgw supplied to the scan line GW is turned off (e.g., has an inactive level), the boost capacitor Cbt may increase the voltage of the first node N1. When the voltage of the first node N1 increases, a black gradient may be more clearly expressed.

[0100] The first node N1 may be a region in which the first gate electrode of the first transistor T1, the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the fourth electrode CE4 of the boosting capacitor Cbt are connected to each other.

[0101] In an embodiment, as in Figure 5 As shown in , the third transistor T3 and the fourth transistor T4 are NMOS transistors, while the first transistor T1, the second transistor T2 and the fifth to seventh transistors T5, T6 and T7 are PMOS transistors. The first transistor T1 directly affecting the brightness of the display device displaying an image may include a semiconductor layer, thereby realizing a display device with high resolution, wherein the semiconductor layer includes polysilicon with high reliability.

[0102] Figure 6 and Figure 7 is a cross-sectional view schematically showing a display device according to one or more embodiments. Figure 8 and Fig. 9 is a cross-sectional view schematically showing a display device according to one or more embodiments. Fig.25 is a cross-sectional view showing a stack structure of a light emitting diode according to an embodiment.

[0103] Reference Figures 6 to 9 , the pixel circuit PC may be disposed on a substrate 100. The substrate 100 may include a glass material or a polymer resin. The substrate 100 may include a structure in which a base layer including a polymer resin and a barrier layer are stacked.

[0104] The polymer resin may include (for example, may be) polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate.

[0105] The barrier layer may include silicon nitride (SiN x ) and / or silicon oxide (SiO x ) of inorganic materials.

[0106] The buffer layer 101 may be disposed on the substrate 100. The buffer layer 101 may prevent or substantially prevent impurities from penetrating into the semiconductor layer of the transistor. The buffer layer 101 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and / or silicon oxide, and may include a single layer or multiple layers, each of which includes one or more of the inorganic insulating materials described above.

[0107] The pixel circuit PC may be disposed on the buffer layer 101. Figure 4 or Figure 5 As described, the pixel circuit PC may include a plurality of transistors and a storage capacitor. For ease of explanation, Figures 6 to 9 Parts of the first transistor T1 , the sixth transistor T6 and the storage capacitor Cst of the pixel circuit PC are shown.

[0108] The first transistor T1 may include a first semiconductor layer A1 on the buffer layer 101 and a first gate electrode G1 overlapping a channel region of the first semiconductor layer A1. The first semiconductor layer A1 may include, for example, a silicon-based semiconductor material such as polycrystalline silicon. The first semiconductor layer A1 may include a channel region, and a first region and a second region respectively arranged on opposite sides of the channel region. Each of the first region and the second region is a region including an impurity concentration higher than that of the channel region. Any one of the first region and the second region may be a source region, and the other may correspond to a drain region.

[0109] The sixth transistor T6 may include a sixth semiconductor layer A6 on the buffer layer 101, and a sixth gate electrode G6 overlapping the channel region of the sixth semiconductor layer A6. The sixth semiconductor layer A6 may include, for example, a silicon-based semiconductor material such as polycrystalline silicon. The sixth semiconductor layer A6 may include a channel region and a first region and a second region respectively arranged on opposite sides of the channel region. Each of the first region and the second region is a region including an impurity concentration higher than that of the channel region. Any one of the first region and the second region may be a source region, and the other may correspond to a drain region.

[0110] The first gate electrode G1 and the sixth gate electrode G6 may each include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single layer or a multilayer, each of which includes one or more of the above materials. The first gate insulating layer 103 for electrical insulation between the first semiconductor layer A1 and the sixth semiconductor layer A6 may be disposed below (e.g., below) the first gate electrode G1 and the sixth gate electrode G6. The first gate insulating layer 103 may include an inorganic insulating material such as silicon nitride, silicon oxynitride and / or silicon oxide, and may include a single layer or a multilayer, each of which includes one or more of the inorganic insulating materials described above.

[0111] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 overlapping each other. In an embodiment, the lower electrode CE1 of the storage capacitor Cst may include a first gate electrode G1. In other words, the first gate electrode G1 may include the lower electrode CE1 of the storage capacitor Cst. For example, the first gate electrode G1 and the lower electrode CE1 of the storage capacitor Cst may be integral.

[0112] The first interlayer insulating layer 105 may be between the lower electrode CE1 and the upper electrode CE2 of the storage capacitor Cst. The first interlayer insulating layer 105 may include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may include a single layer structure or a multilayer structure each including one or more of the above inorganic insulating materials.

[0113] The upper electrode CE2 of the storage capacitor Cst may include a low-resistance conductive material such as Mo, Al, Cu, and / or Ti, and may include a single-layer structure or a multi-layer structure each including one or more of the above materials.

[0114] The second interlayer insulating layer 107 may be disposed on the storage capacitor Cst. The second interlayer insulating layer 107 may include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may include a single layer structure or a multilayer structure each including one or more of the above inorganic insulating materials.

[0115] The source electrode S1 and / or the drain electrode D1 electrically connected to the first semiconductor layer A1 of the first transistor T1 may be disposed on the second interlayer insulating layer 107. The source electrode S6 and / or the drain electrode D6 electrically connected to the sixth semiconductor layer A6 of the sixth transistor T6 may be disposed on the second interlayer insulating layer 107. The source electrodes S1 and S6 and / or the drain electrodes D1 and D6 may be at the same layer as the layer of the data line DL (e.g., in the same layer or on the same layer), and may include the same material as the material of the data line DL. The source electrodes S1 and S6 and / or the drain electrodes D1 and D6 may each include a conductive material including Mo, Al, Cu, etc., and may include a single layer or multiple layers each including one or more of the above materials. In an embodiment, the source electrodes S1 and S6, the drain electrodes D1 and D6, and the data line DL may each include a multilayer structure of Ti / Al / Ti.

[0116] The first planarization layer 109 may be disposed on the pixel circuit PC. The first planarization layer 109 may include a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, and / or an organic insulating material such as an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a p-xylene polymer, a vinyl alcohol polymer, and / or a suitable mixture thereof.

[0117] The connection metal CM may be disposed on the first planarization layer 109. The connection metal CM may include Mo, Al, Cu, and / or Ti, and may have a single layer or multiple layers each including one or more of the above materials.

[0118] The second planarization layer 111 may be disposed between the connection metal CM and the pixel electrode 210. The second planarization layer 111 may include a general polymer (such as PMMA or PS), a polymer derivative having a phenol group, and / or an organic insulating material, such as an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a p-xylene polymer, a vinyl alcohol polymer, and / or a suitable mixture thereof. In an embodiment, the first planarization layer 109 and the second planarization layer 111 may each include polyimide.

[0119] The pixel electrode 210 may be formed on the second planarization layer 111. The pixel electrode 210 may be formed as a (semi) transparent electrode or a reflective electrode. When the pixel electrode 210 is formed as a (semi) transparent electrode, the pixel electrode 210 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). When the pixel electrode 210 is formed as a reflective electrode, a reflective film including silver (Ag), Mg, Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a suitable compound thereof may be formed, and a reflective film including ITO, IZO, ZnO or In may be formed on the reflective film. 2 O 3 In an embodiment, the pixel electrode 210 may have a structure in which an ITO layer, an Ag layer, and an ITO layer are sequentially stacked. The pixel electrode 210 may be electrically connected to the connection metal CM through (eg, penetrating) a contact hole of the second planarization layer 111.

[0120] According to the above reference Figures 6 to 9 In one or more embodiments described, the pixel circuit PC and the pixel electrode 210 are electrically connected to each other through the connection metal CM, but the present disclosure is not limited thereto. According to another embodiment, the connection metal CM may be omitted, and one planarization layer may be between the pixel circuit PC and the pixel electrode 210. According to another embodiment, three or more planarization layers may be between the pixel circuit PC and the pixel electrode 210, and the pixel circuit PC and the pixel electrode 210 may be electrically connected to each other through a plurality of connection metals.

[0121] The pixel defining layer 115 may be disposed on the second planarization layer 111. The pixel electrode 210 may be between the second planarization layer 111 and the pixel defining layer 115. Therefore, it can be said that the pixel defining layer 115 is disposed on the pixel electrode 210. The pixel defining layer 115 may have an opening through which at least a portion of the pixel electrode 210 is exposed. In an embodiment, the pixel defining layer 115 may define a pixel by having an opening corresponding to each sub-pixel, or in other words, having a first sub-opening OP1 through which at least a central portion of the pixel electrode 210 is exposed. The pixel defining layer 115 may cover the side surface of the pixel electrode 210. In other words, when viewed in a direction perpendicular to or substantially perpendicular to the substrate 100 (e.g., the Z-axis direction) (e.g., in a plan view), the pixel defining layer 115 may overlap with the edge of the pixel electrode 210.

[0122] The pixel defining layer 115 may include an organic insulating material and / or an inorganic insulating material. In an embodiment, the pixel defining layer 115 may include an inorganic insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride. When the pixel defining layer 115 includes an inorganic insulating material, the distance between each sub-pixel can be formed to be shorter. In an embodiment, the pixel defining layer 115 may include one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene (BCB) and phenolic resin. In an embodiment, the pixel defining layer 115 may include a multilayer structure including one or more of the inorganic insulating materials described above and one or more of the organic insulating materials described above.

[0123] In some embodiments, the remaining pixel protection layer may be disposed between the pixel electrode 210 and the pixel defining layer 115. The remaining pixel protection layer may be a portion remaining after removing the pixel protection layer protecting the upper surface of the pixel electrode 210 in the manufacturing process of the display device. When observed in a direction perpendicular to or substantially perpendicular to the substrate 100 (e.g., the Z-axis direction) (e.g., in a plan view), the remaining pixel protection layer may be a region where the pixel electrode 210 and the pixel defining layer 115 overlap each other. For example, the remaining pixel protection layer may be positioned along the edge of the pixel electrode 210 to expose the central portion of the pixel electrode 210. The remaining pixel protection layer may include conductive oxides such as ITO, IZO, indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), ZnO, AZO, gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), fluorine-doped tin oxide (FTO), etc.

[0124] The bank layer 300 may be disposed on the pixel defining layer 115. The bank layer 300 may include a second sub-opening OP2 exposing a central portion of the pixel electrode 210. The second sub-opening OP2 of the bank layer 300 may overlap the first sub-opening OP1 of the pixel defining layer 115.

[0125] Still refer to Figures 6 to 9 , in an embodiment, the side surface of the bank layer 300 may have an inclined surface tapered in the forward direction. For example, the width of the upper portion of the second sub-opening OP2 of the bank layer 300 may be greater than the width of the lower portion of the second sub-opening OP2. However, the present disclosure is not limited thereto. In an embodiment, the side surface of the bank layer 300 may be perpendicular to or substantially perpendicular to the substrate 100. In an embodiment, the side surface of the bank layer 300 may have an inclined surface tapered in the opposite direction. In other words, the width of the upper portion of the second sub-opening OP2 of the bank layer 300 may be less than the width of the lower portion of the second sub-opening OP2.

[0126] The bank layer 300 may include a conductive material. For example, the bank layer 300 may include a conductive material including Mo, Al, Cu, Ti, etc., and may be a multilayer or single layer each including one or more of the above materials. Figure 6 As shown in , the bank layer 300 may include a single layer including one of the above materials. Figure 7 As shown in , the bank layer 300 may include a first sub-bank layer 310 and a second sub-bank layer 320. The first sub-bank layer 310 and the second sub-bank layer 320 may include metals different from each other. In an embodiment, the first sub-bank layer 310 may be a layer including Al, and the second sub-bank layer 320 may be a layer including Ti. The thickness of the first sub-bank layer 310 may be formed to be greater than the thickness of the second sub-bank layer 320. In other words, the thickness of the second sub-bank layer 320 may be formed to be less than the thickness of the first sub-bank layer 310. In an embodiment, the thickness of the first sub-bank layer 310 may be about five times the thickness of the second sub-bank layer 320.

[0127] The bank layer 300 and the pixel defining layer 115 may extend from the display area DA to the non-display area NDA to be aligned with the common power line 16 (eg, reference Figure 3 ) is electrically connected. In this case, the pixel defining layer 115 may have an opening portion that exposes a portion of the upper surface of the common power line 16 by overlapping with the common power line 16. The embankment layer 300 may be in direct contact with the common power line 16 through the opening portion of the pixel defining layer 115, or may be electrically connected to the common power line 16 through a conductive layer between the embankment layer 300 and the common power line 16. In other words, the embankment layer 300 may be electrically connected to the common power line 16. In an embodiment, the first sub-embankment layer 310 may be in direct contact with the common power line 16 through the opening portion of the pixel defining layer 115, or may be electrically connected to the common power line 16 through a conductive layer between the first sub-embankment layer 310 and the common power line 16. In other words, the first sub-embankment layer 310 may be electrically connected to the common power line 16.

[0128] The overhang layer 350 may be disposed on the bank layer 300. The overhang layer 350 may include a third sub-opening OP3 exposing a central portion of the pixel electrode 210. The third sub-opening OP3 of the overhang layer 350 may overlap the pixel electrode 210, the first sub-opening OP1 of the pixel defining layer 115, and the second sub-opening OP2 of the bank layer 300. The width of the third sub-opening OP3 may be smaller than the width of the second sub-opening OP2. Therefore, the overhang layer 350 may have a tip TP protruding toward the central portion of the pixel electrode 210. In other words, the tip TP as a part of the overhang layer 350 may protrude toward the pixel electrode 210 from a point where the bottom surface of the overhang layer 350 and the side surface of the bank layer 300 facing the pixel electrode 210 meet each other. When viewed from a direction perpendicular to or substantially perpendicular to the substrate 100 (e.g., the Z-axis direction), the tip TP of the overhang layer 350 may have a ring shape that completely surrounds the pixel electrode 210 (e.g., near the periphery of the pixel electrode 210). Therefore, it can be said that the tip TP of the overhanging layer 350 includes a third sub-opening OP3 overlapping the pixel electrode 210. The length c of the tip TP may be about 5 μm or less. In an embodiment, the length c of the tip TP may be about 0.3 μm to about 1 μm, or may be about 0.3 μm to about 0.7 μm. When viewed from a direction perpendicular to or substantially perpendicular to the substrate 100 (e.g., the z-axis direction), the "length c of the tip TP" may be the distance from the point where the bottom surface of the overhanging layer 350 and the side surface of the embankment layer 300 facing the pixel electrode 210 meet each other to the end of the tip TP closest to the central portion of the pixel electrode 210.

[0129] The overhang layer 350 may include a conductive material such as Mo, Al, Cu and / or Ti. The overhang layer 350 may include an organic insulating material such as acrylic acid, BCB, polyimide or HMDSO. The overhang layer 350 may include an inorganic insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride. The overhang layer 350 may include a single layer structure or a multilayer structure each including one or more of the above materials. In an embodiment, the overhang layer 350 may include Ti.

[0130] Reference Figure 6 and Figure 7, the tip TP of the overhanging layer 350 according to the embodiment may be formed to be higher than the bottom surface of the overhanging layer 350 in which the overhanging layer 350 contacts the bank layer 300 (for example, in the z-axis direction). In other words, the height b from the upper surface of the pixel defining layer 115 to the bottom surface BS of the tip TP of the overhanging layer 350 may be greater than the height a from the upper surface of the pixel defining layer 115 to the upper surface of the bank layer 300. In an embodiment, the height a may be about 0.2 μm to about 0.4 μm, and the height b may be about 0.5 μm to about 0.7 μm. In an embodiment, the height a may be about 0.3 μm, and the height b may be about 0.6 μm. However, the present disclosure is not limited thereto. The height a and the height b may be heights appropriately selected by those skilled in the art according to process conditions. For example, when the opposing electrode 230 does not sufficiently contact the bank layer 300 due to the small thickness of the bank layer 300 and the intermediate layer 220 completely covers the side surface of the bank layer 300, the height a from the upper surface of the pixel defining layer 115 to the upper surface of the bank layer 300 may be formed to be smaller than the height b from the upper surface of the pixel defining layer 115 to the bottom surface BS of the tip TP of the overhang layer 350. In this case, even when the opposing electrode 230 does not sufficiently contact the bank layer 300, the opposing electrode 230 may receive the common power through contact with the overhang layer 350. Therefore, the overhang layer 350 may include a conductive material such as Mo, Al, Cu, and / or Ti.

[0131] Reference Figure 8 and Fig. 9 , the tip TP of the overhanging layer 350 according to the embodiment may be formed to be lower than the bottom surface of the overhanging layer 350 in which the overhanging layer 350 contacts the bank layer 300 (for example, in the z-axis direction). In other words, the height b from the upper surface of the pixel defining layer 115 to the bottom surface BS of the tip TP of the overhanging layer 350 may be less than the height a from the upper surface of the pixel defining layer 115 to the upper surface of the bank layer 300. In an embodiment, the height a may be about 0.6 μm to about 1.0 μm, and the height b may be about 0.5 μm to about 0.7 μm. In an embodiment, the height a may be about 0.9 μm, and the height b may be about 0.6 μm. However, the present disclosure is not limited thereto. The height a and the height b may be heights appropriately selected by those skilled in the art according to process conditions. When the light emission efficiency of the display device is low or the viewing angle of the display device is reduced due to the excessive thickness of the bank layer 300, the height b from the upper surface of the pixel defining layer 115 to the bottom surface BS of the tip TP of the overhanging layer 350 may be formed to be smaller than the height a from the upper surface of the pixel defining layer 115 to the upper surface of the bank layer 300. In this case, since the tip TP of the overhanging layer 350 is formed to be low, the light emission efficiency and the viewing angle of the display device may be improved.

[0132] The intermediate layer 220 may be disposed on the pixel electrode 210, and the opposite electrode 230 may be disposed on the intermediate layer 220. The intermediate layer 220 and the opposite electrode 230 may overlap the pixel electrode 210. The pixel electrode 210, the intermediate layer 220, and the opposite electrode 230 may overlap each other to form a light emitting diode ED.

[0133] As in Fig.25 As shown in , the intermediate layer 220 may include an emission layer 222. The intermediate layer 220 may include a common layer between the pixel electrode 210 and the emission layer 222 and / or between the emission layer 222 and the opposite electrode 230. Hereinafter, the common layer between the pixel electrode 210 and the emission layer 222 may be referred to as a first common layer 221, and the common layer between the emission layer 222 and the opposite electrode 230 may be referred to as a second common layer 223.

[0134] The emission layer 222 may include a polymer organic material or a low molecular weight organic material that emits light of a desired color (eg, a specific or predetermined color such as red, green, or blue). In another embodiment, the emission layer 222 may include an inorganic material or quantum dots.

[0135] The first common layer 221 may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second common layer 223 may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first common layer 221 and the second common layer 223 may each include an organic material.

[0136] The intermediate layer 220 may have a single stack structure including a single emission layer or a tandem structure, which is a multi-stack structure including a plurality of emission layers. When the intermediate layer 220 has a tandem structure, a charge generation layer (CGL) may be disposed between adjacent stacks of the multi-stack structure.

[0137] The opposing electrode 230 may include a conductive material having a low work function. For example, the opposing electrode 230 may include a (semi) transparent layer, and the (semi) transparent layer includes Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), Ca, a suitable alloy thereof, etc. As another example, the opposing electrode 230 may further include a conductive material such as ITO, IZO, ZnO or In on the (semi) transparent layer including one or more of the materials described above. 2 O 3 layer.

[0138] Return to reference Figures 6 to 9 , the intermediate layer 220 may be electrically connected to the pixel electrode 210. In an implementation, the intermediate layer 220 may be in contact with the pixel electrode 210. The opposite electrode 230 may be disposed on the intermediate layer 220.

[0139] Reference Figure 6 and Figure 7 , the relative electrode 230 may be electrically connected to the overhanging layer 350. In an embodiment, the edge or outer portion (e.g., peripheral portion) of the intermediate layer 220 may cover the upper portion of the side surface of the bank layer 300. In an embodiment, a portion (e.g., only a portion) of the edge of the relative electrode 230 or the outer portion (e.g., peripheral portion) of the relative electrode 230 may contact the side surface of the bank layer 300. In an embodiment, the edge or outer portion (e.g., peripheral portion) of the relative electrode 230 may not contact the bank layer 300. In this case, the relative electrode 230 may contact the overhanging layer 350 and may receive a common power supply through the overhanging layer 350. In this case, the overhanging layer 350 may include a conductive material such as Mo, Al, Cu and / or Ti. As used herein, "the edge or outer portion (e.g., peripheral portion) of the relative electrode 230" refers to a portion of the relative electrode 230, which includes the edge of the relative electrode 230. This also applies to the intermediate layer 220.

[0140] Reference Figure 8 and Fig. 9 , the relative electrode 230 may be electrically connected to the bank layer 300. In an embodiment, an edge or an outer portion (e.g., a peripheral portion) of the relative electrode 230 may cover an edge or an outer portion (e.g., a peripheral portion) of the intermediate layer 220 and may be in contact with the side surface of the bank layer 300. In this case, the relative electrode 230 may receive a common power source through the bank layer 300. In an embodiment, the relative electrode 230 may be electrically connected to the overhang layer 350. In other words, an edge or an outer portion (e.g., a peripheral portion) of the relative electrode 230 may be in contact with the overhang layer 350. The relative electrode 230 may receive a common power source through the bank layer 300 and the overhang layer 350. In this case, the overhang layer 350 may include a conductive material such as Mo, Al, Cu and / or Ti. In an embodiment, an edge or an outer portion (e.g., a peripheral portion) of the relative electrode 230 may cover an edge or an outer portion (e.g., a peripheral portion) of the intermediate layer 220 and be in contact with the side surface of the bank layer 300, but may not be in contact with the overhang layer 350. In this case, the overhanging layer 350 may not include a conductive material.

[0141] The dummy intermediate layer 220b may be disposed on the overhanging layer 350, and the dummy opposing electrode 230b may be disposed on the dummy intermediate layer 220b. The intermediate layer 220 and the dummy intermediate layer 220b may be separated and spaced apart from each other, and the opposing electrode 230 and the dummy opposing electrode 230b may be separated and spaced apart from each other. The intermediate layer 220 and the dummy intermediate layer 220b may include the same material and / or the same number of sublayers (e.g., a first common layer, an emission layer, and a second common layer) as each other. The opposing electrode 230 and the dummy opposing electrode 230b may include the same material as each other.

[0142] The capping layer 400 and the encapsulation layer 500 may be disposed on the light emitting diode ED.

[0143] The capping layer 400 may be disposed on the opposite electrode 230. In an implementation, the capping layer 400 may be between the opposite electrode 230 and a first inorganic encapsulating layer 510 which will be described in detail below.

[0144] A dummy capping layer 400b may be further disposed on the dummy opposing electrode 230b. The capping layer 400 and the dummy capping layer 400b may be separated and spaced apart from each other. The capping layer 400 and the dummy capping layer 400b may include the same material as each other. In an embodiment, the capping layer 400 may be omitted as needed or desired.

[0145] The cap layer 400 can improve the external light emission efficiency of the light emitting diode ED by the principle of constructive interference while protecting the opposite electrode 230. The cap layer 400 can be formed by stacking layers having different refractive indices from each other. For example, the refractive index of the cap layer 400 can be about 1.7 to about 1.9.

[0146] The capping layer 400 may be an organic capping layer including an organic material, an inorganic capping layer including an inorganic material, or a composite capping layer including an organic material and an inorganic material.

[0147] The encapsulation layer 500 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figures 6 to 9 It is shown that the encapsulation layer 500 includes a first inorganic encapsulation layer 510 , an organic encapsulation layer 520 on the first inorganic encapsulation layer 510 , and a second inorganic encapsulation layer 530 on the organic encapsulation layer 520 , but the present disclosure is not limited thereto.

[0148] The first inorganic encapsulation layer 510 may include a transparent inorganic material having a low refractive index, and may be deposited by using a suitable method such as chemical vapor deposition. The first inorganic encapsulation layer 510 may include silicon oxide, magnesium fluoride, etc., and may include a single layer or multiple layers each including one or more of the materials described above. The refractive index of the first inorganic encapsulation layer 510 may be about 1.3 to about 1.6.

[0149] The first inorganic encapsulation layer 510 may have relatively excellent step coverage. Therefore, the first inorganic encapsulation layer 510 may cover at least a portion of the inner surface of the opening OP of the undercut structure. In an embodiment, the first inorganic encapsulation layer 510 may be continuously formed to overlap with the upper surface and side surface of the dummy cover layer 400b, the side surface of the dummy relative electrode 230b, the side surface of the dummy intermediate layer 220b, the side surface and bottom surface of the overhanging layer 350, and the upper surface of the cover layer 400 (or cover the upper surface and side surface of the dummy cover layer 400b, the side surface of the dummy relative electrode 230b, the side surface of the dummy intermediate layer 220b, the side surface and bottom surface of the overhanging layer 350, and the upper surface of the cover layer 400). In an embodiment where the cap layer 400 is omitted, the first inorganic encapsulation layer 510 may be continuously formed to overlap (or cover) the upper and side surfaces of the dummy opposing electrode 230b, the side surface of the dummy intermediate layer 220b, the side and bottom surfaces of the overhang layer 350, and the upper surface of the opposing electrode 230. The first inorganic encapsulation layer 510 may reduce or block a path through which impurities (such as moisture and / or air) penetrate.

[0150] The organic encapsulating layer 520 may be formed on the first inorganic encapsulating layer 510. The organic encapsulating layer 520 may provide a flat or substantially flat base surface for components disposed on an upper portion of the organic encapsulating layer 520 by filling at least a portion or all of the opening OP.

[0151] The organic encapsulation layer 520 may include a transparent organic material having a high refractive index. The transparent organic material having a high refractive index may be an acryl-based and / or siloxane-based organic material having a refractive index of about 1.6 or more. In an embodiment, the organic encapsulation layer 520 may include acrylate. In an embodiment, the organic encapsulation layer 520 may include a single-layer structure or a multi-layer structure each including one or more of the above materials.

[0152] The organic encapsulation layer 520 may include high refractive index particles dispersed in a transparent organic material. For example, the high refractive index particles may include zirconium oxide, zinc oxide, titanium oxide, niobium oxide, tantalum oxide, tin oxide, nickel oxide, silicon nitride, indium nitride, gallium nitride, etc.

[0153] The refractive index of the organic encapsulating layer 520 may be greater than that of the first inorganic encapsulating layer 510. For example, the refractive index of the organic encapsulating layer 520 may be about 1.6 to about 2.5. In an embodiment, the organic encapsulating layer 520 may have a multilayer structure including a plurality of layers having different refractive indices from each other.

[0154] In an implementation, the organic encapsulating layer 520 may be completely formed on the substrate 100. In this case, the organic encapsulating layer 520 filling the plurality of openings OP may be integrally formed, and a flatter base surface may be provided.

[0155] The second inorganic encapsulation layer 530 may be disposed on the organic encapsulation layer 520. The second inorganic encapsulation layer 530 may include at least one inorganic material of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The second inorganic encapsulation layer 530 may include a single layer or multiple layers, and the single layer or multiple layers include one or more of the above materials.

[0156] In an implementation, the refractive index of the second inorganic encapsulating layer 530 may be lower than the refractive index of the organic encapsulating layer 520. For example, the refractive index of the second inorganic encapsulating layer 530 may be about 1.3 to about 1.6.

[0157] The second inorganic encapsulating layer 530 may prevent or substantially prevent damage to the organic encapsulating layer 520 in a subsequent process, and may provide a flat or substantially flat base surface for components on the second inorganic encapsulating layer 530 .

[0158] Figures 10 to 17 are cross-sectional views sequentially illustrating some processes of a method of manufacturing a display device according to an embodiment.

[0159] Reference Fig.10 , a pixel circuit PC may be formed on the substrate 100. For ease of description, Fig.10 The above reference shows Figure 6 The first transistor T1, the sixth transistor T6 and the storage capacitor Cst of the pixel circuit PC.

[0160] The substrate 100 may include a glass material or a polymer resin. A buffer layer 101, a first gate insulating layer 103, a first interlayer insulating layer 105, and a second interlayer insulating layer 107 may be formed on the substrate 100. A first planarization layer 109 and a second planarization layer 111 covering the pixel circuit PC may be formed on the second interlayer insulating layer 107. The second planarization layer 111 may be formed to have a flat or substantially flat upper surface. A pixel electrode 210 electrically connected to the pixel circuit PC may be formed on the second planarization layer 111. The pixel electrode 210 may be formed to be electrically connected to the pixel circuit PC through a connecting metal CM. In an embodiment, the pixel electrode 210 may be formed to be in direct contact with the pixel circuit PC.

[0161] The pixel defining layer 115 may be formed on the second planarization layer 111 to have an opening exposing at least a portion of the pixel electrode 210. In an embodiment, the pixel defining layer 115 may be formed on the second planarization layer 111 to have a first sub-opening OP1 exposing a central portion of the pixel electrode 210. In other words, the pixel defining layer 115 may be formed to cover a side surface of the pixel electrode 210.

[0162] In some embodiments, a pixel protection layer may be further formed on the pixel electrode 210. The pixel protection layer may include a conductive oxide such as ITO, IZO, IGZO, ITZO, ZnO, AZO, GZO, ZTO, GTO, FTO, etc. The pixel protection layer may protect the upper surface of the pixel electrode 210 in a subsequent (e.g., future) manufacturing process.

[0163] A preliminary bank layer 300m may be formed on the pixel defining layer 115 and the pixel electrode 210. The preliminary bank layer 300m may be formed by a suitable method such as sputtering. However, the present disclosure is not limited thereto. The preliminary bank layer 300m may be formed by a suitable method deemed appropriate by those skilled in the art.

[0164] Reference Fig.11 By patterning the preliminary bank layer 300m, the bank layer 300 may be formed to have the second sub-opening OP2 exposing all or a portion of the upper portion of the pixel electrode 210 and a portion of the upper portion of the pixel defining layer 115. In other words, by patterning the preliminary bank layer 300m, the bank layer 300 may be formed to have the second sub-opening OP2 overlapping the pixel electrode 210 and the first sub-opening OP1.

[0165] In an embodiment, the preliminary bank layer 300m may be removed by being dry-etched. When the preliminary bank layer 300m is patterned, wet etching may not be used. Fig.11 It is shown that the side surface of the bank layer 300 is formed to have an inclined surface tapered in the forward direction. However, the present disclosure is not limited thereto. In an embodiment, the side surface of the bank layer 300 may be formed to be perpendicular or substantially perpendicular to the substrate 100. In an embodiment, the side surface of the bank layer 300 may be formed to have an inclined surface tapered in the opposite direction.

[0166] After forming the bank layer 300 by patterning the preliminary bank layer 300m, a preliminary sacrificial layer PRm may be formed to fill the first and second sub-openings OP1 and OP2 and cover the bank layer 300. In an embodiment, the preliminary sacrificial layer PRm may include a suitable material including a photosensitive compound (PAC).

[0167] Reference Fig.12, the sacrificial layer PR may be formed by patterning the preliminary sacrificial layer PRm. The preliminary sacrificial layer PRm may be patterned so that a height b from the upper surface of the pixel defining layer 115 to the upper surface of the sacrificial layer PR is formed to be greater than a height a from the upper surface of the pixel defining layer 115 to the upper surface of the bank layer 300. The preliminary sacrificial layer PRm may be patterned by an exposure and development process. In this case, a separate planarization process (e.g., chemical mechanical polishing (CMP)) may not be required.

[0168] Reference Fig.13 , a preliminary overhanging layer 350m may be formed on the bank layer 300 and the sacrificial layer PR. The overhanging layer 350 may be formed to have a single layer structure or a multilayer structure each including a conductive material, an organic insulating material, and / or an inorganic insulating material. In an embodiment, the overhanging layer 350 may include Ti.

[0169] Reference Fig.14 and Fig.15 , the overhang layer 350 may be formed to have a third sub-opening P3 overlapping the first sub-opening OP1 and the second sub-opening OP2 by removing a portion of the preliminary overhang layer 350m. The overhang layer 350 may be formed so that the width of the third sub-opening OP3 of the overhang layer 350 is less than the width of the second sub-opening OP2 of the bank layer 300. In an embodiment, the preliminary overhang layer 350m may be removed by dry etching. Next, the sacrificial layer PR may be removed. In an embodiment, the sacrificial layer PR may be removed by a suitable process such as ashing. Since the height b from the upper surface of the pixel defining layer 115 to the upper surface of the sacrificial layer PR is greater than the height a from the upper surface of the pixel defining layer 115 to the upper surface of the bank layer 300, after the sacrificial layer PR is removed, the height b from the upper surface of the pixel defining layer 115 to the bottom surface of the tip TP of the overhang layer 350 obtained by patterning may be greater than the height a from the upper surface of the pixel defining layer 115 to the upper surface of the bank layer 300.

[0170] Reference Fig.16 and Fig.17, the intermediate layer 220 may be formed on the pixel electrode 210 through the opening OP, and the opposing electrode 230 may be formed on the intermediate layer 220 through the opening OP. The intermediate layer 220 and the opposing electrode 230 may be formed to overlap with the pixel electrode 210. In an embodiment, the intermediate layer 220 and the opposing electrode 230 may each be formed by a deposition method such as thermal evaporation. The edge or outer portion (e.g., peripheral portion) of the opposing electrode 230 may cover the edge or outer portion (e.g., peripheral portion) of the intermediate layer 220. The opposing electrode 230 may be formed to be electrically connected to the bank layer 300. In an embodiment, the opposing electrode 230 may be formed so that the edge or outer portion (e.g., peripheral portion) of the opposing electrode 230 covers the edge or outer portion (e.g., peripheral portion) of the intermediate layer 220 and contacts the side surface of the bank layer 300. The opposing electrode 230 may be formed to be electrically connected to the overhanging layer 350. In an embodiment, the edge or outer portion (e.g., peripheral portion) of the opposing electrode 230 may be formed to contact the overhanging layer 350.

[0171] In an embodiment, the intermediate layer 220 and the relative electrode 230 can be deposited without using a separate mask. Therefore, the deposition material for forming the intermediate layer 220 and the deposition material for forming the relative electrode 230 can form a dummy intermediate layer 220b and a dummy relative electrode 230b on the overhanging layer 350. The intermediate layer 220 and the dummy intermediate layer 220b can be formed to be separated and spaced apart from each other, and the relative electrode 230 and the dummy relative electrode 230b can be formed to be separated and spaced apart from each other. The intermediate layer 220 and the dummy intermediate layer 220b may include the same material and / or the same number of sublayers (e.g., the first common layer, the emission layer and the second common layer) as each other. The relative electrode 230 and the dummy relative electrode 230b may include the same material as each other. The intermediate layer 220 and the dummy intermediate layer 220b may be formed by the same process as each other. The relative electrode 230 and the dummy relative electrode 230b may be formed by the same process as each other.

[0172] The capping layer 400 may be formed on the opposing electrode 230. When the capping layer 400 is formed, a dummy capping layer 400b may also be formed on the dummy opposing electrode 230b. In an embodiment, the dummy capping layer 400b may be disposed between the dummy opposing electrode 230b and the first inorganic encapsulation layer 510, which will be described in detail below. In an embodiment, the process of forming the capping layer 400 may be omitted as needed or desired.

[0173] The first inorganic encapsulating layer 510 may be formed to fill the opening OP. The organic encapsulating layer 520 may be formed on the first inorganic encapsulating layer 510. The second inorganic encapsulating layer 530 may be formed on the organic encapsulating layer 520.

[0174] Figures 18 to 24are cross-sectional views sequentially illustrating some processes of a method of manufacturing a display device according to an embodiment.

[0175] Reference Fig.18 , a preliminary sacrificial layer PRm may be formed to fill the first sub-opening OP1 and the second sub-opening OP2 and cover the bank layer 300. Fig.11 The configuration of the same reference numerals as those described above can be referred to by Fig.11 The methods described are formed in the same or substantially the same manner, and therefore redundant descriptions will not be repeated.

[0176] Reference Fig.19 The preliminary sacrificial layer PRm may be patterned to form the sacrificial layer PR. The preliminary sacrificial layer PRm may be patterned so that a height b from the upper surface of the pixel defining layer 115 to the upper surface of the sacrificial layer PR is formed to be smaller than a height a from the upper surface of the pixel defining layer 115 to the upper surface of the bank layer 300.

[0177] Reference Figure 20 to Figure 22 , a preliminary overhanging layer 350m may be formed on the bank layer 300 and the sacrificial layer PR. The overhanging layer 350 may be formed to have a third sub-opening P3 overlapping the first sub-opening OP1 and the second sub-opening OP2 by removing a portion of the preliminary overhanging layer 350m. Then, the sacrificial layer PR may be removed. A height b from the upper surface of the pixel defining layer 115 to the bottom surface of the tip TP of the overhanging layer 350 obtained by patterning may be less than a height a from the upper surface of the pixel defining layer 115 to the upper surface of the bank layer 300.

[0178] Reference Fig.23 and Fig.24 , the intermediate layer 220 may be formed on the pixel electrode 210 through the opening OP, and the opposite electrode 230 may be formed on the intermediate layer 220 through the opening OP.

[0179] According to one or more embodiments of the present disclosure described above, a display device having reduced process time, reduced cost and / or improved light emission efficiency and a method for manufacturing the same may be provided. However, the spirit and scope of the present disclosure are not limited to the above description.

[0180] The above is an explanation of some embodiments of the present disclosure, and it should not be understood as a limitation of the present disclosure. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications may be made to the embodiments without departing from the spirit and scope of the present disclosure. It is understood that, unless otherwise specified, the description of the features or aspects in each embodiment should generally be considered as other similar features or aspects that can be used in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, unless otherwise specifically stated, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in conjunction with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it should be understood that the above is an explanation of various exemplary embodiments, and should not be understood as being limited to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included in the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. A display device, characterized in that: include: Pixel electrode; a pixel defining layer, on the pixel electrode and having an opening exposing at least a portion of the pixel electrode; a bank layer, on the pixel defining layer; an overhanging layer on the bank layer; An intermediate layer, on the pixel electrode; as well as a counter electrode, on said intermediate layer, wherein the overhang layer includes a tip portion protruding toward the pixel electrode from a point where a bottom surface of the overhang layer and a side surface of the bank layer facing the pixel electrode meet each other, and The height from the upper surface of the pixel defining layer to the upper surface of the bank layer is different from the height from the upper surface of the pixel defining layer to the bottom surface of the tip of the overhang layer.

2. The display device according to claim 1, characterized in that: The tip of the overhanging layer has an opening overlapping with the pixel electrode; The bank layer has an opening overlapping with the pixel electrode; as well as A width of the opening of the tip portion is smaller than a width of the opening of the bank layer.

3. The display device according to claim 1, characterized in that The height from the upper surface of the pixel defining layer to the bottom surface of the tip of the overhanging layer is greater than the height from the upper surface of the pixel defining layer to the upper surface of the bank layer.

4. The display device according to claim 3, characterized in that: The counter electrode is electrically connected to the bank layer.

5. The display device according to claim 3, characterized in that: The counter electrode is electrically connected to the overhanging layer.

6. The display device according to claim 5, characterized in that: The overhanging layer includes a conductive material.

7. The display device according to claim 1, characterized in that: The height from the upper surface of the pixel defining layer to the bottom surface of the tip of the overhanging layer is smaller than the height from the upper surface of the pixel defining layer to the upper surface of the bank layer.

8. The display device according to claim 7, characterized in that: The counter electrode is electrically connected to the bank layer.

9. The display device according to claim 8, characterized in that: The overhanging layer includes an organic insulating material or an inorganic insulating material.

10. The display device according to claim 7, characterized in that: The counter electrode is electrically connected to the overhanging layer.

11. The display device according to claim 10, characterized in that: The overhanging layer includes a conductive material.

12. The display device according to claim 1, characterized in that: Further including: an encapsulation layer on the overhanging layer and the opposing electrode; a dummy intermediate layer on the overhanging layer; as well as a dummy counter electrode, on the dummy intermediate layer, in: The dummy intermediate layer and the dummy relative electrode are located between the overhanging layer and the encapsulation layer; The dummy intermediate layer comprises a material that is the same as that of the intermediate layer; as well as The dummy opposing electrode includes a material that is the same as that of the opposing electrode.

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