SOP packaging structure

Abstract

The utility model discloses an SOP packaging structure. The SOP packaging structure comprises a nail frame, a semiconductor wafer and a positioning fixing piece. The nail frame is used for bearing the semiconductor wafer; the number of the semiconductor wafers is multiple, and the multiple semiconductor wafers are arranged on the nail frame. The positioning and fixing piece is arranged on the nail frame, and the positioning and fixing piece is used for positioning and fixing the semiconductor wafer on the nail frame. According to the utility model, the problem of yield loss caused by improper rib cutting can be solved, the quality requirement is met, the typesetting utilization rate of the semiconductor wafer can be improved, and the cost is reduced.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor packaging, in particular to a SOP packaging structure. Background Art

[0002] Semiconductor packaging refers to the process of processing the tested wafers into independent chips according to the product model and functional requirements. The packaging process is as follows: the wafers from the wafer front-end process are cut into small chips through the dicing process, and then the cut chips are glued to the corresponding substrate (lead frame) frame islands, and then ultra-fine metal (gold, tin, copper, and aluminum) wires or conductive resins are used to connect the bonding pads of the chips to the corresponding lead frames of the substrate to form the required circuits; then the independent chips are packaged and protected with plastic shells, and a series of operations are required after the plastic packaging. After the packaging is completed, the finished product is tested, usually after inspection, testing, and packaging, and finally shipped.

[0003] In the actual rib cutting and forming process, rib cutting mainly uses a cutter to separate the lead of the lead frame. In order to improve the accuracy and stability of the operation, it is often necessary to design the width and direction of the cutter to ensure that the cutting depth and position can meet the requirements. When performing trim processing, a stamping method is usually used to cut and deform the IC material according to the design requirements through a mold and pressure.

[0004] Due to the large width of the cutter and the large spacing between units in the lead frame design, the lead frame has bending problems. At the same time, there will be problems with long and short legs during stamping, which has certain defects. Utility Model Content

[0005] The utility model aims to provide a SOP packaging structure to improve the yield rate of semiconductor wafer cutting and forming.

[0006] In order to solve the above technical problems, the utility model provides a SOP packaging structure, including a nail frame, a semiconductor chip and a positioning fixture;

[0007] The nail rack is used to carry the semiconductor wafer;

[0008] There are a plurality of semiconductor wafers, and the plurality of semiconductor wafers are arranged on the nail rack;

[0009] The positioning and fixing member is arranged on the nail rack, and the positioning and fixing member is used to position and fix the semiconductor wafer located on the nail rack.

[0010] Furthermore, a positioning groove is provided on the nail rack, and the positioning groove matches the semiconductor wafer.

[0011] Furthermore, the semiconductor wafer is arranged in a strip shape.

[0012] Furthermore, the semiconductor wafers are evenly arranged along the length direction of the nail rack.

[0013] Furthermore, the length direction of the semiconductor wafer is perpendicular to the length direction of the nail rack.

[0014] Furthermore, the lead frames of the semiconductor wafer are distributed along the length direction thereof.

[0015] Furthermore, the positioning and fixing member adopts an adhesive layer, and the adhesive layer is used to adhere and fix the end of the semiconductor wafer.

[0016] Compared with the prior art, the utility model has at least the following beneficial effects:

[0017] The utility model increases the number of semiconductor chips arranged on the nail rack by changing the arrangement mode of the semiconductor chips on the nail rack. In addition, the lead frame is not subjected to rib cutting and forming during the cutting process, which can not only solve the yield loss problem caused by improper rib cutting and meet the quality requirements, but also improve the layout utilization rate of the semiconductor chips and reduce the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a diagram of the arrangement of semiconductor wafers on a nail rack in the prior art;

[0019] FIG2( a ) is a schematic diagram of a good product structure formed after cutting a semiconductor wafer;

[0020] Figure 2(b) and Figure 2(c) are schematic diagrams of defective structures formed after cutting of semiconductor wafers.

[0021] Figure 3 It is a schematic diagram of the overall structure of the SOP packaging structure of the utility model. DETAILED DESCRIPTION

[0022] The SOP package structure of the present invention will be described in more detail below in conjunction with the schematic diagram, wherein the preferred embodiment of the present invention is shown, and it should be understood that those skilled in the art can modify the present invention described herein, and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art, and not as a limitation to the present invention.

[0023] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0024] like Figure 3 As shown, an embodiment of the utility model proposes a SOP packaging structure, including a nail frame 1, a semiconductor chip 2 and a positioning fixture 3.

[0025] Specifically, the nail rack 1 is used to carry the semiconductor wafer 2 .

[0026] A plurality of semiconductor wafers 2 are provided, and the plurality of semiconductor wafers 2 are arranged on the nail rack 1 .

[0027] The positioning and fixing member 3 is disposed on the nail rack 1 , and the positioning and fixing member 3 is used to position and fix the semiconductor wafer 2 located on the nail rack 1 .

[0028] In the prior art, the arrangement of the semiconductor wafer 2 is as follows: Figure 1 As shown, due to the large width of the cutter and the large spacing between the units in the lead frame design, the lead frame has a bending problem, and there is also a problem of long and short legs during stamping (as shown in Figure 2(b) and Figure 2(c)).

[0029] In this embodiment, the semiconductor chip 2 is arranged in a strip shape, and the semiconductor chip 2 is evenly arranged along the length direction of the nail frame 1. The length direction of the semiconductor chip 2 is perpendicular to the length direction of the nail frame 1, and the lead frame of the semiconductor chip 2 is distributed along its length direction.

[0030] During the process of cutting and shaping the semiconductor wafer 2, the cutting direction of the cutting knife is perpendicular to the length direction of the semiconductor wafer 2. During the cutting process, the cutting knife passes through the lead frame to cut the semiconductor wafer 2 to form a semiconductor wafer unit.

[0031] Since the cutting blade does not directly contact and cut the lead frame, the lead frame does not deform or bend, which greatly improves the cutting yield of the semiconductor wafer 2 (the cutting effect is shown in Figure 2 (a)). In addition, compared with the prior art, this arrangement of semiconductor wafers 2 can greatly increase the arrangement amount, thereby improving the cutting efficiency of the semiconductor wafer 2, thereby reducing the cutting cost of the semiconductor wafer 2.

[0032] Furthermore, a positioning groove is provided on the nail rack 1 , and the positioning groove matches the semiconductor wafer 2 .

[0033] Specifically, during the arrangement of the semiconductor wafers 2, the semiconductor wafers 2 are distributed in the positioning grooves, so that the semiconductor wafers 2 can be positioned. In addition, the positioning fixture 3 can be used to position and fix the semiconductor wafers 2.

[0034] The positioning and fixing member 3 is an adhesive layer, and the adhesive layer is used to adhere and fix the end of the semiconductor wafer 2.

[0035] When cutting semiconductor wafers, the specific steps are as follows:

[0036] First, the semiconductor wafers 2 are evenly arranged on the nail rack 1 , and the semiconductor wafers 2 are positioned and fixed using the positioning and fixing members 3 .

[0037] Specifically, the semiconductor chips 2 are evenly arranged along the length direction of the nail rack 1 , the length direction of the semiconductor chips 2 is perpendicular to the length direction of the nail rack 1 , and the lead frames of the semiconductor chips 2 are distributed along the length direction thereof.

[0038] Then, the semiconductor wafer 2 is cut using a dicing blade to cut the semiconductor wafer 2 into individual semiconductor wafer units.

[0039] Specifically, when the dicing knife cuts the semiconductor wafer 2, the cutting direction of the dicing knife is perpendicular to the length of the semiconductor wafer 2. The dicing knife cuts by the width of the semiconductor wafer unit each time, and cuts the semiconductor wafer 2 into a plurality of semiconductor wafer units.

[0040] Since a large number of semiconductor wafers 2 are arranged on a single nail rack 1 , multiple semiconductor wafers 2 can be cut in a single cutting process, thereby improving the cutting efficiency of the semiconductor wafers 2 and further reducing the cutting cost of the semiconductor wafers 2 .

[0041] Compared with the prior art, the utility model has at least the following beneficial effects:

[0042] The utility model increases the number of semiconductor chips arranged on the nail rack by changing the arrangement mode of the semiconductor chips on the nail rack. In addition, the lead frame is not subjected to rib cutting and forming during the cutting process, which can not only solve the yield loss problem caused by improper rib cutting and meet the quality requirements, but also improve the layout utilization rate of the semiconductor chips and reduce the cost.

[0043] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A SOP packaging structure, characterized in that: It includes a nail rack, a semiconductor wafer and a positioning fixture; The nail rack is used to carry the semiconductor wafer; There are a plurality of semiconductor wafers, and the plurality of semiconductor wafers are arranged on the nail rack; The positioning and fixing member is arranged on the nail rack, and the positioning and fixing member is used to position and fix the semiconductor wafer located on the nail rack.

2. The SOP packaging structure as claimed in claim 1, characterized in that, The nail rack is provided with a positioning groove, and the positioning groove matches the semiconductor wafer.

3. The SOP packaging structure as claimed in claim 1, characterized in that, The semiconductor wafers are arranged in a strip shape.

4. The SOP packaging structure as claimed in claim 1, characterized in that, The semiconductor wafers are evenly arranged along the length direction of the nail rack.

5. The SOP packaging structure as claimed in claim 1, characterized in that, The length direction of the semiconductor wafer is perpendicular to the length direction of the nail rack.

6. The SOP packaging structure as claimed in claim 5, characterized in that, The lead frames of the semiconductor wafer are distributed along the length direction thereof.

7. The SOP packaging structure according to claim 1, characterized in that, The positioning and fixing member adopts an adhesive layer, and the adhesive layer is used to adhere and fix the end of the semiconductor wafer.

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